1 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
5 ; Make sure the code size estimate for inline asm is 12-bytes per
6 ; instruction, rather than 8 in previous generations.
8 ; GCN-LABEL: {{^}}long_forward_branch_gfx10only:
10 ; GFX9-NEXT: s_cbranch_scc1
13 ; GFX10-NEXT: s_cbranch_scc0
18 define amdgpu_kernel void @long_forward_branch_gfx10only(ptr addrspace(1) %arg, i32 %cnd) #0 {
20 %cmp = icmp eq i32 %cnd, 0
21 br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
24 ; Estimated as 40-bytes on gfx10 (requiring a long branch), but
25 ; 16-bytes on gfx9 (allowing a short branch)
26 call void asm sideeffect
32 store volatile i32 %cnd, ptr addrspace(1) %arg