1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SDAG %s
3 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-sdwa-peephole=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL %s
5 define amdgpu_vs void @fcmp_f32_olt_to_ogt(ptr addrspace(1) inreg %out, float inreg %a) {
6 ; SDAG-LABEL: fcmp_f32_olt_to_ogt:
7 ; SDAG: ; %bb.0: ; %entry
8 ; SDAG-NEXT: s_cmp_gt_f32 s2, 2.0
9 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
10 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
11 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
12 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
13 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
15 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
18 ; GISEL-LABEL: fcmp_f32_olt_to_ogt:
19 ; GISEL: ; %bb.0: ; %entry
20 ; GISEL-NEXT: s_cmp_gt_f32 s2, 2.0
21 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
22 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
23 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
24 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
25 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
26 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
28 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
29 ; GISEL-NEXT: s_endpgm
31 %0 = fcmp olt float 2.0, %a
32 %1 = sext i1 %0 to i32
33 store i32 %1, ptr addrspace(1) %out
37 define amdgpu_vs void @fcmp_f32_ogt_to_olt(ptr addrspace(1) inreg %out, float inreg %a) {
38 ; SDAG-LABEL: fcmp_f32_ogt_to_olt:
39 ; SDAG: ; %bb.0: ; %entry
40 ; SDAG-NEXT: s_cmp_lt_f32 s2, 2.0
41 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
42 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
43 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
44 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
45 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
47 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
50 ; GISEL-LABEL: fcmp_f32_ogt_to_olt:
51 ; GISEL: ; %bb.0: ; %entry
52 ; GISEL-NEXT: s_cmp_lt_f32 s2, 2.0
53 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
54 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
55 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
56 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
57 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
58 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
60 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
61 ; GISEL-NEXT: s_endpgm
63 %0 = fcmp ogt float 2.0, %a
64 %1 = sext i1 %0 to i32
65 store i32 %1, ptr addrspace(1) %out
69 define amdgpu_vs void @fcmp_f32_ole_to_oge(ptr addrspace(1) inreg %out, float inreg %a) {
70 ; SDAG-LABEL: fcmp_f32_ole_to_oge:
71 ; SDAG: ; %bb.0: ; %entry
72 ; SDAG-NEXT: s_cmp_ge_f32 s2, 2.0
73 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
74 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
75 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
76 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
77 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
79 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
82 ; GISEL-LABEL: fcmp_f32_ole_to_oge:
83 ; GISEL: ; %bb.0: ; %entry
84 ; GISEL-NEXT: s_cmp_ge_f32 s2, 2.0
85 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
86 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
87 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
88 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
89 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
90 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
92 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
93 ; GISEL-NEXT: s_endpgm
95 %0 = fcmp ole float 2.0, %a
96 %1 = sext i1 %0 to i32
97 store i32 %1, ptr addrspace(1) %out
101 define amdgpu_vs void @fcmp_f32_oge_to_ole(ptr addrspace(1) inreg %out, float inreg %a) {
102 ; SDAG-LABEL: fcmp_f32_oge_to_ole:
103 ; SDAG: ; %bb.0: ; %entry
104 ; SDAG-NEXT: s_cmp_le_f32 s2, 2.0
105 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
106 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
107 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
108 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
109 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
111 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
112 ; SDAG-NEXT: s_endpgm
114 ; GISEL-LABEL: fcmp_f32_oge_to_ole:
115 ; GISEL: ; %bb.0: ; %entry
116 ; GISEL-NEXT: s_cmp_le_f32 s2, 2.0
117 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
118 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
119 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
120 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
121 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
122 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
123 ; GISEL-NEXT: s_nop 0
124 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
125 ; GISEL-NEXT: s_endpgm
127 %0 = fcmp oge float 2.0, %a
128 %1 = sext i1 %0 to i32
129 store i32 %1, ptr addrspace(1) %out
133 define amdgpu_vs void @fcmp_f32_ult_to_ugt(ptr addrspace(1) inreg %out, float inreg %a) {
134 ; SDAG-LABEL: fcmp_f32_ult_to_ugt:
135 ; SDAG: ; %bb.0: ; %entry
136 ; SDAG-NEXT: s_cmp_nle_f32 s2, 2.0
137 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
138 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
139 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
140 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
141 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
143 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
144 ; SDAG-NEXT: s_endpgm
146 ; GISEL-LABEL: fcmp_f32_ult_to_ugt:
147 ; GISEL: ; %bb.0: ; %entry
148 ; GISEL-NEXT: s_cmp_nle_f32 s2, 2.0
149 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
150 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
151 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
152 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
153 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
154 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
155 ; GISEL-NEXT: s_nop 0
156 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
157 ; GISEL-NEXT: s_endpgm
159 %0 = fcmp ult float 2.0, %a
160 %1 = sext i1 %0 to i32
161 store i32 %1, ptr addrspace(1) %out
165 define amdgpu_vs void @fcmp_f32_ugt_to_ult(ptr addrspace(1) inreg %out, float inreg %a) {
166 ; SDAG-LABEL: fcmp_f32_ugt_to_ult:
167 ; SDAG: ; %bb.0: ; %entry
168 ; SDAG-NEXT: s_cmp_nge_f32 s2, 2.0
169 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
170 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
171 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
172 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
173 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
175 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
176 ; SDAG-NEXT: s_endpgm
178 ; GISEL-LABEL: fcmp_f32_ugt_to_ult:
179 ; GISEL: ; %bb.0: ; %entry
180 ; GISEL-NEXT: s_cmp_nge_f32 s2, 2.0
181 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
182 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
183 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
184 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
185 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
186 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
187 ; GISEL-NEXT: s_nop 0
188 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
189 ; GISEL-NEXT: s_endpgm
191 %0 = fcmp ugt float 2.0, %a
192 %1 = sext i1 %0 to i32
193 store i32 %1, ptr addrspace(1) %out
197 define amdgpu_vs void @fcmp_f32_ule_to_uge(ptr addrspace(1) inreg %out, float inreg %a) {
198 ; SDAG-LABEL: fcmp_f32_ule_to_uge:
199 ; SDAG: ; %bb.0: ; %entry
200 ; SDAG-NEXT: s_cmp_nlt_f32 s2, 2.0
201 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
202 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
203 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
204 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
205 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
207 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
208 ; SDAG-NEXT: s_endpgm
210 ; GISEL-LABEL: fcmp_f32_ule_to_uge:
211 ; GISEL: ; %bb.0: ; %entry
212 ; GISEL-NEXT: s_cmp_nlt_f32 s2, 2.0
213 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
214 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
215 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
216 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
217 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
218 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
219 ; GISEL-NEXT: s_nop 0
220 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
221 ; GISEL-NEXT: s_endpgm
223 %0 = fcmp ule float 2.0, %a
224 %1 = sext i1 %0 to i32
225 store i32 %1, ptr addrspace(1) %out
229 define amdgpu_vs void @fcmp_f32_uge_to_ule(ptr addrspace(1) inreg %out, float inreg %a) {
230 ; SDAG-LABEL: fcmp_f32_uge_to_ule:
231 ; SDAG: ; %bb.0: ; %entry
232 ; SDAG-NEXT: s_cmp_ngt_f32 s2, 2.0
233 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
234 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
235 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
236 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
237 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
239 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
240 ; SDAG-NEXT: s_endpgm
242 ; GISEL-LABEL: fcmp_f32_uge_to_ule:
243 ; GISEL: ; %bb.0: ; %entry
244 ; GISEL-NEXT: s_cmp_ngt_f32 s2, 2.0
245 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
246 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
247 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
248 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
249 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
250 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
251 ; GISEL-NEXT: s_nop 0
252 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
253 ; GISEL-NEXT: s_endpgm
255 %0 = fcmp uge float 2.0, %a
256 %1 = sext i1 %0 to i32
257 store i32 %1, ptr addrspace(1) %out
261 define amdgpu_vs void @fcmp_f16_olt_to_ogt(ptr addrspace(1) inreg %out, half inreg %a) {
262 ; SDAG-LABEL: fcmp_f16_olt_to_ogt:
263 ; SDAG: ; %bb.0: ; %entry
264 ; SDAG-NEXT: s_cmp_gt_f16 s2, 0x4000
265 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
266 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
267 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
268 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
269 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
271 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
272 ; SDAG-NEXT: s_endpgm
274 ; GISEL-LABEL: fcmp_f16_olt_to_ogt:
275 ; GISEL: ; %bb.0: ; %entry
276 ; GISEL-NEXT: s_cmp_gt_f16 s2, 0x4000
277 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
278 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
279 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
280 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
281 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
282 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
283 ; GISEL-NEXT: s_nop 0
284 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
285 ; GISEL-NEXT: s_endpgm
287 %0 = fcmp olt half 2.0, %a
288 %1 = sext i1 %0 to i32
289 store i32 %1, ptr addrspace(1) %out
293 define amdgpu_vs void @fcmp_f16_ogt_to_olt(ptr addrspace(1) inreg %out, half inreg %a) {
294 ; SDAG-LABEL: fcmp_f16_ogt_to_olt:
295 ; SDAG: ; %bb.0: ; %entry
296 ; SDAG-NEXT: s_cmp_lt_f16 s2, 0x4000
297 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
298 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
299 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
300 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
301 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
303 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
304 ; SDAG-NEXT: s_endpgm
306 ; GISEL-LABEL: fcmp_f16_ogt_to_olt:
307 ; GISEL: ; %bb.0: ; %entry
308 ; GISEL-NEXT: s_cmp_lt_f16 s2, 0x4000
309 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
310 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
311 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
312 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
313 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
314 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
315 ; GISEL-NEXT: s_nop 0
316 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
317 ; GISEL-NEXT: s_endpgm
319 %0 = fcmp ogt half 2.0, %a
320 %1 = sext i1 %0 to i32
321 store i32 %1, ptr addrspace(1) %out
325 define amdgpu_vs void @fcmp_f16_ole_to_oge(ptr addrspace(1) inreg %out, half inreg %a) {
326 ; SDAG-LABEL: fcmp_f16_ole_to_oge:
327 ; SDAG: ; %bb.0: ; %entry
328 ; SDAG-NEXT: s_cmp_ge_f16 s2, 0x4000
329 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
330 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
331 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
332 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
333 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
335 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
336 ; SDAG-NEXT: s_endpgm
338 ; GISEL-LABEL: fcmp_f16_ole_to_oge:
339 ; GISEL: ; %bb.0: ; %entry
340 ; GISEL-NEXT: s_cmp_ge_f16 s2, 0x4000
341 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
342 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
343 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
344 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
345 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
346 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
347 ; GISEL-NEXT: s_nop 0
348 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
349 ; GISEL-NEXT: s_endpgm
351 %0 = fcmp ole half 2.0, %a
352 %1 = sext i1 %0 to i32
353 store i32 %1, ptr addrspace(1) %out
357 define amdgpu_vs void @fcmp_f16_oge_to_ole(ptr addrspace(1) inreg %out, half inreg %a) {
358 ; SDAG-LABEL: fcmp_f16_oge_to_ole:
359 ; SDAG: ; %bb.0: ; %entry
360 ; SDAG-NEXT: s_cmp_le_f16 s2, 0x4000
361 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
362 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
363 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
364 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
365 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
367 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
368 ; SDAG-NEXT: s_endpgm
370 ; GISEL-LABEL: fcmp_f16_oge_to_ole:
371 ; GISEL: ; %bb.0: ; %entry
372 ; GISEL-NEXT: s_cmp_le_f16 s2, 0x4000
373 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
374 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
375 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
376 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
377 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
378 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
379 ; GISEL-NEXT: s_nop 0
380 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
381 ; GISEL-NEXT: s_endpgm
383 %0 = fcmp oge half 2.0, %a
384 %1 = sext i1 %0 to i32
385 store i32 %1, ptr addrspace(1) %out
389 define amdgpu_vs void @fcmp_f16_ult_to_ugt(ptr addrspace(1) inreg %out, half inreg %a) {
390 ; SDAG-LABEL: fcmp_f16_ult_to_ugt:
391 ; SDAG: ; %bb.0: ; %entry
392 ; SDAG-NEXT: s_cmp_nle_f16 s2, 0x4000
393 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
394 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
395 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
396 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
397 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
399 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
400 ; SDAG-NEXT: s_endpgm
402 ; GISEL-LABEL: fcmp_f16_ult_to_ugt:
403 ; GISEL: ; %bb.0: ; %entry
404 ; GISEL-NEXT: s_cmp_nle_f16 s2, 0x4000
405 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
406 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
407 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
408 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
409 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
410 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
411 ; GISEL-NEXT: s_nop 0
412 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
413 ; GISEL-NEXT: s_endpgm
415 %0 = fcmp ult half 2.0, %a
416 %1 = sext i1 %0 to i32
417 store i32 %1, ptr addrspace(1) %out
421 define amdgpu_vs void @fcmp_f16_ugt_to_ult(ptr addrspace(1) inreg %out, half inreg %a) {
422 ; SDAG-LABEL: fcmp_f16_ugt_to_ult:
423 ; SDAG: ; %bb.0: ; %entry
424 ; SDAG-NEXT: s_cmp_nge_f16 s2, 0x4000
425 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
426 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
427 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
428 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
429 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
431 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
432 ; SDAG-NEXT: s_endpgm
434 ; GISEL-LABEL: fcmp_f16_ugt_to_ult:
435 ; GISEL: ; %bb.0: ; %entry
436 ; GISEL-NEXT: s_cmp_nge_f16 s2, 0x4000
437 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
438 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
439 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
440 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
441 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
442 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
443 ; GISEL-NEXT: s_nop 0
444 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
445 ; GISEL-NEXT: s_endpgm
447 %0 = fcmp ugt half 2.0, %a
448 %1 = sext i1 %0 to i32
449 store i32 %1, ptr addrspace(1) %out
453 define amdgpu_vs void @fcmp_ule_to_uge(ptr addrspace(1) inreg %out, half inreg %a) {
454 ; SDAG-LABEL: fcmp_ule_to_uge:
455 ; SDAG: ; %bb.0: ; %entry
456 ; SDAG-NEXT: s_cmp_nlt_f16 s2, 0x4000
457 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
458 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
459 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
460 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
461 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
463 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
464 ; SDAG-NEXT: s_endpgm
466 ; GISEL-LABEL: fcmp_ule_to_uge:
467 ; GISEL: ; %bb.0: ; %entry
468 ; GISEL-NEXT: s_cmp_nlt_f16 s2, 0x4000
469 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
470 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
471 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
472 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
473 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
474 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
475 ; GISEL-NEXT: s_nop 0
476 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
477 ; GISEL-NEXT: s_endpgm
479 %0 = fcmp ule half 2.0, %a
480 %1 = sext i1 %0 to i32
481 store i32 %1, ptr addrspace(1) %out
485 define amdgpu_vs void @fcmp_uge_to_ule(ptr addrspace(1) inreg %out, half inreg %a) {
486 ; SDAG-LABEL: fcmp_uge_to_ule:
487 ; SDAG: ; %bb.0: ; %entry
488 ; SDAG-NEXT: s_cmp_ngt_f16 s2, 0x4000
489 ; SDAG-NEXT: v_mov_b32_e32 v0, 0
490 ; SDAG-NEXT: s_cselect_b32 s2, -1, 0
491 ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
492 ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
493 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
495 ; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
496 ; SDAG-NEXT: s_endpgm
498 ; GISEL-LABEL: fcmp_uge_to_ule:
499 ; GISEL: ; %bb.0: ; %entry
500 ; GISEL-NEXT: s_cmp_ngt_f16 s2, 0x4000
501 ; GISEL-NEXT: v_mov_b32_e32 v1, 0
502 ; GISEL-NEXT: s_cselect_b32 s2, 1, 0
503 ; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
504 ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000
505 ; GISEL-NEXT: v_mov_b32_e32 v0, s2
506 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
507 ; GISEL-NEXT: s_nop 0
508 ; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
509 ; GISEL-NEXT: s_endpgm
511 %0 = fcmp uge half 2.0, %a
512 %1 = sext i1 %0 to i32
513 store i32 %1, ptr addrspace(1) %out