llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
   2 # RUN: llc -mtriple=amdgcn -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s
   3
   4 # Test to ensure that this does not crash on undefs
   5 ---
   6 name: copyprop_regsequence_with_undef
   7 tracksRegLiveness: true
   8 body:               |
   9   bb.0:
  10     ; CHECK-LABEL: name: copyprop_regsequence_with_undef
  11     ; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  12     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  13     ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %3:sreg_32, %subreg.sub0, [[DEF]], %subreg.sub1
  14     ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %5:sreg_32, %subreg.sub0, [[DEF1]], %subreg.sub1
  15     ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[REG_SEQUENCE]].sub1, [[REG_SEQUENCE1]].sub1, implicit-def $scc
  16     %0:sreg_32 = IMPLICIT_DEF
  17     %1:sreg_32 = IMPLICIT_DEF
  18     %4:sreg_64 = REG_SEQUENCE undef %10:sreg_32, %subreg.sub0, %0:sreg_32, %subreg.sub1
  19     %5:sreg_64 = REG_SEQUENCE undef %11:sreg_32, %subreg.sub0, %1:sreg_32, %subreg.sub1
  20     %6:sreg_32 = S_ADD_I32 %4.sub1:sreg_64, %5.sub1:sreg_64, implicit-def $scc
  21
  22 ...