| blob | 54fb1dc5c052743911c6666d10abe760d0cebec5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
4 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
7 define i32 @s_add_co_select_user() {
8 ; GFX7-LABEL: s_add_co_select_user:
9 ; GFX7: ; %bb.0: ; %bb
10 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
12 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0
13 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
14 ; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6
15 ; GFX7-NEXT: s_or_b32 s4, s4, s5
16 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0
17 ; GFX7-NEXT: s_addc_u32 s7, s6, 0
18 ; GFX7-NEXT: s_cselect_b64 s[4:5], -1, 0
19 ; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec
20 ; GFX7-NEXT: s_cselect_b32 s4, s7, 0
21 ; GFX7-NEXT: s_cmp_gt_u32 s6, 31
22 ; GFX7-NEXT: v_mov_b32_e32 v1, s4
23 ; GFX7-NEXT: s_cselect_b64 vcc, -1, 0
24 ; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
25 ; GFX7-NEXT: s_setpc_b64 s[30:31]
26 ;
27 ; GFX9-LABEL: s_add_co_select_user:
28 ; GFX9: ; %bb.0: ; %bb
29 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
30 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
31 ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0
32 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
33 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6
34 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
35 ; GFX9-NEXT: s_addc_u32 s7, s6, 0
36 ; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0
37 ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
38 ; GFX9-NEXT: s_cselect_b32 s4, s7, 0
39 ; GFX9-NEXT: s_cmp_gt_u32 s6, 31
40 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
41 ; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
42 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
43 ; GFX9-NEXT: s_setpc_b64 s[30:31]
44 ;
45 ; GFX10-LABEL: s_add_co_select_user:
46 ; GFX10: ; %bb.0: ; %bb
47 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
48 ; GFX10-NEXT: s_mov_b64 s[4:5], 0
49 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
50 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
51 ; GFX10-NEXT: v_add_co_u32 v0, s5, s4, s4
52 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0
53 ; GFX10-NEXT: s_addc_u32 s5, s4, 0
54 ; GFX10-NEXT: s_cselect_b32 s6, -1, 0
55 ; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
56 ; GFX10-NEXT: s_cselect_b32 s5, s5, 0
57 ; GFX10-NEXT: s_cmp_gt_u32 s4, 31
58 ; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
59 ; GFX10-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo
60 ; GFX10-NEXT: s_setpc_b64 s[30:31]
61 ;
62 ; GFX11-LABEL: s_add_co_select_user:
63 ; GFX11: ; %bb.0: ; %bb
64 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
65 ; GFX11-NEXT: s_mov_b64 s[0:1], 0
66 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
67 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
68 ; GFX11-NEXT: v_add_co_u32 v0, s1, s0, s0
69 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
70 ; GFX11-NEXT: s_cmp_lg_u32 s1, 0
71 ; GFX11-NEXT: s_addc_u32 s1, s0, 0
72 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
73 ; GFX11-NEXT: s_and_b32 s2, s2, exec_lo
74 ; GFX11-NEXT: s_cselect_b32 s1, s1, 0
75 ; GFX11-NEXT: s_cmp_gt_u32 s0, 31
76 ; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0
77 ; GFX11-NEXT: v_cndmask_b32_e32 v0, s1, v0, vcc_lo
78 ; GFX11-NEXT: s_setpc_b64 s[30:31]
79 bb:
80 %i = load volatile i32, ptr addrspace(4) null, align 8
81 %i1 = add i32 %i, %i
82 %i2 = icmp ult i32 %i1, %i
83 %i3 = zext i1 %i2 to i32
84 %i4 = add nuw nsw i32 %i3, 0
85 %i5 = add i32 %i4, %i
86 %i6 = icmp ult i32 %i5, %i4
87 %i7 = select i1 %i6, i32 %i5, i32 0
88 %i8 = icmp ugt i32 %i, 31
89 %i9 = select i1 %i8, i32 %i1, i32 %i7
90 ret i32 %i9
91 }
93 define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
94 ; GFX7-LABEL: s_add_co_br_user:
95 ; GFX7: ; %bb.0: ; %bb
96 ; GFX7-NEXT: s_load_dword s2, s[6:7], 0x0
97 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
98 ; GFX7-NEXT: s_add_i32 s0, s2, s2
99 ; GFX7-NEXT: s_cmp_lt_u32 s0, s2
100 ; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
101 ; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
102 ; GFX7-NEXT: s_or_b32 s0, s0, s1
103 ; GFX7-NEXT: s_cmp_lg_u32 s0, 0
104 ; GFX7-NEXT: s_addc_u32 s0, s2, 0
105 ; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
106 ; GFX7-NEXT: s_cbranch_vccnz .LBB1_2
107 ; GFX7-NEXT: ; %bb.1: ; %bb0
108 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
109 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
110 ; GFX7-NEXT: v_mov_b32_e32 v2, 9
111 ; GFX7-NEXT: flat_store_dword v[0:1], v2
112 ; GFX7-NEXT: s_waitcnt vmcnt(0)
113 ; GFX7-NEXT: .LBB1_2: ; %bb1
114 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
115 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
116 ; GFX7-NEXT: v_mov_b32_e32 v2, 10
117 ; GFX7-NEXT: flat_store_dword v[0:1], v2
118 ; GFX7-NEXT: s_waitcnt vmcnt(0)
119 ; GFX7-NEXT: s_endpgm
120 ;
121 ; GFX9-LABEL: s_add_co_br_user:
122 ; GFX9: ; %bb.0: ; %bb
123 ; GFX9-NEXT: s_load_dword s2, s[6:7], 0x0
124 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
125 ; GFX9-NEXT: s_add_i32 s0, s2, s2
126 ; GFX9-NEXT: s_cmp_lt_u32 s0, s2
127 ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
128 ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
129 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
130 ; GFX9-NEXT: s_addc_u32 s0, s2, 0
131 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
132 ; GFX9-NEXT: s_cbranch_vccnz .LBB1_2
133 ; GFX9-NEXT: ; %bb.1: ; %bb0
134 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
135 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
136 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
137 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
138 ; GFX9-NEXT: s_waitcnt vmcnt(0)
139 ; GFX9-NEXT: .LBB1_2: ; %bb1
140 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
141 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
142 ; GFX9-NEXT: v_mov_b32_e32 v2, 10
143 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
144 ; GFX9-NEXT: s_waitcnt vmcnt(0)
145 ; GFX9-NEXT: s_endpgm
146 ;
147 ; GFX10-LABEL: s_add_co_br_user:
148 ; GFX10: ; %bb.0: ; %bb
149 ; GFX10-NEXT: s_load_dword s0, s[6:7], 0x0
150 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
151 ; GFX10-NEXT: s_add_i32 s1, s0, s0
152 ; GFX10-NEXT: s_cmp_lt_u32 s1, s0
153 ; GFX10-NEXT: s_cselect_b32 s1, -1, 0
154 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
155 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0
156 ; GFX10-NEXT: s_addc_u32 s0, s0, 0
157 ; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
158 ; GFX10-NEXT: s_cbranch_vccnz .LBB1_2
159 ; GFX10-NEXT: ; %bb.1: ; %bb0
160 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
161 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
162 ; GFX10-NEXT: v_mov_b32_e32 v2, 9
163 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
164 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
165 ; GFX10-NEXT: .LBB1_2: ; %bb1
166 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
167 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
168 ; GFX10-NEXT: v_mov_b32_e32 v2, 10
169 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
170 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
171 ; GFX10-NEXT: s_endpgm
172 ;
173 ; GFX11-LABEL: s_add_co_br_user:
174 ; GFX11: ; %bb.0: ; %bb
175 ; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0
176 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
177 ; GFX11-NEXT: s_add_i32 s1, s0, s0
178 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
179 ; GFX11-NEXT: s_cmp_lt_u32 s1, s0
180 ; GFX11-NEXT: s_cselect_b32 s1, -1, 0
181 ; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
182 ; GFX11-NEXT: s_cmp_lg_u32 s1, 0
183 ; GFX11-NEXT: s_addc_u32 s0, s0, 0
184 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
185 ; GFX11-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
186 ; GFX11-NEXT: s_cbranch_vccnz .LBB1_2
187 ; GFX11-NEXT: ; %bb.1: ; %bb0
188 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
189 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 9
190 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off dlc
191 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
192 ; GFX11-NEXT: .LBB1_2: ; %bb1
193 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
194 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 10
195 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off dlc
196 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
197 ; GFX11-NEXT: s_nop 0
198 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
199 ; GFX11-NEXT: s_endpgm
200 bb:
201 %i1 = add i32 %i, %i
202 %i2 = icmp ult i32 %i1, %i
203 %i3 = zext i1 %i2 to i32
204 %i4 = add nuw nsw i32 %i3, 0
205 %i5 = add i32 %i4, %i
206 %i6 = icmp ult i32 %i5, %i4
207 %i7 = select i1 %i6, i32 %i5, i32 0
208 br i1 %i6, label %bb0, label %bb1
210 bb0:
211 store volatile i32 9, ptr addrspace(1) null
212 br label %bb1
214 bb1:
215 store volatile i32 10, ptr addrspace(1) null
216 ret void
217 }