1 ; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN
4 ; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
5 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
6 define amdgpu_kernel void @and_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
7 %id = call i32 @llvm.amdgcn.workitem.id.x() #1
8 %ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id
9 %a = load i16, ptr addrspace(1) %in
10 %b = load i16, ptr addrspace(1) %ptr
12 %val16 = and i16 %c, %a
13 %val32 = zext i16 %val16 to i32
14 store i32 %val32, ptr addrspace(1) %out
19 ; GCN: v_or_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
20 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
21 define amdgpu_kernel void @or_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
22 %id = call i32 @llvm.amdgcn.workitem.id.x() #1
23 %ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id
24 %a = load i16, ptr addrspace(1) %in
25 %b = load i16, ptr addrspace(1) %ptr
27 %val16 = or i16 %c, %a
28 %val32 = zext i16 %val16 to i32
29 store i32 %val32, ptr addrspace(1) %out
33 ; GCN-LABEL: xor_zext:
34 ; GCN: v_xor_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
35 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
36 define amdgpu_kernel void @xor_zext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
37 %id = call i32 @llvm.amdgcn.workitem.id.x() #1
38 %ptr = getelementptr i16, ptr addrspace(1) %in, i32 %id
39 %a = load i16, ptr addrspace(1) %in
40 %b = load i16, ptr addrspace(1) %ptr
42 %val16 = xor i16 %c, %a
43 %val32 = zext i16 %val16 to i32
44 store i32 %val32, ptr addrspace(1) %out
48 declare i32 @llvm.amdgcn.workitem.id.x() #1
50 attributes #1 = { nounwind readnone }