| blob | d8a726f251a01e501dc58a464ba2b34bde56ac7b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6 %s
3 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
4 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
5 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=CYPRESS %s
7 declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
9 define amdgpu_kernel void @test_convert_fp32_to_fp16(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
10 ; GFX6-LABEL: test_convert_fp32_to_fp16:
11 ; GFX6: ; %bb.0:
12 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
13 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
14 ; GFX6-NEXT: s_mov_b32 s6, -1
15 ; GFX6-NEXT: s_mov_b32 s10, s6
16 ; GFX6-NEXT: s_mov_b32 s11, s7
17 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
18 ; GFX6-NEXT: s_mov_b32 s8, s2
19 ; GFX6-NEXT: s_mov_b32 s9, s3
20 ; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
21 ; GFX6-NEXT: s_mov_b32 s4, s0
22 ; GFX6-NEXT: s_mov_b32 s5, s1
23 ; GFX6-NEXT: s_waitcnt vmcnt(0)
24 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
25 ; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0
26 ; GFX6-NEXT: s_endpgm
27 ;
28 ; GFX8-LABEL: test_convert_fp32_to_fp16:
29 ; GFX8: ; %bb.0:
30 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
31 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
32 ; GFX8-NEXT: s_mov_b32 s6, -1
33 ; GFX8-NEXT: s_mov_b32 s10, s6
34 ; GFX8-NEXT: s_mov_b32 s11, s7
35 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
36 ; GFX8-NEXT: s_mov_b32 s8, s2
37 ; GFX8-NEXT: s_mov_b32 s9, s3
38 ; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
39 ; GFX8-NEXT: s_mov_b32 s4, s0
40 ; GFX8-NEXT: s_mov_b32 s5, s1
41 ; GFX8-NEXT: s_waitcnt vmcnt(0)
42 ; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
43 ; GFX8-NEXT: buffer_store_short v0, off, s[4:7], 0
44 ; GFX8-NEXT: s_endpgm
45 ;
46 ; GFX11-LABEL: test_convert_fp32_to_fp16:
47 ; GFX11: ; %bb.0:
48 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
49 ; GFX11-NEXT: s_mov_b32 s6, -1
50 ; GFX11-NEXT: s_mov_b32 s7, 0x31016000
51 ; GFX11-NEXT: s_mov_b32 s10, s6
52 ; GFX11-NEXT: s_mov_b32 s11, s7
53 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
54 ; GFX11-NEXT: s_mov_b32 s8, s2
55 ; GFX11-NEXT: s_mov_b32 s9, s3
56 ; GFX11-NEXT: s_mov_b32 s4, s0
57 ; GFX11-NEXT: buffer_load_b32 v0, off, s[8:11], 0
58 ; GFX11-NEXT: s_mov_b32 s5, s1
59 ; GFX11-NEXT: s_waitcnt vmcnt(0)
60 ; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
61 ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
62 ; GFX11-NEXT: s_nop 0
63 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
64 ; GFX11-NEXT: s_endpgm
65 ;
66 ; CYPRESS-LABEL: test_convert_fp32_to_fp16:
67 ; CYPRESS: ; %bb.0:
68 ; CYPRESS-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
69 ; CYPRESS-NEXT: TEX 0 @6
70 ; CYPRESS-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
71 ; CYPRESS-NEXT: MEM_RAT MSKOR T0.XW, T1.X
72 ; CYPRESS-NEXT: CF_END
73 ; CYPRESS-NEXT: PAD
74 ; CYPRESS-NEXT: Fetch clause starting at 6:
75 ; CYPRESS-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
76 ; CYPRESS-NEXT: ALU clause starting at 8:
77 ; CYPRESS-NEXT: MOV * T0.X, KC0[2].Z,
78 ; CYPRESS-NEXT: ALU clause starting at 9:
79 ; CYPRESS-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,
80 ; CYPRESS-NEXT: 3(4.203895e-45), 0(0.000000e+00)
81 ; CYPRESS-NEXT: FLT32_TO_FLT16 T1.W, T0.X,
82 ; CYPRESS-NEXT: LSHL * T0.W, PV.W, literal.x,
83 ; CYPRESS-NEXT: 3(4.203895e-45), 0(0.000000e+00)
84 ; CYPRESS-NEXT: LSHL T0.X, PV.W, PS,
85 ; CYPRESS-NEXT: LSHL * T0.W, literal.x, PS,
86 ; CYPRESS-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
87 ; CYPRESS-NEXT: MOV T0.Y, 0.0,
88 ; CYPRESS-NEXT: MOV * T0.Z, 0.0,
89 ; CYPRESS-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
90 ; CYPRESS-NEXT: 2(2.802597e-45), 0(0.000000e+00)
91 %val = load float, ptr addrspace(1) %in, align 4
92 %cvt = call i16 @llvm.convert.to.fp16.f32(float %val) nounwind readnone
93 store i16 %cvt, ptr addrspace(1) %out, align 2
94 ret void
95 }