llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll

   1 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck --check-prefixes=GCN,CI,ALL %s
   2 ; RUN: llc -mtriple=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,VI,ALL %s
   3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,GFX9,ALL %s
   4 ; RUN: llc -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
   5 ; RUN: llc -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
   6 ; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
   7 ; RUN: llc -mcpu=gfx1100 -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global,-architected-flat-scratch,-user-sgpr-init16-bug < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
   8
   9 ; FIXME: align on alloca seems to be ignored for private_segment_alignment
  10
  11 ; ALL-LABEL: {{^}}large_alloca_compute_shader:
  12
  13 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
  14 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
  15 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
  16 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1
  17 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
  18 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000
  19 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000
  20 ; GFX9-DAG: s_mov_b32 s{{[0-9]+}}, 0xe00000
  21
  22 ; GCNHSA: buffer_store_{{dword|b32}} {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen
  23 ; GCNHSA: buffer_load_{{dword|b32}} {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen
  24
  25 ; GCNHSA: .amdhsa_kernel large_alloca_compute_shader
  26 ; GCNHSA:         .amdhsa_group_segment_fixed_size 0
  27 ; GCNHSA:         .amdhsa_private_segment_fixed_size 32772
  28 ; GCNHSA:         .amdhsa_user_sgpr_private_segment_buffer 1
  29 ; GCNHSA:         .amdhsa_user_sgpr_dispatch_ptr 1
  30 ; GCNHSA:         .amdhsa_user_sgpr_queue_ptr 1
  31 ; GCNHSA:         .amdhsa_user_sgpr_kernarg_segment_ptr 1
  32 ; GCNHSA:         .amdhsa_user_sgpr_dispatch_id 1
  33 ; GCNHSA:         .amdhsa_user_sgpr_flat_scratch_init 1
  34 ; GCNHSA:         .amdhsa_user_sgpr_private_segment_size 0
  35 ; GCNHSA:         .amdhsa_system_sgpr_private_segment_wavefront_offset 1
  36 ; GCNHSA:         .amdhsa_system_sgpr_workgroup_id_x 1
  37 ; GCNHSA:         .amdhsa_system_sgpr_workgroup_id_y 1
  38 ; GCNHSA:         .amdhsa_system_sgpr_workgroup_id_z 1
  39 ; GCNHSA:         .amdhsa_system_sgpr_workgroup_info 0
  40 ; GCNHSA:         .amdhsa_system_vgpr_workitem_id 2
  41 ; GCNHSA:         .amdhsa_next_free_vgpr 3
  42 ; GCNHSA:         .amdhsa_next_free_sgpr 18
  43 ; GCNHSA:         .amdhsa_float_round_mode_32 0
  44 ; GCNHSA:         .amdhsa_float_round_mode_16_64 0
  45 ; GCNHSA:         .amdhsa_float_denorm_mode_32 3
  46 ; GCNHSA:         .amdhsa_float_denorm_mode_16_64 3
  47 ; GCNHSA:         .amdhsa_dx10_clamp 1
  48 ; GCNHSA:         .amdhsa_ieee_mode 1
  49 ; GCNHSA:         .amdhsa_exception_fp_ieee_invalid_op 0
  50 ; GCNHSA:         .amdhsa_exception_fp_denorm_src 0
  51 ; GCNHSA:         .amdhsa_exception_fp_ieee_div_zero 0
  52 ; GCNHSA:         .amdhsa_exception_fp_ieee_overflow 0
  53 ; GCNHSA:         .amdhsa_exception_fp_ieee_underflow 0
  54 ; GCNHSA:         .amdhsa_exception_fp_ieee_inexact 0
  55 ; GCNHSA:         .amdhsa_exception_int_div_zero 0
  56 ; GCNHSA: .end_amdhsa_kernel
  57
  58 ; Scratch size = alloca size + emergency stack slot, align {{.*}}, addrspace(5)
  59 ; ALL: ; ScratchSize: 32772
  60 define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 {
  61   %large = alloca [8192 x i32], align 4, addrspace(5)
  62   %gep = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 8191
  63   store volatile i32 %x, ptr addrspace(5) %gep
  64   %gep1 = getelementptr [8192 x i32], ptr addrspace(5) %large, i32 0, i32 %y
  65   %val = load volatile i32, ptr addrspace(5) %gep1
  66   store volatile i32 %val, ptr addrspace(1) undef
  67   ret void
  68 }
  69
  70 attributes #0 = { nounwind  }
  71
  72 !llvm.module.flags = !{!0}
  73 !0 = !{i32 1, !"amdhsa_code_object_version", i32 400}