1 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s
2 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
5 declare half @llvm.amdgcn.fmad.ftz.f16(half %a, half %b, half %c)
7 ; GCN-LABEL: {{^}}mad_f16:
8 ; GCN: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+$}}
9 define amdgpu_kernel void @mad_f16(
13 ptr addrspace(1) %c) {
14 %a.val = load half, ptr addrspace(1) %a
15 %b.val = load half, ptr addrspace(1) %b
16 %c.val = load half, ptr addrspace(1) %c
17 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %b.val, half %c.val)
18 store half %r.val, ptr addrspace(1) %r
22 ; GCN-LABEL: {{^}}mad_f16_imm_a:
23 ; GCN: v_madmk_f16 {{v[0-9]+}}, {{v[0-9]+}}, 0x4800, {{v[0-9]+}}
24 define amdgpu_kernel void @mad_f16_imm_a(
27 ptr addrspace(1) %c) {
28 %b.val = load half, ptr addrspace(1) %b
29 %c.val = load half, ptr addrspace(1) %c
30 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half 8.0, half %b.val, half %c.val)
31 store half %r.val, ptr addrspace(1) %r
35 ; GCN-LABEL: {{^}}mad_f16_imm_b:
36 ; GCN: v_madmk_f16 {{v[0-9]+}}, {{v[0-9]+}}, 0x4800, {{v[0-9]+$}}
37 define amdgpu_kernel void @mad_f16_imm_b(
40 ptr addrspace(1) %c) {
41 %a.val = load half, ptr addrspace(1) %a
42 %c.val = load half, ptr addrspace(1) %c
43 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half 8.0, half %c.val)
44 store half %r.val, ptr addrspace(1) %r
48 ; GCN-LABEL: {{^}}mad_f16_imm_c:
49 ; GCN: v_madak_f16 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4800{{$}}
50 define amdgpu_kernel void @mad_f16_imm_c(
53 ptr addrspace(1) %b) {
54 %a.val = load half, ptr addrspace(1) %a
55 %b.val = load half, ptr addrspace(1) %b
56 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %b.val, half 8.0)
57 store half %r.val, ptr addrspace(1) %r
61 ; GCN-LABEL: {{^}}mad_f16_neg_b:
62 ; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}
63 ; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}
64 define amdgpu_kernel void @mad_f16_neg_b(
68 ptr addrspace(1) %c) {
69 %a.val = load half, ptr addrspace(1) %a
70 %b.val = load half, ptr addrspace(1) %b
71 %c.val = load half, ptr addrspace(1) %c
72 %neg.b = fsub half -0.0, %b.val
73 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %neg.b, half %c.val)
74 store half %r.val, ptr addrspace(1) %r
78 ; GCN-LABEL: {{^}}mad_f16_abs_b:
79 ; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}}
80 ; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}}
81 define amdgpu_kernel void @mad_f16_abs_b(
85 ptr addrspace(1) %c) {
86 %a.val = load half, ptr addrspace(1) %a
87 %b.val = load half, ptr addrspace(1) %b
88 %c.val = load half, ptr addrspace(1) %c
89 %abs.b = call half @llvm.fabs.f16(half %b.val)
90 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %abs.b, half %c.val)
91 store half %r.val, ptr addrspace(1) %r
95 ; GCN-LABEL: {{^}}mad_f16_neg_abs_b:
96 ; GFX8: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}}
97 ; GFX9: v_mad_legacy_f16 v{{[0-9]+}}, v{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}}
98 define amdgpu_kernel void @mad_f16_neg_abs_b(
102 ptr addrspace(1) %c) {
103 %a.val = load half, ptr addrspace(1) %a
104 %b.val = load half, ptr addrspace(1) %b
105 %c.val = load half, ptr addrspace(1) %c
106 %abs.b = call half @llvm.fabs.f16(half %b.val)
107 %neg.abs.b = fsub half -0.0, %abs.b
108 %r.val = call half @llvm.amdgcn.fmad.ftz.f16(half %a.val, half %neg.abs.b, half %c.val)
109 store half %r.val, ptr addrspace(1) %r
113 declare half @llvm.fabs.f16(half)