| blob | 0393a551dcd41b45cffc156b871b57e2a52bcb3c |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1013 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1013 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1030 %s
4 ; RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s
7 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
8 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
9 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(ulong node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
10 ; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
12 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
13 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
14 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
15 declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
17 ; ERR: in function image_bvh_intersect_ray{{.*}}intrinsic not supported on subtarget
18 ; Arguments are flattened to represent the actual VGPR_A layout, so we have no
19 ; extra moves in the generated kernel.
20 define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
21 ; GCN-LABEL: image_bvh_intersect_ray:
22 ; GCN: ; %bb.0: ; %main_body
23 ; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[0:3]
24 ; GCN-NEXT: s_waitcnt vmcnt(0)
25 ; GCN-NEXT: ; return to shader part epilog
26 main_body:
27 %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
28 %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
29 %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
30 %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
31 %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
32 %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
33 %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
34 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
35 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
36 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
37 %r = bitcast <4 x i32> %v to <4 x float>
38 ret <4 x float> %r
39 }
41 define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
42 ; GFX10-LABEL: image_bvh_intersect_ray_a16:
43 ; GFX10: ; %bb.0: ; %main_body
44 ; GFX10-NEXT: s_mov_b32 s15, s12
45 ; GFX10-NEXT: s_mov_b32 s12, s9
46 ; GFX10-NEXT: s_lshr_b32 s9, s7, 16
47 ; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7
48 ; GFX10-NEXT: s_pack_ll_b32_b16 s7, s9, s8
49 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
50 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
51 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
52 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
53 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
54 ; GFX10-NEXT: v_mov_b32_e32 v5, s5
55 ; GFX10-NEXT: v_mov_b32_e32 v6, s6
56 ; GFX10-NEXT: v_mov_b32_e32 v7, s7
57 ; GFX10-NEXT: s_mov_b32 s14, s11
58 ; GFX10-NEXT: s_mov_b32 s13, s10
59 ; GFX10-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[12:15] a16
60 ; GFX10-NEXT: s_waitcnt vmcnt(0)
61 ; GFX10-NEXT: ; return to shader part epilog
62 ;
63 ; GFX11-LABEL: image_bvh_intersect_ray_a16:
64 ; GFX11: ; %bb.0: ; %main_body
65 ; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
66 ; GFX11-NEXT: s_lshr_b32 s2, s7, 16
67 ; GFX11-NEXT: s_lshr_b32 s3, s5, 16
68 ; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
69 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s3, s2
70 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s5, s7
71 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
72 ; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s3
73 ; GFX11-NEXT: s_pack_ll_b32_b16 s4, s6, s8
74 ; GFX11-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s4
75 ; GFX11-NEXT: s_mov_b32 s15, s12
76 ; GFX11-NEXT: s_mov_b32 s14, s11
77 ; GFX11-NEXT: s_mov_b32 s13, s10
78 ; GFX11-NEXT: s_mov_b32 s12, s9
79 ; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
80 ; GFX11-NEXT: s_waitcnt vmcnt(0)
81 ; GFX11-NEXT: ; return to shader part epilog
82 main_body:
83 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
84 %r = bitcast <4 x i32> %v to <4 x float>
85 ret <4 x float> %r
86 }
88 ; Arguments are flattened to represent the actual VGPR_A layout, so we have no
89 ; extra moves in the generated kernel.
90 define amdgpu_ps <4 x float> @image_bvh64_intersect_ray(<2 x i32> %node_ptr_vec, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
91 ; GCN-LABEL: image_bvh64_intersect_ray:
92 ; GCN: ; %bb.0: ; %main_body
93 ; GCN-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3]
94 ; GCN-NEXT: s_waitcnt vmcnt(0)
95 ; GCN-NEXT: ; return to shader part epilog
96 main_body:
97 %node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
98 %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
99 %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
100 %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
101 %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
102 %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
103 %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
104 %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
105 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
106 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
107 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
108 %r = bitcast <4 x i32> %v to <4 x float>
109 ret <4 x float> %r
110 }
112 define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
113 ; GFX10-LABEL: image_bvh64_intersect_ray_a16:
114 ; GFX10: ; %bb.0: ; %main_body
115 ; GFX10-NEXT: s_mov_b32 s14, s12
116 ; GFX10-NEXT: s_mov_b32 s12, s10
117 ; GFX10-NEXT: s_lshr_b32 s10, s8, 16
118 ; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8
119 ; GFX10-NEXT: s_pack_ll_b32_b16 s8, s10, s9
120 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
121 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
122 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
123 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
124 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
125 ; GFX10-NEXT: v_mov_b32_e32 v5, s5
126 ; GFX10-NEXT: v_mov_b32_e32 v6, s6
127 ; GFX10-NEXT: v_mov_b32_e32 v7, s7
128 ; GFX10-NEXT: v_mov_b32_e32 v8, s8
129 ; GFX10-NEXT: s_mov_b32 s15, s13
130 ; GFX10-NEXT: s_mov_b32 s13, s11
131 ; GFX10-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[12:15] a16
132 ; GFX10-NEXT: s_waitcnt vmcnt(0)
133 ; GFX10-NEXT: ; return to shader part epilog
134 ;
135 ; GFX11-LABEL: image_bvh64_intersect_ray_a16:
136 ; GFX11: ; %bb.0: ; %main_body
137 ; GFX11-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s4
138 ; GFX11-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mov_b32 v7, s1
139 ; GFX11-NEXT: s_lshr_b32 s3, s6, 16
140 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s6, s8
141 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
142 ; GFX11-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v3, s1
143 ; GFX11-NEXT: s_lshr_b32 s0, s8, 16
144 ; GFX11-NEXT: v_mov_b32_e32 v8, s2
145 ; GFX11-NEXT: s_pack_ll_b32_b16 s0, s3, s0
146 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s7, s9
147 ; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s3
148 ; GFX11-NEXT: s_mov_b32 s15, s13
149 ; GFX11-NEXT: s_mov_b32 s14, s12
150 ; GFX11-NEXT: s_mov_b32 s13, s11
151 ; GFX11-NEXT: s_mov_b32 s12, s10
152 ; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
153 ; GFX11-NEXT: s_waitcnt vmcnt(0)
154 ; GFX11-NEXT: ; return to shader part epilog
155 main_body:
156 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
157 %r = bitcast <4 x i32> %v to <4 x float>
158 ret <4 x float> %r
159 }
161 ; TODO: NSA reassign is very limited and cannot work with VGPR tuples and subregs.
163 define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr, ptr %p_ray, <4 x i32> inreg %tdescr) {
164 ; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign:
165 ; GFX1013: ; %bb.0: ; %main_body
166 ; GFX1013-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x24
167 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
168 ; GFX1013-NEXT: v_mov_b32_e32 v6, 4.0
169 ; GFX1013-NEXT: v_mov_b32_e32 v7, 0x40a00000
170 ; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40c00000
171 ; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40e00000
172 ; GFX1013-NEXT: v_mov_b32_e32 v10, 0x41000000
173 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
174 ; GFX1013-NEXT: v_add_co_u32 v2, s0, s4, v0
175 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v3, s0, s5, 0, s0
176 ; GFX1013-NEXT: v_add_co_u32 v4, s0, s6, v0
177 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v5, s0, s7, 0, s0
178 ; GFX1013-NEXT: flat_load_dword v0, v[2:3]
179 ; GFX1013-NEXT: flat_load_dword v1, v[4:5]
180 ; GFX1013-NEXT: v_mov_b32_e32 v2, 0
181 ; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0
182 ; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0
183 ; GFX1013-NEXT: v_mov_b32_e32 v5, 0x40400000
184 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
185 ; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[8:11]
186 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
187 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
188 ; GFX1013-NEXT: s_endpgm
189 ;
190 ; GFX1030-LABEL: image_bvh_intersect_ray_nsa_reassign:
191 ; GFX1030: ; %bb.0: ; %main_body
192 ; GFX1030-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x24
193 ; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0
194 ; GFX1030-NEXT: v_mov_b32_e32 v10, 0x41000000
195 ; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40e00000
196 ; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40c00000
197 ; GFX1030-NEXT: v_mov_b32_e32 v7, 0x40a00000
198 ; GFX1030-NEXT: v_mov_b32_e32 v6, 4.0
199 ; GFX1030-NEXT: v_mov_b32_e32 v5, 0x40400000
200 ; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0
201 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
202 ; GFX1030-NEXT: v_add_co_u32 v0, s0, s0, v2
203 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
204 ; GFX1030-NEXT: v_add_co_u32 v2, s0, s2, v2
205 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0
206 ; GFX1030-NEXT: flat_load_dword v0, v[0:1]
207 ; GFX1030-NEXT: flat_load_dword v1, v[2:3]
208 ; GFX1030-NEXT: v_mov_b32_e32 v2, 0
209 ; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0
210 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
211 ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[4:7]
212 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
213 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
214 ; GFX1030-NEXT: s_endpgm
215 ;
216 ; GFX11-LABEL: image_bvh_intersect_ray_nsa_reassign:
217 ; GFX11: ; %bb.0: ; %main_body
218 ; GFX11-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
219 ; GFX11-NEXT: v_dual_mov_b32 v7, 1.0 :: v_dual_and_b32 v0, 0x3ff, v0
220 ; GFX11-NEXT: v_dual_mov_b32 v5, 0x40a00000 :: v_dual_mov_b32 v6, 0
221 ; GFX11-NEXT: v_mov_b32_e32 v8, 2.0
222 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
223 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
224 ; GFX11-NEXT: v_mov_b32_e32 v4, 4.0
225 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
226 ; GFX11-NEXT: v_add_co_u32 v0, s0, s0, v2
227 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
228 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
229 ; GFX11-NEXT: v_add_co_u32 v2, s0, s2, v2
230 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0
231 ; GFX11-NEXT: flat_load_b32 v9, v[0:1]
232 ; GFX11-NEXT: flat_load_b32 v10, v[2:3]
233 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x40e00000
234 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x40c00000
235 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x41000000
236 ; GFX11-NEXT: v_mov_b32_e32 v3, 0x40400000
237 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
238 ; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v9, v10, v[6:8], v[3:5], v[0:2]], s[4:7]
239 ; GFX11-NEXT: s_waitcnt vmcnt(0)
240 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
241 ; GFX11-NEXT: s_endpgm
242 main_body:
243 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
244 %gep_node_ptr = getelementptr inbounds i32, ptr %p_node_ptr, i32 %lid
245 %node_ptr = load i32, ptr %gep_node_ptr, align 4
246 %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
247 %ray_extent = load float, ptr %gep_ray, align 4
248 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
249 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
250 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
251 %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
252 %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
253 %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
254 %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
255 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
256 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
257 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
258 store <4 x i32> %v, ptr undef
259 ret void
260 }
262 define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_ptr, ptr %p_ray, <4 x i32> inreg %tdescr) {
263 ; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
264 ; GFX1013: ; %bb.0: ; %main_body
265 ; GFX1013-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x24
266 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
267 ; GFX1013-NEXT: v_mov_b32_e32 v6, 0x46004500
268 ; GFX1013-NEXT: v_mov_b32_e32 v7, 0x48004700
269 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
270 ; GFX1013-NEXT: v_add_co_u32 v2, s0, s4, v0
271 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v3, s0, s5, 0, s0
272 ; GFX1013-NEXT: v_add_co_u32 v4, s0, s6, v0
273 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v5, s0, s7, 0, s0
274 ; GFX1013-NEXT: flat_load_dword v0, v[2:3]
275 ; GFX1013-NEXT: flat_load_dword v1, v[4:5]
276 ; GFX1013-NEXT: v_mov_b32_e32 v2, 0
277 ; GFX1013-NEXT: v_mov_b32_e32 v3, 1.0
278 ; GFX1013-NEXT: v_mov_b32_e32 v4, 2.0
279 ; GFX1013-NEXT: v_mov_b32_e32 v5, 0x44004200
280 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
281 ; GFX1013-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[8:11] a16
282 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
283 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
284 ; GFX1013-NEXT: s_endpgm
285 ;
286 ; GFX1030-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
287 ; GFX1030: ; %bb.0: ; %main_body
288 ; GFX1030-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x24
289 ; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 2, v0
290 ; GFX1030-NEXT: v_mov_b32_e32 v4, 2.0
291 ; GFX1030-NEXT: v_mov_b32_e32 v5, 0x44004200
292 ; GFX1030-NEXT: v_mov_b32_e32 v6, 0x46004500
293 ; GFX1030-NEXT: v_mov_b32_e32 v7, 0x48004700
294 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
295 ; GFX1030-NEXT: v_add_co_u32 v0, s0, s0, v2
296 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
297 ; GFX1030-NEXT: v_add_co_u32 v2, s0, s2, v2
298 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0
299 ; GFX1030-NEXT: flat_load_dword v0, v[0:1]
300 ; GFX1030-NEXT: flat_load_dword v1, v[2:3]
301 ; GFX1030-NEXT: v_mov_b32_e32 v2, 0
302 ; GFX1030-NEXT: v_mov_b32_e32 v3, 1.0
303 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
304 ; GFX1030-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[4:7] a16
305 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
306 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
307 ; GFX1030-NEXT: s_endpgm
308 ;
309 ; GFX11-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
310 ; GFX11: ; %bb.0: ; %main_body
311 ; GFX11-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
312 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
313 ; GFX11-NEXT: v_dual_mov_b32 v4, 1.0 :: v_dual_mov_b32 v5, 2.0
314 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
315 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
316 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
317 ; GFX11-NEXT: v_add_co_u32 v0, s0, s0, v2
318 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
319 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
320 ; GFX11-NEXT: v_add_co_u32 v2, s0, s2, v2
321 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s0
322 ; GFX11-NEXT: flat_load_b32 v6, v[0:1]
323 ; GFX11-NEXT: flat_load_b32 v7, v[2:3]
324 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x47004400
325 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x46004200
326 ; GFX11-NEXT: v_dual_mov_b32 v2, 0x48004500 :: v_dual_mov_b32 v3, 0
327 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
328 ; GFX11-NEXT: image_bvh_intersect_ray v[0:3], [v6, v7, v[3:5], v[0:2]], s[4:7] a16
329 ; GFX11-NEXT: s_waitcnt vmcnt(0)
330 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
331 ; GFX11-NEXT: s_endpgm
332 main_body:
333 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
334 %gep_node_ptr = getelementptr inbounds i32, ptr %p_node_ptr, i32 %lid
335 %node_ptr = load i32, ptr %gep_node_ptr, align 4
336 %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
337 %ray_extent = load float, ptr %gep_ray, align 4
338 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
339 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
340 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
341 %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
342 %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
343 %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
344 %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
345 %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
346 %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
347 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
348 store <4 x i32> %v, ptr undef
349 ret void
350 }
352 define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4 x i32> inreg %tdescr) {
353 ; GFX1013-LABEL: image_bvh64_intersect_ray_nsa_reassign:
354 ; GFX1013: ; %bb.0: ; %main_body
355 ; GFX1013-NEXT: s_clause 0x1
356 ; GFX1013-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
357 ; GFX1013-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34
358 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
359 ; GFX1013-NEXT: v_mov_b32_e32 v3, 0
360 ; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0
361 ; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0
362 ; GFX1013-NEXT: v_mov_b32_e32 v6, 0x40400000
363 ; GFX1013-NEXT: v_mov_b32_e32 v7, 4.0
364 ; GFX1013-NEXT: v_mov_b32_e32 v8, 0x40a00000
365 ; GFX1013-NEXT: v_mov_b32_e32 v9, 0x40c00000
366 ; GFX1013-NEXT: v_mov_b32_e32 v10, 0x40e00000
367 ; GFX1013-NEXT: v_mov_b32_e32 v11, 0x41000000
368 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
369 ; GFX1013-NEXT: v_add_co_u32 v0, s0, s0, v0
370 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
371 ; GFX1013-NEXT: flat_load_dword v2, v[0:1]
372 ; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c7
373 ; GFX1013-NEXT: v_bfrev_b32_e32 v1, 4.0
374 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
375 ; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[4:7]
376 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
377 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
378 ; GFX1013-NEXT: s_endpgm
379 ;
380 ; GFX1030-LABEL: image_bvh64_intersect_ray_nsa_reassign:
381 ; GFX1030: ; %bb.0: ; %main_body
382 ; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x24
383 ; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 2, v0
384 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x34
385 ; GFX1030-NEXT: v_mov_b32_e32 v3, 0
386 ; GFX1030-NEXT: v_mov_b32_e32 v11, 0x41000000
387 ; GFX1030-NEXT: v_mov_b32_e32 v10, 0x40e00000
388 ; GFX1030-NEXT: v_mov_b32_e32 v9, 0x40c00000
389 ; GFX1030-NEXT: v_mov_b32_e32 v8, 0x40a00000
390 ; GFX1030-NEXT: v_mov_b32_e32 v7, 4.0
391 ; GFX1030-NEXT: v_mov_b32_e32 v6, 0x40400000
392 ; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0
393 ; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0
394 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
395 ; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v0
396 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
397 ; GFX1030-NEXT: flat_load_dword v2, v[0:1]
398 ; GFX1030-NEXT: v_bfrev_b32_e32 v1, 4.0
399 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c7
400 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
401 ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3]
402 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
403 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
404 ; GFX1030-NEXT: s_endpgm
405 ;
406 ; GFX11-LABEL: image_bvh64_intersect_ray_nsa_reassign:
407 ; GFX11: ; %bb.0: ; %main_body
408 ; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x24
409 ; GFX11-NEXT: v_dual_mov_b32 v7, 1.0 :: v_dual_and_b32 v0, 0x3ff, v0
410 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x34
411 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x41000000
412 ; GFX11-NEXT: v_dual_mov_b32 v3, 0x40400000 :: v_dual_mov_b32 v4, 4.0
413 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
414 ; GFX11-NEXT: v_dual_mov_b32 v5, 0x40a00000 :: v_dual_lshlrev_b32 v0, 2, v0
415 ; GFX11-NEXT: v_mov_b32_e32 v6, 0
416 ; GFX11-NEXT: v_dual_mov_b32 v8, 2.0 :: v_dual_mov_b32 v9, 0xb36211c7
417 ; GFX11-NEXT: v_bfrev_b32_e32 v10, 4.0
418 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
419 ; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v0
420 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
421 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
422 ; GFX11-NEXT: flat_load_b32 v11, v[0:1]
423 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x40c00000
424 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x40e00000
425 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
426 ; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[6:8], v[3:5], v[0:2]], s[0:3]
427 ; GFX11-NEXT: s_waitcnt vmcnt(0)
428 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
429 ; GFX11-NEXT: s_endpgm
430 main_body:
431 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
432 %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
433 %ray_extent = load float, ptr %gep_ray, align 4
434 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
435 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
436 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
437 %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
438 %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
439 %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
440 %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
441 %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
442 %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
443 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
444 store <4 x i32> %v, ptr undef
445 ret void
446 }
448 define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray, <4 x i32> inreg %tdescr) {
449 ; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
450 ; GFX1013: ; %bb.0: ; %main_body
451 ; GFX1013-NEXT: s_clause 0x1
452 ; GFX1013-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
453 ; GFX1013-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34
454 ; GFX1013-NEXT: v_lshlrev_b32_e32 v0, 2, v0
455 ; GFX1013-NEXT: v_mov_b32_e32 v3, 0
456 ; GFX1013-NEXT: v_mov_b32_e32 v4, 1.0
457 ; GFX1013-NEXT: v_mov_b32_e32 v5, 2.0
458 ; GFX1013-NEXT: v_mov_b32_e32 v6, 0x44004200
459 ; GFX1013-NEXT: v_mov_b32_e32 v7, 0x46004500
460 ; GFX1013-NEXT: v_mov_b32_e32 v8, 0x48004700
461 ; GFX1013-NEXT: s_waitcnt lgkmcnt(0)
462 ; GFX1013-NEXT: v_add_co_u32 v0, s0, s0, v0
463 ; GFX1013-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
464 ; GFX1013-NEXT: flat_load_dword v2, v[0:1]
465 ; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c6
466 ; GFX1013-NEXT: v_bfrev_b32_e32 v1, 4.0
467 ; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
468 ; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[4:7] a16
469 ; GFX1013-NEXT: s_waitcnt vmcnt(0)
470 ; GFX1013-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
471 ; GFX1013-NEXT: s_endpgm
472 ;
473 ; GFX1030-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
474 ; GFX1030: ; %bb.0: ; %main_body
475 ; GFX1030-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x24
476 ; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 2, v0
477 ; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x34
478 ; GFX1030-NEXT: v_mov_b32_e32 v3, 0
479 ; GFX1030-NEXT: v_mov_b32_e32 v5, 2.0
480 ; GFX1030-NEXT: v_mov_b32_e32 v4, 1.0
481 ; GFX1030-NEXT: v_mov_b32_e32 v6, 0x44004200
482 ; GFX1030-NEXT: v_mov_b32_e32 v7, 0x46004500
483 ; GFX1030-NEXT: v_mov_b32_e32 v8, 0x48004700
484 ; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
485 ; GFX1030-NEXT: v_add_co_u32 v0, s4, s4, v0
486 ; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
487 ; GFX1030-NEXT: flat_load_dword v2, v[0:1]
488 ; GFX1030-NEXT: v_bfrev_b32_e32 v1, 4.0
489 ; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c6
490 ; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
491 ; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
492 ; GFX1030-NEXT: s_waitcnt vmcnt(0)
493 ; GFX1030-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
494 ; GFX1030-NEXT: s_endpgm
495 ;
496 ; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
497 ; GFX11: ; %bb.0: ; %main_body
498 ; GFX11-NEXT: s_load_b64 s[4:5], s[2:3], 0x24
499 ; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
500 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x34
501 ; GFX11-NEXT: v_mov_b32_e32 v2, 0x48004500
502 ; GFX11-NEXT: v_mov_b32_e32 v4, 1.0
503 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
504 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
505 ; GFX11-NEXT: v_mov_b32_e32 v6, 0xb36211c6
506 ; GFX11-NEXT: v_bfrev_b32_e32 v7, 4.0
507 ; GFX11-NEXT: v_mov_b32_e32 v5, 2.0
508 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
509 ; GFX11-NEXT: v_add_co_u32 v0, s4, s4, v0
510 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
511 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s5, 0, s4
512 ; GFX11-NEXT: flat_load_b32 v8, v[0:1]
513 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x47004400
514 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x46004200
515 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
516 ; GFX11-NEXT: image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[3:5], v[0:2]], s[0:3] a16
517 ; GFX11-NEXT: s_waitcnt vmcnt(0)
518 ; GFX11-NEXT: flat_store_b128 v[0:1], v[0:3]
519 ; GFX11-NEXT: s_endpgm
520 main_body:
521 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
522 %gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
523 %ray_extent = load float, ptr %gep_ray, align 4
524 %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
525 %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
526 %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
527 %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
528 %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
529 %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
530 %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
531 %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
532 %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
533 %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
534 store <4 x i32> %v, ptr undef
535 ret void
536 }
538 declare i32 @llvm.amdgcn.workitem.id.x()