| blob | e7b17c30cf7535cf2731619d2112cf911febb16b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX6 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX8 %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX9 %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX11 %s
6 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s
8 define amdgpu_kernel void @round_f32(ptr addrspace(1) %out, float %x) #0 {
9 ; GFX6-LABEL: round_f32:
10 ; GFX6: ; %bb.0:
11 ; GFX6-NEXT: s_load_dword s6, s[2:3], 0xb
12 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
13 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
14 ; GFX6-NEXT: s_mov_b32 s2, -1
15 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
16 ; GFX6-NEXT: v_trunc_f32_e32 v0, s6
17 ; GFX6-NEXT: v_sub_f32_e32 v1, s6, v0
18 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, 0.5
19 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[4:5]
20 ; GFX6-NEXT: s_brev_b32 s4, -2
21 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
22 ; GFX6-NEXT: v_bfi_b32 v1, s4, v1, v2
23 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
24 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
25 ; GFX6-NEXT: s_endpgm
26 ;
27 ; GFX8-LABEL: round_f32:
28 ; GFX8: ; %bb.0:
29 ; GFX8-NEXT: s_load_dword s6, s[2:3], 0x2c
30 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
31 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
32 ; GFX8-NEXT: s_mov_b32 s2, -1
33 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
34 ; GFX8-NEXT: v_trunc_f32_e32 v0, s6
35 ; GFX8-NEXT: v_sub_f32_e32 v1, s6, v0
36 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, 0.5
37 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[4:5]
38 ; GFX8-NEXT: s_brev_b32 s4, -2
39 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
40 ; GFX8-NEXT: v_bfi_b32 v1, s4, v1, v2
41 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
42 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
43 ; GFX8-NEXT: s_endpgm
44 ;
45 ; GFX9-LABEL: round_f32:
46 ; GFX9: ; %bb.0:
47 ; GFX9-NEXT: s_load_dword s6, s[2:3], 0x2c
48 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
49 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
50 ; GFX9-NEXT: s_mov_b32 s2, -1
51 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
52 ; GFX9-NEXT: v_trunc_f32_e32 v0, s6
53 ; GFX9-NEXT: v_sub_f32_e32 v1, s6, v0
54 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, 0.5
55 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[4:5]
56 ; GFX9-NEXT: s_brev_b32 s4, -2
57 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
58 ; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v2
59 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
60 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
61 ; GFX9-NEXT: s_endpgm
62 ;
63 ; GFX11-LABEL: round_f32:
64 ; GFX11: ; %bb.0:
65 ; GFX11-NEXT: s_clause 0x1
66 ; GFX11-NEXT: s_load_b32 s4, s[2:3], 0x2c
67 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
68 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
69 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
70 ; GFX11-NEXT: v_trunc_f32_e32 v0, s4
71 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
72 ; GFX11-NEXT: v_sub_f32_e32 v1, s4, v0
73 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v1|, 0.5
74 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
75 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s2
76 ; GFX11-NEXT: s_mov_b32 s2, -1
77 ; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s4
78 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
79 ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
80 ; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
81 ; GFX11-NEXT: s_nop 0
82 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
83 ; GFX11-NEXT: s_endpgm
84 ;
85 ; R600-LABEL: round_f32:
86 ; R600: ; %bb.0:
87 ; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
88 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
89 ; R600-NEXT: CF_END
90 ; R600-NEXT: PAD
91 ; R600-NEXT: ALU clause starting at 4:
92 ; R600-NEXT: TRUNC * T0.W, KC0[2].Z,
93 ; R600-NEXT: ADD * T1.W, KC0[2].Z, -PV.W,
94 ; R600-NEXT: SETGE * T1.W, |PV.W|, 0.5,
95 ; R600-NEXT: BFI_INT * T1.W, literal.x, PV.W, KC0[2].Z,
96 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
97 ; R600-NEXT: ADD T0.X, T0.W, PV.W,
98 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
99 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
100 %result = call float @llvm.round.f32(float %x) #1
101 store float %result, ptr addrspace(1) %out
102 ret void
103 }
105 ; The vector tests are really difficult to verify, since it can be hard to
106 ; predict how the scheduler will order the instructions. We already have
107 ; a test for the scalar case, so the vector tests just check that the
108 ; compiler doesn't crash.
109 define amdgpu_kernel void @round_v2f32(ptr addrspace(1) %out, <2 x float> %in) #0 {
110 ; GFX6-LABEL: round_v2f32:
111 ; GFX6: ; %bb.0:
112 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
113 ; GFX6-NEXT: s_brev_b32 s8, -2
114 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
115 ; GFX6-NEXT: s_mov_b32 s6, -1
116 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
117 ; GFX6-NEXT: v_trunc_f32_e32 v0, s3
118 ; GFX6-NEXT: v_sub_f32_e32 v1, s3, v0
119 ; GFX6-NEXT: s_mov_b32 s4, s0
120 ; GFX6-NEXT: s_mov_b32 s5, s1
121 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
122 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
123 ; GFX6-NEXT: v_mov_b32_e32 v2, s3
124 ; GFX6-NEXT: v_bfi_b32 v1, s8, v1, v2
125 ; GFX6-NEXT: v_add_f32_e32 v1, v0, v1
126 ; GFX6-NEXT: v_trunc_f32_e32 v0, s2
127 ; GFX6-NEXT: v_sub_f32_e32 v2, s2, v0
128 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, 0.5
129 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[0:1]
130 ; GFX6-NEXT: v_mov_b32_e32 v3, s2
131 ; GFX6-NEXT: v_bfi_b32 v2, s8, v2, v3
132 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v2
133 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
134 ; GFX6-NEXT: s_endpgm
135 ;
136 ; GFX8-LABEL: round_v2f32:
137 ; GFX8: ; %bb.0:
138 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
139 ; GFX8-NEXT: s_brev_b32 s8, -2
140 ; GFX8-NEXT: s_mov_b32 s7, 0xf000
141 ; GFX8-NEXT: s_mov_b32 s6, -1
142 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
143 ; GFX8-NEXT: v_trunc_f32_e32 v0, s3
144 ; GFX8-NEXT: v_sub_f32_e32 v1, s3, v0
145 ; GFX8-NEXT: s_mov_b32 s4, s0
146 ; GFX8-NEXT: s_mov_b32 s5, s1
147 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
148 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
149 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
150 ; GFX8-NEXT: v_bfi_b32 v1, s8, v1, v2
151 ; GFX8-NEXT: v_add_f32_e32 v1, v0, v1
152 ; GFX8-NEXT: v_trunc_f32_e32 v0, s2
153 ; GFX8-NEXT: v_sub_f32_e32 v2, s2, v0
154 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, 0.5
155 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[0:1]
156 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
157 ; GFX8-NEXT: v_bfi_b32 v2, s8, v2, v3
158 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
159 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
160 ; GFX8-NEXT: s_endpgm
161 ;
162 ; GFX9-LABEL: round_v2f32:
163 ; GFX9: ; %bb.0:
164 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
165 ; GFX9-NEXT: s_brev_b32 s8, -2
166 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
167 ; GFX9-NEXT: s_mov_b32 s2, -1
168 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
169 ; GFX9-NEXT: v_trunc_f32_e32 v0, s7
170 ; GFX9-NEXT: v_sub_f32_e32 v1, s7, v0
171 ; GFX9-NEXT: s_mov_b32 s0, s4
172 ; GFX9-NEXT: s_mov_b32 s1, s5
173 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, 0.5
174 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[4:5]
175 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
176 ; GFX9-NEXT: v_bfi_b32 v1, s8, v1, v2
177 ; GFX9-NEXT: v_add_f32_e32 v1, v0, v1
178 ; GFX9-NEXT: v_trunc_f32_e32 v0, s6
179 ; GFX9-NEXT: v_sub_f32_e32 v2, s6, v0
180 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
181 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
182 ; GFX9-NEXT: v_mov_b32_e32 v3, s6
183 ; GFX9-NEXT: v_bfi_b32 v2, s8, v2, v3
184 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v2
185 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
186 ; GFX9-NEXT: s_endpgm
187 ;
188 ; GFX11-LABEL: round_v2f32:
189 ; GFX11: ; %bb.0:
190 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
191 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
192 ; GFX11-NEXT: v_trunc_f32_e32 v0, s3
193 ; GFX11-NEXT: v_trunc_f32_e32 v2, s2
194 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
195 ; GFX11-NEXT: v_sub_f32_e32 v1, s3, v0
196 ; GFX11-NEXT: v_sub_f32_e32 v3, s2, v2
197 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
198 ; GFX11-NEXT: v_cmp_ge_f32_e64 s4, |v1|, 0.5
199 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s4
200 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
201 ; GFX11-NEXT: v_cmp_ge_f32_e64 s4, |v3|, 0.5
202 ; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s3
203 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
204 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s4
205 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
206 ; GFX11-NEXT: v_add_f32_e32 v1, v0, v1
207 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
208 ; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s2
209 ; GFX11-NEXT: s_mov_b32 s2, -1
210 ; GFX11-NEXT: v_add_f32_e32 v0, v2, v3
211 ; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
212 ; GFX11-NEXT: s_nop 0
213 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
214 ; GFX11-NEXT: s_endpgm
215 ;
216 ; R600-LABEL: round_v2f32:
217 ; R600: ; %bb.0:
218 ; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
219 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
220 ; R600-NEXT: CF_END
221 ; R600-NEXT: PAD
222 ; R600-NEXT: ALU clause starting at 4:
223 ; R600-NEXT: TRUNC * T0.W, KC0[3].X,
224 ; R600-NEXT: ADD T1.W, KC0[3].X, -PV.W,
225 ; R600-NEXT: TRUNC * T2.W, KC0[2].W,
226 ; R600-NEXT: ADD T3.W, KC0[2].W, -PS,
227 ; R600-NEXT: SETGE * T1.W, |PV.W|, 0.5,
228 ; R600-NEXT: BFI_INT T1.W, literal.x, PS, KC0[3].X,
229 ; R600-NEXT: SETGE * T3.W, |PV.W|, 0.5,
230 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
231 ; R600-NEXT: ADD T0.Y, T0.W, PV.W,
232 ; R600-NEXT: BFI_INT * T0.W, literal.x, PS, KC0[2].W,
233 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
234 ; R600-NEXT: ADD T0.X, T2.W, PV.W,
235 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
236 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
237 %result = call <2 x float> @llvm.round.v2f32(<2 x float> %in) #1
238 store <2 x float> %result, ptr addrspace(1) %out
239 ret void
240 }
242 define amdgpu_kernel void @round_v4f32(ptr addrspace(1) %out, <4 x float> %in) #0 {
243 ; GFX6-LABEL: round_v4f32:
244 ; GFX6: ; %bb.0:
245 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0xd
246 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
247 ; GFX6-NEXT: s_brev_b32 s10, -2
248 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
249 ; GFX6-NEXT: s_mov_b32 s2, -1
250 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
251 ; GFX6-NEXT: v_trunc_f32_e32 v0, s7
252 ; GFX6-NEXT: v_sub_f32_e32 v1, s7, v0
253 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
254 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
255 ; GFX6-NEXT: v_mov_b32_e32 v2, s7
256 ; GFX6-NEXT: v_bfi_b32 v1, s10, v1, v2
257 ; GFX6-NEXT: v_add_f32_e32 v3, v0, v1
258 ; GFX6-NEXT: v_trunc_f32_e32 v0, s6
259 ; GFX6-NEXT: v_sub_f32_e32 v1, s6, v0
260 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
261 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
262 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
263 ; GFX6-NEXT: v_bfi_b32 v1, s10, v1, v2
264 ; GFX6-NEXT: v_add_f32_e32 v2, v0, v1
265 ; GFX6-NEXT: v_trunc_f32_e32 v0, s5
266 ; GFX6-NEXT: v_sub_f32_e32 v1, s5, v0
267 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, 0.5
268 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[6:7]
269 ; GFX6-NEXT: v_mov_b32_e32 v4, s5
270 ; GFX6-NEXT: v_bfi_b32 v1, s10, v1, v4
271 ; GFX6-NEXT: v_add_f32_e32 v1, v0, v1
272 ; GFX6-NEXT: v_trunc_f32_e32 v0, s4
273 ; GFX6-NEXT: v_sub_f32_e32 v4, s4, v0
274 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[6:7], |v4|, 0.5
275 ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[6:7]
276 ; GFX6-NEXT: v_mov_b32_e32 v5, s4
277 ; GFX6-NEXT: v_bfi_b32 v4, s10, v4, v5
278 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v4
279 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
280 ; GFX6-NEXT: s_endpgm
281 ;
282 ; GFX8-LABEL: round_v4f32:
283 ; GFX8: ; %bb.0:
284 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34
285 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
286 ; GFX8-NEXT: s_brev_b32 s10, -2
287 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
288 ; GFX8-NEXT: s_mov_b32 s2, -1
289 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
290 ; GFX8-NEXT: v_trunc_f32_e32 v0, s7
291 ; GFX8-NEXT: v_sub_f32_e32 v1, s7, v0
292 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
293 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
294 ; GFX8-NEXT: v_mov_b32_e32 v2, s7
295 ; GFX8-NEXT: v_bfi_b32 v1, s10, v1, v2
296 ; GFX8-NEXT: v_add_f32_e32 v3, v0, v1
297 ; GFX8-NEXT: v_trunc_f32_e32 v0, s6
298 ; GFX8-NEXT: v_sub_f32_e32 v1, s6, v0
299 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
300 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
301 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
302 ; GFX8-NEXT: v_bfi_b32 v1, s10, v1, v2
303 ; GFX8-NEXT: v_add_f32_e32 v2, v0, v1
304 ; GFX8-NEXT: v_trunc_f32_e32 v0, s5
305 ; GFX8-NEXT: v_sub_f32_e32 v1, s5, v0
306 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, 0.5
307 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[6:7]
308 ; GFX8-NEXT: v_mov_b32_e32 v4, s5
309 ; GFX8-NEXT: v_bfi_b32 v1, s10, v1, v4
310 ; GFX8-NEXT: v_add_f32_e32 v1, v0, v1
311 ; GFX8-NEXT: v_trunc_f32_e32 v0, s4
312 ; GFX8-NEXT: v_sub_f32_e32 v4, s4, v0
313 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[6:7], |v4|, 0.5
314 ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[6:7]
315 ; GFX8-NEXT: v_mov_b32_e32 v5, s4
316 ; GFX8-NEXT: v_bfi_b32 v4, s10, v4, v5
317 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v4
318 ; GFX8-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
319 ; GFX8-NEXT: s_endpgm
320 ;
321 ; GFX9-LABEL: round_v4f32:
322 ; GFX9: ; %bb.0:
323 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34
324 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
325 ; GFX9-NEXT: s_brev_b32 s10, -2
326 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
327 ; GFX9-NEXT: s_mov_b32 s2, -1
328 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
329 ; GFX9-NEXT: v_trunc_f32_e32 v0, s7
330 ; GFX9-NEXT: v_sub_f32_e32 v1, s7, v0
331 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
332 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
333 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
334 ; GFX9-NEXT: v_bfi_b32 v1, s10, v1, v2
335 ; GFX9-NEXT: v_add_f32_e32 v3, v0, v1
336 ; GFX9-NEXT: v_trunc_f32_e32 v0, s6
337 ; GFX9-NEXT: v_sub_f32_e32 v1, s6, v0
338 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
339 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
340 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
341 ; GFX9-NEXT: v_bfi_b32 v1, s10, v1, v2
342 ; GFX9-NEXT: v_add_f32_e32 v2, v0, v1
343 ; GFX9-NEXT: v_trunc_f32_e32 v0, s5
344 ; GFX9-NEXT: v_sub_f32_e32 v1, s5, v0
345 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, 0.5
346 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[6:7]
347 ; GFX9-NEXT: v_mov_b32_e32 v4, s5
348 ; GFX9-NEXT: v_bfi_b32 v1, s10, v1, v4
349 ; GFX9-NEXT: v_add_f32_e32 v1, v0, v1
350 ; GFX9-NEXT: v_trunc_f32_e32 v0, s4
351 ; GFX9-NEXT: v_sub_f32_e32 v4, s4, v0
352 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[6:7], |v4|, 0.5
353 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[6:7]
354 ; GFX9-NEXT: v_mov_b32_e32 v5, s4
355 ; GFX9-NEXT: v_bfi_b32 v4, s10, v4, v5
356 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v4
357 ; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
358 ; GFX9-NEXT: s_endpgm
359 ;
360 ; GFX11-LABEL: round_v4f32:
361 ; GFX11: ; %bb.0:
362 ; GFX11-NEXT: s_clause 0x1
363 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x34
364 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
365 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
366 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
367 ; GFX11-NEXT: v_trunc_f32_e32 v0, s7
368 ; GFX11-NEXT: v_trunc_f32_e32 v1, s6
369 ; GFX11-NEXT: v_trunc_f32_e32 v4, s5
370 ; GFX11-NEXT: v_trunc_f32_e32 v5, s4
371 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
372 ; GFX11-NEXT: v_dual_sub_f32 v2, s7, v0 :: v_dual_sub_f32 v3, s6, v1
373 ; GFX11-NEXT: v_dual_sub_f32 v6, s5, v4 :: v_dual_sub_f32 v7, s4, v5
374 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
375 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v2|, 0.5
376 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s2
377 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
378 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v3|, 0.5
379 ; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s7
380 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
381 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s2
382 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v6|, 0.5
383 ; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v3, s6
384 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
385 ; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1.0, s2
386 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v7|, 0.5
387 ; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v8
388 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
389 ; GFX11-NEXT: v_bfi_b32 v6, 0x7fffffff, v6, s5
390 ; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s2
391 ; GFX11-NEXT: s_mov_b32 s2, -1
392 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
393 ; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s4
394 ; GFX11-NEXT: v_dual_add_f32 v1, v4, v6 :: v_dual_add_f32 v0, v5, v7
395 ; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
396 ; GFX11-NEXT: s_nop 0
397 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
398 ; GFX11-NEXT: s_endpgm
399 ;
400 ; R600-LABEL: round_v4f32:
401 ; R600: ; %bb.0:
402 ; R600-NEXT: ALU 25, @4, KC0[CB0:0-32], KC1[]
403 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1
404 ; R600-NEXT: CF_END
405 ; R600-NEXT: PAD
406 ; R600-NEXT: ALU clause starting at 4:
407 ; R600-NEXT: TRUNC * T0.W, KC0[4].X,
408 ; R600-NEXT: ADD T1.W, KC0[4].X, -PV.W,
409 ; R600-NEXT: TRUNC * T2.W, KC0[3].W,
410 ; R600-NEXT: TRUNC T0.Z, KC0[3].Z,
411 ; R600-NEXT: ADD T3.W, KC0[3].W, -PS,
412 ; R600-NEXT: SETGE * T1.W, |PV.W|, 0.5,
413 ; R600-NEXT: BFI_INT T0.Y, literal.x, PS, KC0[4].X,
414 ; R600-NEXT: SETGE T1.Z, |PV.W|, 0.5,
415 ; R600-NEXT: ADD * T1.W, KC0[3].Z, -PV.Z,
416 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
417 ; R600-NEXT: TRUNC * T3.W, KC0[3].Y,
418 ; R600-NEXT: ADD T1.Y, KC0[3].Y, -PV.W,
419 ; R600-NEXT: SETGE T2.Z, |T1.W|, 0.5,
420 ; R600-NEXT: BFI_INT T1.W, literal.x, T1.Z, KC0[3].W,
421 ; R600-NEXT: ADD * T4.W, T0.W, T0.Y,
422 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
423 ; R600-NEXT: ADD T4.Z, T2.W, PV.W,
424 ; R600-NEXT: BFI_INT T0.W, literal.x, PV.Z, KC0[3].Z,
425 ; R600-NEXT: SETGE * T1.W, |PV.Y|, 0.5,
426 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
427 ; R600-NEXT: ADD T4.Y, T0.Z, PV.W,
428 ; R600-NEXT: BFI_INT * T0.W, literal.x, PS, KC0[3].Y,
429 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
430 ; R600-NEXT: ADD T4.X, T3.W, PV.W,
431 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
432 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
433 %result = call <4 x float> @llvm.round.v4f32(<4 x float> %in) #1
434 store <4 x float> %result, ptr addrspace(1) %out
435 ret void
436 }
438 define amdgpu_kernel void @round_v8f32(ptr addrspace(1) %out, <8 x float> %in) #0 {
439 ; GFX6-LABEL: round_v8f32:
440 ; GFX6: ; %bb.0:
441 ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x11
442 ; GFX6-NEXT: s_load_dwordx2 s[12:13], s[2:3], 0x9
443 ; GFX6-NEXT: s_brev_b32 s2, -2
444 ; GFX6-NEXT: s_mov_b32 s15, 0xf000
445 ; GFX6-NEXT: s_mov_b32 s14, -1
446 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
447 ; GFX6-NEXT: v_trunc_f32_e32 v0, s7
448 ; GFX6-NEXT: v_sub_f32_e32 v1, s7, v0
449 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
450 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
451 ; GFX6-NEXT: v_mov_b32_e32 v2, s7
452 ; GFX6-NEXT: v_bfi_b32 v1, s2, v1, v2
453 ; GFX6-NEXT: v_add_f32_e32 v3, v0, v1
454 ; GFX6-NEXT: v_trunc_f32_e32 v0, s6
455 ; GFX6-NEXT: v_sub_f32_e32 v1, s6, v0
456 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
457 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
458 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
459 ; GFX6-NEXT: v_bfi_b32 v1, s2, v1, v2
460 ; GFX6-NEXT: v_add_f32_e32 v2, v0, v1
461 ; GFX6-NEXT: v_trunc_f32_e32 v0, s5
462 ; GFX6-NEXT: v_sub_f32_e32 v1, s5, v0
463 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
464 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
465 ; GFX6-NEXT: v_mov_b32_e32 v4, s5
466 ; GFX6-NEXT: v_bfi_b32 v1, s2, v1, v4
467 ; GFX6-NEXT: v_add_f32_e32 v1, v0, v1
468 ; GFX6-NEXT: v_trunc_f32_e32 v0, s4
469 ; GFX6-NEXT: v_sub_f32_e32 v4, s4, v0
470 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
471 ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
472 ; GFX6-NEXT: v_mov_b32_e32 v5, s4
473 ; GFX6-NEXT: v_bfi_b32 v4, s2, v4, v5
474 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v4
475 ; GFX6-NEXT: v_trunc_f32_e32 v4, s11
476 ; GFX6-NEXT: v_sub_f32_e32 v5, s11, v4
477 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
478 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
479 ; GFX6-NEXT: v_mov_b32_e32 v6, s11
480 ; GFX6-NEXT: v_bfi_b32 v5, s2, v5, v6
481 ; GFX6-NEXT: v_add_f32_e32 v7, v4, v5
482 ; GFX6-NEXT: v_trunc_f32_e32 v4, s10
483 ; GFX6-NEXT: v_sub_f32_e32 v5, s10, v4
484 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
485 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
486 ; GFX6-NEXT: v_mov_b32_e32 v6, s10
487 ; GFX6-NEXT: v_bfi_b32 v5, s2, v5, v6
488 ; GFX6-NEXT: v_add_f32_e32 v6, v4, v5
489 ; GFX6-NEXT: v_trunc_f32_e32 v4, s9
490 ; GFX6-NEXT: v_sub_f32_e32 v5, s9, v4
491 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
492 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
493 ; GFX6-NEXT: v_mov_b32_e32 v8, s9
494 ; GFX6-NEXT: v_bfi_b32 v5, s2, v5, v8
495 ; GFX6-NEXT: v_add_f32_e32 v5, v4, v5
496 ; GFX6-NEXT: v_trunc_f32_e32 v4, s8
497 ; GFX6-NEXT: v_sub_f32_e32 v8, s8, v4
498 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, 0.5
499 ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1.0, s[0:1]
500 ; GFX6-NEXT: v_mov_b32_e32 v9, s8
501 ; GFX6-NEXT: v_bfi_b32 v8, s2, v8, v9
502 ; GFX6-NEXT: v_add_f32_e32 v4, v4, v8
503 ; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16
504 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
505 ; GFX6-NEXT: s_endpgm
506 ;
507 ; GFX8-LABEL: round_v8f32:
508 ; GFX8: ; %bb.0:
509 ; GFX8-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x44
510 ; GFX8-NEXT: s_load_dwordx2 s[12:13], s[2:3], 0x24
511 ; GFX8-NEXT: s_brev_b32 s2, -2
512 ; GFX8-NEXT: s_mov_b32 s15, 0xf000
513 ; GFX8-NEXT: s_mov_b32 s14, -1
514 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
515 ; GFX8-NEXT: v_trunc_f32_e32 v0, s7
516 ; GFX8-NEXT: v_sub_f32_e32 v1, s7, v0
517 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
518 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
519 ; GFX8-NEXT: v_mov_b32_e32 v2, s7
520 ; GFX8-NEXT: v_bfi_b32 v1, s2, v1, v2
521 ; GFX8-NEXT: v_add_f32_e32 v3, v0, v1
522 ; GFX8-NEXT: v_trunc_f32_e32 v0, s6
523 ; GFX8-NEXT: v_sub_f32_e32 v1, s6, v0
524 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
525 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
526 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
527 ; GFX8-NEXT: v_bfi_b32 v1, s2, v1, v2
528 ; GFX8-NEXT: v_add_f32_e32 v2, v0, v1
529 ; GFX8-NEXT: v_trunc_f32_e32 v0, s5
530 ; GFX8-NEXT: v_sub_f32_e32 v1, s5, v0
531 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
532 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
533 ; GFX8-NEXT: v_mov_b32_e32 v4, s5
534 ; GFX8-NEXT: v_bfi_b32 v1, s2, v1, v4
535 ; GFX8-NEXT: v_add_f32_e32 v1, v0, v1
536 ; GFX8-NEXT: v_trunc_f32_e32 v0, s4
537 ; GFX8-NEXT: v_sub_f32_e32 v4, s4, v0
538 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
539 ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
540 ; GFX8-NEXT: v_mov_b32_e32 v5, s4
541 ; GFX8-NEXT: v_bfi_b32 v4, s2, v4, v5
542 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v4
543 ; GFX8-NEXT: v_trunc_f32_e32 v4, s11
544 ; GFX8-NEXT: v_sub_f32_e32 v5, s11, v4
545 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
546 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
547 ; GFX8-NEXT: v_mov_b32_e32 v6, s11
548 ; GFX8-NEXT: v_bfi_b32 v5, s2, v5, v6
549 ; GFX8-NEXT: v_add_f32_e32 v7, v4, v5
550 ; GFX8-NEXT: v_trunc_f32_e32 v4, s10
551 ; GFX8-NEXT: v_sub_f32_e32 v5, s10, v4
552 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
553 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
554 ; GFX8-NEXT: v_mov_b32_e32 v6, s10
555 ; GFX8-NEXT: v_bfi_b32 v5, s2, v5, v6
556 ; GFX8-NEXT: v_add_f32_e32 v6, v4, v5
557 ; GFX8-NEXT: v_trunc_f32_e32 v4, s9
558 ; GFX8-NEXT: v_sub_f32_e32 v5, s9, v4
559 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
560 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
561 ; GFX8-NEXT: v_mov_b32_e32 v8, s9
562 ; GFX8-NEXT: v_bfi_b32 v5, s2, v5, v8
563 ; GFX8-NEXT: v_add_f32_e32 v5, v4, v5
564 ; GFX8-NEXT: v_trunc_f32_e32 v4, s8
565 ; GFX8-NEXT: v_sub_f32_e32 v8, s8, v4
566 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, 0.5
567 ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1.0, s[0:1]
568 ; GFX8-NEXT: v_mov_b32_e32 v9, s8
569 ; GFX8-NEXT: v_bfi_b32 v8, s2, v8, v9
570 ; GFX8-NEXT: v_add_f32_e32 v4, v4, v8
571 ; GFX8-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16
572 ; GFX8-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
573 ; GFX8-NEXT: s_endpgm
574 ;
575 ; GFX9-LABEL: round_v8f32:
576 ; GFX9: ; %bb.0:
577 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x44
578 ; GFX9-NEXT: s_load_dwordx2 s[12:13], s[2:3], 0x24
579 ; GFX9-NEXT: s_brev_b32 s2, -2
580 ; GFX9-NEXT: s_mov_b32 s15, 0xf000
581 ; GFX9-NEXT: s_mov_b32 s14, -1
582 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
583 ; GFX9-NEXT: v_trunc_f32_e32 v0, s7
584 ; GFX9-NEXT: v_sub_f32_e32 v1, s7, v0
585 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
586 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
587 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
588 ; GFX9-NEXT: v_bfi_b32 v1, s2, v1, v2
589 ; GFX9-NEXT: v_add_f32_e32 v3, v0, v1
590 ; GFX9-NEXT: v_trunc_f32_e32 v0, s6
591 ; GFX9-NEXT: v_sub_f32_e32 v1, s6, v0
592 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
593 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
594 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
595 ; GFX9-NEXT: v_bfi_b32 v1, s2, v1, v2
596 ; GFX9-NEXT: v_add_f32_e32 v2, v0, v1
597 ; GFX9-NEXT: v_trunc_f32_e32 v0, s5
598 ; GFX9-NEXT: v_sub_f32_e32 v1, s5, v0
599 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
600 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
601 ; GFX9-NEXT: v_mov_b32_e32 v4, s5
602 ; GFX9-NEXT: v_bfi_b32 v1, s2, v1, v4
603 ; GFX9-NEXT: v_add_f32_e32 v1, v0, v1
604 ; GFX9-NEXT: v_trunc_f32_e32 v0, s4
605 ; GFX9-NEXT: v_sub_f32_e32 v4, s4, v0
606 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
607 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
608 ; GFX9-NEXT: v_mov_b32_e32 v5, s4
609 ; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v5
610 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v4
611 ; GFX9-NEXT: v_trunc_f32_e32 v4, s11
612 ; GFX9-NEXT: v_sub_f32_e32 v5, s11, v4
613 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
614 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
615 ; GFX9-NEXT: v_mov_b32_e32 v6, s11
616 ; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v6
617 ; GFX9-NEXT: v_add_f32_e32 v7, v4, v5
618 ; GFX9-NEXT: v_trunc_f32_e32 v4, s10
619 ; GFX9-NEXT: v_sub_f32_e32 v5, s10, v4
620 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
621 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
622 ; GFX9-NEXT: v_mov_b32_e32 v6, s10
623 ; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v6
624 ; GFX9-NEXT: v_add_f32_e32 v6, v4, v5
625 ; GFX9-NEXT: v_trunc_f32_e32 v4, s9
626 ; GFX9-NEXT: v_sub_f32_e32 v5, s9, v4
627 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v5|, 0.5
628 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[0:1]
629 ; GFX9-NEXT: v_mov_b32_e32 v8, s9
630 ; GFX9-NEXT: v_bfi_b32 v5, s2, v5, v8
631 ; GFX9-NEXT: v_add_f32_e32 v5, v4, v5
632 ; GFX9-NEXT: v_trunc_f32_e32 v4, s8
633 ; GFX9-NEXT: v_sub_f32_e32 v8, s8, v4
634 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, 0.5
635 ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1.0, s[0:1]
636 ; GFX9-NEXT: v_mov_b32_e32 v9, s8
637 ; GFX9-NEXT: v_bfi_b32 v8, s2, v8, v9
638 ; GFX9-NEXT: v_add_f32_e32 v4, v4, v8
639 ; GFX9-NEXT: buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16
640 ; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
641 ; GFX9-NEXT: s_endpgm
642 ;
643 ; GFX11-LABEL: round_v8f32:
644 ; GFX11: ; %bb.0:
645 ; GFX11-NEXT: s_clause 0x1
646 ; GFX11-NEXT: s_load_b256 s[4:11], s[2:3], 0x44
647 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
648 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
649 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
650 ; GFX11-NEXT: v_trunc_f32_e32 v0, s7
651 ; GFX11-NEXT: v_trunc_f32_e32 v1, s6
652 ; GFX11-NEXT: v_trunc_f32_e32 v4, s5
653 ; GFX11-NEXT: v_trunc_f32_e32 v8, s4
654 ; GFX11-NEXT: v_trunc_f32_e32 v5, s11
655 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
656 ; GFX11-NEXT: v_dual_sub_f32 v2, s7, v0 :: v_dual_sub_f32 v3, s6, v1
657 ; GFX11-NEXT: v_sub_f32_e32 v7, s5, v4
658 ; GFX11-NEXT: v_trunc_f32_e32 v9, s9
659 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
660 ; GFX11-NEXT: v_sub_f32_e32 v12, s11, v5
661 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v2|, 0.5
662 ; GFX11-NEXT: v_sub_f32_e32 v11, s4, v8
663 ; GFX11-NEXT: v_trunc_f32_e32 v6, s10
664 ; GFX11-NEXT: v_sub_f32_e32 v14, s9, v9
665 ; GFX11-NEXT: v_trunc_f32_e32 v10, s8
666 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s2
667 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v3|, 0.5
668 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
669 ; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s7
670 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s2
671 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v7|, 0.5
672 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
673 ; GFX11-NEXT: v_bfi_b32 v16, 0x7fffffff, v3, s6
674 ; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s2
675 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v11|, 0.5
676 ; GFX11-NEXT: v_sub_f32_e32 v13, s10, v6
677 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
678 ; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v16
679 ; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s5
680 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
681 ; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 1.0, s2
682 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v12|, 0.5
683 ; GFX11-NEXT: v_add_f32_e32 v1, v4, v7
684 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
685 ; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, s4
686 ; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, 1.0, s2
687 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v13|, 0.5
688 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
689 ; GFX11-NEXT: v_bfi_b32 v12, 0x7fffffff, v12, s11
690 ; GFX11-NEXT: v_cndmask_b32_e64 v13, 0, 1.0, s2
691 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v14|, 0.5
692 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
693 ; GFX11-NEXT: v_add_f32_e32 v7, v5, v12
694 ; GFX11-NEXT: v_bfi_b32 v13, 0x7fffffff, v13, s10
695 ; GFX11-NEXT: v_sub_f32_e32 v15, s8, v10
696 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
697 ; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, 1.0, s2
698 ; GFX11-NEXT: v_add_f32_e32 v6, v6, v13
699 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
700 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v15|, 0.5
701 ; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v14, s9
702 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
703 ; GFX11-NEXT: v_cndmask_b32_e64 v15, 0, 1.0, s2
704 ; GFX11-NEXT: v_dual_add_f32 v5, v9, v0 :: v_dual_add_f32 v0, v8, v11
705 ; GFX11-NEXT: s_mov_b32 s2, -1
706 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
707 ; GFX11-NEXT: v_bfi_b32 v4, 0x7fffffff, v15, s8
708 ; GFX11-NEXT: v_add_f32_e32 v4, v10, v4
709 ; GFX11-NEXT: s_clause 0x1
710 ; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0 offset:16
711 ; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
712 ; GFX11-NEXT: s_nop 0
713 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
714 ; GFX11-NEXT: s_endpgm
715 ;
716 ; R600-LABEL: round_v8f32:
717 ; R600: ; %bb.0:
718 ; R600-NEXT: ALU 50, @4, KC0[CB0:0-32], KC1[]
719 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 0
720 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T1.X, 1
721 ; R600-NEXT: CF_END
722 ; R600-NEXT: ALU clause starting at 4:
723 ; R600-NEXT: TRUNC * T0.W, KC0[6].X,
724 ; R600-NEXT: ADD T0.Z, KC0[6].X, -PV.W,
725 ; R600-NEXT: TRUNC * T1.W, KC0[5].X,
726 ; R600-NEXT: TRUNC * T2.W, KC0[4].W,
727 ; R600-NEXT: ADD T1.Z, KC0[4].W, -PV.W,
728 ; R600-NEXT: ADD T3.W, KC0[5].X, -T1.W,
729 ; R600-NEXT: SETGE * T4.W, |T0.Z|, 0.5,
730 ; R600-NEXT: BFI_INT T0.Y, literal.x, PS, KC0[6].X,
731 ; R600-NEXT: SETGE T0.Z, |PV.W|, 0.5,
732 ; R600-NEXT: SETGE T3.W, |PV.Z|, 0.5,
733 ; R600-NEXT: TRUNC * T4.W, KC0[5].Y,
734 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
735 ; R600-NEXT: ADD T1.Y, KC0[5].Y, -PS,
736 ; R600-NEXT: BFI_INT T1.Z, literal.x, PV.W, KC0[4].W,
737 ; R600-NEXT: BFI_INT T3.W, literal.x, PV.Z, KC0[5].X,
738 ; R600-NEXT: TRUNC * T5.W, KC0[4].Z,
739 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
740 ; R600-NEXT: TRUNC T0.Z, KC0[4].Y,
741 ; R600-NEXT: TRUNC * T6.W, KC0[5].W,
742 ; R600-NEXT: ADD * T7.W, KC0[4].Z, -T5.W,
743 ; R600-NEXT: TRUNC T0.X, KC0[5].Z,
744 ; R600-NEXT: SETGE T2.Y, |PV.W|, 0.5,
745 ; R600-NEXT: ADD T2.Z, KC0[5].W, -T6.W, BS:VEC_102/SCL_221
746 ; R600-NEXT: ADD T7.W, KC0[4].Y, -T0.Z,
747 ; R600-NEXT: ADD * T3.W, T1.W, T3.W,
748 ; R600-NEXT: SETGE T1.X, |PV.W|, 0.5,
749 ; R600-NEXT: SETGE T4.Y, |PV.Z|, 0.5,
750 ; R600-NEXT: ADD T3.Z, T2.W, T1.Z,
751 ; R600-NEXT: BFI_INT T1.W, literal.x, PV.Y, KC0[4].Z,
752 ; R600-NEXT: ADD * T2.W, KC0[5].Z, -PV.X,
753 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
754 ; R600-NEXT: SETGE T2.X, |PS|, 0.5,
755 ; R600-NEXT: ADD T3.Y, T5.W, PV.W,
756 ; R600-NEXT: BFI_INT T1.Z, literal.x, PV.Y, KC0[5].W,
757 ; R600-NEXT: BFI_INT T1.W, literal.x, PV.X, KC0[4].Y,
758 ; R600-NEXT: ADD * T0.W, T0.W, T0.Y,
759 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
760 ; R600-NEXT: ADD T3.X, T0.Z, PV.W,
761 ; R600-NEXT: ADD T0.Z, T6.W, PV.Z,
762 ; R600-NEXT: BFI_INT T1.W, literal.x, PV.X, KC0[5].Z,
763 ; R600-NEXT: SETGE * T2.W, |T1.Y|, 0.5,
764 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
765 ; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
766 ; R600-NEXT: ADD T0.Y, T0.X, PV.W,
767 ; R600-NEXT: BFI_INT * T1.W, literal.y, PS, KC0[5].Y,
768 ; R600-NEXT: 2(2.802597e-45), 2147483647(nan)
769 ; R600-NEXT: ADD T0.X, T4.W, PV.W,
770 ; R600-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
771 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
772 ; R600-NEXT: LSHR * T2.X, PV.W, literal.x,
773 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
774 %result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
775 store <8 x float> %result, ptr addrspace(1) %out
776 ret void
777 }
779 define amdgpu_kernel void @round_f16(ptr addrspace(1) %out, i32 %x.arg) #0 {
780 ; GFX6-LABEL: round_f16:
781 ; GFX6: ; %bb.0:
782 ; GFX6-NEXT: s_load_dword s0, s[2:3], 0xb
783 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
784 ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, s0
785 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
786 ; GFX6-NEXT: v_trunc_f32_e32 v1, v0
787 ; GFX6-NEXT: v_sub_f32_e32 v2, v0, v1
788 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v2|, 0.5
789 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[2:3]
790 ; GFX6-NEXT: s_brev_b32 s2, -2
791 ; GFX6-NEXT: v_bfi_b32 v0, s2, v2, v0
792 ; GFX6-NEXT: v_add_f32_e32 v0, v1, v0
793 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
794 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
795 ; GFX6-NEXT: s_mov_b32 s2, -1
796 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
797 ; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
798 ; GFX6-NEXT: s_endpgm
799 ;
800 ; GFX8-LABEL: round_f16:
801 ; GFX8: ; %bb.0:
802 ; GFX8-NEXT: s_load_dword s4, s[2:3], 0x2c
803 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
804 ; GFX8-NEXT: v_mov_b32_e32 v0, 0x3c00
805 ; GFX8-NEXT: s_movk_i32 s5, 0x7fff
806 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
807 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
808 ; GFX8-NEXT: v_trunc_f16_e32 v1, s4
809 ; GFX8-NEXT: v_sub_f16_e32 v2, s4, v1
810 ; GFX8-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
811 ; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
812 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
813 ; GFX8-NEXT: v_bfi_b32 v0, s5, v0, v2
814 ; GFX8-NEXT: s_mov_b32 s2, -1
815 ; GFX8-NEXT: v_add_f16_e32 v0, v1, v0
816 ; GFX8-NEXT: buffer_store_short v0, off, s[0:3], 0
817 ; GFX8-NEXT: s_endpgm
818 ;
819 ; GFX9-LABEL: round_f16:
820 ; GFX9: ; %bb.0:
821 ; GFX9-NEXT: s_load_dword s4, s[2:3], 0x2c
822 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
823 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
824 ; GFX9-NEXT: s_movk_i32 s5, 0x7fff
825 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
826 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
827 ; GFX9-NEXT: v_trunc_f16_e32 v1, s4
828 ; GFX9-NEXT: v_sub_f16_e32 v2, s4, v1
829 ; GFX9-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
830 ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
831 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
832 ; GFX9-NEXT: v_bfi_b32 v0, s5, v0, v2
833 ; GFX9-NEXT: s_mov_b32 s2, -1
834 ; GFX9-NEXT: v_add_f16_e32 v0, v1, v0
835 ; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
836 ; GFX9-NEXT: s_endpgm
837 ;
838 ; GFX11-LABEL: round_f16:
839 ; GFX11: ; %bb.0:
840 ; GFX11-NEXT: s_clause 0x1
841 ; GFX11-NEXT: s_load_b32 s4, s[2:3], 0x2c
842 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
843 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
844 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
845 ; GFX11-NEXT: v_trunc_f16_e32 v0, s4
846 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
847 ; GFX11-NEXT: v_sub_f16_e32 v1, s4, v0
848 ; GFX11-NEXT: v_cmp_ge_f16_e64 s2, |v1|, 0.5
849 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
850 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x3c00, s2
851 ; GFX11-NEXT: s_mov_b32 s2, -1
852 ; GFX11-NEXT: v_bfi_b32 v1, 0x7fff, v1, s4
853 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
854 ; GFX11-NEXT: v_add_f16_e32 v0, v0, v1
855 ; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0
856 ; GFX11-NEXT: s_nop 0
857 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
858 ; GFX11-NEXT: s_endpgm
859 ;
860 ; R600-LABEL: round_f16:
861 ; R600: ; %bb.0:
862 ; R600-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
863 ; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X
864 ; R600-NEXT: CF_END
865 ; R600-NEXT: PAD
866 ; R600-NEXT: ALU clause starting at 4:
867 ; R600-NEXT: FLT16_TO_FLT32 * T0.W, KC0[2].Z,
868 ; R600-NEXT: TRUNC * T1.W, PV.W,
869 ; R600-NEXT: ADD * T2.W, T0.W, -PV.W,
870 ; R600-NEXT: SETGE * T2.W, |PV.W|, 0.5,
871 ; R600-NEXT: BFI_INT T0.W, literal.x, PV.W, T0.W,
872 ; R600-NEXT: AND_INT * T2.W, KC0[2].Y, literal.y,
873 ; R600-NEXT: 2147483647(nan), 3(4.203895e-45)
874 ; R600-NEXT: ADD * T0.W, T1.W, PV.W,
875 ; R600-NEXT: FLT32_TO_FLT16 T0.W, PV.W,
876 ; R600-NEXT: LSHL * T1.W, T2.W, literal.x,
877 ; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)
878 ; R600-NEXT: LSHL T0.X, PV.W, PS,
879 ; R600-NEXT: LSHL * T0.W, literal.x, PS,
880 ; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
881 ; R600-NEXT: MOV T0.Y, 0.0,
882 ; R600-NEXT: MOV * T0.Z, 0.0,
883 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
884 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
885 %x.arg.trunc = trunc i32 %x.arg to i16
886 %x = bitcast i16 %x.arg.trunc to half
887 %result = call half @llvm.round.f16(half %x) #1
888 store half %result, ptr addrspace(1) %out
889 ret void
890 }
892 ; Should be scalarized
893 define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
894 ; GFX6-LABEL: round_v2f16:
895 ; GFX6: ; %bb.0:
896 ; GFX6-NEXT: s_load_dword s0, s[2:3], 0xb
897 ; GFX6-NEXT: s_brev_b32 s4, -2
898 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
899 ; GFX6-NEXT: s_lshr_b32 s1, s0, 16
900 ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, s1
901 ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, s0
902 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
903 ; GFX6-NEXT: v_trunc_f32_e32 v3, v1
904 ; GFX6-NEXT: v_sub_f32_e32 v5, v1, v3
905 ; GFX6-NEXT: v_trunc_f32_e32 v2, v0
906 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v5|, 0.5
907 ; GFX6-NEXT: v_sub_f32_e32 v4, v0, v2
908 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[2:3]
909 ; GFX6-NEXT: v_bfi_b32 v1, s4, v5, v1
910 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v4|, 0.5
911 ; GFX6-NEXT: v_add_f32_e32 v1, v3, v1
912 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s[2:3]
913 ; GFX6-NEXT: v_bfi_b32 v0, s4, v3, v0
914 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
915 ; GFX6-NEXT: v_add_f32_e32 v0, v2, v0
916 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
917 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
918 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
919 ; GFX6-NEXT: s_mov_b32 s2, -1
920 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
921 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
922 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
923 ; GFX6-NEXT: s_endpgm
924 ;
925 ; GFX8-LABEL: round_v2f16:
926 ; GFX8: ; %bb.0:
927 ; GFX8-NEXT: s_load_dword s4, s[2:3], 0x2c
928 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
929 ; GFX8-NEXT: v_mov_b32_e32 v0, 0x3c00
930 ; GFX8-NEXT: s_movk_i32 s6, 0x7fff
931 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
932 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
933 ; GFX8-NEXT: s_lshr_b32 s5, s4, 16
934 ; GFX8-NEXT: v_trunc_f16_e32 v1, s5
935 ; GFX8-NEXT: v_sub_f16_e32 v2, s5, v1
936 ; GFX8-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
937 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v0, vcc
938 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
939 ; GFX8-NEXT: v_bfi_b32 v2, s6, v2, v3
940 ; GFX8-NEXT: v_add_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
941 ; GFX8-NEXT: v_trunc_f16_e32 v2, s4
942 ; GFX8-NEXT: v_sub_f16_e32 v3, s4, v2
943 ; GFX8-NEXT: v_cmp_ge_f16_e64 vcc, |v3|, 0.5
944 ; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
945 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
946 ; GFX8-NEXT: v_bfi_b32 v0, s6, v0, v3
947 ; GFX8-NEXT: v_add_f16_e32 v0, v2, v0
948 ; GFX8-NEXT: s_mov_b32 s2, -1
949 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
950 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
951 ; GFX8-NEXT: s_endpgm
952 ;
953 ; GFX9-LABEL: round_v2f16:
954 ; GFX9: ; %bb.0:
955 ; GFX9-NEXT: s_load_dword s4, s[2:3], 0x2c
956 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
957 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
958 ; GFX9-NEXT: s_movk_i32 s6, 0x7fff
959 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
960 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
961 ; GFX9-NEXT: s_lshr_b32 s5, s4, 16
962 ; GFX9-NEXT: v_trunc_f16_e32 v1, s5
963 ; GFX9-NEXT: v_sub_f16_e32 v2, s5, v1
964 ; GFX9-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
965 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v0, vcc
966 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
967 ; GFX9-NEXT: v_bfi_b32 v2, s6, v2, v3
968 ; GFX9-NEXT: v_add_f16_e32 v1, v1, v2
969 ; GFX9-NEXT: v_trunc_f16_e32 v2, s4
970 ; GFX9-NEXT: v_sub_f16_e32 v3, s4, v2
971 ; GFX9-NEXT: v_cmp_ge_f16_e64 vcc, |v3|, 0.5
972 ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
973 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
974 ; GFX9-NEXT: v_bfi_b32 v0, s6, v0, v3
975 ; GFX9-NEXT: v_add_f16_e32 v0, v2, v0
976 ; GFX9-NEXT: s_mov_b32 s2, -1
977 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
978 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
979 ; GFX9-NEXT: s_endpgm
980 ;
981 ; GFX11-LABEL: round_v2f16:
982 ; GFX11: ; %bb.0:
983 ; GFX11-NEXT: s_clause 0x1
984 ; GFX11-NEXT: s_load_b32 s4, s[2:3], 0x2c
985 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
986 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
987 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
988 ; GFX11-NEXT: s_lshr_b32 s5, s4, 16
989 ; GFX11-NEXT: v_trunc_f16_e32 v1, s4
990 ; GFX11-NEXT: v_trunc_f16_e32 v0, s5
991 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
992 ; GFX11-NEXT: v_sub_f16_e32 v3, s4, v1
993 ; GFX11-NEXT: v_sub_f16_e32 v2, s5, v0
994 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
995 ; GFX11-NEXT: v_cmp_ge_f16_e64 s2, |v2|, 0.5
996 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s2
997 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
998 ; GFX11-NEXT: v_cmp_ge_f16_e64 s2, |v3|, 0.5
999 ; GFX11-NEXT: v_bfi_b32 v2, 0x7fff, v2, s5
1000 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1001 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x3c00, s2
1002 ; GFX11-NEXT: s_mov_b32 s2, -1
1003 ; GFX11-NEXT: v_add_f16_e32 v0, v0, v2
1004 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
1005 ; GFX11-NEXT: v_bfi_b32 v3, 0x7fff, v3, s4
1006 ; GFX11-NEXT: v_add_f16_e32 v1, v1, v3
1007 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1008 ; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
1009 ; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
1010 ; GFX11-NEXT: s_nop 0
1011 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1012 ; GFX11-NEXT: s_endpgm
1013 ;
1014 ; R600-LABEL: round_v2f16:
1015 ; R600: ; %bb.0:
1016 ; R600-NEXT: ALU 22, @4, KC0[CB0:0-32], KC1[]
1017 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1018 ; R600-NEXT: CF_END
1019 ; R600-NEXT: PAD
1020 ; R600-NEXT: ALU clause starting at 4:
1021 ; R600-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,
1022 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
1023 ; R600-NEXT: FLT16_TO_FLT32 * T0.W, PV.W,
1024 ; R600-NEXT: FLT16_TO_FLT32 T1.W, KC0[2].Z,
1025 ; R600-NEXT: TRUNC * T2.W, PV.W,
1026 ; R600-NEXT: ADD T3.W, T0.W, -PS,
1027 ; R600-NEXT: TRUNC * T4.W, PV.W,
1028 ; R600-NEXT: ADD T5.W, T1.W, -PS,
1029 ; R600-NEXT: SETGE * T3.W, |PV.W|, 0.5,
1030 ; R600-NEXT: BFI_INT T0.W, literal.x, PS, T0.W,
1031 ; R600-NEXT: SETGE * T3.W, |PV.W|, 0.5,
1032 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
1033 ; R600-NEXT: BFI_INT T1.W, literal.x, PS, T1.W, BS:VEC_021/SCL_122
1034 ; R600-NEXT: ADD * T0.W, T2.W, PV.W,
1035 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
1036 ; R600-NEXT: FLT32_TO_FLT16 T0.W, PS,
1037 ; R600-NEXT: ADD * T1.W, T4.W, PV.W,
1038 ; R600-NEXT: FLT32_TO_FLT16 T1.W, PS,
1039 ; R600-NEXT: LSHL * T0.W, PV.W, literal.x,
1040 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
1041 ; R600-NEXT: OR_INT T0.X, PV.W, PS,
1042 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1043 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1044 %in = bitcast i32 %in.arg to <2 x half>
1045 %result = call <2 x half> @llvm.round.v2f16(<2 x half> %in)
1046 store <2 x half> %result, ptr addrspace(1) %out
1047 ret void
1048 }
1050 declare float @llvm.round.f32(float) #1
1051 declare <2 x float> @llvm.round.v2f32(<2 x float>) #1
1052 declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
1053 declare <8 x float> @llvm.round.v8f32(<8 x float>) #1
1055 declare half @llvm.round.f16(half) #1
1056 declare <2 x half> @llvm.round.v2f16(<2 x half>) #1
1057 declare <4 x half> @llvm.round.v4f16(<4 x half>) #1
1058 declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
1060 attributes #0 = { nounwind }
1061 attributes #1 = { nounwind readnone }