| blob | a4bde5c9d8215359e0c2d634bcfc50ca9f35ecad |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
6 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s
8 define amdgpu_kernel void @s_lshr_v2i16(ptr addrspace(1) %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
9 ; GFX9-LABEL: s_lshr_v2i16:
10 ; GFX9: ; %bb.0:
11 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
12 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
13 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
14 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
15 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, s7, v1
16 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
17 ; GFX9-NEXT: s_endpgm
18 ;
19 ; VI-LABEL: s_lshr_v2i16:
20 ; VI: ; %bb.0:
21 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
22 ; VI-NEXT: s_waitcnt lgkmcnt(0)
23 ; VI-NEXT: s_and_b32 s4, s2, 0xffff
24 ; VI-NEXT: s_lshr_b32 s2, s2, 16
25 ; VI-NEXT: s_lshr_b32 s5, s3, 16
26 ; VI-NEXT: s_lshr_b32 s2, s2, s5
27 ; VI-NEXT: s_lshr_b32 s3, s4, s3
28 ; VI-NEXT: s_lshl_b32 s2, s2, 16
29 ; VI-NEXT: s_or_b32 s2, s3, s2
30 ; VI-NEXT: v_mov_b32_e32 v0, s0
31 ; VI-NEXT: v_mov_b32_e32 v1, s1
32 ; VI-NEXT: v_mov_b32_e32 v2, s2
33 ; VI-NEXT: flat_store_dword v[0:1], v2
34 ; VI-NEXT: s_endpgm
35 ;
36 ; CI-LABEL: s_lshr_v2i16:
37 ; CI: ; %bb.0:
38 ; CI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
39 ; CI-NEXT: s_mov_b32 s7, 0xf000
40 ; CI-NEXT: s_mov_b32 s6, -1
41 ; CI-NEXT: s_waitcnt lgkmcnt(0)
42 ; CI-NEXT: s_mov_b32 s4, s0
43 ; CI-NEXT: s_mov_b32 s5, s1
44 ; CI-NEXT: s_and_b32 s0, s2, 0xffff
45 ; CI-NEXT: s_lshr_b32 s1, s2, 16
46 ; CI-NEXT: s_lshr_b32 s2, s3, 16
47 ; CI-NEXT: s_lshr_b32 s1, s1, s2
48 ; CI-NEXT: s_lshl_b32 s1, s1, 16
49 ; CI-NEXT: s_lshr_b32 s0, s0, s3
50 ; CI-NEXT: s_or_b32 s0, s0, s1
51 ; CI-NEXT: v_mov_b32_e32 v0, s0
52 ; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0
53 ; CI-NEXT: s_endpgm
54 ;
55 ; GFX10-LABEL: s_lshr_v2i16:
56 ; GFX10: ; %bb.0:
57 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
58 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
59 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
60 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, s7, s6
61 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
62 ; GFX10-NEXT: s_endpgm
63 ;
64 ; GFX11-LABEL: s_lshr_v2i16:
65 ; GFX11: ; %bb.0:
66 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
67 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
68 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
69 ; GFX11-NEXT: v_pk_lshrrev_b16 v1, s3, s2
70 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
71 ; GFX11-NEXT: s_nop 0
72 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
73 ; GFX11-NEXT: s_endpgm
74 %result = lshr <2 x i16> %lhs, %rhs
75 store <2 x i16> %result, ptr addrspace(1) %out
76 ret void
77 }
79 define amdgpu_kernel void @v_lshr_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
80 ; GFX9-LABEL: v_lshr_v2i16:
81 ; GFX9: ; %bb.0:
82 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
83 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
84 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
85 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
86 ; GFX9-NEXT: s_waitcnt vmcnt(0)
87 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0
88 ; GFX9-NEXT: global_store_dword v2, v0, s[4:5]
89 ; GFX9-NEXT: s_endpgm
90 ;
91 ; VI-LABEL: v_lshr_v2i16:
92 ; VI: ; %bb.0:
93 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
94 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
95 ; VI-NEXT: s_waitcnt lgkmcnt(0)
96 ; VI-NEXT: v_mov_b32_e32 v1, s3
97 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
98 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
99 ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
100 ; VI-NEXT: v_mov_b32_e32 v3, s1
101 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
102 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
103 ; VI-NEXT: s_waitcnt vmcnt(0)
104 ; VI-NEXT: v_lshrrev_b16_e32 v4, v1, v0
105 ; VI-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
106 ; VI-NEXT: v_or_b32_e32 v0, v4, v0
107 ; VI-NEXT: flat_store_dword v[2:3], v0
108 ; VI-NEXT: s_endpgm
109 ;
110 ; CI-LABEL: v_lshr_v2i16:
111 ; CI: ; %bb.0:
112 ; CI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
113 ; CI-NEXT: s_mov_b32 s7, 0xf000
114 ; CI-NEXT: s_mov_b32 s6, 0
115 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
116 ; CI-NEXT: v_mov_b32_e32 v1, 0
117 ; CI-NEXT: s_waitcnt lgkmcnt(0)
118 ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
119 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
120 ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
121 ; CI-NEXT: s_waitcnt vmcnt(0)
122 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
123 ; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2
124 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v3
125 ; CI-NEXT: v_lshrrev_b32_e32 v2, v3, v2
126 ; CI-NEXT: v_lshrrev_b32_e32 v3, v5, v4
127 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
128 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
129 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
130 ; CI-NEXT: s_endpgm
131 ;
132 ; GFX10-LABEL: v_lshr_v2i16:
133 ; GFX10: ; %bb.0:
134 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
135 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0
136 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
137 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
138 ; GFX10-NEXT: s_waitcnt vmcnt(0)
139 ; GFX10-NEXT: v_pk_lshrrev_b16 v0, v1, v0
140 ; GFX10-NEXT: global_store_dword v2, v0, s[4:5]
141 ; GFX10-NEXT: s_endpgm
142 ;
143 ; GFX11-LABEL: v_lshr_v2i16:
144 ; GFX11: ; %bb.0:
145 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
146 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
147 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
148 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
149 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
150 ; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
151 ; GFX11-NEXT: s_waitcnt vmcnt(0)
152 ; GFX11-NEXT: v_pk_lshrrev_b16 v0, v1, v0
153 ; GFX11-NEXT: global_store_b32 v2, v0, s[0:1]
154 ; GFX11-NEXT: s_nop 0
155 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
156 ; GFX11-NEXT: s_endpgm
157 %tid = call i32 @llvm.amdgcn.workitem.id.x()
158 %tid.ext = sext i32 %tid to i64
159 %in.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i64 %tid.ext
160 %out.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 %tid.ext
161 %b_ptr = getelementptr <2 x i16>, ptr addrspace(1) %in.gep, i32 1
162 %a = load <2 x i16>, ptr addrspace(1) %in.gep
163 %b = load <2 x i16>, ptr addrspace(1) %b_ptr
164 %result = lshr <2 x i16> %a, %b
165 store <2 x i16> %result, ptr addrspace(1) %out.gep
166 ret void
167 }
169 define amdgpu_kernel void @lshr_v_s_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in, <2 x i16> %sgpr) #0 {
170 ; GFX9-LABEL: lshr_v_s_v2i16:
171 ; GFX9: ; %bb.0:
172 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
173 ; GFX9-NEXT: s_load_dword s0, s[2:3], 0x34
174 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
175 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
176 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
177 ; GFX9-NEXT: s_waitcnt vmcnt(0)
178 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, s0, v1
179 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
180 ; GFX9-NEXT: s_endpgm
181 ;
182 ; VI-LABEL: lshr_v_s_v2i16:
183 ; VI: ; %bb.0:
184 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
185 ; VI-NEXT: s_load_dword s0, s[2:3], 0x34
186 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
187 ; VI-NEXT: s_waitcnt lgkmcnt(0)
188 ; VI-NEXT: v_mov_b32_e32 v1, s7
189 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
190 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
191 ; VI-NEXT: flat_load_dword v3, v[0:1]
192 ; VI-NEXT: s_lshr_b32 s1, s0, 16
193 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
194 ; VI-NEXT: v_mov_b32_e32 v2, s1
195 ; VI-NEXT: v_mov_b32_e32 v1, s5
196 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
197 ; VI-NEXT: s_waitcnt vmcnt(0)
198 ; VI-NEXT: v_lshrrev_b16_e32 v4, s0, v3
199 ; VI-NEXT: v_lshrrev_b16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
200 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
201 ; VI-NEXT: flat_store_dword v[0:1], v2
202 ; VI-NEXT: s_endpgm
203 ;
204 ; CI-LABEL: lshr_v_s_v2i16:
205 ; CI: ; %bb.0:
206 ; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x9
207 ; CI-NEXT: s_load_dword s0, s[2:3], 0xd
208 ; CI-NEXT: s_mov_b32 s11, 0xf000
209 ; CI-NEXT: s_mov_b32 s10, 0
210 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
211 ; CI-NEXT: s_waitcnt lgkmcnt(0)
212 ; CI-NEXT: s_mov_b64 s[8:9], s[6:7]
213 ; CI-NEXT: v_mov_b32_e32 v1, 0
214 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
215 ; CI-NEXT: s_lshr_b32 s1, s0, 16
216 ; CI-NEXT: s_mov_b64 s[6:7], s[10:11]
217 ; CI-NEXT: s_waitcnt vmcnt(0)
218 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
219 ; CI-NEXT: v_and_b32_e32 v2, 0xffff, v2
220 ; CI-NEXT: v_lshrrev_b32_e32 v3, s1, v3
221 ; CI-NEXT: v_lshrrev_b32_e32 v2, s0, v2
222 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
223 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
224 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
225 ; CI-NEXT: s_endpgm
226 ;
227 ; GFX10-LABEL: lshr_v_s_v2i16:
228 ; GFX10: ; %bb.0:
229 ; GFX10-NEXT: s_clause 0x1
230 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
231 ; GFX10-NEXT: s_load_dword s0, s[2:3], 0x34
232 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
233 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
234 ; GFX10-NEXT: global_load_dword v1, v0, s[6:7]
235 ; GFX10-NEXT: s_waitcnt vmcnt(0)
236 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, s0, v1
237 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
238 ; GFX10-NEXT: s_endpgm
239 ;
240 ; GFX11-LABEL: lshr_v_s_v2i16:
241 ; GFX11: ; %bb.0:
242 ; GFX11-NEXT: s_clause 0x1
243 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x24
244 ; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x34
245 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
246 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
247 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
248 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
249 ; GFX11-NEXT: global_load_b32 v1, v0, s[6:7]
250 ; GFX11-NEXT: s_waitcnt vmcnt(0)
251 ; GFX11-NEXT: v_pk_lshrrev_b16 v1, s0, v1
252 ; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]
253 ; GFX11-NEXT: s_nop 0
254 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
255 ; GFX11-NEXT: s_endpgm
256 %tid = call i32 @llvm.amdgcn.workitem.id.x()
257 %tid.ext = sext i32 %tid to i64
258 %in.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i64 %tid.ext
259 %out.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 %tid.ext
260 %vgpr = load <2 x i16>, ptr addrspace(1) %in.gep
261 %result = lshr <2 x i16> %vgpr, %sgpr
262 store <2 x i16> %result, ptr addrspace(1) %out.gep
263 ret void
264 }
266 define amdgpu_kernel void @lshr_s_v_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in, <2 x i16> %sgpr) #0 {
267 ; GFX9-LABEL: lshr_s_v_v2i16:
268 ; GFX9: ; %bb.0:
269 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
270 ; GFX9-NEXT: s_load_dword s0, s[2:3], 0x34
271 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
272 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
273 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
274 ; GFX9-NEXT: s_waitcnt vmcnt(0)
275 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, s0
276 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
277 ; GFX9-NEXT: s_endpgm
278 ;
279 ; VI-LABEL: lshr_s_v_v2i16:
280 ; VI: ; %bb.0:
281 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
282 ; VI-NEXT: s_load_dword s0, s[2:3], 0x34
283 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
284 ; VI-NEXT: s_waitcnt lgkmcnt(0)
285 ; VI-NEXT: v_mov_b32_e32 v1, s7
286 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
287 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
288 ; VI-NEXT: flat_load_dword v3, v[0:1]
289 ; VI-NEXT: s_lshr_b32 s1, s0, 16
290 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
291 ; VI-NEXT: v_mov_b32_e32 v2, s1
292 ; VI-NEXT: v_mov_b32_e32 v1, s5
293 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
294 ; VI-NEXT: s_waitcnt vmcnt(0)
295 ; VI-NEXT: v_lshrrev_b16_e64 v4, v3, s0
296 ; VI-NEXT: v_lshrrev_b16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
297 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
298 ; VI-NEXT: flat_store_dword v[0:1], v2
299 ; VI-NEXT: s_endpgm
300 ;
301 ; CI-LABEL: lshr_s_v_v2i16:
302 ; CI: ; %bb.0:
303 ; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x9
304 ; CI-NEXT: s_load_dword s0, s[2:3], 0xd
305 ; CI-NEXT: s_mov_b32 s11, 0xf000
306 ; CI-NEXT: s_mov_b32 s10, 0
307 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
308 ; CI-NEXT: s_waitcnt lgkmcnt(0)
309 ; CI-NEXT: s_mov_b64 s[8:9], s[6:7]
310 ; CI-NEXT: v_mov_b32_e32 v1, 0
311 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
312 ; CI-NEXT: s_lshr_b32 s1, s0, 16
313 ; CI-NEXT: s_and_b32 s0, s0, 0xffff
314 ; CI-NEXT: s_mov_b64 s[6:7], s[10:11]
315 ; CI-NEXT: s_waitcnt vmcnt(0)
316 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
317 ; CI-NEXT: v_lshr_b32_e32 v3, s1, v3
318 ; CI-NEXT: v_lshr_b32_e32 v2, s0, v2
319 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
320 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
321 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
322 ; CI-NEXT: s_endpgm
323 ;
324 ; GFX10-LABEL: lshr_s_v_v2i16:
325 ; GFX10: ; %bb.0:
326 ; GFX10-NEXT: s_clause 0x1
327 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
328 ; GFX10-NEXT: s_load_dword s0, s[2:3], 0x34
329 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
330 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
331 ; GFX10-NEXT: global_load_dword v1, v0, s[6:7]
332 ; GFX10-NEXT: s_waitcnt vmcnt(0)
333 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, v1, s0
334 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
335 ; GFX10-NEXT: s_endpgm
336 ;
337 ; GFX11-LABEL: lshr_s_v_v2i16:
338 ; GFX11: ; %bb.0:
339 ; GFX11-NEXT: s_clause 0x1
340 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x24
341 ; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x34
342 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
343 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
344 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
345 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
346 ; GFX11-NEXT: global_load_b32 v1, v0, s[6:7]
347 ; GFX11-NEXT: s_waitcnt vmcnt(0)
348 ; GFX11-NEXT: v_pk_lshrrev_b16 v1, v1, s0
349 ; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]
350 ; GFX11-NEXT: s_nop 0
351 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
352 ; GFX11-NEXT: s_endpgm
353 %tid = call i32 @llvm.amdgcn.workitem.id.x()
354 %tid.ext = sext i32 %tid to i64
355 %in.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i64 %tid.ext
356 %out.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 %tid.ext
357 %vgpr = load <2 x i16>, ptr addrspace(1) %in.gep
358 %result = lshr <2 x i16> %sgpr, %vgpr
359 store <2 x i16> %result, ptr addrspace(1) %out.gep
360 ret void
361 }
363 define amdgpu_kernel void @lshr_imm_v_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
364 ; GFX9-LABEL: lshr_imm_v_v2i16:
365 ; GFX9: ; %bb.0:
366 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
367 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
368 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
369 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
370 ; GFX9-NEXT: s_waitcnt vmcnt(0)
371 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, v1, 8 op_sel_hi:[1,0]
372 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
373 ; GFX9-NEXT: s_endpgm
374 ;
375 ; VI-LABEL: lshr_imm_v_v2i16:
376 ; VI: ; %bb.0:
377 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
378 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
379 ; VI-NEXT: v_mov_b32_e32 v4, 8
380 ; VI-NEXT: s_waitcnt lgkmcnt(0)
381 ; VI-NEXT: v_mov_b32_e32 v1, s3
382 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
383 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
384 ; VI-NEXT: flat_load_dword v3, v[0:1]
385 ; VI-NEXT: v_mov_b32_e32 v1, s1
386 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
387 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
388 ; VI-NEXT: s_waitcnt vmcnt(0)
389 ; VI-NEXT: v_lshrrev_b16_e64 v2, v3, 8
390 ; VI-NEXT: v_lshrrev_b16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
391 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
392 ; VI-NEXT: flat_store_dword v[0:1], v2
393 ; VI-NEXT: s_endpgm
394 ;
395 ; CI-LABEL: lshr_imm_v_v2i16:
396 ; CI: ; %bb.0:
397 ; CI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
398 ; CI-NEXT: s_mov_b32 s7, 0xf000
399 ; CI-NEXT: s_mov_b32 s6, 0
400 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
401 ; CI-NEXT: v_mov_b32_e32 v1, 0
402 ; CI-NEXT: s_waitcnt lgkmcnt(0)
403 ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
404 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
405 ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
406 ; CI-NEXT: s_waitcnt vmcnt(0)
407 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
408 ; CI-NEXT: v_lshr_b32_e32 v3, 8, v3
409 ; CI-NEXT: v_lshr_b32_e32 v2, 8, v2
410 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
411 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
412 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
413 ; CI-NEXT: s_endpgm
414 ;
415 ; GFX10-LABEL: lshr_imm_v_v2i16:
416 ; GFX10: ; %bb.0:
417 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
418 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
419 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
420 ; GFX10-NEXT: global_load_dword v1, v0, s[6:7]
421 ; GFX10-NEXT: s_waitcnt vmcnt(0)
422 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, v1, 8 op_sel_hi:[1,0]
423 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
424 ; GFX10-NEXT: s_endpgm
425 ;
426 ; GFX11-LABEL: lshr_imm_v_v2i16:
427 ; GFX11: ; %bb.0:
428 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
429 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
430 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
431 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
432 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
433 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
434 ; GFX11-NEXT: s_waitcnt vmcnt(0)
435 ; GFX11-NEXT: v_pk_lshrrev_b16 v1, v1, 8 op_sel_hi:[1,0]
436 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
437 ; GFX11-NEXT: s_nop 0
438 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
439 ; GFX11-NEXT: s_endpgm
440 %tid = call i32 @llvm.amdgcn.workitem.id.x()
441 %tid.ext = sext i32 %tid to i64
442 %in.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i64 %tid.ext
443 %out.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 %tid.ext
444 %vgpr = load <2 x i16>, ptr addrspace(1) %in.gep
445 %result = lshr <2 x i16> <i16 8, i16 8>, %vgpr
446 store <2 x i16> %result, ptr addrspace(1) %out.gep
447 ret void
448 }
450 define amdgpu_kernel void @lshr_v_imm_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
451 ; GFX9-LABEL: lshr_v_imm_v2i16:
452 ; GFX9: ; %bb.0:
453 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
454 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
455 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
456 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
457 ; GFX9-NEXT: s_waitcnt vmcnt(0)
458 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
459 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
460 ; GFX9-NEXT: s_endpgm
461 ;
462 ; VI-LABEL: lshr_v_imm_v2i16:
463 ; VI: ; %bb.0:
464 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
465 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
466 ; VI-NEXT: s_waitcnt lgkmcnt(0)
467 ; VI-NEXT: v_mov_b32_e32 v1, s3
468 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
469 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
470 ; VI-NEXT: flat_load_dword v3, v[0:1]
471 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
472 ; VI-NEXT: v_mov_b32_e32 v1, s1
473 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
474 ; VI-NEXT: s_waitcnt vmcnt(0)
475 ; VI-NEXT: v_lshrrev_b32_e32 v2, 24, v3
476 ; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
477 ; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
478 ; VI-NEXT: flat_store_dword v[0:1], v2
479 ; VI-NEXT: s_endpgm
480 ;
481 ; CI-LABEL: lshr_v_imm_v2i16:
482 ; CI: ; %bb.0:
483 ; CI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
484 ; CI-NEXT: s_mov_b32 s7, 0xf000
485 ; CI-NEXT: s_mov_b32 s6, 0
486 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
487 ; CI-NEXT: v_mov_b32_e32 v1, 0
488 ; CI-NEXT: s_waitcnt lgkmcnt(0)
489 ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
490 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
491 ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
492 ; CI-NEXT: s_waitcnt vmcnt(0)
493 ; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2
494 ; CI-NEXT: v_and_b32_e32 v2, 0xff00ff, v2
495 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
496 ; CI-NEXT: s_endpgm
497 ;
498 ; GFX10-LABEL: lshr_v_imm_v2i16:
499 ; GFX10: ; %bb.0:
500 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
501 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
502 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
503 ; GFX10-NEXT: global_load_dword v1, v0, s[6:7]
504 ; GFX10-NEXT: s_waitcnt vmcnt(0)
505 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
506 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
507 ; GFX10-NEXT: s_endpgm
508 ;
509 ; GFX11-LABEL: lshr_v_imm_v2i16:
510 ; GFX11: ; %bb.0:
511 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
512 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
513 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
514 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
515 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
516 ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
517 ; GFX11-NEXT: s_waitcnt vmcnt(0)
518 ; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
519 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
520 ; GFX11-NEXT: s_nop 0
521 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
522 ; GFX11-NEXT: s_endpgm
523 %tid = call i32 @llvm.amdgcn.workitem.id.x()
524 %tid.ext = sext i32 %tid to i64
525 %in.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i64 %tid.ext
526 %out.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 %tid.ext
527 %vgpr = load <2 x i16>, ptr addrspace(1) %in.gep
528 %result = lshr <2 x i16> %vgpr, <i16 8, i16 8>
529 store <2 x i16> %result, ptr addrspace(1) %out.gep
530 ret void
531 }
533 define amdgpu_kernel void @v_lshr_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
534 ; GFX9-LABEL: v_lshr_v4i16:
535 ; GFX9: ; %bb.0:
536 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
537 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
538 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
539 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v4, s[6:7]
540 ; GFX9-NEXT: s_waitcnt vmcnt(0)
541 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1
542 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0
543 ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
544 ; GFX9-NEXT: s_endpgm
545 ;
546 ; VI-LABEL: v_lshr_v4i16:
547 ; VI: ; %bb.0:
548 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
549 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
550 ; VI-NEXT: s_waitcnt lgkmcnt(0)
551 ; VI-NEXT: v_mov_b32_e32 v1, s3
552 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
553 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
554 ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
555 ; VI-NEXT: v_mov_b32_e32 v5, s1
556 ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
557 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
558 ; VI-NEXT: s_waitcnt vmcnt(0)
559 ; VI-NEXT: v_lshrrev_b16_e32 v6, v3, v1
560 ; VI-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
561 ; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v0
562 ; VI-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
563 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
564 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
565 ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
566 ; VI-NEXT: s_endpgm
567 ;
568 ; CI-LABEL: v_lshr_v4i16:
569 ; CI: ; %bb.0:
570 ; CI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
571 ; CI-NEXT: s_mov_b32 s7, 0xf000
572 ; CI-NEXT: s_mov_b32 s6, 0
573 ; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
574 ; CI-NEXT: v_mov_b32_e32 v5, 0
575 ; CI-NEXT: s_waitcnt lgkmcnt(0)
576 ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
577 ; CI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
578 ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
579 ; CI-NEXT: s_waitcnt vmcnt(0)
580 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
581 ; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0
582 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
583 ; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1
584 ; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
585 ; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
586 ; CI-NEXT: v_lshrrev_b32_e32 v1, v3, v1
587 ; CI-NEXT: v_lshrrev_b32_e32 v3, v9, v7
588 ; CI-NEXT: v_lshrrev_b32_e32 v0, v2, v0
589 ; CI-NEXT: v_lshrrev_b32_e32 v2, v8, v6
590 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
591 ; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
592 ; CI-NEXT: v_or_b32_e32 v1, v1, v3
593 ; CI-NEXT: v_or_b32_e32 v0, v0, v2
594 ; CI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64
595 ; CI-NEXT: s_endpgm
596 ;
597 ; GFX10-LABEL: v_lshr_v4i16:
598 ; GFX10: ; %bb.0:
599 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
600 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
601 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
602 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v4, s[6:7]
603 ; GFX10-NEXT: s_waitcnt vmcnt(0)
604 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1
605 ; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0
606 ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
607 ; GFX10-NEXT: s_endpgm
608 ;
609 ; GFX11-LABEL: v_lshr_v4i16:
610 ; GFX11: ; %bb.0:
611 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
612 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
613 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
614 ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
615 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
616 ; GFX11-NEXT: global_load_b128 v[0:3], v4, s[2:3]
617 ; GFX11-NEXT: s_waitcnt vmcnt(0)
618 ; GFX11-NEXT: v_pk_lshrrev_b16 v1, v3, v1
619 ; GFX11-NEXT: v_pk_lshrrev_b16 v0, v2, v0
620 ; GFX11-NEXT: global_store_b64 v4, v[0:1], s[0:1]
621 ; GFX11-NEXT: s_nop 0
622 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
623 ; GFX11-NEXT: s_endpgm
624 %tid = call i32 @llvm.amdgcn.workitem.id.x()
625 %tid.ext = sext i32 %tid to i64
626 %in.gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %in, i64 %tid.ext
627 %out.gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %out, i64 %tid.ext
628 %b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %in.gep, i32 1
629 %a = load <4 x i16>, ptr addrspace(1) %in.gep
630 %b = load <4 x i16>, ptr addrspace(1) %b_ptr
631 %result = lshr <4 x i16> %a, %b
632 store <4 x i16> %result, ptr addrspace(1) %out.gep
633 ret void
634 }
636 define amdgpu_kernel void @lshr_v_imm_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
637 ; GFX9-LABEL: lshr_v_imm_v4i16:
638 ; GFX9: ; %bb.0:
639 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
640 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
641 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
642 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
643 ; GFX9-NEXT: s_waitcnt vmcnt(0)
644 ; GFX9-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
645 ; GFX9-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
646 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
647 ; GFX9-NEXT: s_endpgm
648 ;
649 ; VI-LABEL: lshr_v_imm_v4i16:
650 ; VI: ; %bb.0:
651 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
652 ; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
653 ; VI-NEXT: s_waitcnt lgkmcnt(0)
654 ; VI-NEXT: v_mov_b32_e32 v1, s3
655 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
656 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
657 ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
658 ; VI-NEXT: v_mov_b32_e32 v3, s1
659 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
660 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
661 ; VI-NEXT: s_waitcnt vmcnt(0)
662 ; VI-NEXT: v_lshrrev_b32_e32 v4, 24, v1
663 ; VI-NEXT: v_lshrrev_b32_e32 v5, 24, v0
664 ; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
665 ; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
666 ; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
667 ; VI-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
668 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
669 ; VI-NEXT: s_endpgm
670 ;
671 ; CI-LABEL: lshr_v_imm_v4i16:
672 ; CI: ; %bb.0:
673 ; CI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
674 ; CI-NEXT: s_mov_b32 s7, 0xf000
675 ; CI-NEXT: s_mov_b32 s6, 0
676 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
677 ; CI-NEXT: v_mov_b32_e32 v1, 0
678 ; CI-NEXT: s_waitcnt lgkmcnt(0)
679 ; CI-NEXT: s_mov_b64 s[4:5], s[2:3]
680 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
681 ; CI-NEXT: s_mov_b64 s[2:3], s[6:7]
682 ; CI-NEXT: s_waitcnt vmcnt(0)
683 ; CI-NEXT: v_lshrrev_b32_e32 v3, 8, v3
684 ; CI-NEXT: v_lshrrev_b32_e32 v2, 8, v2
685 ; CI-NEXT: v_and_b32_e32 v3, 0xff00ff, v3
686 ; CI-NEXT: v_and_b32_e32 v2, 0xff00ff, v2
687 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
688 ; CI-NEXT: s_endpgm
689 ;
690 ; GFX10-LABEL: lshr_v_imm_v4i16:
691 ; GFX10: ; %bb.0:
692 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
693 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0
694 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
695 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[6:7]
696 ; GFX10-NEXT: s_waitcnt vmcnt(0)
697 ; GFX10-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
698 ; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
699 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
700 ; GFX10-NEXT: s_endpgm
701 ;
702 ; GFX11-LABEL: lshr_v_imm_v4i16:
703 ; GFX11: ; %bb.0:
704 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
705 ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
706 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
707 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
708 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
709 ; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
710 ; GFX11-NEXT: s_waitcnt vmcnt(0)
711 ; GFX11-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]
712 ; GFX11-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]
713 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
714 ; GFX11-NEXT: s_nop 0
715 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
716 ; GFX11-NEXT: s_endpgm
717 %tid = call i32 @llvm.amdgcn.workitem.id.x()
718 %tid.ext = sext i32 %tid to i64
719 %in.gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %in, i64 %tid.ext
720 %out.gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %out, i64 %tid.ext
721 %vgpr = load <4 x i16>, ptr addrspace(1) %in.gep
722 %result = lshr <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
723 store <4 x i16> %result, ptr addrspace(1) %out.gep
724 ret void
725 }
727 declare i32 @llvm.amdgcn.workitem.id.x() #1
729 attributes #0 = { nounwind }
730 attributes #1 = { nounwind readnone }