llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
   3
   4 ---
   5 name:            global_load_saddr_to_valu
   6 tracksRegLiveness: true
   7 body:             |
   8   ; GCN-LABEL: name: global_load_saddr_to_valu
   9   ; GCN: bb.0:
  10   ; GCN-NEXT:   successors: %bb.1(0x80000000)
  11   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
  12   ; GCN-NEXT: {{  $}}
  13   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  14   ; GCN-NEXT: {{  $}}
  15   ; GCN-NEXT: bb.1:
  16   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  17   ; GCN-NEXT: {{  $}}
  18   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
  19   ; GCN-NEXT:   [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[PHI]], 0, 0, implicit $exec
  20   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  21   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  22   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  23   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  24   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  25   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
  26   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
  27   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  28   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  29   ; GCN-NEXT: {{  $}}
  30   ; GCN-NEXT: bb.2:
  31   ; GCN-NEXT:   S_ENDPGM 0
  32   bb.0:
  33     liveins: $vgpr0_vgpr1
  34       %0:sreg_64 = COPY $vgpr0_vgpr1
  35
  36   bb.1:
  37       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
  38       %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  39       %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec
  40       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
  41       S_CMP_LG_U64 %2, 0, implicit-def $scc
  42       S_CBRANCH_SCC1 %bb.1, implicit $scc
  43
  44   bb.2:
  45       S_ENDPGM 0
  46 ...
  47
  48 ---
  49 name:            global_load_saddr_to_valu_non_zero_vaddr
  50 tracksRegLiveness: true
  51 body:             |
  52   ; GCN-LABEL: name: global_load_saddr_to_valu_non_zero_vaddr
  53   ; GCN: bb.0:
  54   ; GCN-NEXT:   successors: %bb.1(0x80000000)
  55   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
  56   ; GCN-NEXT: {{  $}}
  57   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  58   ; GCN-NEXT: {{  $}}
  59   ; GCN-NEXT: bb.1:
  60   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  61   ; GCN-NEXT: {{  $}}
  62   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
  63   ; GCN-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
  64   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
  65   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
  66   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  67   ; GCN-NEXT:   [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
  68   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  69   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  70   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  71   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  72   ; GCN-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  73   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
  74   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
  75   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  76   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  77   ; GCN-NEXT: {{  $}}
  78   ; GCN-NEXT: bb.2:
  79   ; GCN-NEXT:   S_ENDPGM 0
  80   bb.0:
  81     liveins: $vgpr0_vgpr1
  82       %0:sreg_64 = COPY $vgpr0_vgpr1
  83
  84   bb.1:
  85       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
  86       %3:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
  87       %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec
  88       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
  89       S_CMP_LG_U64 %2, 0, implicit-def $scc
  90       S_CBRANCH_SCC1 %bb.1, implicit $scc
  91
  92   bb.2:
  93       S_ENDPGM 0
  94 ...
  95
  96
  97 ---
  98 name:            global_load_saddr_to_valu_undef_vaddr
  99 tracksRegLiveness: true
 100 body:             |
 101   ; GCN-LABEL: name: global_load_saddr_to_valu_undef_vaddr
 102   ; GCN: bb.0:
 103   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 104   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
 105   ; GCN-NEXT: {{  $}}
 106   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 107   ; GCN-NEXT: {{  $}}
 108   ; GCN-NEXT: bb.1:
 109   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 110   ; GCN-NEXT: {{  $}}
 111   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
 112   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
 113   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
 114   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
 115   ; GCN-NEXT:   [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], undef %4:vgpr_32, 0, 0, implicit $exec
 116   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
 117   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
 118   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
 119   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
 120   ; GCN-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 121   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
 122   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
 123   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
 124   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 125   ; GCN-NEXT: {{  $}}
 126   ; GCN-NEXT: bb.2:
 127   ; GCN-NEXT:   S_ENDPGM 0
 128   bb.0:
 129     liveins: $vgpr0_vgpr1
 130       %0:sreg_64 = COPY $vgpr0_vgpr1
 131
 132   bb.1:
 133       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
 134       %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, undef %3:vgpr_32, 0, 0, implicit $exec
 135       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
 136       S_CMP_LG_U64 %2, 0, implicit-def $scc
 137       S_CBRANCH_SCC1 %bb.1, implicit $scc
 138
 139   bb.2:
 140       S_ENDPGM 0
 141 ...
 142
 143 ---
 144 name:            global_store_saddr_to_valu
 145 tracksRegLiveness: true
 146 body:             |
 147   ; GCN-LABEL: name: global_store_saddr_to_valu
 148   ; GCN: bb.0:
 149   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 150   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
 151   ; GCN-NEXT: {{  $}}
 152   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 153   ; GCN-NEXT: {{  $}}
 154   ; GCN-NEXT: bb.1:
 155   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 156   ; GCN-NEXT: {{  $}}
 157   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
 158   ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
 159   ; GCN-NEXT:   GLOBAL_STORE_DWORD [[PHI]], [[DEF]], 0, 0, implicit $exec
 160   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
 161   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
 162   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
 163   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
 164   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 165   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
 166   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
 167   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
 168   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 169   ; GCN-NEXT: {{  $}}
 170   ; GCN-NEXT: bb.2:
 171   ; GCN-NEXT:   S_ENDPGM 0
 172   bb.0:
 173     liveins: $vgpr0_vgpr1
 174       %0:sreg_64 = COPY $vgpr0_vgpr1
 175
 176   bb.1:
 177       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
 178       %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 179       %4:vgpr_32 = IMPLICIT_DEF
 180       GLOBAL_STORE_DWORD_SADDR %3, %4, %1, 0, 0, implicit $exec
 181       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
 182       S_CMP_LG_U64 %2, 0, implicit-def $scc
 183       S_CBRANCH_SCC1 %bb.1, implicit $scc
 184
 185   bb.2:
 186       S_ENDPGM 0
 187 ...
 188
 189 ---
 190 name:            global_addtid_load_saddr_to_valu
 191 tracksRegLiveness: true
 192 body:             |
 193   ; GCN-LABEL: name: global_addtid_load_saddr_to_valu
 194   ; GCN: bb.0:
 195   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 196   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
 197   ; GCN-NEXT: {{  $}}
 198   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 199   ; GCN-NEXT: {{  $}}
 200   ; GCN-NEXT: bb.1:
 201   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 202   ; GCN-NEXT: {{  $}}
 203   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
 204   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
 205   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
 206   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
 207   ; GCN-NEXT:   [[GLOBAL_LOAD_DWORD_ADDTID_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR [[REG_SEQUENCE]], 0, 0, implicit $exec
 208   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
 209   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
 210   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
 211   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
 212   ; GCN-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 213   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
 214   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
 215   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
 216   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 217   ; GCN-NEXT: {{  $}}
 218   ; GCN-NEXT: bb.2:
 219   ; GCN-NEXT:   S_ENDPGM 0
 220   bb.0:
 221     liveins: $vgpr0_vgpr1
 222       %0:sreg_64 = COPY $vgpr0_vgpr1
 223
 224   bb.1:
 225       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
 226       %4:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR %1, 0, 0, implicit $exec
 227       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
 228       S_CMP_LG_U64 %2, 0, implicit-def $scc
 229       S_CBRANCH_SCC1 %bb.1, implicit $scc
 230
 231   bb.2:
 232       S_ENDPGM 0
 233 ...
 234
 235 ---
 236 name:            global_store_addtid_saddr_to_valu
 237 tracksRegLiveness: true
 238 body:             |
 239   ; GCN-LABEL: name: global_store_addtid_saddr_to_valu
 240   ; GCN: bb.0:
 241   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 242   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
 243   ; GCN-NEXT: {{  $}}
 244   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 245   ; GCN-NEXT: {{  $}}
 246   ; GCN-NEXT: bb.1:
 247   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 248   ; GCN-NEXT: {{  $}}
 249   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
 250   ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
 251   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
 252   ; GCN-NEXT:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
 253   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
 254   ; GCN-NEXT:   GLOBAL_STORE_DWORD_ADDTID_SADDR [[DEF]], [[REG_SEQUENCE]], 0, 0, implicit $exec
 255   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
 256   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
 257   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
 258   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
 259   ; GCN-NEXT:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 260   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
 261   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
 262   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
 263   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 264   ; GCN-NEXT: {{  $}}
 265   ; GCN-NEXT: bb.2:
 266   ; GCN-NEXT:   S_ENDPGM 0
 267   bb.0:
 268     liveins: $vgpr0_vgpr1
 269       %0:sreg_64 = COPY $vgpr0_vgpr1
 270
 271   bb.1:
 272       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
 273       %4:vgpr_32 = IMPLICIT_DEF
 274       GLOBAL_STORE_DWORD_ADDTID_SADDR %4, %1, 0, 0, implicit $exec
 275       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
 276       S_CMP_LG_U64 %2, 0, implicit-def $scc
 277       S_CBRANCH_SCC1 %bb.1, implicit $scc
 278
 279   bb.2:
 280       S_ENDPGM 0
 281 ...
 282
 283 ---
 284 name:            global_atomic_noret_saddr_to_valu
 285 tracksRegLiveness: true
 286 body:             |
 287   ; GCN-LABEL: name: global_atomic_noret_saddr_to_valu
 288   ; GCN: bb.0:
 289   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 290   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
 291   ; GCN-NEXT: {{  $}}
 292   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 293   ; GCN-NEXT: {{  $}}
 294   ; GCN-NEXT: bb.1:
 295   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 296   ; GCN-NEXT: {{  $}}
 297   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
 298   ; GCN-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 299   ; GCN-NEXT:   GLOBAL_ATOMIC_ADD [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
 300   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
 301   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
 302   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
 303   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
 304   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 305   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
 306   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
 307   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
 308   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 309   ; GCN-NEXT: {{  $}}
 310   ; GCN-NEXT: bb.2:
 311   ; GCN-NEXT:   S_ENDPGM 0
 312   bb.0:
 313     liveins: $vgpr0_vgpr1
 314       %0:sreg_64 = COPY $vgpr0_vgpr1
 315
 316   bb.1:
 317       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
 318       %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 319       GLOBAL_ATOMIC_ADD_SADDR %3, %3, %1, 0, 0, implicit $exec
 320       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
 321       S_CMP_LG_U64 %2, 0, implicit-def $scc
 322       S_CBRANCH_SCC1 %bb.1, implicit $scc
 323
 324   bb.2:
 325       S_ENDPGM 0
 326 ...
 327
 328 ---
 329 name:            global_atomic_rtn_saddr_to_valu
 330 tracksRegLiveness: true
 331 body:             |
 332   ; GCN-LABEL: name: global_atomic_rtn_saddr_to_valu
 333   ; GCN: bb.0:
 334   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 335   ; GCN-NEXT:   liveins: $vgpr0_vgpr1
 336   ; GCN-NEXT: {{  $}}
 337   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 338   ; GCN-NEXT: {{  $}}
 339   ; GCN-NEXT: bb.1:
 340   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 341   ; GCN-NEXT: {{  $}}
 342   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
 343   ; GCN-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 344   ; GCN-NEXT:   [[GLOBAL_ATOMIC_ADD_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_RTN [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
 345   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
 346   ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
 347   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
 348   ; GCN-NEXT:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
 349   ; GCN-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
 350   ; GCN-NEXT:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
 351   ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
 352   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
 353   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 354   ; GCN-NEXT: {{  $}}
 355   ; GCN-NEXT: bb.2:
 356   ; GCN-NEXT:   S_ENDPGM 0
 357   bb.0:
 358     liveins: $vgpr0_vgpr1
 359       %0:sreg_64 = COPY $vgpr0_vgpr1
 360
 361   bb.1:
 362       %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
 363       %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
 364       %4:vgpr_32 = GLOBAL_ATOMIC_ADD_SADDR_RTN %3, %3, %1, 0, 0, implicit $exec
 365       %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
 366       S_CMP_LG_U64 %2, 0, implicit-def $scc
 367       S_CBRANCH_SCC1 %bb.1, implicit $scc
 368
 369   bb.2:
 370       S_ENDPGM 0
 371 ...
 372
 373 ---
 374 name:            scratch_load_saddr_to_valu
 375 tracksRegLiveness: true
 376 body:             |
 377   ; GCN-LABEL: name: scratch_load_saddr_to_valu
 378   ; GCN: bb.0:
 379   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 380   ; GCN-NEXT:   liveins: $vgpr0
 381   ; GCN-NEXT: {{  $}}
 382   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 383   ; GCN-NEXT: {{  $}}
 384   ; GCN-NEXT: bb.1:
 385   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 386   ; GCN-NEXT: {{  $}}
 387   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
 388   ; GCN-NEXT:   [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
 389   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
 390   ; GCN-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
 391   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
 392   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc
 393   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 394   ; GCN-NEXT: {{  $}}
 395   ; GCN-NEXT: bb.2:
 396   ; GCN-NEXT:   S_ENDPGM 0
 397   bb.0:
 398     liveins: $vgpr0
 399       %0:sgpr_32 = COPY $vgpr0
 400
 401   bb.1:
 402       %1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
 403       %4:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %1, 0, 0, implicit $exec, implicit $flat_scr
 404       %2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
 405       S_CMP_LG_U32 %2, 0, implicit-def $scc
 406       S_CBRANCH_SCC1 %bb.1, implicit $scc
 407
 408   bb.2:
 409       S_ENDPGM 0
 410 ...
 411
 412 ---
 413 name:            scratch_store_saddr_to_valu
 414 tracksRegLiveness: true
 415 body:             |
 416   ; GCN-LABEL: name: scratch_store_saddr_to_valu
 417   ; GCN: bb.0:
 418   ; GCN-NEXT:   successors: %bb.1(0x80000000)
 419   ; GCN-NEXT:   liveins: $vgpr0
 420   ; GCN-NEXT: {{  $}}
 421   ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 422   ; GCN-NEXT: {{  $}}
 423   ; GCN-NEXT: bb.1:
 424   ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 425   ; GCN-NEXT: {{  $}}
 426   ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
 427   ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
 428   ; GCN-NEXT:   SCRATCH_STORE_DWORD [[DEF]], [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
 429   ; GCN-NEXT:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
 430   ; GCN-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
 431   ; GCN-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
 432   ; GCN-NEXT:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc
 433   ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
 434   ; GCN-NEXT: {{  $}}
 435   ; GCN-NEXT: bb.2:
 436   ; GCN-NEXT:   S_ENDPGM 0
 437   bb.0:
 438     liveins: $vgpr0
 439       %0:sgpr_32 = COPY $vgpr0
 440
 441   bb.1:
 442       %1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
 443       %4:vgpr_32 = IMPLICIT_DEF
 444       SCRATCH_STORE_DWORD_SADDR %4, %1, 0, 0, implicit $exec, implicit $flat_scr
 445       %2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
 446       S_CMP_LG_U32 %2, 0, implicit-def $scc
 447       S_CBRANCH_SCC1 %bb.1, implicit $scc
 448
 449   bb.2:
 450       S_ENDPGM 0
 451 ...