llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX8 %s
   3 # RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX12 %s
   4
   5 ---
   6 name:            lshlrev_b64
   7 body:             |
   8   bb.0:
   9     ; GFX8-LABEL: name: lshlrev_b64
  10     ; GFX8: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  11     ; GFX8-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  12     ; GFX8-NEXT: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  13     ; GFX8-NEXT: [[V_LSHL_ADD_U64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_ADD_U64_e64 [[DEF]], [[DEF1]], [[DEF2]], implicit $exec
  14     ; GFX8-NEXT: [[DEF3:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  15     ; GFX8-NEXT: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  16     ; GFX8-NEXT: [[V_LSHLREV_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_e64 [[DEF4]], [[V_LSHL_ADD_U64_e64_]], implicit $exec
  17     ;
  18     ; GFX12-LABEL: name: lshlrev_b64
  19     ; GFX12: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  20     ; GFX12-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  21     ; GFX12-NEXT: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  22     ; GFX12-NEXT: [[V_LSHL_ADD_U64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_ADD_U64_e64 [[DEF]], [[DEF1]], [[DEF2]], implicit $exec
  23     ; GFX12-NEXT: [[DEF3:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  24     ; GFX12-NEXT: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  25     ; GFX12-NEXT: [[V_LSHLREV_B64_pseudo_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_pseudo_e64 [[DEF4]], [[V_LSHL_ADD_U64_e64_]], implicit $exec
  26     %0:vreg_64 = IMPLICIT_DEF
  27     %1:vgpr_32 = IMPLICIT_DEF
  28     %2:vreg_64 = IMPLICIT_DEF
  29     %3:vreg_64 = V_LSHL_ADD_U64_e64 %0:vreg_64, %1:vgpr_32, %2:vreg_64, implicit $exec
  30     %4:sreg_64 = COPY %3:vreg_64
  31     %5:sreg_32 = IMPLICIT_DEF
  32     %6:sreg_64 = S_LSHL_B64 killed %4:sreg_64, %5:sreg_32, implicit-def dead $scc
  33 ...