llvm/test/CodeGen/AMDGPU/regcoalesce-cannot-join-failures.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s
   3
   4 ---
   5 name: couldnt_join_subrange_implicit_def_pred_block
   6 tracksRegLiveness: true
   7 body:             |
   8   ; CHECK-LABEL: name: couldnt_join_subrange_implicit_def_pred_block
   9   ; CHECK: bb.0:
  10   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  11   ; CHECK-NEXT: {{  $}}
  12   ; CHECK-NEXT:   undef [[DEF:%[0-9]+]].sub0:sreg_64_xexec = IMPLICIT_DEF
  13   ; CHECK-NEXT: {{  $}}
  14   ; CHECK-NEXT: bb.1:
  15   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  16   ; CHECK-NEXT: {{  $}}
  17   ; CHECK-NEXT:   [[DEF:%[0-9]+]].sub1:sreg_64_xexec = COPY [[DEF]].sub0
  18   ; CHECK-NEXT:   S_BRANCH %bb.2
  19   ; CHECK-NEXT: {{  $}}
  20   ; CHECK-NEXT: bb.2:
  21   ; CHECK-NEXT:   S_ENDPGM 0, implicit [[DEF]]
  22   bb.0:
  23     successors: %bb.1
  24
  25     undef %0.sub0:sreg_64_xexec = IMPLICIT_DEF
  26
  27   bb.1:
  28     successors: %bb.2
  29
  30     %1:sreg_64 = COPY %0:sreg_64_xexec
  31     %0.sub1:sreg_64_xexec = COPY %0.sub0:sreg_64_xexec
  32     S_BRANCH %bb.2
  33
  34   bb.2:
  35     dead %2:sreg_32_xm0 = COPY %0.sub0:sreg_64_xexec
  36     S_ENDPGM 0, implicit killed %1
  37
  38 ...
  39 ---
  40 name: couldnt_join_subrange_no_implicit_def_inst
  41 tracksRegLiveness: true
  42 body:             |
  43   bb.0:
  44     ; CHECK-LABEL: name: couldnt_join_subrange_no_implicit_def_inst
  45     ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64 = S_MOV_B32 0
  46     ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64 = COPY [[S_MOV_B32_]].sub0
  47     ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]].sub1
  48     undef %0.sub0:sreg_64 = S_MOV_B32 0
  49     %1:sreg_64 = COPY %0:sreg_64
  50     %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
  51     S_ENDPGM 0, implicit %1.sub1:sreg_64
  52
  53 ...
  54 ---
  55 name: couldnt_join_subrange0
  56 tracksRegLiveness: true
  57 body:             |
  58   ; CHECK-LABEL: name: couldnt_join_subrange0
  59   ; CHECK: bb.0:
  60   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  61   ; CHECK-NEXT: {{  $}}
  62   ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64 = S_MOV_B32 -1
  63   ; CHECK-NEXT: {{  $}}
  64   ; CHECK-NEXT: bb.1:
  65   ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64 = S_MOV_B32 0
  66   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY [[S_MOV_B32_]]
  67   ; CHECK-NEXT:   dead [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64 = COPY [[S_MOV_B32_]].sub0
  68   ; CHECK-NEXT:   S_ENDPGM 0, implicit [[COPY]].sub1
  69   bb.0:
  70     successors: %bb.1
  71     undef %0.sub1:sreg_64 = S_MOV_B32 -1
  72
  73   bb.1:
  74     %0.sub0:sreg_64 = S_MOV_B32 0
  75     %1:sreg_64 = COPY %0:sreg_64
  76     dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
  77     S_ENDPGM 0, implicit %1.sub1:sreg_64
  78
  79 ...
  80 ---
  81 name: lanes_not_tracked_subreg_join_couldnt_join_subrange
  82 tracksRegLiveness: true
  83 body:             |
  84   bb.0:
  85
  86     ; CHECK-LABEL: name: lanes_not_tracked_subreg_join_couldnt_join_subrange
  87     ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 0
  88     ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = S_MOV_B32 0
  89     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub1
  90     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
  91     ; CHECK-NEXT: S_ENDPGM 0
  92     undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
  93     %1:sreg_64 = COPY %0
  94     %0.sub1:sreg_64_xexec = S_MOV_B32 0
  95     S_NOP 0, implicit %0.sub1
  96     S_NOP 0, implicit %1
  97     S_ENDPGM 0
  98
  99 ...
 100 ---
 101 name: couldnt_join_subrange1
 102 tracksRegLiveness: true
 103 body:             |
 104   ; CHECK-LABEL: name: couldnt_join_subrange1
 105   ; CHECK: bb.0:
 106   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
 107   ; CHECK-NEXT: {{  $}}
 108   ; CHECK-NEXT:   undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 0
 109   ; CHECK-NEXT:   [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_MOV_B32_]].sub0
 110   ; CHECK-NEXT: {{  $}}
 111   ; CHECK-NEXT: bb.1:
 112   ; CHECK-NEXT:   S_NOP 0, implicit [[S_MOV_B32_]].sub1
 113   ; CHECK-NEXT:   S_ENDPGM 0, implicit [[S_MOV_B32_]]
 114   bb.0:
 115     successors: %bb.1
 116
 117     undef %0.sub0:sreg_64_xexec = S_MOV_B32 0
 118     %1:sreg_64 = COPY %0
 119     %0.sub1:sreg_64_xexec = COPY %0.sub0
 120
 121   bb.1:
 122
 123     S_NOP 0, implicit %0.sub1
 124     S_ENDPGM 0, implicit %1
 125
 126 ...