| blob | f692584ef92be257b6c88c8d4b9a7c69788cd1e7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s
3 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
6 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
8 define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
9 ; R600-LABEL: rotl_i32:
10 ; R600: ; %bb.0: ; %entry
11 ; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
12 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
13 ; R600-NEXT: CF_END
14 ; R600-NEXT: PAD
15 ; R600-NEXT: ALU clause starting at 4:
16 ; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[2].W,
17 ; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
18 ; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[2].Z, KC0[2].Z, PV.W,
19 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
20 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
21 ;
22 ; SI-LABEL: rotl_i32:
23 ; SI: ; %bb.0: ; %entry
24 ; SI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
25 ; SI-NEXT: s_mov_b32 s7, 0xf000
26 ; SI-NEXT: s_waitcnt lgkmcnt(0)
27 ; SI-NEXT: s_sub_i32 s3, 32, s3
28 ; SI-NEXT: s_mov_b32 s6, -1
29 ; SI-NEXT: s_mov_b32 s4, s0
30 ; SI-NEXT: s_mov_b32 s5, s1
31 ; SI-NEXT: v_mov_b32_e32 v0, s3
32 ; SI-NEXT: v_alignbit_b32 v0, s2, s2, v0
33 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
34 ; SI-NEXT: s_endpgm
35 ;
36 ; GFX8-LABEL: rotl_i32:
37 ; GFX8: ; %bb.0: ; %entry
38 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
39 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
40 ; GFX8-NEXT: s_sub_i32 s3, 32, s3
41 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
42 ; GFX8-NEXT: v_alignbit_b32 v2, s2, s2, v0
43 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
44 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
45 ; GFX8-NEXT: flat_store_dword v[0:1], v2
46 ; GFX8-NEXT: s_endpgm
47 ;
48 ; GFX10-LABEL: rotl_i32:
49 ; GFX10: ; %bb.0: ; %entry
50 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
51 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
52 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
53 ; GFX10-NEXT: s_sub_i32 s0, 32, s7
54 ; GFX10-NEXT: v_alignbit_b32 v1, s6, s6, s0
55 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
56 ; GFX10-NEXT: s_endpgm
57 ;
58 ; GFX11-LABEL: rotl_i32:
59 ; GFX11: ; %bb.0: ; %entry
60 ; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
61 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
62 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
63 ; GFX11-NEXT: s_sub_i32 s3, 32, s3
64 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
65 ; GFX11-NEXT: v_alignbit_b32 v1, s2, s2, s3
66 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
67 ; GFX11-NEXT: s_nop 0
68 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
69 ; GFX11-NEXT: s_endpgm
70 entry:
71 %0 = shl i32 %x, %y
72 %1 = sub i32 32, %y
73 %2 = lshr i32 %x, %1
74 %3 = or i32 %0, %2
75 store i32 %3, ptr addrspace(1) %in
76 ret void
77 }
79 define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
80 ; R600-LABEL: rotl_v2i32:
81 ; R600: ; %bb.0: ; %entry
82 ; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
83 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
84 ; R600-NEXT: CF_END
85 ; R600-NEXT: PAD
86 ; R600-NEXT: ALU clause starting at 4:
87 ; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[3].Z,
88 ; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
89 ; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].X, PV.W,
90 ; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[3].Y,
91 ; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
92 ; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[2].W, KC0[2].W, PV.W,
93 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
94 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
95 ;
96 ; SI-LABEL: rotl_v2i32:
97 ; SI: ; %bb.0: ; %entry
98 ; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0xb
99 ; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
100 ; SI-NEXT: s_mov_b32 s3, 0xf000
101 ; SI-NEXT: s_mov_b32 s2, -1
102 ; SI-NEXT: s_waitcnt lgkmcnt(0)
103 ; SI-NEXT: s_sub_i32 s7, 32, s7
104 ; SI-NEXT: s_sub_i32 s6, 32, s6
105 ; SI-NEXT: v_mov_b32_e32 v0, s7
106 ; SI-NEXT: v_alignbit_b32 v1, s5, s5, v0
107 ; SI-NEXT: v_mov_b32_e32 v0, s6
108 ; SI-NEXT: v_alignbit_b32 v0, s4, s4, v0
109 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
110 ; SI-NEXT: s_endpgm
111 ;
112 ; GFX8-LABEL: rotl_v2i32:
113 ; GFX8: ; %bb.0: ; %entry
114 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x2c
115 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
116 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
117 ; GFX8-NEXT: s_sub_i32 s2, 32, s6
118 ; GFX8-NEXT: s_sub_i32 s3, 32, s7
119 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
120 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
121 ; GFX8-NEXT: v_alignbit_b32 v1, s5, s5, v0
122 ; GFX8-NEXT: v_alignbit_b32 v0, s4, s4, v2
123 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
124 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
125 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
126 ; GFX8-NEXT: s_endpgm
127 ;
128 ; GFX10-LABEL: rotl_v2i32:
129 ; GFX10: ; %bb.0: ; %entry
130 ; GFX10-NEXT: s_clause 0x1
131 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x2c
132 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
133 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
134 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
135 ; GFX10-NEXT: s_sub_i32 s2, 32, s7
136 ; GFX10-NEXT: s_sub_i32 s3, 32, s6
137 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s5, s2
138 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s4, s3
139 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
140 ; GFX10-NEXT: s_endpgm
141 ;
142 ; GFX11-LABEL: rotl_v2i32:
143 ; GFX11: ; %bb.0: ; %entry
144 ; GFX11-NEXT: s_clause 0x1
145 ; GFX11-NEXT: s_load_b128 s[4:7], s[2:3], 0x2c
146 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
147 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
148 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
149 ; GFX11-NEXT: s_sub_i32 s2, 32, s7
150 ; GFX11-NEXT: s_sub_i32 s3, 32, s6
151 ; GFX11-NEXT: v_alignbit_b32 v1, s5, s5, s2
152 ; GFX11-NEXT: v_alignbit_b32 v0, s4, s4, s3
153 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
154 ; GFX11-NEXT: s_nop 0
155 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
156 ; GFX11-NEXT: s_endpgm
157 entry:
158 %0 = shl <2 x i32> %x, %y
159 %1 = sub <2 x i32> <i32 32, i32 32>, %y
160 %2 = lshr <2 x i32> %x, %1
161 %3 = or <2 x i32> %0, %2
162 store <2 x i32> %3, ptr addrspace(1) %in
163 ret void
164 }
166 define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
167 ; R600-LABEL: rotl_v4i32:
168 ; R600: ; %bb.0: ; %entry
169 ; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
170 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
171 ; R600-NEXT: CF_END
172 ; R600-NEXT: PAD
173 ; R600-NEXT: ALU clause starting at 4:
174 ; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[5].X,
175 ; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
176 ; R600-NEXT: BIT_ALIGN_INT T0.W, KC0[4].X, KC0[4].X, PV.W,
177 ; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].W,
178 ; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
179 ; R600-NEXT: BIT_ALIGN_INT T0.Z, KC0[3].W, KC0[3].W, PS,
180 ; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].Z,
181 ; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
182 ; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].Z, KC0[3].Z, PV.W,
183 ; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].Y,
184 ; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)
185 ; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[3].Y, KC0[3].Y, PV.W,
186 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
187 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
188 ;
189 ; SI-LABEL: rotl_v4i32:
190 ; SI: ; %bb.0: ; %entry
191 ; SI-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0xd
192 ; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
193 ; SI-NEXT: s_mov_b32 s3, 0xf000
194 ; SI-NEXT: s_mov_b32 s2, -1
195 ; SI-NEXT: s_waitcnt lgkmcnt(0)
196 ; SI-NEXT: s_sub_i32 s8, 32, s8
197 ; SI-NEXT: s_sub_i32 s9, 32, s9
198 ; SI-NEXT: s_sub_i32 s11, 32, s11
199 ; SI-NEXT: s_sub_i32 s10, 32, s10
200 ; SI-NEXT: v_mov_b32_e32 v0, s11
201 ; SI-NEXT: v_alignbit_b32 v3, s7, s7, v0
202 ; SI-NEXT: v_mov_b32_e32 v0, s10
203 ; SI-NEXT: v_alignbit_b32 v2, s6, s6, v0
204 ; SI-NEXT: v_mov_b32_e32 v0, s9
205 ; SI-NEXT: v_alignbit_b32 v1, s5, s5, v0
206 ; SI-NEXT: v_mov_b32_e32 v0, s8
207 ; SI-NEXT: v_alignbit_b32 v0, s4, s4, v0
208 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
209 ; SI-NEXT: s_endpgm
210 ;
211 ; GFX8-LABEL: rotl_v4i32:
212 ; GFX8: ; %bb.0: ; %entry
213 ; GFX8-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x34
214 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
215 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
216 ; GFX8-NEXT: s_sub_i32 s3, 32, s9
217 ; GFX8-NEXT: s_sub_i32 s9, 32, s11
218 ; GFX8-NEXT: s_sub_i32 s2, 32, s8
219 ; GFX8-NEXT: s_sub_i32 s8, 32, s10
220 ; GFX8-NEXT: v_mov_b32_e32 v0, s9
221 ; GFX8-NEXT: v_alignbit_b32 v3, s7, s7, v0
222 ; GFX8-NEXT: v_mov_b32_e32 v0, s8
223 ; GFX8-NEXT: v_alignbit_b32 v2, s6, s6, v0
224 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
225 ; GFX8-NEXT: v_alignbit_b32 v1, s5, s5, v0
226 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
227 ; GFX8-NEXT: v_mov_b32_e32 v5, s1
228 ; GFX8-NEXT: v_alignbit_b32 v0, s4, s4, v0
229 ; GFX8-NEXT: v_mov_b32_e32 v4, s0
230 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
231 ; GFX8-NEXT: s_endpgm
232 ;
233 ; GFX10-LABEL: rotl_v4i32:
234 ; GFX10: ; %bb.0: ; %entry
235 ; GFX10-NEXT: s_clause 0x1
236 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x34
237 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
238 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
239 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
240 ; GFX10-NEXT: s_sub_i32 s2, 32, s8
241 ; GFX10-NEXT: s_sub_i32 s3, 32, s9
242 ; GFX10-NEXT: s_sub_i32 s8, 32, s11
243 ; GFX10-NEXT: s_sub_i32 s9, 32, s10
244 ; GFX10-NEXT: v_alignbit_b32 v3, s7, s7, s8
245 ; GFX10-NEXT: v_alignbit_b32 v2, s6, s6, s9
246 ; GFX10-NEXT: v_alignbit_b32 v1, s5, s5, s3
247 ; GFX10-NEXT: v_alignbit_b32 v0, s4, s4, s2
248 ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
249 ; GFX10-NEXT: s_endpgm
250 ;
251 ; GFX11-LABEL: rotl_v4i32:
252 ; GFX11: ; %bb.0: ; %entry
253 ; GFX11-NEXT: s_clause 0x1
254 ; GFX11-NEXT: s_load_b256 s[4:11], s[2:3], 0x34
255 ; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
256 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
257 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
258 ; GFX11-NEXT: s_sub_i32 s2, 32, s8
259 ; GFX11-NEXT: s_sub_i32 s3, 32, s9
260 ; GFX11-NEXT: s_sub_i32 s8, 32, s11
261 ; GFX11-NEXT: s_sub_i32 s9, 32, s10
262 ; GFX11-NEXT: v_alignbit_b32 v3, s7, s7, s8
263 ; GFX11-NEXT: v_alignbit_b32 v2, s6, s6, s9
264 ; GFX11-NEXT: v_alignbit_b32 v1, s5, s5, s3
265 ; GFX11-NEXT: v_alignbit_b32 v0, s4, s4, s2
266 ; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
267 ; GFX11-NEXT: s_nop 0
268 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
269 ; GFX11-NEXT: s_endpgm
270 entry:
271 %0 = shl <4 x i32> %x, %y
272 %1 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
273 %2 = lshr <4 x i32> %x, %1
274 %3 = or <4 x i32> %0, %2
275 store <4 x i32> %3, ptr addrspace(1) %in
276 ret void
277 }
279 declare i16 @llvm.fshl.i16(i16, i16, i16)
281 define void @test_rotl_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr addrspace(1) nocapture readonly %sourceB, ptr addrspace(1) nocapture %destValues) {
282 ; R600-LABEL: test_rotl_i16:
283 ; R600: ; %bb.0: ; %entry
284 ; R600-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
285 ; R600-NEXT: TEX 0 @8
286 ; R600-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
287 ; R600-NEXT: TEX 0 @10
288 ; R600-NEXT: ALU 21, @14, KC0[CB0:0-32], KC1[]
289 ; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X
290 ; R600-NEXT: CF_END
291 ; R600-NEXT: PAD
292 ; R600-NEXT: Fetch clause starting at 8:
293 ; R600-NEXT: VTX_READ_16 T0.X, T0.X, 48, #1
294 ; R600-NEXT: Fetch clause starting at 10:
295 ; R600-NEXT: VTX_READ_16 T1.X, T1.X, 32, #1
296 ; R600-NEXT: ALU clause starting at 12:
297 ; R600-NEXT: MOV * T0.X, KC0[2].Z,
298 ; R600-NEXT: ALU clause starting at 13:
299 ; R600-NEXT: MOV * T1.X, KC0[2].Y,
300 ; R600-NEXT: ALU clause starting at 14:
301 ; R600-NEXT: SUB_INT T0.W, 0.0, T0.X,
302 ; R600-NEXT: AND_INT * T1.W, T0.X, literal.x,
303 ; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
304 ; R600-NEXT: AND_INT * T0.W, PV.W, literal.x,
305 ; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
306 ; R600-NEXT: LSHR T0.Z, T1.X, PV.W,
307 ; R600-NEXT: LSHL T0.W, T1.X, T1.W,
308 ; R600-NEXT: ADD_INT * T1.W, KC0[2].W, literal.x,
309 ; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)
310 ; R600-NEXT: AND_INT T2.W, PS, literal.x,
311 ; R600-NEXT: OR_INT * T0.W, PV.W, PV.Z,
312 ; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)
313 ; R600-NEXT: AND_INT T0.W, PS, literal.x,
314 ; R600-NEXT: LSHL * T2.W, PV.W, literal.y,
315 ; R600-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
316 ; R600-NEXT: LSHL T0.X, PV.W, PS,
317 ; R600-NEXT: LSHL * T0.W, literal.x, PS,
318 ; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
319 ; R600-NEXT: MOV T0.Y, 0.0,
320 ; R600-NEXT: MOV * T0.Z, 0.0,
321 ; R600-NEXT: LSHR * T1.X, T1.W, literal.x,
322 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
323 ;
324 ; SI-LABEL: test_rotl_i16:
325 ; SI: ; %bb.0: ; %entry
326 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
327 ; SI-NEXT: s_mov_b32 s6, 0
328 ; SI-NEXT: s_mov_b32 s7, 0xf000
329 ; SI-NEXT: s_mov_b32 s4, s6
330 ; SI-NEXT: s_mov_b32 s5, s6
331 ; SI-NEXT: buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:48
332 ; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:32
333 ; SI-NEXT: s_waitcnt vmcnt(1)
334 ; SI-NEXT: v_and_b32_e32 v1, 15, v2
335 ; SI-NEXT: v_sub_i32_e32 v2, vcc, 0, v2
336 ; SI-NEXT: s_waitcnt vmcnt(0)
337 ; SI-NEXT: v_lshlrev_b32_e32 v1, v1, v0
338 ; SI-NEXT: v_and_b32_e32 v2, 15, v2
339 ; SI-NEXT: v_lshrrev_b32_e32 v0, v2, v0
340 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
341 ; SI-NEXT: buffer_store_short v0, v[4:5], s[4:7], 0 addr64 offset:8
342 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
343 ; SI-NEXT: s_setpc_b64 s[30:31]
344 ;
345 ; GFX8-LABEL: test_rotl_i16:
346 ; GFX8: ; %bb.0: ; %entry
347 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
348 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 32, v0
349 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
350 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 48, v2
351 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
352 ; GFX8-NEXT: flat_load_ushort v2, v[2:3]
353 ; GFX8-NEXT: flat_load_ushort v0, v[0:1]
354 ; GFX8-NEXT: s_waitcnt vmcnt(0)
355 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, v2, v0
356 ; GFX8-NEXT: v_sub_u16_e32 v2, 0, v2
357 ; GFX8-NEXT: v_lshrrev_b16_e32 v0, v2, v0
358 ; GFX8-NEXT: v_or_b32_e32 v2, v1, v0
359 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4
360 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
361 ; GFX8-NEXT: flat_store_short v[0:1], v2
362 ; GFX8-NEXT: s_waitcnt vmcnt(0)
363 ; GFX8-NEXT: s_setpc_b64 s[30:31]
364 ;
365 ; GFX10-LABEL: test_rotl_i16:
366 ; GFX10: ; %bb.0: ; %entry
367 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
368 ; GFX10-NEXT: global_load_ushort v6, v[2:3], off offset:48
369 ; GFX10-NEXT: global_load_ushort v7, v[0:1], off offset:32
370 ; GFX10-NEXT: s_waitcnt vmcnt(1)
371 ; GFX10-NEXT: v_sub_nc_u16 v0, 0, v6
372 ; GFX10-NEXT: s_waitcnt vmcnt(0)
373 ; GFX10-NEXT: v_lshlrev_b16 v1, v6, v7
374 ; GFX10-NEXT: v_lshrrev_b16 v0, v0, v7
375 ; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
376 ; GFX10-NEXT: global_store_short v[4:5], v0, off offset:8
377 ; GFX10-NEXT: s_setpc_b64 s[30:31]
378 ;
379 ; GFX11-LABEL: test_rotl_i16:
380 ; GFX11: ; %bb.0: ; %entry
381 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
382 ; GFX11-NEXT: global_load_u16 v2, v[2:3], off offset:48
383 ; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:32
384 ; GFX11-NEXT: s_waitcnt vmcnt(1)
385 ; GFX11-NEXT: v_sub_nc_u16 v1, 0, v2
386 ; GFX11-NEXT: s_waitcnt vmcnt(0)
387 ; GFX11-NEXT: v_lshlrev_b16 v2, v2, v0
388 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
389 ; GFX11-NEXT: v_lshrrev_b16 v0, v1, v0
390 ; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
391 ; GFX11-NEXT: global_store_b16 v[4:5], v0, off offset:8
392 ; GFX11-NEXT: s_setpc_b64 s[30:31]
393 entry:
394 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16
395 %a = load i16, ptr addrspace(1) %arrayidx
396 %arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %sourceB, i64 24
397 %b = load i16, ptr addrspace(1) %arrayidx2
398 %c = tail call i16 @llvm.fshl.i16(i16 %a, i16 %a, i16 %b)
399 %arrayidx5 = getelementptr inbounds i16, ptr addrspace(1) %destValues, i64 4
400 store i16 %c, ptr addrspace(1) %arrayidx5
401 ret void
402 }