| blob | 1700ce302cc9dbd89220377e029a4c09723f6d9e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI
3 ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI
5 ; XXX - Why the packing?
6 define amdgpu_kernel void @scalar_to_vector_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
7 ; SI-LABEL: scalar_to_vector_v2i32:
8 ; SI: ; %bb.0:
9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
10 ; SI-NEXT: s_mov_b32 s7, 0xf000
11 ; SI-NEXT: s_mov_b32 s6, -1
12 ; SI-NEXT: s_mov_b32 s10, s6
13 ; SI-NEXT: s_mov_b32 s11, s7
14 ; SI-NEXT: s_waitcnt lgkmcnt(0)
15 ; SI-NEXT: s_mov_b32 s8, s2
16 ; SI-NEXT: s_mov_b32 s9, s3
17 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
18 ; SI-NEXT: s_waitcnt vmcnt(0)
19 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
20 ; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
21 ; SI-NEXT: s_mov_b32 s4, s0
22 ; SI-NEXT: s_mov_b32 s5, s1
23 ; SI-NEXT: v_mov_b32_e32 v1, v0
24 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
25 ; SI-NEXT: s_endpgm
26 ;
27 ; VI-LABEL: scalar_to_vector_v2i32:
28 ; VI: ; %bb.0:
29 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
30 ; VI-NEXT: s_mov_b32 s7, 0xf000
31 ; VI-NEXT: s_mov_b32 s6, -1
32 ; VI-NEXT: s_mov_b32 s10, s6
33 ; VI-NEXT: s_mov_b32 s11, s7
34 ; VI-NEXT: s_waitcnt lgkmcnt(0)
35 ; VI-NEXT: s_mov_b32 s8, s2
36 ; VI-NEXT: s_mov_b32 s9, s3
37 ; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
38 ; VI-NEXT: s_mov_b32 s4, s0
39 ; VI-NEXT: s_mov_b32 s5, s1
40 ; VI-NEXT: s_waitcnt vmcnt(0)
41 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
42 ; VI-NEXT: v_alignbit_b32 v0, v1, v0, 16
43 ; VI-NEXT: v_mov_b32_e32 v1, v0
44 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
45 ; VI-NEXT: s_endpgm
46 %tmp1 = load i32, ptr addrspace(1) %in, align 4
47 %bc = bitcast i32 %tmp1 to <2 x i16>
48 %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
49 store <4 x i16> %tmp2, ptr addrspace(1) %out, align 8
50 ret void
51 }
53 define amdgpu_kernel void @scalar_to_vector_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
54 ; SI-LABEL: scalar_to_vector_v2f32:
55 ; SI: ; %bb.0:
56 ; SI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x9
57 ; SI-NEXT: s_mov_b32 s7, 0xf000
58 ; SI-NEXT: s_mov_b32 s6, -1
59 ; SI-NEXT: s_mov_b32 s10, s6
60 ; SI-NEXT: s_mov_b32 s11, s7
61 ; SI-NEXT: s_waitcnt lgkmcnt(0)
62 ; SI-NEXT: s_mov_b32 s8, s2
63 ; SI-NEXT: s_mov_b32 s9, s3
64 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
65 ; SI-NEXT: s_waitcnt vmcnt(0)
66 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
67 ; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
68 ; SI-NEXT: s_mov_b32 s4, s0
69 ; SI-NEXT: s_mov_b32 s5, s1
70 ; SI-NEXT: v_mov_b32_e32 v1, v0
71 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
72 ; SI-NEXT: s_endpgm
73 ;
74 ; VI-LABEL: scalar_to_vector_v2f32:
75 ; VI: ; %bb.0:
76 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x24
77 ; VI-NEXT: s_mov_b32 s7, 0xf000
78 ; VI-NEXT: s_mov_b32 s6, -1
79 ; VI-NEXT: s_mov_b32 s10, s6
80 ; VI-NEXT: s_mov_b32 s11, s7
81 ; VI-NEXT: s_waitcnt lgkmcnt(0)
82 ; VI-NEXT: s_mov_b32 s8, s2
83 ; VI-NEXT: s_mov_b32 s9, s3
84 ; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
85 ; VI-NEXT: s_mov_b32 s4, s0
86 ; VI-NEXT: s_mov_b32 s5, s1
87 ; VI-NEXT: s_waitcnt vmcnt(0)
88 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
89 ; VI-NEXT: v_alignbit_b32 v0, v1, v0, 16
90 ; VI-NEXT: v_mov_b32_e32 v1, v0
91 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
92 ; VI-NEXT: s_endpgm
93 %tmp1 = load float, ptr addrspace(1) %in, align 4
94 %bc = bitcast float %tmp1 to <2 x i16>
95 %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
96 store <4 x i16> %tmp2, ptr addrspace(1) %out, align 8
97 ret void
98 }
100 define amdgpu_kernel void @scalar_to_vector_v4i16() {
101 ; SI-LABEL: scalar_to_vector_v4i16:
102 ; SI: ; %bb.0: ; %bb
103 ; SI-NEXT: s_mov_b32 s3, 0xf000
104 ; SI-NEXT: s_mov_b32 s2, -1
105 ; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
106 ; SI-NEXT: s_waitcnt vmcnt(0)
107 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
108 ; SI-NEXT: v_or_b32_e32 v2, v1, v0
109 ; SI-NEXT: v_and_b32_e32 v1, 0xff00, v2
110 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
111 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
112 ; SI-NEXT: v_or_b32_e32 v1, v0, v3
113 ; SI-NEXT: v_or_b32_e32 v0, v2, v3
114 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
115 ; SI-NEXT: s_endpgm
116 ;
117 ; VI-LABEL: scalar_to_vector_v4i16:
118 ; VI: ; %bb.0: ; %bb
119 ; VI-NEXT: s_mov_b32 s3, 0xf000
120 ; VI-NEXT: s_mov_b32 s2, -1
121 ; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
122 ; VI-NEXT: s_waitcnt vmcnt(0)
123 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v0
124 ; VI-NEXT: v_or_b32_e32 v2, v1, v0
125 ; VI-NEXT: v_and_b32_e32 v1, 0xffffff00, v2
126 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
127 ; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
128 ; VI-NEXT: v_or_b32_sdwa v1, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
129 ; VI-NEXT: v_or_b32_sdwa v0, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
130 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
131 ; VI-NEXT: s_endpgm
132 bb:
133 %tmp = load <2 x i8>, ptr addrspace(1) undef, align 1
134 %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
135 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
136 store <8 x i8> %tmp2, ptr addrspace(1) undef, align 8
137 ret void
138 }
140 define amdgpu_kernel void @scalar_to_vector_v4f16() {
141 ; SI-LABEL: scalar_to_vector_v4f16:
142 ; SI: ; %bb.0: ; %bb
143 ; SI-NEXT: s_mov_b32 s3, 0xf000
144 ; SI-NEXT: s_mov_b32 s2, -1
145 ; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
146 ; SI-NEXT: s_waitcnt vmcnt(0)
147 ; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
148 ; SI-NEXT: v_or_b32_e32 v2, v1, v0
149 ; SI-NEXT: v_and_b32_e32 v1, 0xff00, v2
150 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
151 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
152 ; SI-NEXT: v_or_b32_e32 v1, v0, v3
153 ; SI-NEXT: v_or_b32_e32 v0, v2, v3
154 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
155 ; SI-NEXT: s_endpgm
156 ;
157 ; VI-LABEL: scalar_to_vector_v4f16:
158 ; VI: ; %bb.0: ; %bb
159 ; VI-NEXT: s_mov_b32 s3, 0xf000
160 ; VI-NEXT: s_mov_b32 s2, -1
161 ; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
162 ; VI-NEXT: s_waitcnt vmcnt(0)
163 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v0
164 ; VI-NEXT: v_or_b32_e32 v0, v1, v0
165 ; VI-NEXT: v_and_b32_e32 v1, 0xffffff00, v0
166 ; VI-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
167 ; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
168 ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
169 ; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
170 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
171 ; VI-NEXT: s_endpgm
172 bb:
173 %load = load half, ptr addrspace(1) undef, align 1
174 %tmp = bitcast half %load to <2 x i8>
175 %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
176 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
177 store <8 x i8> %tmp2, ptr addrspace(1) undef, align 8
178 ret void
179 }
181 ; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed
182 ; to produce one, but for some reason never made it to selection.
185 ; define amdgpu_kernel void @scalar_to_vector_test2(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
186 ; %tmp1 = load i32, ptr addrspace(1) %in, align 4
187 ; %bc = bitcast i32 %tmp1 to <4 x i8>
189 ; %tmp2 = shufflevector <4 x i8> %bc, <4 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
190 ; store <8 x i8> %tmp2, ptr addrspace(1) %out, align 4
191 ; ret void
192 ; }
194 ; define amdgpu_kernel void @scalar_to_vector_test3(ptr addrspace(1) %out) nounwind {
195 ; %newvec0 = insertelement <2 x i64> undef, i64 12345, i32 0
196 ; %newvec1 = insertelement <2 x i64> %newvec0, i64 undef, i32 1
197 ; %bc = bitcast <2 x i64> %newvec1 to <4 x i32>
198 ; %add = add <4 x i32> %bc, <i32 1, i32 2, i32 3, i32 4>
199 ; store <4 x i32> %add, ptr addrspace(1) %out, align 16
200 ; ret void
201 ; }
203 ; define amdgpu_kernel void @scalar_to_vector_test4(ptr addrspace(1) %out) nounwind {
204 ; %newvec0 = insertelement <4 x i32> undef, i32 12345, i32 0
205 ; %bc = bitcast <4 x i32> %newvec0 to <8 x i16>
206 ; %add = add <8 x i16> %bc, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>
207 ; store <8 x i16> %add, ptr addrspace(1) %out, align 16
208 ; ret void
209 ; }
211 ; define amdgpu_kernel void @scalar_to_vector_test5(ptr addrspace(1) %out) nounwind {
212 ; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0
213 ; %bc = bitcast <2 x i32> %newvec0 to <4 x i16>
214 ; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4>
215 ; store <4 x i16> %add, ptr addrspace(1) %out, align 16
216 ; ret void
217 ; }
219 define amdgpu_kernel void @scalar_to_vector_test6(ptr addrspace(1) %out, i8 zeroext %val) nounwind {
220 ; SI-LABEL: scalar_to_vector_test6:
221 ; SI: ; %bb.0:
222 ; SI-NEXT: s_load_dword s4, s[2:3], 0xb
223 ; SI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
224 ; SI-NEXT: s_mov_b32 s3, 0xf000
225 ; SI-NEXT: s_mov_b32 s2, -1
226 ; SI-NEXT: s_waitcnt lgkmcnt(0)
227 ; SI-NEXT: v_mov_b32_e32 v0, s4
228 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
229 ; SI-NEXT: s_endpgm
230 ;
231 ; VI-LABEL: scalar_to_vector_test6:
232 ; VI: ; %bb.0:
233 ; VI-NEXT: s_load_dword s4, s[2:3], 0x2c
234 ; VI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
235 ; VI-NEXT: s_mov_b32 s3, 0xf000
236 ; VI-NEXT: s_mov_b32 s2, -1
237 ; VI-NEXT: s_waitcnt lgkmcnt(0)
238 ; VI-NEXT: v_mov_b32_e32 v0, s4
239 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
240 ; VI-NEXT: s_endpgm
241 %newvec0 = insertelement <4 x i8> undef, i8 %val, i32 0
242 %bc = bitcast <4 x i8> %newvec0 to <2 x half>
243 store <2 x half> %bc, ptr addrspace(1) %out
244 ret void
245 }