llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
   3
   4 # Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be
   5 # fully determined from the instruction description.
   6 ---
   7 name:            regsequence_with_regsequence_use_op
   8 tracksRegLiveness: true
   9 body:             |
  10   bb.0:
  11     liveins: $agpr0, $agpr1
  12
  13     ; GCN-LABEL: name: regsequence_with_regsequence_use_op
  14     ; GCN: liveins: $agpr0, $agpr1
  15     ; GCN-NEXT: {{  $}}
  16     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
  17     ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
  18     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  19     ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  20     ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF]], %subreg.sub2
  21     ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
  22     %0:vgpr_32 = COPY $agpr0
  23     %1:vgpr_32 = COPY $agpr1
  24     %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
  25     %3:vgpr_32 = IMPLICIT_DEF
  26     %4:vreg_96_align2 = REG_SEQUENCE killed %2:vreg_64_align2, %subreg.sub0_sub1, killed %3:vgpr_32, %subreg.sub2
  27     S_ENDPGM 0, implicit %4
  28 ...
  29 ---
  30 name:            insert_subreg_with_regsequence_use_op
  31 tracksRegLiveness: true
  32 body:             |
  33   bb.0:
  34     liveins: $agpr0, $agpr1
  35
  36     ; GCN-LABEL: name: insert_subreg_with_regsequence_use_op
  37     ; GCN: liveins: $agpr0, $agpr1
  38     ; GCN-NEXT: {{  $}}
  39     ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
  40     ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
  41     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
  42     ; GCN-NEXT: S_NOP 0, implicit-def %3
  43     ; GCN-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64_align2 = INSERT_SUBREG %3, [[REG_SEQUENCE]], %subreg.sub0_sub1
  44     ; GCN-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
  45     %0:vgpr_32 = COPY $agpr0
  46     %1:vgpr_32 = COPY $agpr1
  47     %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
  48     S_NOP 0, implicit-def %3:vreg_64_align2
  49     %4:vreg_64_align2 = INSERT_SUBREG %3, %2, %subreg.sub0_sub1
  50     S_ENDPGM 0, implicit %4
  51 ...