| blob | b714fda6f1d07647005c1d03646f6655a46b07c8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
5 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
7 define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
8 ; GFX6-LABEL: v_uaddsat_i8:
9 ; GFX6: ; %bb.0:
10 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11 ; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
12 ; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
13 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
14 ; GFX6-NEXT: v_min_u32_e32 v0, 0xff, v0
15 ; GFX6-NEXT: s_setpc_b64 s[30:31]
16 ;
17 ; GFX8-LABEL: v_uaddsat_i8:
18 ; GFX8: ; %bb.0:
19 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20 ; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
21 ; GFX8-NEXT: v_min_u16_e32 v0, 0xff, v0
22 ; GFX8-NEXT: s_setpc_b64 s[30:31]
23 ;
24 ; GFX9-LABEL: v_uaddsat_i8:
25 ; GFX9: ; %bb.0:
26 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27 ; GFX9-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
28 ; GFX9-NEXT: v_min_u16_e32 v0, 0xff, v0
29 ; GFX9-NEXT: s_setpc_b64 s[30:31]
30 ;
31 ; GFX10-LABEL: v_uaddsat_i8:
32 ; GFX10: ; %bb.0:
33 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
34 ; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
35 ; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
36 ; GFX10-NEXT: v_add_nc_u16 v0, v0, v1
37 ; GFX10-NEXT: v_min_u16 v0, 0xff, v0
38 ; GFX10-NEXT: s_setpc_b64 s[30:31]
39 %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
40 ret i8 %result
41 }
43 define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
44 ; GFX6-LABEL: v_uaddsat_i16:
45 ; GFX6: ; %bb.0:
46 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
47 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
48 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
49 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
50 ; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
51 ; GFX6-NEXT: s_setpc_b64 s[30:31]
52 ;
53 ; GFX8-LABEL: v_uaddsat_i16:
54 ; GFX8: ; %bb.0:
55 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
56 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
57 ; GFX8-NEXT: s_setpc_b64 s[30:31]
58 ;
59 ; GFX9-LABEL: v_uaddsat_i16:
60 ; GFX9: ; %bb.0:
61 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
62 ; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
63 ; GFX9-NEXT: s_setpc_b64 s[30:31]
64 ;
65 ; GFX10-LABEL: v_uaddsat_i16:
66 ; GFX10: ; %bb.0:
67 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
68 ; GFX10-NEXT: v_add_nc_u16 v0, v0, v1 clamp
69 ; GFX10-NEXT: s_setpc_b64 s[30:31]
70 %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
71 ret i16 %result
72 }
74 define i32 @v_uaddsat_i32(i32 %lhs, i32 %rhs) {
75 ; GFX6-LABEL: v_uaddsat_i32:
76 ; GFX6: ; %bb.0:
77 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
78 ; GFX6-NEXT: v_not_b32_e32 v2, v1
79 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v2
80 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
81 ; GFX6-NEXT: s_setpc_b64 s[30:31]
82 ;
83 ; GFX8-LABEL: v_uaddsat_i32:
84 ; GFX8: ; %bb.0:
85 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
86 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp
87 ; GFX8-NEXT: s_setpc_b64 s[30:31]
88 ;
89 ; GFX9-LABEL: v_uaddsat_i32:
90 ; GFX9: ; %bb.0:
91 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
92 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp
93 ; GFX9-NEXT: s_setpc_b64 s[30:31]
94 ;
95 ; GFX10-LABEL: v_uaddsat_i32:
96 ; GFX10: ; %bb.0:
97 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
98 ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp
99 ; GFX10-NEXT: s_setpc_b64 s[30:31]
100 %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
101 ret i32 %result
102 }
104 define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
105 ; GFX6-LABEL: v_uaddsat_v2i16:
106 ; GFX6: ; %bb.0:
107 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
108 ; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
109 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
110 ; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
111 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
112 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
113 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
114 ; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
115 ; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
116 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v1
117 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
118 ; GFX6-NEXT: s_setpc_b64 s[30:31]
119 ;
120 ; GFX8-LABEL: v_uaddsat_v2i16:
121 ; GFX8: ; %bb.0:
122 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
123 ; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
124 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
125 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
126 ; GFX8-NEXT: s_setpc_b64 s[30:31]
127 ;
128 ; GFX9-LABEL: v_uaddsat_v2i16:
129 ; GFX9: ; %bb.0:
130 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
131 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
132 ; GFX9-NEXT: s_setpc_b64 s[30:31]
133 ;
134 ; GFX10-LABEL: v_uaddsat_v2i16:
135 ; GFX10: ; %bb.0:
136 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
137 ; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
138 ; GFX10-NEXT: s_setpc_b64 s[30:31]
139 %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
140 ret <2 x i16> %result
141 }
143 define <3 x i16> @v_uaddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
144 ; GFX6-LABEL: v_uaddsat_v3i16:
145 ; GFX6: ; %bb.0:
146 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
147 ; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
148 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
149 ; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5
150 ; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
151 ; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
152 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
153 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
154 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
155 ; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
156 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
157 ; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
158 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
159 ; GFX6-NEXT: v_min_u32_e32 v3, 0xffff, v2
160 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
161 ; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v3
162 ; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16
163 ; GFX6-NEXT: s_setpc_b64 s[30:31]
164 ;
165 ; GFX8-LABEL: v_uaddsat_v3i16:
166 ; GFX8: ; %bb.0:
167 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
168 ; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
169 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp
170 ; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp
171 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
172 ; GFX8-NEXT: s_setpc_b64 s[30:31]
173 ;
174 ; GFX9-LABEL: v_uaddsat_v3i16:
175 ; GFX9: ; %bb.0:
176 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
177 ; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
178 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
179 ; GFX9-NEXT: s_setpc_b64 s[30:31]
180 ;
181 ; GFX10-LABEL: v_uaddsat_v3i16:
182 ; GFX10: ; %bb.0:
183 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
184 ; GFX10-NEXT: v_pk_add_u16 v0, v0, v2 clamp
185 ; GFX10-NEXT: v_pk_add_u16 v1, v1, v3 clamp
186 ; GFX10-NEXT: s_setpc_b64 s[30:31]
187 %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
188 ret <3 x i16> %result
189 }
191 define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
192 ; GFX6-LABEL: v_uaddsat_v4i16:
193 ; GFX6: ; %bb.0:
194 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
195 ; GFX6-NEXT: v_and_b32_e32 v5, 0xffff, v5
196 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
197 ; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4
198 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
199 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
200 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
201 ; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
202 ; GFX6-NEXT: v_and_b32_e32 v7, 0xffff, v7
203 ; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
204 ; GFX6-NEXT: v_and_b32_e32 v6, 0xffff, v6
205 ; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
206 ; GFX6-NEXT: v_min_u32_e32 v0, 0xffff, v0
207 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
208 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
209 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v6
210 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v7
211 ; GFX6-NEXT: v_min_u32_e32 v2, 0xffff, v2
212 ; GFX6-NEXT: v_min_u32_e32 v1, 0xffff, v1
213 ; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
214 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
215 ; GFX6-NEXT: s_setpc_b64 s[30:31]
216 ;
217 ; GFX8-LABEL: v_uaddsat_v4i16:
218 ; GFX8: ; %bb.0:
219 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
220 ; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
221 ; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp
222 ; GFX8-NEXT: v_add_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
223 ; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp
224 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
225 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
226 ; GFX8-NEXT: s_setpc_b64 s[30:31]
227 ;
228 ; GFX9-LABEL: v_uaddsat_v4i16:
229 ; GFX9: ; %bb.0:
230 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
231 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
232 ; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
233 ; GFX9-NEXT: s_setpc_b64 s[30:31]
234 ;
235 ; GFX10-LABEL: v_uaddsat_v4i16:
236 ; GFX10: ; %bb.0:
237 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
238 ; GFX10-NEXT: v_pk_add_u16 v0, v0, v2 clamp
239 ; GFX10-NEXT: v_pk_add_u16 v1, v1, v3 clamp
240 ; GFX10-NEXT: s_setpc_b64 s[30:31]
241 %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
242 %cast = bitcast <4 x i16> %result to <2 x float>
243 ret <2 x float> %cast
244 }
246 define <2 x i32> @v_uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
247 ; GFX6-LABEL: v_uaddsat_v2i32:
248 ; GFX6: ; %bb.0:
249 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
250 ; GFX6-NEXT: v_not_b32_e32 v4, v2
251 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v4
252 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
253 ; GFX6-NEXT: v_not_b32_e32 v2, v3
254 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v2
255 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
256 ; GFX6-NEXT: s_setpc_b64 s[30:31]
257 ;
258 ; GFX8-LABEL: v_uaddsat_v2i32:
259 ; GFX8: ; %bb.0:
260 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
261 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v2 clamp
262 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v3 clamp
263 ; GFX8-NEXT: s_setpc_b64 s[30:31]
264 ;
265 ; GFX9-LABEL: v_uaddsat_v2i32:
266 ; GFX9: ; %bb.0:
267 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
268 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v2 clamp
269 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v3 clamp
270 ; GFX9-NEXT: s_setpc_b64 s[30:31]
271 ;
272 ; GFX10-LABEL: v_uaddsat_v2i32:
273 ; GFX10: ; %bb.0:
274 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
275 ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v2 clamp
276 ; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v3 clamp
277 ; GFX10-NEXT: s_setpc_b64 s[30:31]
278 %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
279 ret <2 x i32> %result
280 }
282 define <3 x i32> @v_uaddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
283 ; GFX6-LABEL: v_uaddsat_v3i32:
284 ; GFX6: ; %bb.0:
285 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
286 ; GFX6-NEXT: v_not_b32_e32 v6, v3
287 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v6
288 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
289 ; GFX6-NEXT: v_not_b32_e32 v3, v4
290 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v3
291 ; GFX6-NEXT: v_not_b32_e32 v3, v5
292 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v3
293 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
294 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
295 ; GFX6-NEXT: s_setpc_b64 s[30:31]
296 ;
297 ; GFX8-LABEL: v_uaddsat_v3i32:
298 ; GFX8: ; %bb.0:
299 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
300 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v3 clamp
301 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v4 clamp
302 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v5 clamp
303 ; GFX8-NEXT: s_setpc_b64 s[30:31]
304 ;
305 ; GFX9-LABEL: v_uaddsat_v3i32:
306 ; GFX9: ; %bb.0:
307 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
308 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v3 clamp
309 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v4 clamp
310 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v5 clamp
311 ; GFX9-NEXT: s_setpc_b64 s[30:31]
312 ;
313 ; GFX10-LABEL: v_uaddsat_v3i32:
314 ; GFX10: ; %bb.0:
315 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
316 ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v3 clamp
317 ; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v4 clamp
318 ; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v5 clamp
319 ; GFX10-NEXT: s_setpc_b64 s[30:31]
320 %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
321 ret <3 x i32> %result
322 }
324 define <4 x i32> @v_uaddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
325 ; GFX6-LABEL: v_uaddsat_v4i32:
326 ; GFX6: ; %bb.0:
327 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
328 ; GFX6-NEXT: v_not_b32_e32 v8, v4
329 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v8
330 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
331 ; GFX6-NEXT: v_not_b32_e32 v4, v5
332 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v4
333 ; GFX6-NEXT: v_not_b32_e32 v4, v6
334 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v4
335 ; GFX6-NEXT: v_not_b32_e32 v4, v7
336 ; GFX6-NEXT: v_min_u32_e32 v3, v3, v4
337 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
338 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6
339 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7
340 ; GFX6-NEXT: s_setpc_b64 s[30:31]
341 ;
342 ; GFX8-LABEL: v_uaddsat_v4i32:
343 ; GFX8: ; %bb.0:
344 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
345 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v4 clamp
346 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v5 clamp
347 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v6 clamp
348 ; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v7 clamp
349 ; GFX8-NEXT: s_setpc_b64 s[30:31]
350 ;
351 ; GFX9-LABEL: v_uaddsat_v4i32:
352 ; GFX9: ; %bb.0:
353 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
354 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v4 clamp
355 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v5 clamp
356 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v6 clamp
357 ; GFX9-NEXT: v_add_u32_e64 v3, v3, v7 clamp
358 ; GFX9-NEXT: s_setpc_b64 s[30:31]
359 ;
360 ; GFX10-LABEL: v_uaddsat_v4i32:
361 ; GFX10: ; %bb.0:
362 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
363 ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v4 clamp
364 ; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v5 clamp
365 ; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v6 clamp
366 ; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v7 clamp
367 ; GFX10-NEXT: s_setpc_b64 s[30:31]
368 %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
369 ret <4 x i32> %result
370 }
372 define <8 x i32> @v_uaddsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {
373 ; GFX6-LABEL: v_uaddsat_v8i32:
374 ; GFX6: ; %bb.0:
375 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
376 ; GFX6-NEXT: v_not_b32_e32 v16, v8
377 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v16
378 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v8
379 ; GFX6-NEXT: v_not_b32_e32 v8, v9
380 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v8
381 ; GFX6-NEXT: v_not_b32_e32 v8, v10
382 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v8
383 ; GFX6-NEXT: v_not_b32_e32 v8, v11
384 ; GFX6-NEXT: v_min_u32_e32 v3, v3, v8
385 ; GFX6-NEXT: v_not_b32_e32 v8, v12
386 ; GFX6-NEXT: v_min_u32_e32 v4, v4, v8
387 ; GFX6-NEXT: v_not_b32_e32 v8, v13
388 ; GFX6-NEXT: v_min_u32_e32 v5, v5, v8
389 ; GFX6-NEXT: v_not_b32_e32 v8, v14
390 ; GFX6-NEXT: v_min_u32_e32 v6, v6, v8
391 ; GFX6-NEXT: v_not_b32_e32 v8, v15
392 ; GFX6-NEXT: v_min_u32_e32 v7, v7, v8
393 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v9
394 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v10
395 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v11
396 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v12
397 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v13
398 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v14
399 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v15
400 ; GFX6-NEXT: s_setpc_b64 s[30:31]
401 ;
402 ; GFX8-LABEL: v_uaddsat_v8i32:
403 ; GFX8: ; %bb.0:
404 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
405 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v8 clamp
406 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v9 clamp
407 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v10 clamp
408 ; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v11 clamp
409 ; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v12 clamp
410 ; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v13 clamp
411 ; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v14 clamp
412 ; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v15 clamp
413 ; GFX8-NEXT: s_setpc_b64 s[30:31]
414 ;
415 ; GFX9-LABEL: v_uaddsat_v8i32:
416 ; GFX9: ; %bb.0:
417 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
418 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v8 clamp
419 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v9 clamp
420 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v10 clamp
421 ; GFX9-NEXT: v_add_u32_e64 v3, v3, v11 clamp
422 ; GFX9-NEXT: v_add_u32_e64 v4, v4, v12 clamp
423 ; GFX9-NEXT: v_add_u32_e64 v5, v5, v13 clamp
424 ; GFX9-NEXT: v_add_u32_e64 v6, v6, v14 clamp
425 ; GFX9-NEXT: v_add_u32_e64 v7, v7, v15 clamp
426 ; GFX9-NEXT: s_setpc_b64 s[30:31]
427 ;
428 ; GFX10-LABEL: v_uaddsat_v8i32:
429 ; GFX10: ; %bb.0:
430 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
431 ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v8 clamp
432 ; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v9 clamp
433 ; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v10 clamp
434 ; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v11 clamp
435 ; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v12 clamp
436 ; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v13 clamp
437 ; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v14 clamp
438 ; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v15 clamp
439 ; GFX10-NEXT: s_setpc_b64 s[30:31]
440 %result = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)
441 ret <8 x i32> %result
442 }
444 define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
445 ; GFX6-LABEL: v_uaddsat_v16i32:
446 ; GFX6: ; %bb.0:
447 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
448 ; GFX6-NEXT: v_not_b32_e32 v31, v16
449 ; GFX6-NEXT: v_min_u32_e32 v0, v0, v31
450 ; GFX6-NEXT: buffer_load_dword v31, off, s[0:3], s32
451 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16
452 ; GFX6-NEXT: v_not_b32_e32 v16, v17
453 ; GFX6-NEXT: v_min_u32_e32 v1, v1, v16
454 ; GFX6-NEXT: v_not_b32_e32 v16, v18
455 ; GFX6-NEXT: v_min_u32_e32 v2, v2, v16
456 ; GFX6-NEXT: v_not_b32_e32 v16, v19
457 ; GFX6-NEXT: v_min_u32_e32 v3, v3, v16
458 ; GFX6-NEXT: v_not_b32_e32 v16, v20
459 ; GFX6-NEXT: v_min_u32_e32 v4, v4, v16
460 ; GFX6-NEXT: v_not_b32_e32 v16, v21
461 ; GFX6-NEXT: v_min_u32_e32 v5, v5, v16
462 ; GFX6-NEXT: v_not_b32_e32 v16, v22
463 ; GFX6-NEXT: v_min_u32_e32 v6, v6, v16
464 ; GFX6-NEXT: v_not_b32_e32 v16, v23
465 ; GFX6-NEXT: v_min_u32_e32 v7, v7, v16
466 ; GFX6-NEXT: v_not_b32_e32 v16, v24
467 ; GFX6-NEXT: v_min_u32_e32 v8, v8, v16
468 ; GFX6-NEXT: v_not_b32_e32 v16, v25
469 ; GFX6-NEXT: v_min_u32_e32 v9, v9, v16
470 ; GFX6-NEXT: v_not_b32_e32 v16, v26
471 ; GFX6-NEXT: v_min_u32_e32 v10, v10, v16
472 ; GFX6-NEXT: v_not_b32_e32 v16, v27
473 ; GFX6-NEXT: v_min_u32_e32 v11, v11, v16
474 ; GFX6-NEXT: v_not_b32_e32 v16, v28
475 ; GFX6-NEXT: v_min_u32_e32 v12, v12, v16
476 ; GFX6-NEXT: v_not_b32_e32 v16, v29
477 ; GFX6-NEXT: v_min_u32_e32 v13, v13, v16
478 ; GFX6-NEXT: v_not_b32_e32 v16, v30
479 ; GFX6-NEXT: v_min_u32_e32 v14, v14, v16
480 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v17
481 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v18
482 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v19
483 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v20
484 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v21
485 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v22
486 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v23
487 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v24
488 ; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v25
489 ; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v26
490 ; GFX6-NEXT: v_add_i32_e32 v11, vcc, v11, v27
491 ; GFX6-NEXT: v_add_i32_e32 v12, vcc, v12, v28
492 ; GFX6-NEXT: v_add_i32_e32 v13, vcc, v13, v29
493 ; GFX6-NEXT: v_add_i32_e32 v14, vcc, v14, v30
494 ; GFX6-NEXT: s_waitcnt vmcnt(0)
495 ; GFX6-NEXT: v_not_b32_e32 v16, v31
496 ; GFX6-NEXT: v_min_u32_e32 v15, v15, v16
497 ; GFX6-NEXT: v_add_i32_e32 v15, vcc, v15, v31
498 ; GFX6-NEXT: s_setpc_b64 s[30:31]
499 ;
500 ; GFX8-LABEL: v_uaddsat_v16i32:
501 ; GFX8: ; %bb.0:
502 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
503 ; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v16 clamp
504 ; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32
505 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v17 clamp
506 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v18 clamp
507 ; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v19 clamp
508 ; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v20 clamp
509 ; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v21 clamp
510 ; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v22 clamp
511 ; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v23 clamp
512 ; GFX8-NEXT: v_add_u32_e64 v8, s[4:5], v8, v24 clamp
513 ; GFX8-NEXT: v_add_u32_e64 v9, s[4:5], v9, v25 clamp
514 ; GFX8-NEXT: v_add_u32_e64 v10, s[4:5], v10, v26 clamp
515 ; GFX8-NEXT: v_add_u32_e64 v11, s[4:5], v11, v27 clamp
516 ; GFX8-NEXT: v_add_u32_e64 v12, s[4:5], v12, v28 clamp
517 ; GFX8-NEXT: v_add_u32_e64 v13, s[4:5], v13, v29 clamp
518 ; GFX8-NEXT: v_add_u32_e64 v14, s[4:5], v14, v30 clamp
519 ; GFX8-NEXT: s_waitcnt vmcnt(0)
520 ; GFX8-NEXT: v_add_u32_e64 v15, s[4:5], v15, v16 clamp
521 ; GFX8-NEXT: s_setpc_b64 s[30:31]
522 ;
523 ; GFX9-LABEL: v_uaddsat_v16i32:
524 ; GFX9: ; %bb.0:
525 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
526 ; GFX9-NEXT: v_add_u32_e64 v0, v0, v16 clamp
527 ; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32
528 ; GFX9-NEXT: v_add_u32_e64 v1, v1, v17 clamp
529 ; GFX9-NEXT: v_add_u32_e64 v2, v2, v18 clamp
530 ; GFX9-NEXT: v_add_u32_e64 v3, v3, v19 clamp
531 ; GFX9-NEXT: v_add_u32_e64 v4, v4, v20 clamp
532 ; GFX9-NEXT: v_add_u32_e64 v5, v5, v21 clamp
533 ; GFX9-NEXT: v_add_u32_e64 v6, v6, v22 clamp
534 ; GFX9-NEXT: v_add_u32_e64 v7, v7, v23 clamp
535 ; GFX9-NEXT: v_add_u32_e64 v8, v8, v24 clamp
536 ; GFX9-NEXT: v_add_u32_e64 v9, v9, v25 clamp
537 ; GFX9-NEXT: v_add_u32_e64 v10, v10, v26 clamp
538 ; GFX9-NEXT: v_add_u32_e64 v11, v11, v27 clamp
539 ; GFX9-NEXT: v_add_u32_e64 v12, v12, v28 clamp
540 ; GFX9-NEXT: v_add_u32_e64 v13, v13, v29 clamp
541 ; GFX9-NEXT: v_add_u32_e64 v14, v14, v30 clamp
542 ; GFX9-NEXT: s_waitcnt vmcnt(0)
543 ; GFX9-NEXT: v_add_u32_e64 v15, v15, v16 clamp
544 ; GFX9-NEXT: s_setpc_b64 s[30:31]
545 ;
546 ; GFX10-LABEL: v_uaddsat_v16i32:
547 ; GFX10: ; %bb.0:
548 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
549 ; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
550 ; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp
551 ; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp
552 ; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp
553 ; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp
554 ; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp
555 ; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp
556 ; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp
557 ; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp
558 ; GFX10-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp
559 ; GFX10-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp
560 ; GFX10-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp
561 ; GFX10-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp
562 ; GFX10-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp
563 ; GFX10-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp
564 ; GFX10-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp
565 ; GFX10-NEXT: s_waitcnt vmcnt(0)
566 ; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp
567 ; GFX10-NEXT: s_setpc_b64 s[30:31]
568 %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
569 ret <16 x i32> %result
570 }
573 define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {
574 ; GFX6-LABEL: v_uaddsat_i64:
575 ; GFX6: ; %bb.0:
576 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
577 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v0, v2
578 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
579 ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
580 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
581 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
582 ; GFX6-NEXT: s_setpc_b64 s[30:31]
583 ;
584 ; GFX8-LABEL: v_uaddsat_i64:
585 ; GFX8: ; %bb.0:
586 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
587 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v2
588 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
589 ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
590 ; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
591 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
592 ; GFX8-NEXT: s_setpc_b64 s[30:31]
593 ;
594 ; GFX9-LABEL: v_uaddsat_i64:
595 ; GFX9: ; %bb.0:
596 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
597 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
598 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc
599 ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
600 ; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc
601 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc
602 ; GFX9-NEXT: s_setpc_b64 s[30:31]
603 ;
604 ; GFX10-LABEL: v_uaddsat_i64:
605 ; GFX10: ; %bb.0:
606 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
607 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
608 ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
609 ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
610 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc_lo
611 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc_lo
612 ; GFX10-NEXT: s_setpc_b64 s[30:31]
613 %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
614 ret i64 %result
615 }
617 declare i8 @llvm.uadd.sat.i8(i8, i8) #0
618 declare i16 @llvm.uadd.sat.i16(i16, i16) #0
619 declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>) #0
620 declare <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16>, <3 x i16>) #0
621 declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>) #0
622 declare i32 @llvm.uadd.sat.i32(i32, i32) #0
623 declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>) #0
624 declare <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32>, <3 x i32>) #0
625 declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #0
626 declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>) #0
627 declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>) #0
628 declare i64 @llvm.uadd.sat.i64(i64, i64) #0
630 attributes #0 = { nounwind readnone speculatable willreturn }