| blob | 1468c7b99b5c251e6a34c36ffa8b1373b1943341 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=GFX6 %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
6 define amdgpu_kernel void @test_udivrem(ptr addrspace(1) %out0, [8 x i32], ptr addrspace(1) %out1, [8 x i32], i32 %x, [8 x i32], i32 %y) {
7 ; R600-LABEL: test_udivrem:
8 ; R600: ; %bb.0:
9 ; R600-NEXT: ALU 21, @4, KC0[CB0:0-32], KC1[]
10 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
11 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
12 ; R600-NEXT: CF_END
13 ; R600-NEXT: ALU clause starting at 4:
14 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[9].X,
15 ; R600-NEXT: RECIP_UINT * T0.X, KC0[9].X,
16 ; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,
17 ; R600-NEXT: MULHI * T0.Y, T0.X, PS,
18 ; R600-NEXT: ADD_INT * T0.W, T0.X, PS,
19 ; R600-NEXT: MULHI * T0.X, KC0[6].W, PV.W,
20 ; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[9].X,
21 ; R600-NEXT: SUB_INT * T0.W, KC0[6].W, PS,
22 ; R600-NEXT: SUB_INT T1.W, PV.W, KC0[9].X,
23 ; R600-NEXT: SETGE_UINT * T2.W, PV.W, KC0[9].X,
24 ; R600-NEXT: CNDE_INT * T0.W, PS, T0.W, PV.W,
25 ; R600-NEXT: ADD_INT T0.Z, T0.X, 1,
26 ; R600-NEXT: SUB_INT T1.W, PV.W, KC0[9].X,
27 ; R600-NEXT: SETGE_UINT * T3.W, PV.W, KC0[9].X,
28 ; R600-NEXT: CNDE_INT T1.X, PS, T0.W, PV.W,
29 ; R600-NEXT: CNDE_INT T0.W, T2.W, T0.X, PV.Z,
30 ; R600-NEXT: LSHR * T0.X, KC0[4].Z, literal.x,
31 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
32 ; R600-NEXT: ADD_INT * T1.W, PV.W, 1,
33 ; R600-NEXT: CNDE_INT T2.X, T3.W, T0.W, PV.W,
34 ; R600-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
35 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
36 ;
37 ; GFX6-LABEL: test_udivrem:
38 ; GFX6: ; %bb.0:
39 ; GFX6-NEXT: s_load_dword s8, s[2:3], 0x26
40 ; GFX6-NEXT: s_load_dword s9, s[2:3], 0x1d
41 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
42 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
43 ; GFX6-NEXT: s_sub_i32 s0, 0, s8
44 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
45 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
46 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
47 ; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
48 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
49 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x13
50 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
51 ; GFX6-NEXT: s_mov_b32 s2, -1
52 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
53 ; GFX6-NEXT: s_mov_b32 s6, s2
54 ; GFX6-NEXT: s_mov_b32 s7, s3
55 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
56 ; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
57 ; GFX6-NEXT: v_readfirstlane_b32 s10, v0
58 ; GFX6-NEXT: s_mul_i32 s10, s10, s8
59 ; GFX6-NEXT: s_sub_i32 s9, s9, s10
60 ; GFX6-NEXT: s_sub_i32 s10, s9, s8
61 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
62 ; GFX6-NEXT: s_cmp_ge_u32 s9, s8
63 ; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
64 ; GFX6-NEXT: s_cselect_b32 s9, s10, s9
65 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
66 ; GFX6-NEXT: s_sub_i32 s10, s9, s8
67 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
68 ; GFX6-NEXT: s_cmp_ge_u32 s9, s8
69 ; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
70 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
71 ; GFX6-NEXT: s_cselect_b32 s8, s10, s9
72 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
73 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
74 ; GFX6-NEXT: s_waitcnt expcnt(0)
75 ; GFX6-NEXT: v_mov_b32_e32 v0, s8
76 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
77 ; GFX6-NEXT: s_endpgm
78 ;
79 ; GFX8-LABEL: test_udivrem:
80 ; GFX8: ; %bb.0:
81 ; GFX8-NEXT: s_load_dword s4, s[2:3], 0x98
82 ; GFX8-NEXT: s_load_dword s5, s[2:3], 0x74
83 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
84 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s4
85 ; GFX8-NEXT: s_sub_i32 s0, 0, s4
86 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
87 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
88 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
89 ; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0
90 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
91 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x4c
92 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
93 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
94 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
95 ; GFX8-NEXT: v_mov_b32_e32 v3, s3
96 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
97 ; GFX8-NEXT: v_mul_hi_u32 v4, s5, v0
98 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
99 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
100 ; GFX8-NEXT: v_readfirstlane_b32 s0, v4
101 ; GFX8-NEXT: s_mul_i32 s0, s0, s4
102 ; GFX8-NEXT: s_sub_i32 s0, s5, s0
103 ; GFX8-NEXT: s_sub_i32 s1, s0, s4
104 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v4
105 ; GFX8-NEXT: s_cmp_ge_u32 s0, s4
106 ; GFX8-NEXT: s_cselect_b64 vcc, -1, 0
107 ; GFX8-NEXT: s_cselect_b32 s0, s1, s0
108 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
109 ; GFX8-NEXT: s_sub_i32 s1, s0, s4
110 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v4
111 ; GFX8-NEXT: s_cmp_ge_u32 s0, s4
112 ; GFX8-NEXT: s_cselect_b64 vcc, -1, 0
113 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
114 ; GFX8-NEXT: s_cselect_b32 s0, s1, s0
115 ; GFX8-NEXT: flat_store_dword v[0:1], v4
116 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
117 ; GFX8-NEXT: flat_store_dword v[2:3], v0
118 ; GFX8-NEXT: s_endpgm
119 %result0 = udiv i32 %x, %y
120 store i32 %result0, ptr addrspace(1) %out0
121 %result1 = urem i32 %x, %y
122 store i32 %result1, ptr addrspace(1) %out1
123 ret void
124 }
126 define amdgpu_kernel void @test_udivrem_v2(ptr addrspace(1) %out, <2 x i32> %x, <2 x i32> %y) {
127 ; R600-LABEL: test_udivrem_v2:
128 ; R600: ; %bb.0:
129 ; R600-NEXT: ALU 29, @4, KC0[CB0:0-32], KC1[]
130 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
131 ; R600-NEXT: CF_END
132 ; R600-NEXT: PAD
133 ; R600-NEXT: ALU clause starting at 4:
134 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[3].Z,
135 ; R600-NEXT: RECIP_UINT * T0.X, KC0[3].Z,
136 ; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,
137 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[3].Y,
138 ; R600-NEXT: RECIP_UINT * T0.Z, KC0[3].Y,
139 ; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,
140 ; R600-NEXT: MULHI * T0.W, T0.Z, PS,
141 ; R600-NEXT: ADD_INT T0.W, T0.Z, PS,
142 ; R600-NEXT: MULHI * T0.Y, T0.X, T0.Y,
143 ; R600-NEXT: ADD_INT T1.W, T0.X, PS,
144 ; R600-NEXT: MULHI * T0.X, KC0[2].W, PV.W,
145 ; R600-NEXT: MULHI * T0.Y, KC0[3].X, PV.W,
146 ; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[3].Z,
147 ; R600-NEXT: SUB_INT T0.W, KC0[3].X, PS,
148 ; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[3].Y,
149 ; R600-NEXT: SUB_INT T0.Z, KC0[2].W, PS,
150 ; R600-NEXT: SETGE_UINT T1.W, PV.W, KC0[3].Z,
151 ; R600-NEXT: SUB_INT * T2.W, PV.W, KC0[3].Z,
152 ; R600-NEXT: CNDE_INT T1.Z, PV.W, T0.W, PS,
153 ; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Y,
154 ; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Y,
155 ; R600-NEXT: CNDE_INT T0.Z, PV.W, T0.Z, PS,
156 ; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Z,
157 ; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Z,
158 ; R600-NEXT: CNDE_INT T0.Y, PV.W, T1.Z, PS,
159 ; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Y,
160 ; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Y,
161 ; R600-NEXT: CNDE_INT T0.X, PV.W, T0.Z, PS,
162 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
163 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
164 ;
165 ; GFX6-LABEL: test_udivrem_v2:
166 ; GFX6: ; %bb.0:
167 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0xb
168 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
169 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
170 ; GFX6-NEXT: s_sub_i32 s0, 0, s6
171 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s7
172 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
173 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
174 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
175 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
176 ; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
177 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
178 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
179 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
180 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
181 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
182 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
183 ; GFX6-NEXT: s_mul_i32 s0, s0, s6
184 ; GFX6-NEXT: s_sub_i32 s0, s4, s0
185 ; GFX6-NEXT: s_sub_i32 s1, s0, s6
186 ; GFX6-NEXT: s_cmp_ge_u32 s0, s6
187 ; GFX6-NEXT: s_cselect_b32 s0, s1, s0
188 ; GFX6-NEXT: s_sub_i32 s1, s0, s6
189 ; GFX6-NEXT: s_cmp_ge_u32 s0, s6
190 ; GFX6-NEXT: s_cselect_b32 s4, s1, s0
191 ; GFX6-NEXT: s_sub_i32 s0, 0, s7
192 ; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
193 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9
194 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
195 ; GFX6-NEXT: s_mov_b32 s2, -1
196 ; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
197 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
198 ; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
199 ; GFX6-NEXT: v_readfirstlane_b32 s6, v0
200 ; GFX6-NEXT: s_mul_i32 s6, s6, s7
201 ; GFX6-NEXT: s_sub_i32 s5, s5, s6
202 ; GFX6-NEXT: s_sub_i32 s6, s5, s7
203 ; GFX6-NEXT: s_cmp_ge_u32 s5, s7
204 ; GFX6-NEXT: s_cselect_b32 s5, s6, s5
205 ; GFX6-NEXT: s_sub_i32 s6, s5, s7
206 ; GFX6-NEXT: s_cmp_ge_u32 s5, s7
207 ; GFX6-NEXT: s_cselect_b32 s5, s6, s5
208 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
209 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
210 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
211 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
212 ; GFX6-NEXT: s_endpgm
213 ;
214 ; GFX8-LABEL: test_udivrem_v2:
215 ; GFX8: ; %bb.0:
216 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x2c
217 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
218 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6
219 ; GFX8-NEXT: s_sub_i32 s0, 0, s6
220 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s7
221 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
222 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
223 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
224 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
225 ; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0
226 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
227 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
228 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
229 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
230 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
231 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
232 ; GFX8-NEXT: s_mul_i32 s0, s0, s6
233 ; GFX8-NEXT: s_sub_i32 s0, s4, s0
234 ; GFX8-NEXT: s_sub_i32 s1, s0, s6
235 ; GFX8-NEXT: s_cmp_ge_u32 s0, s6
236 ; GFX8-NEXT: s_cselect_b32 s0, s1, s0
237 ; GFX8-NEXT: s_sub_i32 s1, s0, s6
238 ; GFX8-NEXT: s_cmp_ge_u32 s0, s6
239 ; GFX8-NEXT: s_cselect_b32 s4, s1, s0
240 ; GFX8-NEXT: s_sub_i32 s0, 0, s7
241 ; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1
242 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
243 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
244 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
245 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
246 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
247 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
248 ; GFX8-NEXT: v_mul_hi_u32 v1, s5, v0
249 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
250 ; GFX8-NEXT: v_readfirstlane_b32 s2, v1
251 ; GFX8-NEXT: s_mul_i32 s2, s2, s7
252 ; GFX8-NEXT: s_sub_i32 s2, s5, s2
253 ; GFX8-NEXT: s_sub_i32 s3, s2, s7
254 ; GFX8-NEXT: s_cmp_ge_u32 s2, s7
255 ; GFX8-NEXT: s_cselect_b32 s2, s3, s2
256 ; GFX8-NEXT: s_sub_i32 s3, s2, s7
257 ; GFX8-NEXT: s_cmp_ge_u32 s2, s7
258 ; GFX8-NEXT: s_cselect_b32 s2, s3, s2
259 ; GFX8-NEXT: v_mov_b32_e32 v1, s2
260 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
261 ; GFX8-NEXT: s_endpgm
262 %result0 = udiv <2 x i32> %x, %y
263 store <2 x i32> %result0, ptr addrspace(1) %out
264 %result1 = urem <2 x i32> %x, %y
265 store <2 x i32> %result1, ptr addrspace(1) %out
266 ret void
267 }
269 define amdgpu_kernel void @test_udivrem_v4(ptr addrspace(1) %out, <4 x i32> %x, <4 x i32> %y) {
270 ; R600-LABEL: test_udivrem_v4:
271 ; R600: ; %bb.0:
272 ; R600-NEXT: ALU 57, @4, KC0[CB0:0-32], KC1[]
273 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1
274 ; R600-NEXT: CF_END
275 ; R600-NEXT: PAD
276 ; R600-NEXT: ALU clause starting at 4:
277 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[5].X,
278 ; R600-NEXT: RECIP_UINT * T0.X, KC0[5].X,
279 ; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,
280 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[4].Z,
281 ; R600-NEXT: RECIP_UINT * T0.Z, KC0[4].Z,
282 ; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,
283 ; R600-NEXT: MULHI * T0.W, T0.Z, PS,
284 ; R600-NEXT: ADD_INT T0.W, T0.Z, PS,
285 ; R600-NEXT: MULHI * T0.Y, T0.X, T0.Y,
286 ; R600-NEXT: ADD_INT T1.W, T0.X, PS,
287 ; R600-NEXT: MULHI * T0.X, KC0[3].Z, PV.W,
288 ; R600-NEXT: MULHI * T0.Y, KC0[4].X, PV.W,
289 ; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[5].X,
290 ; R600-NEXT: RECIP_UINT * T0.Z, KC0[4].Y,
291 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[4].W,
292 ; R600-NEXT: RECIP_UINT * T1.X, KC0[4].W,
293 ; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,
294 ; R600-NEXT: SUB_INT T1.W, 0.0, KC0[4].Y,
295 ; R600-NEXT: MULHI * T0.W, T1.X, PS,
296 ; R600-NEXT: ADD_INT T0.W, T1.X, PS,
297 ; R600-NEXT: MULLO_INT * T1.X, PV.W, T0.Z,
298 ; R600-NEXT: MULHI * T0.W, KC0[3].W, PV.W,
299 ; R600-NEXT: MULLO_INT * T0.W, PS, KC0[4].W,
300 ; R600-NEXT: SUB_INT T0.W, KC0[3].W, PS,
301 ; R600-NEXT: MULHI * T1.X, T0.Z, T1.X,
302 ; R600-NEXT: SETGE_UINT T1.Y, PV.W, KC0[4].W,
303 ; R600-NEXT: ADD_INT T0.Z, T0.Z, PS,
304 ; R600-NEXT: SUB_INT T1.W, KC0[4].X, T0.Y,
305 ; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[4].Z,
306 ; R600-NEXT: SUB_INT T0.Y, KC0[3].Z, PS,
307 ; R600-NEXT: SETGE_UINT T1.Z, PV.W, KC0[5].X,
308 ; R600-NEXT: SUB_INT * T2.W, PV.W, KC0[5].X,
309 ; R600-NEXT: MULHI * T0.X, KC0[3].Y, T0.Z,
310 ; R600-NEXT: SUB_INT T1.X, T0.W, KC0[4].W,
311 ; R600-NEXT: CNDE_INT T2.Y, T1.Z, T1.W, T2.W,
312 ; R600-NEXT: SETGE_UINT T0.Z, T0.Y, KC0[4].Z,
313 ; R600-NEXT: SUB_INT T1.W, T0.Y, KC0[4].Z,
314 ; R600-NEXT: MULLO_INT * T0.X, PS, KC0[4].Y,
315 ; R600-NEXT: CNDE_INT T2.X, PV.Z, T0.Y, PV.W,
316 ; R600-NEXT: SETGE_UINT T0.Y, PV.Y, KC0[5].X,
317 ; R600-NEXT: SUB_INT T0.Z, PV.Y, KC0[5].X,
318 ; R600-NEXT: SUB_INT T1.W, KC0[3].Y, PS,
319 ; R600-NEXT: CNDE_INT * T0.W, T1.Y, T0.W, PV.X,
320 ; R600-NEXT: SETGE_UINT T0.X, PS, KC0[4].W,
321 ; R600-NEXT: SUB_INT T1.Y, PS, KC0[4].W,
322 ; R600-NEXT: SETGE_UINT T1.Z, PV.W, KC0[4].Y,
323 ; R600-NEXT: SUB_INT T2.W, PV.W, KC0[4].Y,
324 ; R600-NEXT: CNDE_INT * T3.W, PV.Y, T2.Y, PV.Z,
325 ; R600-NEXT: CNDE_INT T0.Y, PV.Z, T1.W, PV.W,
326 ; R600-NEXT: CNDE_INT T3.Z, PV.X, T0.W, PV.Y, BS:VEC_021/SCL_122
327 ; R600-NEXT: SETGE_UINT T0.W, T2.X, KC0[4].Z,
328 ; R600-NEXT: SUB_INT * T1.W, T2.X, KC0[4].Z,
329 ; R600-NEXT: CNDE_INT T3.Y, PV.W, T2.X, PS,
330 ; R600-NEXT: SETGE_UINT T0.W, PV.Y, KC0[4].Y,
331 ; R600-NEXT: SUB_INT * T1.W, PV.Y, KC0[4].Y,
332 ; R600-NEXT: CNDE_INT T3.X, PV.W, T0.Y, PS,
333 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
334 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
335 ;
336 ; GFX6-LABEL: test_udivrem_v4:
337 ; GFX6: ; %bb.0:
338 ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0xd
339 ; GFX6-NEXT: s_load_dwordx2 s[12:13], s[2:3], 0x9
340 ; GFX6-NEXT: s_mov_b32 s15, 0xf000
341 ; GFX6-NEXT: s_mov_b32 s14, -1
342 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
343 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
344 ; GFX6-NEXT: s_sub_i32 s0, 0, s8
345 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s9
346 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
347 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
348 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
349 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
350 ; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
351 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
352 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
353 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
354 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
355 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
356 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s10
357 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
358 ; GFX6-NEXT: s_mul_i32 s0, s0, s8
359 ; GFX6-NEXT: s_sub_i32 s0, s4, s0
360 ; GFX6-NEXT: s_sub_i32 s1, s0, s8
361 ; GFX6-NEXT: s_cmp_ge_u32 s0, s8
362 ; GFX6-NEXT: s_cselect_b32 s0, s1, s0
363 ; GFX6-NEXT: s_sub_i32 s1, s0, s8
364 ; GFX6-NEXT: s_cmp_ge_u32 s0, s8
365 ; GFX6-NEXT: s_cselect_b32 s0, s1, s0
366 ; GFX6-NEXT: s_sub_i32 s1, 0, s9
367 ; GFX6-NEXT: v_mul_lo_u32 v0, s1, v1
368 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
369 ; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
370 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
371 ; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
372 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
373 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
374 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s11
375 ; GFX6-NEXT: v_readfirstlane_b32 s1, v0
376 ; GFX6-NEXT: s_mul_i32 s1, s1, s9
377 ; GFX6-NEXT: s_sub_i32 s1, s5, s1
378 ; GFX6-NEXT: s_sub_i32 s4, s1, s9
379 ; GFX6-NEXT: s_cmp_ge_u32 s1, s9
380 ; GFX6-NEXT: s_cselect_b32 s1, s4, s1
381 ; GFX6-NEXT: s_sub_i32 s4, s1, s9
382 ; GFX6-NEXT: s_cmp_ge_u32 s1, s9
383 ; GFX6-NEXT: s_cselect_b32 s1, s4, s1
384 ; GFX6-NEXT: s_sub_i32 s4, 0, s10
385 ; GFX6-NEXT: v_mul_lo_u32 v0, s4, v1
386 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
387 ; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
388 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
389 ; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0
390 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
391 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
392 ; GFX6-NEXT: v_readfirstlane_b32 s4, v0
393 ; GFX6-NEXT: s_mul_i32 s4, s4, s10
394 ; GFX6-NEXT: s_sub_i32 s4, s6, s4
395 ; GFX6-NEXT: s_sub_i32 s5, s4, s10
396 ; GFX6-NEXT: s_cmp_ge_u32 s4, s10
397 ; GFX6-NEXT: s_cselect_b32 s4, s5, s4
398 ; GFX6-NEXT: s_sub_i32 s5, s4, s10
399 ; GFX6-NEXT: s_cmp_ge_u32 s4, s10
400 ; GFX6-NEXT: s_cselect_b32 s4, s5, s4
401 ; GFX6-NEXT: s_sub_i32 s5, 0, s11
402 ; GFX6-NEXT: v_mul_lo_u32 v0, s5, v1
403 ; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
404 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
405 ; GFX6-NEXT: v_mul_hi_u32 v2, s7, v0
406 ; GFX6-NEXT: v_mov_b32_e32 v0, s0
407 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
408 ; GFX6-NEXT: v_readfirstlane_b32 s0, v2
409 ; GFX6-NEXT: s_mul_i32 s0, s0, s11
410 ; GFX6-NEXT: s_sub_i32 s0, s7, s0
411 ; GFX6-NEXT: s_sub_i32 s1, s0, s11
412 ; GFX6-NEXT: s_cmp_ge_u32 s0, s11
413 ; GFX6-NEXT: s_cselect_b32 s0, s1, s0
414 ; GFX6-NEXT: s_sub_i32 s1, s0, s11
415 ; GFX6-NEXT: s_cmp_ge_u32 s0, s11
416 ; GFX6-NEXT: s_cselect_b32 s0, s1, s0
417 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
418 ; GFX6-NEXT: v_mov_b32_e32 v3, s0
419 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0
420 ; GFX6-NEXT: s_endpgm
421 ;
422 ; GFX8-LABEL: test_udivrem_v4:
423 ; GFX8: ; %bb.0:
424 ; GFX8-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x34
425 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
426 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s8
427 ; GFX8-NEXT: s_sub_i32 s0, 0, s8
428 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s9
429 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
430 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
431 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
432 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
433 ; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0
434 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
435 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
436 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
437 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
438 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
439 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s10
440 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
441 ; GFX8-NEXT: s_mul_i32 s0, s0, s8
442 ; GFX8-NEXT: s_sub_i32 s0, s4, s0
443 ; GFX8-NEXT: s_sub_i32 s1, s0, s8
444 ; GFX8-NEXT: s_cmp_ge_u32 s0, s8
445 ; GFX8-NEXT: s_cselect_b32 s0, s1, s0
446 ; GFX8-NEXT: s_sub_i32 s1, s0, s8
447 ; GFX8-NEXT: s_cmp_ge_u32 s0, s8
448 ; GFX8-NEXT: s_cselect_b32 s4, s1, s0
449 ; GFX8-NEXT: s_sub_i32 s0, 0, s9
450 ; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1
451 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
452 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
453 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
454 ; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
455 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
456 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
457 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s11
458 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
459 ; GFX8-NEXT: s_mul_i32 s0, s0, s9
460 ; GFX8-NEXT: s_sub_i32 s0, s5, s0
461 ; GFX8-NEXT: s_sub_i32 s1, s0, s9
462 ; GFX8-NEXT: s_cmp_ge_u32 s0, s9
463 ; GFX8-NEXT: s_cselect_b32 s0, s1, s0
464 ; GFX8-NEXT: s_sub_i32 s1, s0, s9
465 ; GFX8-NEXT: s_cmp_ge_u32 s0, s9
466 ; GFX8-NEXT: s_cselect_b32 s5, s1, s0
467 ; GFX8-NEXT: s_sub_i32 s0, 0, s10
468 ; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1
469 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
470 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
471 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
472 ; GFX8-NEXT: v_mul_hi_u32 v0, s6, v0
473 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
474 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
475 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
476 ; GFX8-NEXT: s_mul_i32 s0, s0, s10
477 ; GFX8-NEXT: s_sub_i32 s0, s6, s0
478 ; GFX8-NEXT: s_sub_i32 s1, s0, s10
479 ; GFX8-NEXT: s_cmp_ge_u32 s0, s10
480 ; GFX8-NEXT: s_cselect_b32 s0, s1, s0
481 ; GFX8-NEXT: s_sub_i32 s1, s0, s10
482 ; GFX8-NEXT: s_cmp_ge_u32 s0, s10
483 ; GFX8-NEXT: s_cselect_b32 s6, s1, s0
484 ; GFX8-NEXT: s_sub_i32 s0, 0, s11
485 ; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1
486 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24
487 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
488 ; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
489 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
490 ; GFX8-NEXT: v_mov_b32_e32 v5, s1
491 ; GFX8-NEXT: v_mov_b32_e32 v4, s0
492 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
493 ; GFX8-NEXT: v_mul_hi_u32 v3, s7, v0
494 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
495 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
496 ; GFX8-NEXT: v_readfirstlane_b32 s2, v3
497 ; GFX8-NEXT: s_mul_i32 s2, s2, s11
498 ; GFX8-NEXT: s_sub_i32 s2, s7, s2
499 ; GFX8-NEXT: s_sub_i32 s3, s2, s11
500 ; GFX8-NEXT: s_cmp_ge_u32 s2, s11
501 ; GFX8-NEXT: s_cselect_b32 s2, s3, s2
502 ; GFX8-NEXT: s_sub_i32 s3, s2, s11
503 ; GFX8-NEXT: s_cmp_ge_u32 s2, s11
504 ; GFX8-NEXT: s_cselect_b32 s2, s3, s2
505 ; GFX8-NEXT: v_mov_b32_e32 v3, s2
506 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
507 ; GFX8-NEXT: s_endpgm
508 %result0 = udiv <4 x i32> %x, %y
509 store <4 x i32> %result0, ptr addrspace(1) %out
510 %result1 = urem <4 x i32> %x, %y
511 store <4 x i32> %result1, ptr addrspace(1) %out
512 ret void
513 }