1 ; RUN: llc < %s -mtriple=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
2 ; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
4 ; GCN-LABEL: {{^}}icmp_2_users:
5 ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1
6 ; GCN: s_cbranch_scc1 [[LABEL:.LBB[0-9_A-Z]+]]
9 define amdgpu_kernel void @icmp_2_users(ptr addrspace(1) %out, i32 %cond) {
11 %0 = icmp sgt i32 %cond, 0
12 %1 = sext i1 %0 to i32
13 br i1 %0, label %IF, label %ENDIF
16 store i32 %1, ptr addrspace(1) %out
19 ENDIF: ; preds = %IF, %main_body
23 ; GCN-LABEL: {{^}}fix_sgpr_live_ranges_crash:
24 ; GCN: s_cbranch_scc1 [[BB0:.L[A-Z0-9_]+]]
25 ; GCN: {{^}}[[LOOP:.L[A-Z0-9_]+]]:
26 ; GCN: s_cbranch_scc1 [[LOOP]]
28 define amdgpu_kernel void @fix_sgpr_live_ranges_crash(i32 %arg, i32 %arg1, i1 %c0) {
30 %cnd = trunc i32 %arg to i1
31 br i1 %cnd, label %bb2, label %bb5
34 %tmp = mul i32 10, %arg1
37 bb3: ; preds = %bb3, %bb2
38 %val = load volatile i32, ptr addrspace(4) undef
39 %tmp4 = icmp eq i32 %val, %arg1
40 br i1 %tmp4, label %bb5, label %bb3
42 bb5: ; preds = %bb3, %bb
43 %tmp6 = tail call i32 @llvm.amdgcn.workitem.id.y() #1
44 %tmp10 = icmp ult i32 %tmp6, %arg
45 br i1 %tmp10, label %bb11, label %bb12
47 bb11: ; preds = %bb11, %bb5
48 br i1 %c0, label %bb11, label %bb12
50 bb12: ; preds = %bb11, %bb5
54 ; Function Attrs: nounwind readnone
55 declare i32 @llvm.amdgcn.workitem.id.y() #1
57 attributes #1 = { nounwind readnone }