1 # RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fix-cmse-cve-2021-35465 --float-abi=hard --run-pass=arm-pseudo %s -o - | \
4 ; ModuleID = 'cmse-vlldm-no-reorder.ll'
5 source_filename = "cmse-vlldm-no-reorder.ll"
6 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
7 target triple = "thumbv8m.main"
9 @g = hidden local_unnamed_addr global float (...)* null, align 4
10 @a = hidden local_unnamed_addr global float 0.000000e+00, align 4
12 ; Function Attrs: nounwind
13 define hidden void @f() local_unnamed_addr #0 {
15 %0 = load float ()*, float ()** bitcast (float (...)** @g to float ()**), align 4
16 %call = tail call nnan ninf nsz float %0() #2
17 store float %call, float* @a, align 4
21 ; Function Attrs: nounwind
22 declare void @llvm.stackprotector(i8*, i8**) #1
24 attributes #0 = { nounwind "target-cpu"="cortex-m33" }
25 attributes #1 = { nounwind }
26 attributes #2 = { nounwind "cmse_nonsecure_call" }
32 exposesReturnsTwice: false
34 regBankSelected: false
37 tracksRegLiveness: true
42 isFrameAddressTaken: false
43 isReturnAddressTaken: false
53 cvBytesOfCalleeSavedRegisters: 0
54 hasOpaqueSPAdjustment: false
56 hasMustTailInVarArgFunc: false
62 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
63 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
64 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
65 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
66 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
67 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
70 machineFunctionInfo: {}
75 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
76 frame-setup CFI_INSTRUCTION def_cfa_offset 8
77 frame-setup CFI_INSTRUCTION offset $lr, -4
78 frame-setup CFI_INSTRUCTION offset $r7, -8
79 renamable $r0 = t2MOVi32imm @g
80 renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from `float ()** bitcast (float (...)** @g to float ()**)`)
81 tBLXNS_CALL killed renamable $r0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s0
82 renamable $r0 = t2MOVi32imm @a
83 VSTRS killed renamable $s0, killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into @a)
84 $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc
88 # CHECK-LABEL: bb.0.entry:
89 # CHECK: $sp = t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, $r4, $r5, $r6, undef $r7, $r8, $r9, $r10, $r11
90 # CHECK-NEXT: $r0 = t2BICri $r0, 1, 14 /* CC::al */, $noreg, $noreg
91 # CHECK-NEXT: $sp = tSUBspi $sp, 34, 14 /* CC::al */, $noreg
92 # CHECK-NEXT: VLSTM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $d0, implicit undef $d1, implicit undef $d2, implicit undef $d3, implicit undef $d4, implicit undef $d5, implicit undef $d6, implicit undef $d7, implicit $d8, implicit $d9, implicit $d10, implicit $d11, implicit $d12, implicit $d13, implicit $d14, implicit $d15
93 # CHECK-NEXT: $r1 = tMOVr $r0, 14 /* CC::al */, $noreg
94 # CHECK-NEXT: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
95 # CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
96 # CHECK-NEXT: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
97 # CHECK-NEXT: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg
98 # CHECK-NEXT: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg
99 # CHECK-NEXT: $r7 = tMOVr $r0, 14 /* CC::al */, $noreg
100 # CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
101 # CHECK-NEXT: $r9 = tMOVr $r0, 14 /* CC::al */, $noreg
102 # CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
103 # CHECK-NEXT: $r11 = tMOVr $r0, 14 /* CC::al */, $noreg
104 # CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
105 # CHECK-NEXT: t2MSR_M 3072, $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
106 # CHECK-NEXT: tBLXNSr 14 /* CC::al */, $noreg, killed $r0, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s0
107 # CHECK-NEXT: $r12 = VMOVRS $s0, 14 /* CC::al */, $noreg
108 # CHECK-NEXT: VLLDM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $d0, implicit-def $d1, implicit-def $d2, implicit-def $d3, implicit-def $d4, implicit-def $d5, implicit-def $d6, implicit-def $d7, implicit-def $d8, implicit-def $d9, implicit-def $d10, implicit-def $d11, implicit-def $d12, implicit-def $d13, implicit-def $d14, implicit-def $d15
109 # CHECK-NEXT: $s0 = VMOVSR $r12, 14 /* CC::al */, $noreg
110 # CHECK-NEXT: $sp = tADDspi $sp, 34, 14 /* CC::al */, $noreg
111 # CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11