| blob | a8421ae9a6a89f611a3c0b5aa60053b995573648 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=ARM,ARM6
3 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=ARM,ARM78
4 ; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=ARM,ARM78
5 ; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=THUMB,THUMB6
6 ; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=THUMB,THUMB78
7 ; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=THUMB,THUMB78
9 ; We are looking for the following pattern here:
10 ; (X & (C << Y)) ==/!= 0
11 ; It may be optimal to hoist the constant:
12 ; ((X l>> Y) & C) ==/!= 0
14 ;------------------------------------------------------------------------------;
15 ; A few scalar test
16 ;------------------------------------------------------------------------------;
18 ; i8 scalar
20 define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
21 ; ARM-LABEL: scalar_i8_signbit_eq:
22 ; ARM: @ %bb.0:
23 ; ARM-NEXT: uxtb r1, r1
24 ; ARM-NEXT: uxtb r0, r0
25 ; ARM-NEXT: lsr r0, r0, r1
26 ; ARM-NEXT: mov r1, #1
27 ; ARM-NEXT: eor r0, r1, r0, lsr #7
28 ; ARM-NEXT: bx lr
29 ;
30 ; THUMB6-LABEL: scalar_i8_signbit_eq:
31 ; THUMB6: @ %bb.0:
32 ; THUMB6-NEXT: uxtb r1, r1
33 ; THUMB6-NEXT: uxtb r0, r0
34 ; THUMB6-NEXT: lsrs r0, r1
35 ; THUMB6-NEXT: movs r1, #128
36 ; THUMB6-NEXT: ands r1, r0
37 ; THUMB6-NEXT: rsbs r0, r1, #0
38 ; THUMB6-NEXT: adcs r0, r1
39 ; THUMB6-NEXT: bx lr
40 ;
41 ; THUMB78-LABEL: scalar_i8_signbit_eq:
42 ; THUMB78: @ %bb.0:
43 ; THUMB78-NEXT: uxtb r1, r1
44 ; THUMB78-NEXT: uxtb r0, r0
45 ; THUMB78-NEXT: lsrs r0, r1
46 ; THUMB78-NEXT: movs r1, #1
47 ; THUMB78-NEXT: eor.w r0, r1, r0, lsr #7
48 ; THUMB78-NEXT: bx lr
49 %t0 = shl i8 128, %y
50 %t1 = and i8 %t0, %x
51 %res = icmp eq i8 %t1, 0
52 ret i1 %res
53 }
55 define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
56 ; ARM-LABEL: scalar_i8_lowestbit_eq:
57 ; ARM: @ %bb.0:
58 ; ARM-NEXT: uxtb r1, r1
59 ; ARM-NEXT: uxtb r0, r0
60 ; ARM-NEXT: mov r2, #1
61 ; ARM-NEXT: bic r0, r2, r0, lsr r1
62 ; ARM-NEXT: bx lr
63 ;
64 ; THUMB6-LABEL: scalar_i8_lowestbit_eq:
65 ; THUMB6: @ %bb.0:
66 ; THUMB6-NEXT: uxtb r1, r1
67 ; THUMB6-NEXT: uxtb r0, r0
68 ; THUMB6-NEXT: lsrs r0, r1
69 ; THUMB6-NEXT: movs r1, #1
70 ; THUMB6-NEXT: ands r1, r0
71 ; THUMB6-NEXT: rsbs r0, r1, #0
72 ; THUMB6-NEXT: adcs r0, r1
73 ; THUMB6-NEXT: bx lr
74 ;
75 ; THUMB78-LABEL: scalar_i8_lowestbit_eq:
76 ; THUMB78: @ %bb.0:
77 ; THUMB78-NEXT: uxtb r1, r1
78 ; THUMB78-NEXT: uxtb r0, r0
79 ; THUMB78-NEXT: lsrs r0, r1
80 ; THUMB78-NEXT: movs r1, #1
81 ; THUMB78-NEXT: bic.w r0, r1, r0
82 ; THUMB78-NEXT: bx lr
83 %t0 = shl i8 1, %y
84 %t1 = and i8 %t0, %x
85 %res = icmp eq i8 %t1, 0
86 ret i1 %res
87 }
89 define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
90 ; ARM-LABEL: scalar_i8_bitsinmiddle_eq:
91 ; ARM: @ %bb.0:
92 ; ARM-NEXT: uxtb r1, r1
93 ; ARM-NEXT: uxtb r0, r0
94 ; ARM-NEXT: mov r2, #24
95 ; ARM-NEXT: and r0, r2, r0, lsr r1
96 ; ARM-NEXT: clz r0, r0
97 ; ARM-NEXT: lsr r0, r0, #5
98 ; ARM-NEXT: bx lr
99 ;
100 ; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:
101 ; THUMB6: @ %bb.0:
102 ; THUMB6-NEXT: uxtb r1, r1
103 ; THUMB6-NEXT: uxtb r0, r0
104 ; THUMB6-NEXT: lsrs r0, r1
105 ; THUMB6-NEXT: movs r1, #24
106 ; THUMB6-NEXT: ands r1, r0
107 ; THUMB6-NEXT: rsbs r0, r1, #0
108 ; THUMB6-NEXT: adcs r0, r1
109 ; THUMB6-NEXT: bx lr
110 ;
111 ; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq:
112 ; THUMB78: @ %bb.0:
113 ; THUMB78-NEXT: uxtb r1, r1
114 ; THUMB78-NEXT: uxtb r0, r0
115 ; THUMB78-NEXT: lsrs r0, r1
116 ; THUMB78-NEXT: and r0, r0, #24
117 ; THUMB78-NEXT: clz r0, r0
118 ; THUMB78-NEXT: lsrs r0, r0, #5
119 ; THUMB78-NEXT: bx lr
120 %t0 = shl i8 24, %y
121 %t1 = and i8 %t0, %x
122 %res = icmp eq i8 %t1, 0
123 ret i1 %res
124 }
126 ; i16 scalar
128 define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
129 ; ARM-LABEL: scalar_i16_signbit_eq:
130 ; ARM: @ %bb.0:
131 ; ARM-NEXT: uxth r1, r1
132 ; ARM-NEXT: uxth r0, r0
133 ; ARM-NEXT: lsr r0, r0, r1
134 ; ARM-NEXT: mov r1, #1
135 ; ARM-NEXT: eor r0, r1, r0, lsr #15
136 ; ARM-NEXT: bx lr
137 ;
138 ; THUMB6-LABEL: scalar_i16_signbit_eq:
139 ; THUMB6: @ %bb.0:
140 ; THUMB6-NEXT: uxth r1, r1
141 ; THUMB6-NEXT: uxth r0, r0
142 ; THUMB6-NEXT: lsrs r0, r1
143 ; THUMB6-NEXT: movs r1, #1
144 ; THUMB6-NEXT: lsls r1, r1, #15
145 ; THUMB6-NEXT: ands r1, r0
146 ; THUMB6-NEXT: rsbs r0, r1, #0
147 ; THUMB6-NEXT: adcs r0, r1
148 ; THUMB6-NEXT: bx lr
149 ;
150 ; THUMB78-LABEL: scalar_i16_signbit_eq:
151 ; THUMB78: @ %bb.0:
152 ; THUMB78-NEXT: uxth r1, r1
153 ; THUMB78-NEXT: uxth r0, r0
154 ; THUMB78-NEXT: lsrs r0, r1
155 ; THUMB78-NEXT: movs r1, #1
156 ; THUMB78-NEXT: eor.w r0, r1, r0, lsr #15
157 ; THUMB78-NEXT: bx lr
158 %t0 = shl i16 32768, %y
159 %t1 = and i16 %t0, %x
160 %res = icmp eq i16 %t1, 0
161 ret i1 %res
162 }
164 define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
165 ; ARM-LABEL: scalar_i16_lowestbit_eq:
166 ; ARM: @ %bb.0:
167 ; ARM-NEXT: uxth r1, r1
168 ; ARM-NEXT: uxth r0, r0
169 ; ARM-NEXT: mov r2, #1
170 ; ARM-NEXT: bic r0, r2, r0, lsr r1
171 ; ARM-NEXT: bx lr
172 ;
173 ; THUMB6-LABEL: scalar_i16_lowestbit_eq:
174 ; THUMB6: @ %bb.0:
175 ; THUMB6-NEXT: uxth r1, r1
176 ; THUMB6-NEXT: uxth r0, r0
177 ; THUMB6-NEXT: lsrs r0, r1
178 ; THUMB6-NEXT: movs r1, #1
179 ; THUMB6-NEXT: ands r1, r0
180 ; THUMB6-NEXT: rsbs r0, r1, #0
181 ; THUMB6-NEXT: adcs r0, r1
182 ; THUMB6-NEXT: bx lr
183 ;
184 ; THUMB78-LABEL: scalar_i16_lowestbit_eq:
185 ; THUMB78: @ %bb.0:
186 ; THUMB78-NEXT: uxth r1, r1
187 ; THUMB78-NEXT: uxth r0, r0
188 ; THUMB78-NEXT: lsrs r0, r1
189 ; THUMB78-NEXT: movs r1, #1
190 ; THUMB78-NEXT: bic.w r0, r1, r0
191 ; THUMB78-NEXT: bx lr
192 %t0 = shl i16 1, %y
193 %t1 = and i16 %t0, %x
194 %res = icmp eq i16 %t1, 0
195 ret i1 %res
196 }
198 define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
199 ; ARM-LABEL: scalar_i16_bitsinmiddle_eq:
200 ; ARM: @ %bb.0:
201 ; ARM-NEXT: uxth r1, r1
202 ; ARM-NEXT: uxth r0, r0
203 ; ARM-NEXT: mov r2, #4080
204 ; ARM-NEXT: and r0, r2, r0, lsr r1
205 ; ARM-NEXT: clz r0, r0
206 ; ARM-NEXT: lsr r0, r0, #5
207 ; ARM-NEXT: bx lr
208 ;
209 ; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:
210 ; THUMB6: @ %bb.0:
211 ; THUMB6-NEXT: uxth r1, r1
212 ; THUMB6-NEXT: uxth r0, r0
213 ; THUMB6-NEXT: lsrs r0, r1
214 ; THUMB6-NEXT: movs r1, #255
215 ; THUMB6-NEXT: lsls r1, r1, #4
216 ; THUMB6-NEXT: ands r1, r0
217 ; THUMB6-NEXT: rsbs r0, r1, #0
218 ; THUMB6-NEXT: adcs r0, r1
219 ; THUMB6-NEXT: bx lr
220 ;
221 ; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq:
222 ; THUMB78: @ %bb.0:
223 ; THUMB78-NEXT: uxth r1, r1
224 ; THUMB78-NEXT: uxth r0, r0
225 ; THUMB78-NEXT: lsrs r0, r1
226 ; THUMB78-NEXT: and r0, r0, #4080
227 ; THUMB78-NEXT: clz r0, r0
228 ; THUMB78-NEXT: lsrs r0, r0, #5
229 ; THUMB78-NEXT: bx lr
230 %t0 = shl i16 4080, %y
231 %t1 = and i16 %t0, %x
232 %res = icmp eq i16 %t1, 0
233 ret i1 %res
234 }
236 ; i32 scalar
238 define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {
239 ; ARM-LABEL: scalar_i32_signbit_eq:
240 ; ARM: @ %bb.0:
241 ; ARM-NEXT: mvn r0, r0, lsr r1
242 ; ARM-NEXT: lsr r0, r0, #31
243 ; ARM-NEXT: bx lr
244 ;
245 ; THUMB6-LABEL: scalar_i32_signbit_eq:
246 ; THUMB6: @ %bb.0:
247 ; THUMB6-NEXT: lsrs r0, r1
248 ; THUMB6-NEXT: movs r1, #1
249 ; THUMB6-NEXT: lsls r1, r1, #31
250 ; THUMB6-NEXT: ands r0, r1
251 ; THUMB6-NEXT: rsbs r1, r0, #0
252 ; THUMB6-NEXT: adcs r0, r1
253 ; THUMB6-NEXT: bx lr
254 ;
255 ; THUMB78-LABEL: scalar_i32_signbit_eq:
256 ; THUMB78: @ %bb.0:
257 ; THUMB78-NEXT: lsrs r0, r1
258 ; THUMB78-NEXT: mvns r0, r0
259 ; THUMB78-NEXT: lsrs r0, r0, #31
260 ; THUMB78-NEXT: bx lr
261 %t0 = shl i32 2147483648, %y
262 %t1 = and i32 %t0, %x
263 %res = icmp eq i32 %t1, 0
264 ret i1 %res
265 }
267 define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {
268 ; ARM-LABEL: scalar_i32_lowestbit_eq:
269 ; ARM: @ %bb.0:
270 ; ARM-NEXT: mov r2, #1
271 ; ARM-NEXT: bic r0, r2, r0, lsr r1
272 ; ARM-NEXT: bx lr
273 ;
274 ; THUMB6-LABEL: scalar_i32_lowestbit_eq:
275 ; THUMB6: @ %bb.0:
276 ; THUMB6-NEXT: lsrs r0, r1
277 ; THUMB6-NEXT: movs r1, #1
278 ; THUMB6-NEXT: ands r0, r1
279 ; THUMB6-NEXT: rsbs r1, r0, #0
280 ; THUMB6-NEXT: adcs r0, r1
281 ; THUMB6-NEXT: bx lr
282 ;
283 ; THUMB78-LABEL: scalar_i32_lowestbit_eq:
284 ; THUMB78: @ %bb.0:
285 ; THUMB78-NEXT: lsrs r0, r1
286 ; THUMB78-NEXT: movs r1, #1
287 ; THUMB78-NEXT: bic.w r0, r1, r0
288 ; THUMB78-NEXT: bx lr
289 %t0 = shl i32 1, %y
290 %t1 = and i32 %t0, %x
291 %res = icmp eq i32 %t1, 0
292 ret i1 %res
293 }
295 define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {
296 ; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:
297 ; ARM6: @ %bb.0:
298 ; ARM6-NEXT: mov r2, #65280
299 ; ARM6-NEXT: orr r2, r2, #16711680
300 ; ARM6-NEXT: and r0, r2, r0, lsr r1
301 ; ARM6-NEXT: clz r0, r0
302 ; ARM6-NEXT: lsr r0, r0, #5
303 ; ARM6-NEXT: bx lr
304 ;
305 ; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:
306 ; ARM78: @ %bb.0:
307 ; ARM78-NEXT: movw r2, #65280
308 ; ARM78-NEXT: movt r2, #255
309 ; ARM78-NEXT: and r0, r2, r0, lsr r1
310 ; ARM78-NEXT: clz r0, r0
311 ; ARM78-NEXT: lsr r0, r0, #5
312 ; ARM78-NEXT: bx lr
313 ;
314 ; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
315 ; THUMB6: @ %bb.0:
316 ; THUMB6-NEXT: lsrs r0, r1
317 ; THUMB6-NEXT: ldr r1, .LCPI8_0
318 ; THUMB6-NEXT: ands r0, r1
319 ; THUMB6-NEXT: rsbs r1, r0, #0
320 ; THUMB6-NEXT: adcs r0, r1
321 ; THUMB6-NEXT: bx lr
322 ; THUMB6-NEXT: .p2align 2
323 ; THUMB6-NEXT: @ %bb.1:
324 ; THUMB6-NEXT: .LCPI8_0:
325 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
326 ;
327 ; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
328 ; THUMB78: @ %bb.0:
329 ; THUMB78-NEXT: lsrs r0, r1
330 ; THUMB78-NEXT: movw r1, #65280
331 ; THUMB78-NEXT: movt r1, #255
332 ; THUMB78-NEXT: ands r0, r1
333 ; THUMB78-NEXT: clz r0, r0
334 ; THUMB78-NEXT: lsrs r0, r0, #5
335 ; THUMB78-NEXT: bx lr
336 %t0 = shl i32 16776960, %y
337 %t1 = and i32 %t0, %x
338 %res = icmp eq i32 %t1, 0
339 ret i1 %res
340 }
342 ; i64 scalar
344 define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
345 ; ARM6-LABEL: scalar_i64_signbit_eq:
346 ; ARM6: @ %bb.0:
347 ; ARM6-NEXT: lsr r0, r1, r2
348 ; ARM6-NEXT: subs r1, r2, #32
349 ; ARM6-NEXT: movpl r0, #0
350 ; ARM6-NEXT: mvn r0, r0
351 ; ARM6-NEXT: lsr r0, r0, #31
352 ; ARM6-NEXT: bx lr
353 ;
354 ; ARM78-LABEL: scalar_i64_signbit_eq:
355 ; ARM78: @ %bb.0:
356 ; ARM78-NEXT: lsr r0, r1, r2
357 ; ARM78-NEXT: subs r1, r2, #32
358 ; ARM78-NEXT: movwpl r0, #0
359 ; ARM78-NEXT: mvn r0, r0
360 ; ARM78-NEXT: lsr r0, r0, #31
361 ; ARM78-NEXT: bx lr
362 ;
363 ; THUMB6-LABEL: scalar_i64_signbit_eq:
364 ; THUMB6: @ %bb.0:
365 ; THUMB6-NEXT: push {r7, lr}
366 ; THUMB6-NEXT: bl __lshrdi3
367 ; THUMB6-NEXT: movs r0, #1
368 ; THUMB6-NEXT: lsls r2, r0, #31
369 ; THUMB6-NEXT: ands r2, r1
370 ; THUMB6-NEXT: rsbs r0, r2, #0
371 ; THUMB6-NEXT: adcs r0, r2
372 ; THUMB6-NEXT: pop {r7, pc}
373 ;
374 ; THUMB78-LABEL: scalar_i64_signbit_eq:
375 ; THUMB78: @ %bb.0:
376 ; THUMB78-NEXT: lsr.w r0, r1, r2
377 ; THUMB78-NEXT: subs.w r1, r2, #32
378 ; THUMB78-NEXT: it pl
379 ; THUMB78-NEXT: movpl r0, #0
380 ; THUMB78-NEXT: mvns r0, r0
381 ; THUMB78-NEXT: lsrs r0, r0, #31
382 ; THUMB78-NEXT: bx lr
383 %t0 = shl i64 9223372036854775808, %y
384 %t1 = and i64 %t0, %x
385 %res = icmp eq i64 %t1, 0
386 ret i1 %res
387 }
389 define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
390 ; ARM-LABEL: scalar_i64_lowestbit_eq:
391 ; ARM: @ %bb.0:
392 ; ARM-NEXT: rsb r3, r2, #32
393 ; ARM-NEXT: lsr r0, r0, r2
394 ; ARM-NEXT: subs r2, r2, #32
395 ; ARM-NEXT: orr r0, r0, r1, lsl r3
396 ; ARM-NEXT: lsrpl r0, r1, r2
397 ; ARM-NEXT: mov r1, #1
398 ; ARM-NEXT: bic r0, r1, r0
399 ; ARM-NEXT: bx lr
400 ;
401 ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
402 ; THUMB6: @ %bb.0:
403 ; THUMB6-NEXT: push {r7, lr}
404 ; THUMB6-NEXT: bl __lshrdi3
405 ; THUMB6-NEXT: movs r1, #1
406 ; THUMB6-NEXT: ands r0, r1
407 ; THUMB6-NEXT: rsbs r1, r0, #0
408 ; THUMB6-NEXT: adcs r0, r1
409 ; THUMB6-NEXT: pop {r7, pc}
410 ;
411 ; THUMB78-LABEL: scalar_i64_lowestbit_eq:
412 ; THUMB78: @ %bb.0:
413 ; THUMB78-NEXT: rsb.w r3, r2, #32
414 ; THUMB78-NEXT: lsrs r0, r2
415 ; THUMB78-NEXT: subs r2, #32
416 ; THUMB78-NEXT: lsl.w r3, r1, r3
417 ; THUMB78-NEXT: orr.w r0, r0, r3
418 ; THUMB78-NEXT: it pl
419 ; THUMB78-NEXT: lsrpl.w r0, r1, r2
420 ; THUMB78-NEXT: movs r1, #1
421 ; THUMB78-NEXT: bic.w r0, r1, r0
422 ; THUMB78-NEXT: bx lr
423 %t0 = shl i64 1, %y
424 %t1 = and i64 %t0, %x
425 %res = icmp eq i64 %t1, 0
426 ret i1 %res
427 }
429 define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
430 ; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
431 ; ARM6: @ %bb.0:
432 ; ARM6-NEXT: rsb r3, r2, #32
433 ; ARM6-NEXT: lsr r0, r0, r2
434 ; ARM6-NEXT: orr r0, r0, r1, lsl r3
435 ; ARM6-NEXT: subs r3, r2, #32
436 ; ARM6-NEXT: lsrpl r0, r1, r3
437 ; ARM6-NEXT: lsr r1, r1, r2
438 ; ARM6-NEXT: movpl r1, #0
439 ; ARM6-NEXT: pkhbt r0, r1, r0
440 ; ARM6-NEXT: clz r0, r0
441 ; ARM6-NEXT: lsr r0, r0, #5
442 ; ARM6-NEXT: bx lr
443 ;
444 ; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
445 ; ARM78: @ %bb.0:
446 ; ARM78-NEXT: rsb r3, r2, #32
447 ; ARM78-NEXT: lsr r0, r0, r2
448 ; ARM78-NEXT: orr r0, r0, r1, lsl r3
449 ; ARM78-NEXT: subs r3, r2, #32
450 ; ARM78-NEXT: lsrpl r0, r1, r3
451 ; ARM78-NEXT: lsr r1, r1, r2
452 ; ARM78-NEXT: movwpl r1, #0
453 ; ARM78-NEXT: pkhbt r0, r1, r0
454 ; ARM78-NEXT: clz r0, r0
455 ; ARM78-NEXT: lsr r0, r0, #5
456 ; ARM78-NEXT: bx lr
457 ;
458 ; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
459 ; THUMB6: @ %bb.0:
460 ; THUMB6-NEXT: push {r7, lr}
461 ; THUMB6-NEXT: bl __lshrdi3
462 ; THUMB6-NEXT: ldr r2, .LCPI11_0
463 ; THUMB6-NEXT: ands r2, r0
464 ; THUMB6-NEXT: uxth r0, r1
465 ; THUMB6-NEXT: adds r1, r2, r0
466 ; THUMB6-NEXT: rsbs r0, r1, #0
467 ; THUMB6-NEXT: adcs r0, r1
468 ; THUMB6-NEXT: pop {r7, pc}
469 ; THUMB6-NEXT: .p2align 2
470 ; THUMB6-NEXT: @ %bb.1:
471 ; THUMB6-NEXT: .LCPI11_0:
472 ; THUMB6-NEXT: .long 4294901760 @ 0xffff0000
473 ;
474 ; THUMB78-LABEL: scalar_i64_bitsinmiddle_eq:
475 ; THUMB78: @ %bb.0:
476 ; THUMB78-NEXT: rsb.w r3, r2, #32
477 ; THUMB78-NEXT: lsrs r0, r2
478 ; THUMB78-NEXT: lsl.w r3, r1, r3
479 ; THUMB78-NEXT: orrs r0, r3
480 ; THUMB78-NEXT: subs.w r3, r2, #32
481 ; THUMB78-NEXT: it pl
482 ; THUMB78-NEXT: lsrpl.w r0, r1, r3
483 ; THUMB78-NEXT: lsr.w r1, r1, r2
484 ; THUMB78-NEXT: it pl
485 ; THUMB78-NEXT: movpl r1, #0
486 ; THUMB78-NEXT: pkhbt r0, r1, r0
487 ; THUMB78-NEXT: clz r0, r0
488 ; THUMB78-NEXT: lsrs r0, r0, #5
489 ; THUMB78-NEXT: bx lr
490 %t0 = shl i64 281474976645120, %y
491 %t1 = and i64 %t0, %x
492 %res = icmp eq i64 %t1, 0
493 ret i1 %res
494 }
496 ;------------------------------------------------------------------------------;
497 ; A few trivial vector tests
498 ;------------------------------------------------------------------------------;
500 define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
501 ; ARM6-LABEL: vec_4xi32_splat_eq:
502 ; ARM6: @ %bb.0:
503 ; ARM6-NEXT: push {r11, lr}
504 ; ARM6-NEXT: ldr r12, [sp, #8]
505 ; ARM6-NEXT: mov lr, #1
506 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
507 ; ARM6-NEXT: ldr r12, [sp, #12]
508 ; ARM6-NEXT: bic r1, lr, r1, lsr r12
509 ; ARM6-NEXT: ldr r12, [sp, #16]
510 ; ARM6-NEXT: bic r2, lr, r2, lsr r12
511 ; ARM6-NEXT: ldr r12, [sp, #20]
512 ; ARM6-NEXT: bic r3, lr, r3, lsr r12
513 ; ARM6-NEXT: pop {r11, pc}
514 ;
515 ; ARM78-LABEL: vec_4xi32_splat_eq:
516 ; ARM78: @ %bb.0:
517 ; ARM78-NEXT: mov r12, sp
518 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
519 ; ARM78-NEXT: vmov d19, r2, r3
520 ; ARM78-NEXT: vneg.s32 q8, q8
521 ; ARM78-NEXT: vmov d18, r0, r1
522 ; ARM78-NEXT: vmov.i32 q10, #0x1
523 ; ARM78-NEXT: vshl.u32 q8, q9, q8
524 ; ARM78-NEXT: vtst.32 q8, q8, q10
525 ; ARM78-NEXT: vmvn q8, q8
526 ; ARM78-NEXT: vmovn.i32 d16, q8
527 ; ARM78-NEXT: vmov r0, r1, d16
528 ; ARM78-NEXT: bx lr
529 ;
530 ; THUMB6-LABEL: vec_4xi32_splat_eq:
531 ; THUMB6: @ %bb.0:
532 ; THUMB6-NEXT: push {r4, r5, r7, lr}
533 ; THUMB6-NEXT: ldr r4, [sp, #16]
534 ; THUMB6-NEXT: lsrs r0, r4
535 ; THUMB6-NEXT: movs r4, #1
536 ; THUMB6-NEXT: ands r0, r4
537 ; THUMB6-NEXT: rsbs r5, r0, #0
538 ; THUMB6-NEXT: adcs r0, r5
539 ; THUMB6-NEXT: ldr r5, [sp, #20]
540 ; THUMB6-NEXT: lsrs r1, r5
541 ; THUMB6-NEXT: ands r1, r4
542 ; THUMB6-NEXT: rsbs r5, r1, #0
543 ; THUMB6-NEXT: adcs r1, r5
544 ; THUMB6-NEXT: ldr r5, [sp, #24]
545 ; THUMB6-NEXT: lsrs r2, r5
546 ; THUMB6-NEXT: ands r2, r4
547 ; THUMB6-NEXT: rsbs r5, r2, #0
548 ; THUMB6-NEXT: adcs r2, r5
549 ; THUMB6-NEXT: ldr r5, [sp, #28]
550 ; THUMB6-NEXT: lsrs r3, r5
551 ; THUMB6-NEXT: ands r3, r4
552 ; THUMB6-NEXT: rsbs r4, r3, #0
553 ; THUMB6-NEXT: adcs r3, r4
554 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
555 ;
556 ; THUMB78-LABEL: vec_4xi32_splat_eq:
557 ; THUMB78: @ %bb.0:
558 ; THUMB78-NEXT: mov r12, sp
559 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
560 ; THUMB78-NEXT: vmov d19, r2, r3
561 ; THUMB78-NEXT: vneg.s32 q8, q8
562 ; THUMB78-NEXT: vmov d18, r0, r1
563 ; THUMB78-NEXT: vmov.i32 q10, #0x1
564 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
565 ; THUMB78-NEXT: vtst.32 q8, q8, q10
566 ; THUMB78-NEXT: vmvn q8, q8
567 ; THUMB78-NEXT: vmovn.i32 d16, q8
568 ; THUMB78-NEXT: vmov r0, r1, d16
569 ; THUMB78-NEXT: bx lr
570 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
571 %t1 = and <4 x i32> %t0, %x
572 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
573 ret <4 x i1> %res
574 }
576 define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
577 ; ARM6-LABEL: vec_4xi32_nonsplat_eq:
578 ; ARM6: @ %bb.0:
579 ; ARM6-NEXT: ldr r12, [sp, #4]
580 ; ARM6-NEXT: mov r0, #1
581 ; ARM6-NEXT: bic r1, r0, r1, lsr r12
582 ; ARM6-NEXT: ldr r12, [sp, #8]
583 ; ARM6-NEXT: mov r0, #65280
584 ; ARM6-NEXT: orr r0, r0, #16711680
585 ; ARM6-NEXT: and r0, r0, r2, lsr r12
586 ; ARM6-NEXT: clz r0, r0
587 ; ARM6-NEXT: lsr r2, r0, #5
588 ; ARM6-NEXT: ldr r0, [sp, #12]
589 ; ARM6-NEXT: mvn r0, r3, lsr r0
590 ; ARM6-NEXT: lsr r3, r0, #31
591 ; ARM6-NEXT: mov r0, #1
592 ; ARM6-NEXT: bx lr
593 ;
594 ; ARM78-LABEL: vec_4xi32_nonsplat_eq:
595 ; ARM78: @ %bb.0:
596 ; ARM78-NEXT: mov r12, sp
597 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
598 ; ARM78-NEXT: adr r12, .LCPI13_0
599 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128]
600 ; ARM78-NEXT: vshl.u32 q8, q9, q8
601 ; ARM78-NEXT: vmov d19, r2, r3
602 ; ARM78-NEXT: vmov d18, r0, r1
603 ; ARM78-NEXT: vtst.32 q8, q8, q9
604 ; ARM78-NEXT: vmvn q8, q8
605 ; ARM78-NEXT: vmovn.i32 d16, q8
606 ; ARM78-NEXT: vmov r0, r1, d16
607 ; ARM78-NEXT: bx lr
608 ; ARM78-NEXT: .p2align 4
609 ; ARM78-NEXT: @ %bb.1:
610 ; ARM78-NEXT: .LCPI13_0:
611 ; ARM78-NEXT: .long 0 @ 0x0
612 ; ARM78-NEXT: .long 1 @ 0x1
613 ; ARM78-NEXT: .long 16776960 @ 0xffff00
614 ; ARM78-NEXT: .long 2147483648 @ 0x80000000
615 ;
616 ; THUMB6-LABEL: vec_4xi32_nonsplat_eq:
617 ; THUMB6: @ %bb.0:
618 ; THUMB6-NEXT: push {r4, lr}
619 ; THUMB6-NEXT: ldr r0, [sp, #12]
620 ; THUMB6-NEXT: lsrs r1, r0
621 ; THUMB6-NEXT: movs r0, #1
622 ; THUMB6-NEXT: ands r1, r0
623 ; THUMB6-NEXT: rsbs r4, r1, #0
624 ; THUMB6-NEXT: adcs r1, r4
625 ; THUMB6-NEXT: ldr r4, [sp, #16]
626 ; THUMB6-NEXT: lsrs r2, r4
627 ; THUMB6-NEXT: ldr r4, .LCPI13_0
628 ; THUMB6-NEXT: ands r2, r4
629 ; THUMB6-NEXT: rsbs r4, r2, #0
630 ; THUMB6-NEXT: adcs r2, r4
631 ; THUMB6-NEXT: ldr r4, [sp, #20]
632 ; THUMB6-NEXT: lsrs r3, r4
633 ; THUMB6-NEXT: lsls r4, r0, #31
634 ; THUMB6-NEXT: ands r3, r4
635 ; THUMB6-NEXT: rsbs r4, r3, #0
636 ; THUMB6-NEXT: adcs r3, r4
637 ; THUMB6-NEXT: pop {r4, pc}
638 ; THUMB6-NEXT: .p2align 2
639 ; THUMB6-NEXT: @ %bb.1:
640 ; THUMB6-NEXT: .LCPI13_0:
641 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
642 ;
643 ; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
644 ; THUMB78: @ %bb.0:
645 ; THUMB78-NEXT: mov r12, sp
646 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
647 ; THUMB78-NEXT: adr.w r12, .LCPI13_0
648 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128]
649 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
650 ; THUMB78-NEXT: vmov d19, r2, r3
651 ; THUMB78-NEXT: vmov d18, r0, r1
652 ; THUMB78-NEXT: vtst.32 q8, q8, q9
653 ; THUMB78-NEXT: vmvn q8, q8
654 ; THUMB78-NEXT: vmovn.i32 d16, q8
655 ; THUMB78-NEXT: vmov r0, r1, d16
656 ; THUMB78-NEXT: bx lr
657 ; THUMB78-NEXT: .p2align 4
658 ; THUMB78-NEXT: @ %bb.1:
659 ; THUMB78-NEXT: .LCPI13_0:
660 ; THUMB78-NEXT: .long 0 @ 0x0
661 ; THUMB78-NEXT: .long 1 @ 0x1
662 ; THUMB78-NEXT: .long 16776960 @ 0xffff00
663 ; THUMB78-NEXT: .long 2147483648 @ 0x80000000
664 %t0 = shl <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
665 %t1 = and <4 x i32> %t0, %x
666 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
667 ret <4 x i1> %res
668 }
670 define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
671 ; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
672 ; ARM6: @ %bb.0:
673 ; ARM6-NEXT: push {r11, lr}
674 ; ARM6-NEXT: ldr r2, [sp, #12]
675 ; ARM6-NEXT: mov lr, #1
676 ; ARM6-NEXT: ldr r12, [sp, #8]
677 ; ARM6-NEXT: bic r1, lr, r1, lsr r2
678 ; ARM6-NEXT: ldr r2, [sp, #20]
679 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
680 ; ARM6-NEXT: bic r3, lr, r3, lsr r2
681 ; ARM6-NEXT: mov r2, #1
682 ; ARM6-NEXT: pop {r11, pc}
683 ;
684 ; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
685 ; ARM78: @ %bb.0:
686 ; ARM78-NEXT: mov r12, sp
687 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
688 ; ARM78-NEXT: vmov d19, r2, r3
689 ; ARM78-NEXT: vneg.s32 q8, q8
690 ; ARM78-NEXT: vmov d18, r0, r1
691 ; ARM78-NEXT: vmov.i32 q10, #0x1
692 ; ARM78-NEXT: vshl.u32 q8, q9, q8
693 ; ARM78-NEXT: vtst.32 q8, q8, q10
694 ; ARM78-NEXT: vmvn q8, q8
695 ; ARM78-NEXT: vmovn.i32 d16, q8
696 ; ARM78-NEXT: vmov r0, r1, d16
697 ; ARM78-NEXT: bx lr
698 ;
699 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:
700 ; THUMB6: @ %bb.0:
701 ; THUMB6-NEXT: push {r4, lr}
702 ; THUMB6-NEXT: ldr r2, [sp, #8]
703 ; THUMB6-NEXT: lsrs r0, r2
704 ; THUMB6-NEXT: movs r2, #1
705 ; THUMB6-NEXT: ands r0, r2
706 ; THUMB6-NEXT: rsbs r4, r0, #0
707 ; THUMB6-NEXT: adcs r0, r4
708 ; THUMB6-NEXT: ldr r4, [sp, #12]
709 ; THUMB6-NEXT: lsrs r1, r4
710 ; THUMB6-NEXT: ands r1, r2
711 ; THUMB6-NEXT: rsbs r4, r1, #0
712 ; THUMB6-NEXT: adcs r1, r4
713 ; THUMB6-NEXT: ldr r4, [sp, #20]
714 ; THUMB6-NEXT: lsrs r3, r4
715 ; THUMB6-NEXT: ands r3, r2
716 ; THUMB6-NEXT: rsbs r4, r3, #0
717 ; THUMB6-NEXT: adcs r3, r4
718 ; THUMB6-NEXT: pop {r4, pc}
719 ;
720 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:
721 ; THUMB78: @ %bb.0:
722 ; THUMB78-NEXT: mov r12, sp
723 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
724 ; THUMB78-NEXT: vmov d19, r2, r3
725 ; THUMB78-NEXT: vneg.s32 q8, q8
726 ; THUMB78-NEXT: vmov d18, r0, r1
727 ; THUMB78-NEXT: vmov.i32 q10, #0x1
728 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
729 ; THUMB78-NEXT: vtst.32 q8, q8, q10
730 ; THUMB78-NEXT: vmvn q8, q8
731 ; THUMB78-NEXT: vmovn.i32 d16, q8
732 ; THUMB78-NEXT: vmov r0, r1, d16
733 ; THUMB78-NEXT: bx lr
734 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
735 %t1 = and <4 x i32> %t0, %x
736 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
737 ret <4 x i1> %res
738 }
739 define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
740 ; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:
741 ; ARM6: @ %bb.0:
742 ; ARM6-NEXT: push {r11, lr}
743 ; ARM6-NEXT: ldr r2, [sp, #12]
744 ; ARM6-NEXT: mov lr, #1
745 ; ARM6-NEXT: ldr r12, [sp, #8]
746 ; ARM6-NEXT: bic r1, lr, r1, lsr r2
747 ; ARM6-NEXT: ldr r2, [sp, #20]
748 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
749 ; ARM6-NEXT: bic r3, lr, r3, lsr r2
750 ; ARM6-NEXT: pop {r11, pc}
751 ;
752 ; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:
753 ; ARM78: @ %bb.0:
754 ; ARM78-NEXT: vmov.i32 q8, #0x1
755 ; ARM78-NEXT: mov r12, sp
756 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
757 ; ARM78-NEXT: vshl.u32 q8, q8, q9
758 ; ARM78-NEXT: vmov d19, r2, r3
759 ; ARM78-NEXT: vmov d18, r0, r1
760 ; ARM78-NEXT: vtst.32 q8, q8, q9
761 ; ARM78-NEXT: vmvn q8, q8
762 ; ARM78-NEXT: vmovn.i32 d16, q8
763 ; ARM78-NEXT: vmov r0, r1, d16
764 ; ARM78-NEXT: bx lr
765 ;
766 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:
767 ; THUMB6: @ %bb.0:
768 ; THUMB6-NEXT: push {r4, lr}
769 ; THUMB6-NEXT: ldr r2, [sp, #8]
770 ; THUMB6-NEXT: lsrs r0, r2
771 ; THUMB6-NEXT: movs r2, #1
772 ; THUMB6-NEXT: ands r0, r2
773 ; THUMB6-NEXT: rsbs r4, r0, #0
774 ; THUMB6-NEXT: adcs r0, r4
775 ; THUMB6-NEXT: ldr r4, [sp, #12]
776 ; THUMB6-NEXT: lsrs r1, r4
777 ; THUMB6-NEXT: ands r1, r2
778 ; THUMB6-NEXT: rsbs r4, r1, #0
779 ; THUMB6-NEXT: adcs r1, r4
780 ; THUMB6-NEXT: ldr r4, [sp, #20]
781 ; THUMB6-NEXT: lsrs r3, r4
782 ; THUMB6-NEXT: ands r3, r2
783 ; THUMB6-NEXT: rsbs r2, r3, #0
784 ; THUMB6-NEXT: adcs r3, r2
785 ; THUMB6-NEXT: pop {r4, pc}
786 ;
787 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:
788 ; THUMB78: @ %bb.0:
789 ; THUMB78-NEXT: vmov.i32 q8, #0x1
790 ; THUMB78-NEXT: mov r12, sp
791 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
792 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
793 ; THUMB78-NEXT: vmov d19, r2, r3
794 ; THUMB78-NEXT: vmov d18, r0, r1
795 ; THUMB78-NEXT: vtst.32 q8, q8, q9
796 ; THUMB78-NEXT: vmvn q8, q8
797 ; THUMB78-NEXT: vmovn.i32 d16, q8
798 ; THUMB78-NEXT: vmov r0, r1, d16
799 ; THUMB78-NEXT: bx lr
800 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
801 %t1 = and <4 x i32> %t0, %x
802 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
803 ret <4 x i1> %res
804 }
805 define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
806 ; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:
807 ; ARM6: @ %bb.0:
808 ; ARM6-NEXT: push {r11, lr}
809 ; ARM6-NEXT: ldr r2, [sp, #12]
810 ; ARM6-NEXT: mov lr, #1
811 ; ARM6-NEXT: ldr r12, [sp, #8]
812 ; ARM6-NEXT: bic r1, lr, r1, lsr r2
813 ; ARM6-NEXT: ldr r2, [sp, #20]
814 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
815 ; ARM6-NEXT: bic r3, lr, r3, lsr r2
816 ; ARM6-NEXT: pop {r11, pc}
817 ;
818 ; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:
819 ; ARM78: @ %bb.0:
820 ; ARM78-NEXT: vmov.i32 q8, #0x1
821 ; ARM78-NEXT: mov r12, sp
822 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
823 ; ARM78-NEXT: vshl.u32 q8, q8, q9
824 ; ARM78-NEXT: vmov d19, r2, r3
825 ; ARM78-NEXT: vmov d18, r0, r1
826 ; ARM78-NEXT: vtst.32 q8, q8, q9
827 ; ARM78-NEXT: vmvn q8, q8
828 ; ARM78-NEXT: vmovn.i32 d16, q8
829 ; ARM78-NEXT: vmov r0, r1, d16
830 ; ARM78-NEXT: bx lr
831 ;
832 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:
833 ; THUMB6: @ %bb.0:
834 ; THUMB6-NEXT: push {r4, lr}
835 ; THUMB6-NEXT: ldr r2, [sp, #8]
836 ; THUMB6-NEXT: lsrs r0, r2
837 ; THUMB6-NEXT: movs r2, #1
838 ; THUMB6-NEXT: ands r0, r2
839 ; THUMB6-NEXT: rsbs r4, r0, #0
840 ; THUMB6-NEXT: adcs r0, r4
841 ; THUMB6-NEXT: ldr r4, [sp, #12]
842 ; THUMB6-NEXT: lsrs r1, r4
843 ; THUMB6-NEXT: ands r1, r2
844 ; THUMB6-NEXT: rsbs r4, r1, #0
845 ; THUMB6-NEXT: adcs r1, r4
846 ; THUMB6-NEXT: ldr r4, [sp, #20]
847 ; THUMB6-NEXT: lsrs r3, r4
848 ; THUMB6-NEXT: ands r3, r2
849 ; THUMB6-NEXT: rsbs r2, r3, #0
850 ; THUMB6-NEXT: adcs r3, r2
851 ; THUMB6-NEXT: pop {r4, pc}
852 ;
853 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:
854 ; THUMB78: @ %bb.0:
855 ; THUMB78-NEXT: vmov.i32 q8, #0x1
856 ; THUMB78-NEXT: mov r12, sp
857 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
858 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
859 ; THUMB78-NEXT: vmov d19, r2, r3
860 ; THUMB78-NEXT: vmov d18, r0, r1
861 ; THUMB78-NEXT: vtst.32 q8, q8, q9
862 ; THUMB78-NEXT: vmvn q8, q8
863 ; THUMB78-NEXT: vmovn.i32 d16, q8
864 ; THUMB78-NEXT: vmov r0, r1, d16
865 ; THUMB78-NEXT: bx lr
866 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
867 %t1 = and <4 x i32> %t0, %x
868 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
869 ret <4 x i1> %res
870 }
872 ;------------------------------------------------------------------------------;
873 ; A special tests
874 ;------------------------------------------------------------------------------;
876 define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
877 ; ARM-LABEL: scalar_i8_signbit_ne:
878 ; ARM: @ %bb.0:
879 ; ARM-NEXT: uxtb r1, r1
880 ; ARM-NEXT: uxtb r0, r0
881 ; ARM-NEXT: lsr r0, r0, r1
882 ; ARM-NEXT: lsr r0, r0, #7
883 ; ARM-NEXT: bx lr
884 ;
885 ; THUMB-LABEL: scalar_i8_signbit_ne:
886 ; THUMB: @ %bb.0:
887 ; THUMB-NEXT: uxtb r1, r1
888 ; THUMB-NEXT: uxtb r0, r0
889 ; THUMB-NEXT: lsrs r0, r1
890 ; THUMB-NEXT: lsrs r0, r0, #7
891 ; THUMB-NEXT: bx lr
892 %t0 = shl i8 128, %y
893 %t1 = and i8 %t0, %x
894 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate
895 ret i1 %res
896 }
898 ;------------------------------------------------------------------------------;
899 ; What if X is a constant too?
900 ;------------------------------------------------------------------------------;
902 define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
903 ; ARM6-LABEL: scalar_i32_x_is_const_eq:
904 ; ARM6: @ %bb.0:
905 ; ARM6-NEXT: ldr r1, .LCPI18_0
906 ; ARM6-NEXT: mov r2, #1
907 ; ARM6-NEXT: bic r0, r2, r1, lsl r0
908 ; ARM6-NEXT: bx lr
909 ; ARM6-NEXT: .p2align 2
910 ; ARM6-NEXT: @ %bb.1:
911 ; ARM6-NEXT: .LCPI18_0:
912 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
913 ;
914 ; ARM78-LABEL: scalar_i32_x_is_const_eq:
915 ; ARM78: @ %bb.0:
916 ; ARM78-NEXT: movw r1, #43605
917 ; ARM78-NEXT: mov r2, #1
918 ; ARM78-NEXT: movt r1, #43605
919 ; ARM78-NEXT: bic r0, r2, r1, lsl r0
920 ; ARM78-NEXT: bx lr
921 ;
922 ; THUMB6-LABEL: scalar_i32_x_is_const_eq:
923 ; THUMB6: @ %bb.0:
924 ; THUMB6-NEXT: ldr r1, .LCPI18_0
925 ; THUMB6-NEXT: lsls r1, r0
926 ; THUMB6-NEXT: movs r2, #1
927 ; THUMB6-NEXT: ands r2, r1
928 ; THUMB6-NEXT: rsbs r0, r2, #0
929 ; THUMB6-NEXT: adcs r0, r2
930 ; THUMB6-NEXT: bx lr
931 ; THUMB6-NEXT: .p2align 2
932 ; THUMB6-NEXT: @ %bb.1:
933 ; THUMB6-NEXT: .LCPI18_0:
934 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
935 ;
936 ; THUMB78-LABEL: scalar_i32_x_is_const_eq:
937 ; THUMB78: @ %bb.0:
938 ; THUMB78-NEXT: movw r1, #43605
939 ; THUMB78-NEXT: movt r1, #43605
940 ; THUMB78-NEXT: lsl.w r0, r1, r0
941 ; THUMB78-NEXT: movs r1, #1
942 ; THUMB78-NEXT: bic.w r0, r1, r0
943 ; THUMB78-NEXT: bx lr
944 %t0 = shl i32 2857740885, %y
945 %t1 = and i32 %t0, 1
946 %res = icmp eq i32 %t1, 0
947 ret i1 %res
948 }
949 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
950 ; ARM6-LABEL: scalar_i32_x_is_const2_eq:
951 ; ARM6: @ %bb.0:
952 ; ARM6-NEXT: ldr r2, .LCPI19_0
953 ; ARM6-NEXT: mov r1, #1
954 ; ARM6-NEXT: and r0, r2, r1, lsl r0
955 ; ARM6-NEXT: clz r0, r0
956 ; ARM6-NEXT: lsr r0, r0, #5
957 ; ARM6-NEXT: bx lr
958 ; ARM6-NEXT: .p2align 2
959 ; ARM6-NEXT: @ %bb.1:
960 ; ARM6-NEXT: .LCPI19_0:
961 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
962 ;
963 ; ARM78-LABEL: scalar_i32_x_is_const2_eq:
964 ; ARM78: @ %bb.0:
965 ; ARM78-NEXT: movw r1, #43605
966 ; ARM78-NEXT: mov r2, #1
967 ; ARM78-NEXT: movt r1, #43605
968 ; ARM78-NEXT: and r0, r1, r2, lsl r0
969 ; ARM78-NEXT: clz r0, r0
970 ; ARM78-NEXT: lsr r0, r0, #5
971 ; ARM78-NEXT: bx lr
972 ;
973 ; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
974 ; THUMB6: @ %bb.0:
975 ; THUMB6-NEXT: movs r1, #1
976 ; THUMB6-NEXT: lsls r1, r0
977 ; THUMB6-NEXT: ldr r2, .LCPI19_0
978 ; THUMB6-NEXT: ands r2, r1
979 ; THUMB6-NEXT: rsbs r0, r2, #0
980 ; THUMB6-NEXT: adcs r0, r2
981 ; THUMB6-NEXT: bx lr
982 ; THUMB6-NEXT: .p2align 2
983 ; THUMB6-NEXT: @ %bb.1:
984 ; THUMB6-NEXT: .LCPI19_0:
985 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
986 ;
987 ; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
988 ; THUMB78: @ %bb.0:
989 ; THUMB78-NEXT: movs r1, #1
990 ; THUMB78-NEXT: lsl.w r0, r1, r0
991 ; THUMB78-NEXT: movw r1, #43605
992 ; THUMB78-NEXT: movt r1, #43605
993 ; THUMB78-NEXT: ands r0, r1
994 ; THUMB78-NEXT: clz r0, r0
995 ; THUMB78-NEXT: lsrs r0, r0, #5
996 ; THUMB78-NEXT: bx lr
997 %t0 = shl i32 1, %y
998 %t1 = and i32 %t0, 2857740885
999 %res = icmp eq i32 %t1, 0
1000 ret i1 %res
1001 }
1003 ;------------------------------------------------------------------------------;
1004 ; A few negative tests
1005 ;------------------------------------------------------------------------------;
1007 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
1008 ; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1009 ; ARM6: @ %bb.0:
1010 ; ARM6-NEXT: uxtb r1, r1
1011 ; ARM6-NEXT: mov r2, #24
1012 ; ARM6-NEXT: and r0, r0, r2, lsl r1
1013 ; ARM6-NEXT: sxtb r1, r0
1014 ; ARM6-NEXT: mov r0, #0
1015 ; ARM6-NEXT: cmp r1, #0
1016 ; ARM6-NEXT: movmi r0, #1
1017 ; ARM6-NEXT: bx lr
1018 ;
1019 ; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1020 ; ARM78: @ %bb.0:
1021 ; ARM78-NEXT: uxtb r1, r1
1022 ; ARM78-NEXT: mov r2, #24
1023 ; ARM78-NEXT: and r0, r0, r2, lsl r1
1024 ; ARM78-NEXT: sxtb r1, r0
1025 ; ARM78-NEXT: mov r0, #0
1026 ; ARM78-NEXT: cmp r1, #0
1027 ; ARM78-NEXT: movwmi r0, #1
1028 ; ARM78-NEXT: bx lr
1029 ;
1030 ; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1031 ; THUMB6: @ %bb.0:
1032 ; THUMB6-NEXT: uxtb r1, r1
1033 ; THUMB6-NEXT: movs r2, #24
1034 ; THUMB6-NEXT: lsls r2, r1
1035 ; THUMB6-NEXT: ands r2, r0
1036 ; THUMB6-NEXT: sxtb r0, r2
1037 ; THUMB6-NEXT: cmp r0, #0
1038 ; THUMB6-NEXT: bmi .LBB20_2
1039 ; THUMB6-NEXT: @ %bb.1:
1040 ; THUMB6-NEXT: movs r0, #0
1041 ; THUMB6-NEXT: bx lr
1042 ; THUMB6-NEXT: .LBB20_2:
1043 ; THUMB6-NEXT: movs r0, #1
1044 ; THUMB6-NEXT: bx lr
1045 ;
1046 ; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1047 ; THUMB78: @ %bb.0:
1048 ; THUMB78-NEXT: uxtb r1, r1
1049 ; THUMB78-NEXT: movs r2, #24
1050 ; THUMB78-NEXT: lsl.w r1, r2, r1
1051 ; THUMB78-NEXT: ands r0, r1
1052 ; THUMB78-NEXT: sxtb r1, r0
1053 ; THUMB78-NEXT: movs r0, #0
1054 ; THUMB78-NEXT: cmp r1, #0
1055 ; THUMB78-NEXT: it mi
1056 ; THUMB78-NEXT: movmi r0, #1
1057 ; THUMB78-NEXT: bx lr
1058 %t0 = shl i8 24, %y
1059 %t1 = and i8 %t0, %x
1060 %res = icmp slt i8 %t1, 0
1061 ret i1 %res
1062 }
1064 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
1065 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
1066 ; ARM: @ %bb.0:
1067 ; ARM-NEXT: mov r0, #0
1068 ; ARM-NEXT: bx lr
1069 ;
1070 ; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
1071 ; THUMB6: @ %bb.0:
1072 ; THUMB6-NEXT: uxtb r1, r1
1073 ; THUMB6-NEXT: movs r2, #127
1074 ; THUMB6-NEXT: mvns r2, r2
1075 ; THUMB6-NEXT: lsls r2, r1
1076 ; THUMB6-NEXT: ands r2, r0
1077 ; THUMB6-NEXT: uxtb r0, r2
1078 ; THUMB6-NEXT: subs r1, r0, #1
1079 ; THUMB6-NEXT: rsbs r0, r1, #0
1080 ; THUMB6-NEXT: adcs r0, r1
1081 ; THUMB6-NEXT: bx lr
1082 ;
1083 ; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
1084 ; THUMB78: @ %bb.0:
1085 ; THUMB78-NEXT: movs r0, #0
1086 ; THUMB78-NEXT: bx lr
1087 %t0 = shl i8 128, %y
1088 %t1 = and i8 %t0, %x
1089 %res = icmp eq i8 %t1, 1 ; should be comparing with 0
1090 ret i1 %res
1091 }