| blob | 0060b4458081bc9e6af9c57cd89bfe889ae20e36 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefixes=CHECK-T1,CHECK-T16
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
6 ; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
7 ; RUN: llc < %s -mtriple=armv5te-none-eabi -mattr=+dsp | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
8 ; RUN: llc < %s -mtriple=armv5te-none-eabi -mattr=+dsp,thumb-mode | FileCheck %s --check-prefixes=CHECK-T1,CHECK-T15TE
9 ; RUN: llc < %s -mtriple=armv6-none-eabi -mattr=+dsp,thumb-mode | FileCheck %s --check-prefixes=CHECK-T1,CHECK-T16
10 ; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
12 declare i4 @llvm.sadd.sat.i4(i4, i4)
13 declare i8 @llvm.sadd.sat.i8(i8, i8)
14 declare i16 @llvm.sadd.sat.i16(i16, i16)
15 declare i32 @llvm.sadd.sat.i32(i32, i32)
16 declare i64 @llvm.sadd.sat.i64(i64, i64)
18 define i32 @func(i32 %x, i32 %y) nounwind {
19 ; CHECK-T1-LABEL: func:
20 ; CHECK-T1: @ %bb.0:
21 ; CHECK-T1-NEXT: adds r0, r0, r1
22 ; CHECK-T1-NEXT: bvc .LBB0_2
23 ; CHECK-T1-NEXT: @ %bb.1:
24 ; CHECK-T1-NEXT: asrs r1, r0, #31
25 ; CHECK-T1-NEXT: movs r0, #1
26 ; CHECK-T1-NEXT: lsls r0, r0, #31
27 ; CHECK-T1-NEXT: eors r0, r1
28 ; CHECK-T1-NEXT: .LBB0_2:
29 ; CHECK-T1-NEXT: bx lr
30 ;
31 ; CHECK-T2NODSP-LABEL: func:
32 ; CHECK-T2NODSP: @ %bb.0:
33 ; CHECK-T2NODSP-NEXT: adds r0, r0, r1
34 ; CHECK-T2NODSP-NEXT: mov.w r1, #-2147483648
35 ; CHECK-T2NODSP-NEXT: it vs
36 ; CHECK-T2NODSP-NEXT: eorvs.w r0, r1, r0, asr #31
37 ; CHECK-T2NODSP-NEXT: bx lr
38 ;
39 ; CHECK-T2DSP-LABEL: func:
40 ; CHECK-T2DSP: @ %bb.0:
41 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
42 ; CHECK-T2DSP-NEXT: bx lr
43 ;
44 ; CHECK-ARMNODPS-LABEL: func:
45 ; CHECK-ARMNODPS: @ %bb.0:
46 ; CHECK-ARMNODPS-NEXT: adds r0, r0, r1
47 ; CHECK-ARMNODPS-NEXT: mov r1, #-2147483648
48 ; CHECK-ARMNODPS-NEXT: eorvs r0, r1, r0, asr #31
49 ; CHECK-ARMNODPS-NEXT: bx lr
50 ;
51 ; CHECK-ARMBASEDSP-LABEL: func:
52 ; CHECK-ARMBASEDSP: @ %bb.0:
53 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
54 ; CHECK-ARMBASEDSP-NEXT: bx lr
55 ;
56 ; CHECK-ARMDSP-LABEL: func:
57 ; CHECK-ARMDSP: @ %bb.0:
58 ; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
59 ; CHECK-ARMDSP-NEXT: bx lr
60 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
61 ret i32 %tmp
62 }
64 define i64 @func2(i64 %x, i64 %y) nounwind {
65 ; CHECK-T16-LABEL: func2:
66 ; CHECK-T16: @ %bb.0:
67 ; CHECK-T16-NEXT: .save {r4, lr}
68 ; CHECK-T16-NEXT: push {r4, lr}
69 ; CHECK-T16-NEXT: mov r4, r1
70 ; CHECK-T16-NEXT: eors r1, r3
71 ; CHECK-T16-NEXT: adds r2, r0, r2
72 ; CHECK-T16-NEXT: adcs r3, r4
73 ; CHECK-T16-NEXT: eors r4, r3
74 ; CHECK-T16-NEXT: bics r4, r1
75 ; CHECK-T16-NEXT: asrs r1, r3, #31
76 ; CHECK-T16-NEXT: cmp r4, #0
77 ; CHECK-T16-NEXT: mov r0, r1
78 ; CHECK-T16-NEXT: bmi .LBB1_2
79 ; CHECK-T16-NEXT: @ %bb.1:
80 ; CHECK-T16-NEXT: mov r0, r2
81 ; CHECK-T16-NEXT: .LBB1_2:
82 ; CHECK-T16-NEXT: cmp r4, #0
83 ; CHECK-T16-NEXT: bmi .LBB1_4
84 ; CHECK-T16-NEXT: @ %bb.3:
85 ; CHECK-T16-NEXT: mov r1, r3
86 ; CHECK-T16-NEXT: pop {r4, pc}
87 ; CHECK-T16-NEXT: .LBB1_4:
88 ; CHECK-T16-NEXT: movs r2, #1
89 ; CHECK-T16-NEXT: lsls r2, r2, #31
90 ; CHECK-T16-NEXT: eors r1, r2
91 ; CHECK-T16-NEXT: pop {r4, pc}
92 ;
93 ; CHECK-T2-LABEL: func2:
94 ; CHECK-T2: @ %bb.0:
95 ; CHECK-T2-NEXT: adds r0, r0, r2
96 ; CHECK-T2-NEXT: eor.w r12, r1, r3
97 ; CHECK-T2-NEXT: adc.w r2, r1, r3
98 ; CHECK-T2-NEXT: eors r1, r2
99 ; CHECK-T2-NEXT: bics.w r1, r1, r12
100 ; CHECK-T2-NEXT: it mi
101 ; CHECK-T2-NEXT: asrmi r0, r2, #31
102 ; CHECK-T2-NEXT: mov.w r1, #-2147483648
103 ; CHECK-T2-NEXT: it mi
104 ; CHECK-T2-NEXT: eormi.w r2, r1, r2, asr #31
105 ; CHECK-T2-NEXT: mov r1, r2
106 ; CHECK-T2-NEXT: bx lr
107 ;
108 ; CHECK-ARM-LABEL: func2:
109 ; CHECK-ARM: @ %bb.0:
110 ; CHECK-ARM-NEXT: adds r0, r0, r2
111 ; CHECK-ARM-NEXT: eor r12, r1, r3
112 ; CHECK-ARM-NEXT: adc r2, r1, r3
113 ; CHECK-ARM-NEXT: eor r1, r1, r2
114 ; CHECK-ARM-NEXT: bics r1, r1, r12
115 ; CHECK-ARM-NEXT: asrmi r0, r2, #31
116 ; CHECK-ARM-NEXT: mov r1, #-2147483648
117 ; CHECK-ARM-NEXT: eormi r2, r1, r2, asr #31
118 ; CHECK-ARM-NEXT: mov r1, r2
119 ; CHECK-ARM-NEXT: bx lr
120 ;
121 ; CHECK-T15TE-LABEL: func2:
122 ; CHECK-T15TE: @ %bb.0:
123 ; CHECK-T15TE-NEXT: .save {r4, lr}
124 ; CHECK-T15TE-NEXT: push {r4, lr}
125 ; CHECK-T15TE-NEXT: movs r4, r1
126 ; CHECK-T15TE-NEXT: eors r1, r3
127 ; CHECK-T15TE-NEXT: adds r2, r0, r2
128 ; CHECK-T15TE-NEXT: adcs r3, r4
129 ; CHECK-T15TE-NEXT: eors r4, r3
130 ; CHECK-T15TE-NEXT: bics r4, r1
131 ; CHECK-T15TE-NEXT: asrs r1, r3, #31
132 ; CHECK-T15TE-NEXT: cmp r4, #0
133 ; CHECK-T15TE-NEXT: mov r12, r1
134 ; CHECK-T15TE-NEXT: mov r0, r12
135 ; CHECK-T15TE-NEXT: bmi .LBB1_2
136 ; CHECK-T15TE-NEXT: @ %bb.1:
137 ; CHECK-T15TE-NEXT: movs r0, r2
138 ; CHECK-T15TE-NEXT: .LBB1_2:
139 ; CHECK-T15TE-NEXT: cmp r4, #0
140 ; CHECK-T15TE-NEXT: bmi .LBB1_4
141 ; CHECK-T15TE-NEXT: @ %bb.3:
142 ; CHECK-T15TE-NEXT: movs r1, r3
143 ; CHECK-T15TE-NEXT: pop {r4, pc}
144 ; CHECK-T15TE-NEXT: .LBB1_4:
145 ; CHECK-T15TE-NEXT: movs r2, #1
146 ; CHECK-T15TE-NEXT: lsls r2, r2, #31
147 ; CHECK-T15TE-NEXT: eors r1, r2
148 ; CHECK-T15TE-NEXT: pop {r4, pc}
149 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
150 ret i64 %tmp
151 }
153 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
154 ; CHECK-T1-LABEL: func16:
155 ; CHECK-T1: @ %bb.0:
156 ; CHECK-T1-NEXT: adds r0, r0, r1
157 ; CHECK-T1-NEXT: ldr r1, .LCPI2_0
158 ; CHECK-T1-NEXT: cmp r0, r1
159 ; CHECK-T1-NEXT: blt .LBB2_2
160 ; CHECK-T1-NEXT: @ %bb.1:
161 ; CHECK-T1-NEXT: {{movs|mov}} r0, r1
162 ; CHECK-T1-NEXT: .LBB2_2:
163 ; CHECK-T1-NEXT: ldr r1, .LCPI2_1
164 ; CHECK-T1-NEXT: cmp r0, r1
165 ; CHECK-T1-NEXT: bgt .LBB2_4
166 ; CHECK-T1-NEXT: @ %bb.3:
167 ; CHECK-T1-NEXT: {{movs|mov}} r0, r1
168 ; CHECK-T1-NEXT: .LBB2_4:
169 ; CHECK-T1-NEXT: bx lr
170 ; CHECK-T1-NEXT: .p2align 2
171 ; CHECK-T1-NEXT: @ %bb.5:
172 ; CHECK-T1-NEXT: .LCPI2_0:
173 ; CHECK-T1-NEXT: .long 32767 @ 0x7fff
174 ; CHECK-T1-NEXT: .LCPI2_1:
175 ; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
176 ;
177 ; CHECK-T2NODSP-LABEL: func16:
178 ; CHECK-T2NODSP: @ %bb.0:
179 ; CHECK-T2NODSP-NEXT: add r0, r1
180 ; CHECK-T2NODSP-NEXT: ssat r0, #16, r0
181 ; CHECK-T2NODSP-NEXT: bx lr
182 ;
183 ; CHECK-T2DSP-LABEL: func16:
184 ; CHECK-T2DSP: @ %bb.0:
185 ; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1
186 ; CHECK-T2DSP-NEXT: sxth r0, r0
187 ; CHECK-T2DSP-NEXT: bx lr
188 ;
189 ; CHECK-ARMNODPS-LABEL: func16:
190 ; CHECK-ARMNODPS: @ %bb.0:
191 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
192 ; CHECK-ARMNODPS-NEXT: mov r1, #255
193 ; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
194 ; CHECK-ARMNODPS-NEXT: cmp r0, r1
195 ; CHECK-ARMNODPS-NEXT: movlt r1, r0
196 ; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
197 ; CHECK-ARMNODPS-NEXT: cmn r1, #32768
198 ; CHECK-ARMNODPS-NEXT: movgt r0, r1
199 ; CHECK-ARMNODPS-NEXT: bx lr
200 ; CHECK-ARMNODPS-NEXT: .p2align 2
201 ; CHECK-ARMNODPS-NEXT: @ %bb.1:
202 ; CHECK-ARMNODPS-NEXT: .LCPI2_0:
203 ; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000
204 ;
205 ; CHECK-ARMBASEDSP-LABEL: func16:
206 ; CHECK-ARMBASEDSP: @ %bb.0:
207 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #16
208 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #16
209 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
210 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #16
211 ; CHECK-ARMBASEDSP-NEXT: bx lr
212 ;
213 ; CHECK-ARMDSP-LABEL: func16:
214 ; CHECK-ARMDSP: @ %bb.0:
215 ; CHECK-ARMDSP-NEXT: qadd16 r0, r0, r1
216 ; CHECK-ARMDSP-NEXT: sxth r0, r0
217 ; CHECK-ARMDSP-NEXT: bx lr
218 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
219 ret i16 %tmp
220 }
222 define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
223 ; CHECK-T1-LABEL: func8:
224 ; CHECK-T1: @ %bb.0:
225 ; CHECK-T1-NEXT: adds r0, r0, r1
226 ; CHECK-T1-NEXT: movs r1, #127
227 ; CHECK-T1-NEXT: cmp r0, #127
228 ; CHECK-T1-NEXT: blt .LBB3_2
229 ; CHECK-T1-NEXT: @ %bb.1:
230 ; CHECK-T1-NEXT: {{movs|mov}} r0, r1
231 ; CHECK-T1-NEXT: .LBB3_2:
232 ; CHECK-T1-NEXT: mvns r1, r1
233 ; CHECK-T1-NEXT: cmp r0, r1
234 ; CHECK-T1-NEXT: bgt .LBB3_4
235 ; CHECK-T1-NEXT: @ %bb.3:
236 ; CHECK-T1-NEXT: {{movs|mov}} r0, r1
237 ; CHECK-T1-NEXT: .LBB3_4:
238 ; CHECK-T1-NEXT: bx lr
239 ;
240 ; CHECK-T2NODSP-LABEL: func8:
241 ; CHECK-T2NODSP: @ %bb.0:
242 ; CHECK-T2NODSP-NEXT: add r0, r1
243 ; CHECK-T2NODSP-NEXT: ssat r0, #8, r0
244 ; CHECK-T2NODSP-NEXT: bx lr
245 ;
246 ; CHECK-T2DSP-LABEL: func8:
247 ; CHECK-T2DSP: @ %bb.0:
248 ; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1
249 ; CHECK-T2DSP-NEXT: sxtb r0, r0
250 ; CHECK-T2DSP-NEXT: bx lr
251 ;
252 ; CHECK-ARMNODPS-LABEL: func8:
253 ; CHECK-ARMNODPS: @ %bb.0:
254 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
255 ; CHECK-ARMNODPS-NEXT: cmp r0, #127
256 ; CHECK-ARMNODPS-NEXT: movge r0, #127
257 ; CHECK-ARMNODPS-NEXT: cmn r0, #128
258 ; CHECK-ARMNODPS-NEXT: mvnle r0, #127
259 ; CHECK-ARMNODPS-NEXT: bx lr
260 ;
261 ; CHECK-ARMBASEDSP-LABEL: func8:
262 ; CHECK-ARMBASEDSP: @ %bb.0:
263 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #24
264 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #24
265 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
266 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #24
267 ; CHECK-ARMBASEDSP-NEXT: bx lr
268 ;
269 ; CHECK-ARMDSP-LABEL: func8:
270 ; CHECK-ARMDSP: @ %bb.0:
271 ; CHECK-ARMDSP-NEXT: qadd8 r0, r0, r1
272 ; CHECK-ARMDSP-NEXT: sxtb r0, r0
273 ; CHECK-ARMDSP-NEXT: bx lr
274 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
275 ret i8 %tmp
276 }
278 define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
279 ; CHECK-T1-LABEL: func3:
280 ; CHECK-T1: @ %bb.0:
281 ; CHECK-T1-NEXT: adds r0, r0, r1
282 ; CHECK-T1-NEXT: movs r1, #7
283 ; CHECK-T1-NEXT: cmp r0, #7
284 ; CHECK-T1-NEXT: blt .LBB4_2
285 ; CHECK-T1-NEXT: @ %bb.1:
286 ; CHECK-T1-NEXT: {{movs|mov}} r0, r1
287 ; CHECK-T1-NEXT: .LBB4_2:
288 ; CHECK-T1-NEXT: mvns r1, r1
289 ; CHECK-T1-NEXT: cmp r0, r1
290 ; CHECK-T1-NEXT: bgt .LBB4_4
291 ; CHECK-T1-NEXT: @ %bb.3:
292 ; CHECK-T1-NEXT: {{movs|mov}} r0, r1
293 ; CHECK-T1-NEXT: .LBB4_4:
294 ; CHECK-T1-NEXT: bx lr
295 ;
296 ; CHECK-T2NODSP-LABEL: func3:
297 ; CHECK-T2NODSP: @ %bb.0:
298 ; CHECK-T2NODSP-NEXT: add r0, r1
299 ; CHECK-T2NODSP-NEXT: ssat r0, #4, r0
300 ; CHECK-T2NODSP-NEXT: bx lr
301 ;
302 ; CHECK-T2DSP-LABEL: func3:
303 ; CHECK-T2DSP: @ %bb.0:
304 ; CHECK-T2DSP-NEXT: lsls r1, r1, #28
305 ; CHECK-T2DSP-NEXT: lsls r0, r0, #28
306 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
307 ; CHECK-T2DSP-NEXT: asrs r0, r0, #28
308 ; CHECK-T2DSP-NEXT: bx lr
309 ;
310 ; CHECK-ARMNODPS-LABEL: func3:
311 ; CHECK-ARMNODPS: @ %bb.0:
312 ; CHECK-ARMNODPS-NEXT: add r0, r0, r1
313 ; CHECK-ARMNODPS-NEXT: cmp r0, #7
314 ; CHECK-ARMNODPS-NEXT: movge r0, #7
315 ; CHECK-ARMNODPS-NEXT: cmn r0, #8
316 ; CHECK-ARMNODPS-NEXT: mvnle r0, #7
317 ; CHECK-ARMNODPS-NEXT: bx lr
318 ;
319 ; CHECK-ARMBASEDSP-LABEL: func3:
320 ; CHECK-ARMBASEDSP: @ %bb.0:
321 ; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #28
322 ; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #28
323 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
324 ; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #28
325 ; CHECK-ARMBASEDSP-NEXT: bx lr
326 ;
327 ; CHECK-ARMDSP-LABEL: func3:
328 ; CHECK-ARMDSP: @ %bb.0:
329 ; CHECK-ARMDSP-NEXT: lsl r0, r0, #28
330 ; CHECK-ARMDSP-NEXT: lsl r1, r1, #28
331 ; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
332 ; CHECK-ARMDSP-NEXT: asr r0, r0, #28
333 ; CHECK-ARMDSP-NEXT: bx lr
334 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y)
335 ret i4 %tmp
336 }