| blob | 543ddcd3efac963790ec05034400db69ec2c364a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv7a-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK7A
3 ; RUN: llc -mtriple=thumbv6m-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK6M
4 ; RUN: llc -mtriple=thumbv7m-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK7M
5 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK81M
7 define i32 @xori64i32(i64 %a) {
8 ; CHECK7A-LABEL: xori64i32:
9 ; CHECK7A: @ %bb.0:
10 ; CHECK7A-NEXT: mvn r0, #-2147483648
11 ; CHECK7A-NEXT: eor r0, r0, r1, asr #31
12 ; CHECK7A-NEXT: bx lr
13 ;
14 ; CHECK6M-LABEL: xori64i32:
15 ; CHECK6M: @ %bb.0:
16 ; CHECK6M-NEXT: asrs r1, r1, #31
17 ; CHECK6M-NEXT: ldr r0, .LCPI0_0
18 ; CHECK6M-NEXT: eors r0, r1
19 ; CHECK6M-NEXT: bx lr
20 ; CHECK6M-NEXT: .p2align 2
21 ; CHECK6M-NEXT: @ %bb.1:
22 ; CHECK6M-NEXT: .LCPI0_0:
23 ; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
24 ;
25 ; CHECK7M-LABEL: xori64i32:
26 ; CHECK7M: @ %bb.0:
27 ; CHECK7M-NEXT: mvn r0, #-2147483648
28 ; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
29 ; CHECK7M-NEXT: bx lr
30 ;
31 ; CHECK81M-LABEL: xori64i32:
32 ; CHECK81M: @ %bb.0:
33 ; CHECK81M-NEXT: mvn r0, #-2147483648
34 ; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
35 ; CHECK81M-NEXT: bx lr
36 %shr4 = ashr i64 %a, 63
37 %conv5 = trunc i64 %shr4 to i32
38 %xor = xor i32 %conv5, 2147483647
39 ret i32 %xor
40 }
42 define i64 @selecti64i64(i64 %a) {
43 ; CHECK7A-LABEL: selecti64i64:
44 ; CHECK7A: @ %bb.0:
45 ; CHECK7A-NEXT: mvn r0, #-2147483648
46 ; CHECK7A-NEXT: eor r0, r0, r1, asr #31
47 ; CHECK7A-NEXT: asr r1, r1, #31
48 ; CHECK7A-NEXT: bx lr
49 ;
50 ; CHECK6M-LABEL: selecti64i64:
51 ; CHECK6M: @ %bb.0:
52 ; CHECK6M-NEXT: asrs r1, r1, #31
53 ; CHECK6M-NEXT: ldr r0, .LCPI1_0
54 ; CHECK6M-NEXT: eors r0, r1
55 ; CHECK6M-NEXT: bx lr
56 ; CHECK6M-NEXT: .p2align 2
57 ; CHECK6M-NEXT: @ %bb.1:
58 ; CHECK6M-NEXT: .LCPI1_0:
59 ; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
60 ;
61 ; CHECK7M-LABEL: selecti64i64:
62 ; CHECK7M: @ %bb.0:
63 ; CHECK7M-NEXT: mvn r0, #-2147483648
64 ; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
65 ; CHECK7M-NEXT: asrs r1, r1, #31
66 ; CHECK7M-NEXT: bx lr
67 ;
68 ; CHECK81M-LABEL: selecti64i64:
69 ; CHECK81M: @ %bb.0:
70 ; CHECK81M-NEXT: mvn r0, #-2147483648
71 ; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
72 ; CHECK81M-NEXT: asrs r1, r1, #31
73 ; CHECK81M-NEXT: bx lr
74 %c = icmp sgt i64 %a, -1
75 %s = select i1 %c, i64 2147483647, i64 -2147483648
76 ret i64 %s
77 }
79 define i32 @selecti64i32(i64 %a) {
80 ; CHECK7A-LABEL: selecti64i32:
81 ; CHECK7A: @ %bb.0:
82 ; CHECK7A-NEXT: mvn r0, #-2147483648
83 ; CHECK7A-NEXT: eor r0, r0, r1, asr #31
84 ; CHECK7A-NEXT: bx lr
85 ;
86 ; CHECK6M-LABEL: selecti64i32:
87 ; CHECK6M: @ %bb.0:
88 ; CHECK6M-NEXT: ldr r0, .LCPI2_0
89 ; CHECK6M-NEXT: cmp r1, #0
90 ; CHECK6M-NEXT: bge .LBB2_2
91 ; CHECK6M-NEXT: @ %bb.1:
92 ; CHECK6M-NEXT: adds r0, r0, #1
93 ; CHECK6M-NEXT: .LBB2_2:
94 ; CHECK6M-NEXT: bx lr
95 ; CHECK6M-NEXT: .p2align 2
96 ; CHECK6M-NEXT: @ %bb.3:
97 ; CHECK6M-NEXT: .LCPI2_0:
98 ; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
99 ;
100 ; CHECK7M-LABEL: selecti64i32:
101 ; CHECK7M: @ %bb.0:
102 ; CHECK7M-NEXT: mvn r0, #-2147483648
103 ; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31
104 ; CHECK7M-NEXT: bx lr
105 ;
106 ; CHECK81M-LABEL: selecti64i32:
107 ; CHECK81M: @ %bb.0:
108 ; CHECK81M-NEXT: mvn r0, #-2147483648
109 ; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31
110 ; CHECK81M-NEXT: bx lr
111 %c = icmp sgt i64 %a, -1
112 %s = select i1 %c, i32 2147483647, i32 -2147483648
113 ret i32 %s
114 }
116 define i64 @selecti32i64(i32 %a) {
117 ; CHECK7A-LABEL: selecti32i64:
118 ; CHECK7A: @ %bb.0:
119 ; CHECK7A-NEXT: mvn r1, #-2147483648
120 ; CHECK7A-NEXT: eor r2, r1, r0, asr #31
121 ; CHECK7A-NEXT: asr r1, r0, #31
122 ; CHECK7A-NEXT: mov r0, r2
123 ; CHECK7A-NEXT: bx lr
124 ;
125 ; CHECK6M-LABEL: selecti32i64:
126 ; CHECK6M: @ %bb.0:
127 ; CHECK6M-NEXT: asrs r1, r0, #31
128 ; CHECK6M-NEXT: ldr r0, .LCPI3_0
129 ; CHECK6M-NEXT: eors r0, r1
130 ; CHECK6M-NEXT: bx lr
131 ; CHECK6M-NEXT: .p2align 2
132 ; CHECK6M-NEXT: @ %bb.1:
133 ; CHECK6M-NEXT: .LCPI3_0:
134 ; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff
135 ;
136 ; CHECK7M-LABEL: selecti32i64:
137 ; CHECK7M: @ %bb.0:
138 ; CHECK7M-NEXT: mvn r1, #-2147483648
139 ; CHECK7M-NEXT: eor.w r2, r1, r0, asr #31
140 ; CHECK7M-NEXT: asrs r1, r0, #31
141 ; CHECK7M-NEXT: mov r0, r2
142 ; CHECK7M-NEXT: bx lr
143 ;
144 ; CHECK81M-LABEL: selecti32i64:
145 ; CHECK81M: @ %bb.0:
146 ; CHECK81M-NEXT: mvn r1, #-2147483648
147 ; CHECK81M-NEXT: eor.w r2, r1, r0, asr #31
148 ; CHECK81M-NEXT: asrs r1, r0, #31
149 ; CHECK81M-NEXT: mov r0, r2
150 ; CHECK81M-NEXT: bx lr
151 %c = icmp sgt i32 %a, -1
152 %s = select i1 %c, i64 2147483647, i64 -2147483648
153 ret i64 %s
154 }
158 define i8 @xori32i8(i32 %a) {
159 ; CHECK7A-LABEL: xori32i8:
160 ; CHECK7A: @ %bb.0:
161 ; CHECK7A-NEXT: mov r1, #84
162 ; CHECK7A-NEXT: eor r0, r1, r0, asr #31
163 ; CHECK7A-NEXT: bx lr
164 ;
165 ; CHECK6M-LABEL: xori32i8:
166 ; CHECK6M: @ %bb.0:
167 ; CHECK6M-NEXT: asrs r1, r0, #31
168 ; CHECK6M-NEXT: movs r0, #84
169 ; CHECK6M-NEXT: eors r0, r1
170 ; CHECK6M-NEXT: bx lr
171 ;
172 ; CHECK7M-LABEL: xori32i8:
173 ; CHECK7M: @ %bb.0:
174 ; CHECK7M-NEXT: movs r1, #84
175 ; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
176 ; CHECK7M-NEXT: bx lr
177 ;
178 ; CHECK81M-LABEL: xori32i8:
179 ; CHECK81M: @ %bb.0:
180 ; CHECK81M-NEXT: movs r1, #84
181 ; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
182 ; CHECK81M-NEXT: bx lr
183 %shr4 = ashr i32 %a, 31
184 %conv5 = trunc i32 %shr4 to i8
185 %xor = xor i8 %conv5, 84
186 ret i8 %xor
187 }
189 define i32 @selecti32i32(i32 %a) {
190 ; CHECK7A-LABEL: selecti32i32:
191 ; CHECK7A: @ %bb.0:
192 ; CHECK7A-NEXT: mov r1, #84
193 ; CHECK7A-NEXT: eor r0, r1, r0, asr #31
194 ; CHECK7A-NEXT: bx lr
195 ;
196 ; CHECK6M-LABEL: selecti32i32:
197 ; CHECK6M: @ %bb.0:
198 ; CHECK6M-NEXT: asrs r1, r0, #31
199 ; CHECK6M-NEXT: movs r0, #84
200 ; CHECK6M-NEXT: eors r0, r1
201 ; CHECK6M-NEXT: bx lr
202 ;
203 ; CHECK7M-LABEL: selecti32i32:
204 ; CHECK7M: @ %bb.0:
205 ; CHECK7M-NEXT: movs r1, #84
206 ; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
207 ; CHECK7M-NEXT: bx lr
208 ;
209 ; CHECK81M-LABEL: selecti32i32:
210 ; CHECK81M: @ %bb.0:
211 ; CHECK81M-NEXT: movs r1, #84
212 ; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
213 ; CHECK81M-NEXT: bx lr
214 %c = icmp sgt i32 %a, -1
215 %s = select i1 %c, i32 84, i32 -85
216 ret i32 %s
217 }
219 define i8 @selecti32i8(i32 %a) {
220 ; CHECK7A-LABEL: selecti32i8:
221 ; CHECK7A: @ %bb.0:
222 ; CHECK7A-NEXT: mov r1, #84
223 ; CHECK7A-NEXT: eor r0, r1, r0, asr #31
224 ; CHECK7A-NEXT: bx lr
225 ;
226 ; CHECK6M-LABEL: selecti32i8:
227 ; CHECK6M: @ %bb.0:
228 ; CHECK6M-NEXT: asrs r1, r0, #31
229 ; CHECK6M-NEXT: movs r0, #84
230 ; CHECK6M-NEXT: eors r0, r1
231 ; CHECK6M-NEXT: bx lr
232 ;
233 ; CHECK7M-LABEL: selecti32i8:
234 ; CHECK7M: @ %bb.0:
235 ; CHECK7M-NEXT: movs r1, #84
236 ; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31
237 ; CHECK7M-NEXT: bx lr
238 ;
239 ; CHECK81M-LABEL: selecti32i8:
240 ; CHECK81M: @ %bb.0:
241 ; CHECK81M-NEXT: movs r1, #84
242 ; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31
243 ; CHECK81M-NEXT: bx lr
244 %c = icmp sgt i32 %a, -1
245 %s = select i1 %c, i8 84, i8 -85
246 ret i8 %s
247 }
249 define i32 @selecti8i32(i8 %a) {
250 ; CHECK7A-LABEL: selecti8i32:
251 ; CHECK7A: @ %bb.0:
252 ; CHECK7A-NEXT: sxtb r0, r0
253 ; CHECK7A-NEXT: mov r1, #84
254 ; CHECK7A-NEXT: eor r0, r1, r0, asr #7
255 ; CHECK7A-NEXT: bx lr
256 ;
257 ; CHECK6M-LABEL: selecti8i32:
258 ; CHECK6M: @ %bb.0:
259 ; CHECK6M-NEXT: sxtb r0, r0
260 ; CHECK6M-NEXT: asrs r1, r0, #7
261 ; CHECK6M-NEXT: movs r0, #84
262 ; CHECK6M-NEXT: eors r0, r1
263 ; CHECK6M-NEXT: bx lr
264 ;
265 ; CHECK7M-LABEL: selecti8i32:
266 ; CHECK7M: @ %bb.0:
267 ; CHECK7M-NEXT: sxtb r0, r0
268 ; CHECK7M-NEXT: movs r1, #84
269 ; CHECK7M-NEXT: eor.w r0, r1, r0, asr #7
270 ; CHECK7M-NEXT: bx lr
271 ;
272 ; CHECK81M-LABEL: selecti8i32:
273 ; CHECK81M: @ %bb.0:
274 ; CHECK81M-NEXT: sxtb r0, r0
275 ; CHECK81M-NEXT: movs r1, #84
276 ; CHECK81M-NEXT: eor.w r0, r1, r0, asr #7
277 ; CHECK81M-NEXT: bx lr
278 %c = icmp sgt i8 %a, -1
279 %s = select i1 %c, i32 84, i32 -85
280 ret i32 %s
281 }
283 define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
284 ; CHECK7A-LABEL: icmpasreq:
285 ; CHECK7A: @ %bb.0:
286 ; CHECK7A-NEXT: cmp r0, #0
287 ; CHECK7A-NEXT: movpl r1, r2
288 ; CHECK7A-NEXT: mov r0, r1
289 ; CHECK7A-NEXT: bx lr
290 ;
291 ; CHECK6M-LABEL: icmpasreq:
292 ; CHECK6M: @ %bb.0:
293 ; CHECK6M-NEXT: cmp r0, #0
294 ; CHECK6M-NEXT: bmi .LBB8_2
295 ; CHECK6M-NEXT: @ %bb.1:
296 ; CHECK6M-NEXT: mov r1, r2
297 ; CHECK6M-NEXT: .LBB8_2:
298 ; CHECK6M-NEXT: mov r0, r1
299 ; CHECK6M-NEXT: bx lr
300 ;
301 ; CHECK7M-LABEL: icmpasreq:
302 ; CHECK7M: @ %bb.0:
303 ; CHECK7M-NEXT: cmp r0, #0
304 ; CHECK7M-NEXT: it pl
305 ; CHECK7M-NEXT: movpl r1, r2
306 ; CHECK7M-NEXT: mov r0, r1
307 ; CHECK7M-NEXT: bx lr
308 ;
309 ; CHECK81M-LABEL: icmpasreq:
310 ; CHECK81M: @ %bb.0:
311 ; CHECK81M-NEXT: cmp r0, #0
312 ; CHECK81M-NEXT: csel r0, r1, r2, mi
313 ; CHECK81M-NEXT: bx lr
314 %sh = ashr i32 %input, 31
315 %c = icmp eq i32 %sh, -1
316 %s = select i1 %c, i32 %a, i32 %b
317 ret i32 %s
318 }
320 define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
321 ; CHECK7A-LABEL: icmpasrne:
322 ; CHECK7A: @ %bb.0:
323 ; CHECK7A-NEXT: cmn r0, #1
324 ; CHECK7A-NEXT: movle r1, r2
325 ; CHECK7A-NEXT: mov r0, r1
326 ; CHECK7A-NEXT: bx lr
327 ;
328 ; CHECK6M-LABEL: icmpasrne:
329 ; CHECK6M: @ %bb.0:
330 ; CHECK6M-NEXT: cmp r0, #0
331 ; CHECK6M-NEXT: bge .LBB9_2
332 ; CHECK6M-NEXT: @ %bb.1:
333 ; CHECK6M-NEXT: mov r1, r2
334 ; CHECK6M-NEXT: .LBB9_2:
335 ; CHECK6M-NEXT: mov r0, r1
336 ; CHECK6M-NEXT: bx lr
337 ;
338 ; CHECK7M-LABEL: icmpasrne:
339 ; CHECK7M: @ %bb.0:
340 ; CHECK7M-NEXT: cmp.w r0, #-1
341 ; CHECK7M-NEXT: it le
342 ; CHECK7M-NEXT: movle r1, r2
343 ; CHECK7M-NEXT: mov r0, r1
344 ; CHECK7M-NEXT: bx lr
345 ;
346 ; CHECK81M-LABEL: icmpasrne:
347 ; CHECK81M: @ %bb.0:
348 ; CHECK81M-NEXT: cmp.w r0, #-1
349 ; CHECK81M-NEXT: csel r0, r1, r2, gt
350 ; CHECK81M-NEXT: bx lr
351 %sh = ashr i32 %input, 31
352 %c = icmp ne i32 %sh, -1
353 %s = select i1 %c, i32 %a, i32 %b
354 ret i32 %s
355 }
357 define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
358 ; CHECK7A-LABEL: oneusecmp:
359 ; CHECK7A: @ %bb.0:
360 ; CHECK7A-NEXT: cmp r0, #0
361 ; CHECK7A-NEXT: movmi r1, r2
362 ; CHECK7A-NEXT: mov r2, #127
363 ; CHECK7A-NEXT: eor r0, r2, r0, asr #31
364 ; CHECK7A-NEXT: add r0, r0, r1
365 ; CHECK7A-NEXT: bx lr
366 ;
367 ; CHECK6M-LABEL: oneusecmp:
368 ; CHECK6M: @ %bb.0:
369 ; CHECK6M-NEXT: cmp r0, #0
370 ; CHECK6M-NEXT: bmi .LBB10_2
371 ; CHECK6M-NEXT: @ %bb.1:
372 ; CHECK6M-NEXT: mov r2, r1
373 ; CHECK6M-NEXT: .LBB10_2:
374 ; CHECK6M-NEXT: asrs r0, r0, #31
375 ; CHECK6M-NEXT: movs r1, #127
376 ; CHECK6M-NEXT: eors r1, r0
377 ; CHECK6M-NEXT: adds r0, r1, r2
378 ; CHECK6M-NEXT: bx lr
379 ;
380 ; CHECK7M-LABEL: oneusecmp:
381 ; CHECK7M: @ %bb.0:
382 ; CHECK7M-NEXT: cmp r0, #0
383 ; CHECK7M-NEXT: it mi
384 ; CHECK7M-NEXT: movmi r1, r2
385 ; CHECK7M-NEXT: movs r2, #127
386 ; CHECK7M-NEXT: eor.w r0, r2, r0, asr #31
387 ; CHECK7M-NEXT: add r0, r1
388 ; CHECK7M-NEXT: bx lr
389 ;
390 ; CHECK81M-LABEL: oneusecmp:
391 ; CHECK81M: @ %bb.0:
392 ; CHECK81M-NEXT: cmp r0, #0
393 ; CHECK81M-NEXT: csel r1, r2, r1, mi
394 ; CHECK81M-NEXT: movs r2, #127
395 ; CHECK81M-NEXT: eor.w r0, r2, r0, asr #31
396 ; CHECK81M-NEXT: add r0, r1
397 ; CHECK81M-NEXT: bx lr
398 %c = icmp sle i32 %a, -1
399 %s = select i1 %c, i32 -128, i32 127
400 %s2 = select i1 %c, i32 %d, i32 %b
401 %x = add i32 %s, %s2
402 ret i32 %x
403 }