1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s
4 # The and -> ands transform is sensitive to scheduling; make sure we don't
5 # transform cases which aren't legal.
8 target triple = "armv7-unknown-unknown"
9 define i32 @foo_transform(i32 %in) {
12 define i32 @foo_notransform(i32 %in) {
19 tracksRegLiveness: true
24 ; CHECK-LABEL: name: foo_transform
26 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
27 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 4, 14 /* CC::al */, $noreg, $noreg
28 ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr
29 ; CHECK: [[MOVCCi16_:%[0-9]+]]:gpr = MOVCCi16 [[MOVi]], 5, 0 /* CC::eq */, $cpsr
30 ; CHECK: $r0 = COPY killed [[MOVCCi16_]]
31 ; CHECK: $r1 = COPY killed [[ANDri]]
32 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
34 %2:gpr = MOVi 4, 14, $noreg, $noreg
35 %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
36 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
37 %3:gpr = MOVCCi16 %2, 5, 0, $cpsr
40 BX_RET 14, $noreg, implicit $r0, implicit $r1
43 tracksRegLiveness: true
49 %2:gpr = MOVi 4, 14, $noreg, $noreg
50 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
51 %3:gpr = MOVCCi16 %2, 5, 0, $cpsr
52 %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
55 BX_RET 14, $noreg, implicit $r0, implicit $r1