1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
4 declare <32 x i8> @llvm.loongarch.lasx.xvreplve0.b(<32 x i8>)
6 define <32 x i8> @lasx_xvreplve0_b(<32 x i8> %va) nounwind {
7 ; CHECK-LABEL: lasx_xvreplve0_b:
8 ; CHECK: # %bb.0: # %entry
9 ; CHECK-NEXT: xvreplve0.b $xr0, $xr0
12 %res = call <32 x i8> @llvm.loongarch.lasx.xvreplve0.b(<32 x i8> %va)
16 declare <16 x i16> @llvm.loongarch.lasx.xvreplve0.h(<16 x i16>)
18 define <16 x i16> @lasx_xvreplve0_h(<16 x i16> %va) nounwind {
19 ; CHECK-LABEL: lasx_xvreplve0_h:
20 ; CHECK: # %bb.0: # %entry
21 ; CHECK-NEXT: xvreplve0.h $xr0, $xr0
24 %res = call <16 x i16> @llvm.loongarch.lasx.xvreplve0.h(<16 x i16> %va)
28 declare <8 x i32> @llvm.loongarch.lasx.xvreplve0.w(<8 x i32>)
30 define <8 x i32> @lasx_xvreplve0_w(<8 x i32> %va) nounwind {
31 ; CHECK-LABEL: lasx_xvreplve0_w:
32 ; CHECK: # %bb.0: # %entry
33 ; CHECK-NEXT: xvreplve0.w $xr0, $xr0
36 %res = call <8 x i32> @llvm.loongarch.lasx.xvreplve0.w(<8 x i32> %va)
40 declare <4 x i64> @llvm.loongarch.lasx.xvreplve0.d(<4 x i64>)
42 define <4 x i64> @lasx_xvreplve0_d(<4 x i64> %va) nounwind {
43 ; CHECK-LABEL: lasx_xvreplve0_d:
44 ; CHECK: # %bb.0: # %entry
45 ; CHECK-NEXT: xvreplve0.d $xr0, $xr0
48 %res = call <4 x i64> @llvm.loongarch.lasx.xvreplve0.d(<4 x i64> %va)
52 declare <32 x i8> @llvm.loongarch.lasx.xvreplve0.q(<32 x i8>)
54 define <32 x i8> @lasx_xvreplve0_q(<32 x i8> %va) nounwind {
55 ; CHECK-LABEL: lasx_xvreplve0_q:
56 ; CHECK: # %bb.0: # %entry
57 ; CHECK-NEXT: xvreplve0.q $xr0, $xr0
60 %res = call <32 x i8> @llvm.loongarch.lasx.xvreplve0.q(<32 x i8> %va)