1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
5 define void @add_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
6 define void @add_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
7 define void @add_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
8 define void @add_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }
15 tracksRegLiveness: true
18 liveins: $a0, $a1, $a2
20 ; P5600-LABEL: name: add_v16i8
21 ; P5600: liveins: $a0, $a1, $a2
22 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
23 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
24 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
25 ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
26 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
27 ; P5600: [[ADD:%[0-9]+]]:fprb(<16 x s8>) = G_ADD [[LOAD1]], [[LOAD]]
28 ; P5600: G_STORE [[ADD]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
33 %3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
34 %4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
35 %5:_(<16 x s8>) = G_ADD %4, %3
36 G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
44 tracksRegLiveness: true
47 liveins: $a0, $a1, $a2
49 ; P5600-LABEL: name: add_v8i16
50 ; P5600: liveins: $a0, $a1, $a2
51 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
52 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
53 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
54 ; P5600: [[LOAD:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
55 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
56 ; P5600: [[ADD:%[0-9]+]]:fprb(<8 x s16>) = G_ADD [[LOAD1]], [[LOAD]]
57 ; P5600: G_STORE [[ADD]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
62 %3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
63 %4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
64 %5:_(<8 x s16>) = G_ADD %4, %3
65 G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
73 tracksRegLiveness: true
76 liveins: $a0, $a1, $a2
78 ; P5600-LABEL: name: add_v4i32
79 ; P5600: liveins: $a0, $a1, $a2
80 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
81 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
82 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
83 ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
84 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
85 ; P5600: [[ADD:%[0-9]+]]:fprb(<4 x s32>) = G_ADD [[LOAD1]], [[LOAD]]
86 ; P5600: G_STORE [[ADD]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
91 %3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
92 %4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
93 %5:_(<4 x s32>) = G_ADD %4, %3
94 G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
102 tracksRegLiveness: true
105 liveins: $a0, $a1, $a2
107 ; P5600-LABEL: name: add_v2i64
108 ; P5600: liveins: $a0, $a1, $a2
109 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
110 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
111 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
112 ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
113 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
114 ; P5600: [[ADD:%[0-9]+]]:fprb(<2 x s64>) = G_ADD [[LOAD1]], [[LOAD]]
115 ; P5600: G_STORE [[ADD]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
120 %3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
121 %4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
122 %5:_(<2 x s64>) = G_ADD %4, %3
123 G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)