1 ; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix --code-model=small < \
2 ; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK32,CHECK-SMALL,CHECK-SMALL32 %s
4 ; RUN: llc --verify-machineinstrs -mtriple powerpc-ibm-aix --code-model=large < \
5 ; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK32,CHECK-LARGE,CHECK-LARGE32 %s
7 ; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix --code-model=small < \
8 ; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK64,CHECK-SMALL,CHECK-SMALL64 %s
10 ; RUN: llc --verify-machineinstrs -mtriple powerpc64-ibm-aix --code-model=large < \
11 ; RUN: %s | FileCheck --check-prefixes=CHECK,CHECK64,CHECK-LARGE,CHECK-LARGE64 %s
13 @a = external dso_local global i32, code_model "small", align 4
14 @b = external dso_local global i32, code_model "large", align 4
15 @c = dso_local global i32 55, code_model "small", align 4
16 @d = dso_local global i32 41, code_model "large", align 4
17 @e = external dso_local global i32, align 4
18 @f = dso_local global i32 2748, align 4
20 @large_aliasee = global i32 10, code_model "large", align 4
21 @small_aliasee = global i32 171, code_model "small", align 4
22 @normal_aliasee = global i32 2748, align 4
24 @al = alias i32, ptr @large_aliasee
25 @as = alias i32, ptr @small_aliasee
26 @an = alias i32, ptr @normal_aliasee
28 define i32 @A() local_unnamed_addr {
30 %0 = load i32, ptr @a, align 4
33 ; CHECK32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_A:[0-9]+]](2) # @a
34 ; CHECK64: ld [[SCRATCH:[0-9]+]], L..C[[TL_A:[0-9]+]](2) # @a
35 ; CHECK: lwz 3, 0([[SCRATCH]])
38 define i32 @B() local_unnamed_addr {
40 %0 = load i32, ptr @b, align 4
43 ; CHECK: addis [[HI:[0-9]+]], L..C[[TL_B:[0-9]+]]@u(2)
44 ; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_B]]@l([[HI]])
45 ; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_B]]@l([[HI]])
46 ; CHECK: lwz 3, 0([[ADDR]])
49 define i32 @C() local_unnamed_addr {
51 %0 = load i32, ptr @c, align 4
54 ; CHECK32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_C:[0-9]+]](2) # @c
55 ; CHECK64: ld [[SCRATCH:[0-9]+]], L..C[[TL_C:[0-9]+]](2) # @c
56 ; CHECK: lwz 3, 0([[SCRATCH]])
59 define i32 @D() local_unnamed_addr {
61 %0 = load i32, ptr @d, align 4
64 ; CHECK: addis [[HI:[0-9]+]], L..C[[TL_D:[0-9]+]]@u(2)
65 ; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_D]]@l([[HI]])
66 ; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_D]]@l([[HI]])
67 ; CHECK: lwz 3, 0([[ADDR]])
72 %0 = load i32, ptr @e, align 4
75 ; CHECK-LARGE: addis [[HI:[0-9]+]], L..C[[TL_E:[0-9]+]]@u(2)
76 ; CHECK-LARGE32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_E]]@l([[HI]])
77 ; CHECK-SMALL32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_E:[0-9]+]](2)
78 ; CHECK-LARGE64: ld [[SCRATCH:[0-9]+]], L..C[[TL_E]]@l([[HI]])
79 ; CHECK-SMALL64: ld [[SCRATCH:[0-9]+]], L..C[[TL_E:[0-9]+]](2)
80 ; CHECK: lwz 3, 0([[SCRATCH]])
85 %0 = load i32, ptr @f, align 4
88 ; CHECK-LARGE: addis [[HI:[0-9]+]], L..C[[TL_F:[0-9]+]]@u(2)
89 ; CHECK-LARGE32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_F]]@l([[HI]])
90 ; CHECK-SMALL32: lwz [[SCRATCH:[0-9]+]], L..C[[TL_F:[0-9]+]](2)
91 ; CHECK-LARGE64: ld [[SCRATCH:[0-9]+]], L..C[[TL_F]]@l([[HI]])
92 ; CHECK-SMALL64: ld [[SCRATCH:[0-9]+]], L..C[[TL_F:[0-9]+]](2)
93 ; CHECK: lwz 3, 0([[SCRATCH]])
96 define noundef nonnull ptr @addr_a() local_unnamed_addr {
100 ; CHECK32: lwz 3, L..C[[TL_A]](2) # @a
101 ; CHECK64: ld 3, L..C[[TL_A]](2) # @a
104 define noundef nonnull ptr @addr_b() local_unnamed_addr {
108 ; CHECK: addis [[HI:[0-9]+]], L..C[[TL_B]]@u(2)
109 ; CHECK32: lwz 3, L..C[[TL_B]]@l([[HI]])
110 ; CHECK64: ld 3, L..C[[TL_B]]@l([[HI]])
114 define noundef nonnull ptr @addr_c() local_unnamed_addr {
118 ; CHECK32: lwz 3, L..C[[TL_C]](2) # @c
119 ; CHECK64: ld 3, L..C[[TL_C]](2) # @c
122 define noundef nonnull ptr @addr_d() local_unnamed_addr {
126 ; CHECK: addis [[HI:[0-9]+]], L..C[[TL_D]]@u(2)
127 ; CHECK32: lwz 3, L..C[[TL_D]]@l([[HI]])
128 ; CHECK64: ld 3, L..C[[TL_D]]@l([[HI]])
132 %tmp = load i32, ptr @al
135 ; CHECK: addis [[HI:[0-9]+]], L..C[[TL_AL:[0-9]+]]@u(2)
136 ; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_AL]]@l([[HI]])
137 ; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_AL]]@l([[HI]])
138 ; CHECK: lwz 3, 0([[ADDR]])
141 %tmp = load i32, ptr @as
144 ; CHECK32: lwz [[ADDR:[0-9]+]], L..C[[TL_AS:[0-9]+]](2)
145 ; CHECK64: ld [[ADDR:[0-9]+]], L..C[[TL_AS:[0-9]+]](2)
146 ; CHECK: lwz 3, 0([[ADDR]])
148 ;; Check TOC entires have correct storage mapping class
149 ; CHECK: L..C[[TL_A]]:
150 ; CHECK: .tc a[TC],a[UA]
151 ; CHECK: L..C[[TL_B]]:
152 ; CHECK: .tc b[TE],b[UA]
153 ; CHECK: L..C[[TL_C]]:
154 ; CHECK: .tc c[TC],c[RW]
155 ; CHECK: L..C[[TL_D]]:
156 ; CHECK: .tc d[TE],d[RW]
157 ; CHECK: L..C[[TL_E]]:
158 ; CHECK-SMALL: .tc e[TC],e[UA]
159 ; CHECK-LARGE: .tc e[TE],e[UA]
160 ; CHECK: L..C[[TL_F]]:
161 ; CHECK-SMALL: .tc f[TC],f[RW]
162 ; CHECK-LARGE: .tc f[TE],f[RW]
163 ; CHECK: L..C[[TL_AL]]:
164 ; CHECK: .tc al[TE],al
165 ; CHECK: L..C[[TL_AS]]:
166 ; CHECK: .tc as[TC],as