| blob | 158ec7a3427c83dbbe922402fcecfe26f46524b8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; This test is a copy of mma-intrinsics.ll except that it uses mcpu=future.
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
4 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
5 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
7 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
8 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
10 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
11 ; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0
12 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
13 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
14 ; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0-BE
15 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix- \
16 ; RUN: -mcpu=future -vec-extabi \
17 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX64
18 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix- \
19 ; RUN: -mcpu=future -vec-extabi \
20 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX32
22 ; TODO: This test is missing some of the tests from mma-intrinsics.ll because
23 ; those tests do not work for mcpu=future. Once the fixes are in they
24 ; should be added back to this file.
26 ; assemble_acc
27 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
28 define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
29 ; CHECK-LABEL: ass_acc:
30 ; CHECK: # %bb.0: # %entry
31 ; CHECK-NEXT: vmr v3, v2
32 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
33 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
34 ; CHECK-NEXT: stxv v4, 48(r3)
35 ; CHECK-NEXT: stxv v5, 32(r3)
36 ; CHECK-NEXT: stxv v2, 16(r3)
37 ; CHECK-NEXT: stxv v3, 0(r3)
38 ; CHECK-NEXT: blr
39 ;
40 ; CHECK-BE-LABEL: ass_acc:
41 ; CHECK-BE: # %bb.0: # %entry
42 ; CHECK-BE-NEXT: vmr v3, v2
43 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
44 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
45 ; CHECK-BE-NEXT: stxv v5, 48(r3)
46 ; CHECK-BE-NEXT: stxv v4, 32(r3)
47 ; CHECK-BE-NEXT: stxv v3, 16(r3)
48 ; CHECK-BE-NEXT: stxv v2, 0(r3)
49 ; CHECK-BE-NEXT: blr
50 ;
51 ; CHECK-O0-LABEL: ass_acc:
52 ; CHECK-O0: # %bb.0: # %entry
53 ; CHECK-O0-NEXT: vmr v4, v2
54 ; CHECK-O0-NEXT: # implicit-def: $vsrp17
55 ; CHECK-O0-NEXT: vmr v3, v4
56 ; CHECK-O0-NEXT: vmr v2, v4
57 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
58 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
59 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
60 ; CHECK-O0-NEXT: stxv vs0, 48(r3)
61 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
62 ; CHECK-O0-NEXT: stxv vs0, 32(r3)
63 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
64 ; CHECK-O0-NEXT: stxv vs0, 16(r3)
65 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
66 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
67 ; CHECK-O0-NEXT: blr
68 ;
69 ; CHECK-O0-BE-LABEL: ass_acc:
70 ; CHECK-O0-BE: # %bb.0: # %entry
71 ; CHECK-O0-BE-NEXT: vmr v4, v2
72 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17
73 ; CHECK-O0-BE-NEXT: vmr v3, v4
74 ; CHECK-O0-BE-NEXT: vmr v2, v4
75 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
76 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
77 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
78 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
79 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
80 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)
81 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
82 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)
83 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
84 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
85 ; CHECK-O0-BE-NEXT: blr
86 ;
87 ; CHECK-AIX64-LABEL: ass_acc:
88 ; CHECK-AIX64: # %bb.0: # %entry
89 ; CHECK-AIX64-NEXT: vmr 3, 2
90 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 34, 34, 0
91 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
92 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
93 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
94 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
95 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
96 ; CHECK-AIX64-NEXT: blr
97 ;
98 ; CHECK-AIX32-LABEL: ass_acc:
99 ; CHECK-AIX32: # %bb.0: # %entry
100 ; CHECK-AIX32-NEXT: vmr 3, 2
101 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 34, 34, 0
102 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
103 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
104 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
105 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
106 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
107 ; CHECK-AIX32-NEXT: blr
108 entry:
109 %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
110 store <512 x i1> %0, ptr %ptr, align 64
111 ret void
112 }
114 ; xxmtacc with a loaded and stored vector quad.
115 define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
116 ; CHECK-LABEL: ld_st_xxmtacc:
117 ; CHECK: # %bb.0: # %entry
118 ; CHECK-NEXT: lxv v3, 0(r3)
119 ; CHECK-NEXT: lxv v5, 32(r3)
120 ; CHECK-NEXT: lxv v2, 16(r3)
121 ; CHECK-NEXT: lxv v4, 48(r3)
122 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
123 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
124 ; CHECK-NEXT: stxv v4, 48(r7)
125 ; CHECK-NEXT: stxv v5, 32(r7)
126 ; CHECK-NEXT: stxv v2, 16(r7)
127 ; CHECK-NEXT: stxv v3, 0(r7)
128 ; CHECK-NEXT: blr
129 ;
130 ; CHECK-BE-LABEL: ld_st_xxmtacc:
131 ; CHECK-BE: # %bb.0: # %entry
132 ; CHECK-BE-NEXT: lxv v3, 48(r3)
133 ; CHECK-BE-NEXT: lxv v5, 16(r3)
134 ; CHECK-BE-NEXT: lxv v2, 32(r3)
135 ; CHECK-BE-NEXT: lxv v4, 0(r3)
136 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
137 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
138 ; CHECK-BE-NEXT: stxv v5, 48(r7)
139 ; CHECK-BE-NEXT: stxv v4, 32(r7)
140 ; CHECK-BE-NEXT: stxv v3, 16(r7)
141 ; CHECK-BE-NEXT: stxv v2, 0(r7)
142 ; CHECK-BE-NEXT: blr
143 ;
144 ; CHECK-O0-LABEL: ld_st_xxmtacc:
145 ; CHECK-O0: # %bb.0: # %entry
146 ; CHECK-O0-NEXT: lxv vs0, 0(r3)
147 ; CHECK-O0-NEXT: # implicit-def: $vsrp18
148 ; CHECK-O0-NEXT: xxlor v5, vs0, vs0
149 ; CHECK-O0-NEXT: lxv vs0, 16(r3)
150 ; CHECK-O0-NEXT: xxlor v4, vs0, vs0
151 ; CHECK-O0-NEXT: lxv vs0, 32(r3)
152 ; CHECK-O0-NEXT: # implicit-def: $vsrp17
153 ; CHECK-O0-NEXT: xxlor v3, vs0, vs0
154 ; CHECK-O0-NEXT: lxv vs0, 48(r3)
155 ; CHECK-O0-NEXT: xxlor v2, vs0, vs0
156 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
157 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
158 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
159 ; CHECK-O0-NEXT: stxv vs0, 48(r7)
160 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
161 ; CHECK-O0-NEXT: stxv vs0, 32(r7)
162 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
163 ; CHECK-O0-NEXT: stxv vs0, 16(r7)
164 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
165 ; CHECK-O0-NEXT: stxv vs0, 0(r7)
166 ; CHECK-O0-NEXT: blr
167 ;
168 ; CHECK-O0-BE-LABEL: ld_st_xxmtacc:
169 ; CHECK-O0-BE: # %bb.0: # %entry
170 ; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)
171 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18
172 ; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0
173 ; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)
174 ; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0
175 ; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)
176 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17
177 ; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0
178 ; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
179 ; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0
180 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
181 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
182 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
183 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)
184 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
185 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)
186 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
187 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)
188 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
189 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)
190 ; CHECK-O0-BE-NEXT: blr
191 ;
192 ; CHECK-AIX64-LABEL: ld_st_xxmtacc:
193 ; CHECK-AIX64: # %bb.0: # %entry
194 ; CHECK-AIX64-NEXT: lxv 3, 48(3)
195 ; CHECK-AIX64-NEXT: lxv 5, 16(3)
196 ; CHECK-AIX64-NEXT: lxv 2, 32(3)
197 ; CHECK-AIX64-NEXT: lxv 4, 0(3)
198 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 36, 34, 0
199 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
200 ; CHECK-AIX64-NEXT: stxv 5, 48(5)
201 ; CHECK-AIX64-NEXT: stxv 4, 32(5)
202 ; CHECK-AIX64-NEXT: stxv 3, 16(5)
203 ; CHECK-AIX64-NEXT: stxv 2, 0(5)
204 ; CHECK-AIX64-NEXT: blr
205 ;
206 ; CHECK-AIX32-LABEL: ld_st_xxmtacc:
207 ; CHECK-AIX32: # %bb.0: # %entry
208 ; CHECK-AIX32-NEXT: lxv 3, 48(3)
209 ; CHECK-AIX32-NEXT: lxv 5, 16(3)
210 ; CHECK-AIX32-NEXT: lxv 2, 32(3)
211 ; CHECK-AIX32-NEXT: lxv 4, 0(3)
212 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 36, 34, 0
213 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
214 ; CHECK-AIX32-NEXT: stxv 5, 48(5)
215 ; CHECK-AIX32-NEXT: stxv 4, 32(5)
216 ; CHECK-AIX32-NEXT: stxv 3, 16(5)
217 ; CHECK-AIX32-NEXT: stxv 2, 0(5)
218 ; CHECK-AIX32-NEXT: blr
219 entry:
220 %0 = load <512 x i1>, ptr %vqp, align 64
221 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
222 store <512 x i1> %1, ptr %resp, align 64
223 ret void
224 }
226 declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
228 ; xxmtacc used with an instruction that is not a load or store.
229 define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
230 ; CHECK-LABEL: ld_op_st_xxmtacc:
231 ; CHECK: # %bb.0: # %entry
232 ; CHECK-NEXT: lxv v5, 0(r3)
233 ; CHECK-NEXT: lxv v1, 32(r3)
234 ; CHECK-NEXT: lxv v4, 16(r3)
235 ; CHECK-NEXT: lxv v0, 48(r3)
236 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
237 ; CHECK-NEXT: xvi4ger8pp wacc0, v2, v2
238 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
239 ; CHECK-NEXT: stxv v4, 48(r7)
240 ; CHECK-NEXT: stxv v5, 32(r7)
241 ; CHECK-NEXT: stxv v2, 16(r7)
242 ; CHECK-NEXT: stxv v3, 0(r7)
243 ; CHECK-NEXT: blr
244 ;
245 ; CHECK-BE-LABEL: ld_op_st_xxmtacc:
246 ; CHECK-BE: # %bb.0: # %entry
247 ; CHECK-BE-NEXT: lxv v5, 48(r3)
248 ; CHECK-BE-NEXT: lxv v1, 16(r3)
249 ; CHECK-BE-NEXT: lxv v4, 32(r3)
250 ; CHECK-BE-NEXT: lxv v0, 0(r3)
251 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
252 ; CHECK-BE-NEXT: xvi4ger8pp wacc0, v2, v2
253 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
254 ; CHECK-BE-NEXT: stxv v5, 48(r7)
255 ; CHECK-BE-NEXT: stxv v4, 32(r7)
256 ; CHECK-BE-NEXT: stxv v3, 16(r7)
257 ; CHECK-BE-NEXT: stxv v2, 0(r7)
258 ; CHECK-BE-NEXT: blr
259 ;
260 ; CHECK-O0-LABEL: ld_op_st_xxmtacc:
261 ; CHECK-O0: # %bb.0: # %entry
262 ; CHECK-O0-NEXT: lxv vs0, 0(r3)
263 ; CHECK-O0-NEXT: # implicit-def: $vsrp16
264 ; CHECK-O0-NEXT: xxlor v1, vs0, vs0
265 ; CHECK-O0-NEXT: lxv vs0, 16(r3)
266 ; CHECK-O0-NEXT: xxlor v0, vs0, vs0
267 ; CHECK-O0-NEXT: lxv vs0, 32(r3)
268 ; CHECK-O0-NEXT: # implicit-def: $vsrp18
269 ; CHECK-O0-NEXT: xxlor v5, vs0, vs0
270 ; CHECK-O0-NEXT: lxv vs0, 48(r3)
271 ; CHECK-O0-NEXT: xxlor v4, vs0, vs0
272 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
273 ; CHECK-O0-NEXT: xvi4ger8pp wacc0, v2, v2
274 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
275 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
276 ; CHECK-O0-NEXT: stxv vs0, 48(r7)
277 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
278 ; CHECK-O0-NEXT: stxv vs0, 32(r7)
279 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
280 ; CHECK-O0-NEXT: stxv vs0, 16(r7)
281 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
282 ; CHECK-O0-NEXT: stxv vs0, 0(r7)
283 ; CHECK-O0-NEXT: blr
284 ;
285 ; CHECK-O0-BE-LABEL: ld_op_st_xxmtacc:
286 ; CHECK-O0-BE: # %bb.0: # %entry
287 ; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)
288 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp16
289 ; CHECK-O0-BE-NEXT: xxlor v1, vs0, vs0
290 ; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)
291 ; CHECK-O0-BE-NEXT: xxlor v0, vs0, vs0
292 ; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)
293 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18
294 ; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0
295 ; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
296 ; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0
297 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
298 ; CHECK-O0-BE-NEXT: xvi4ger8pp wacc0, v2, v2
299 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
300 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
301 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)
302 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
303 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)
304 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
305 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)
306 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
307 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)
308 ; CHECK-O0-BE-NEXT: blr
309 ;
310 ; CHECK-AIX64-LABEL: ld_op_st_xxmtacc:
311 ; CHECK-AIX64: # %bb.0: # %entry
312 ; CHECK-AIX64-NEXT: lxv 5, 48(3)
313 ; CHECK-AIX64-NEXT: lxv 1, 16(3)
314 ; CHECK-AIX64-NEXT: lxv 4, 32(3)
315 ; CHECK-AIX64-NEXT: lxv 0, 0(3)
316 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 32, 36, 0
317 ; CHECK-AIX64-NEXT: xvi4ger8pp 0, 2, 2
318 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
319 ; CHECK-AIX64-NEXT: stxv 5, 48(5)
320 ; CHECK-AIX64-NEXT: stxv 4, 32(5)
321 ; CHECK-AIX64-NEXT: stxv 3, 16(5)
322 ; CHECK-AIX64-NEXT: stxv 2, 0(5)
323 ; CHECK-AIX64-NEXT: blr
324 ;
325 ; CHECK-AIX32-LABEL: ld_op_st_xxmtacc:
326 ; CHECK-AIX32: # %bb.0: # %entry
327 ; CHECK-AIX32-NEXT: lxv 5, 48(3)
328 ; CHECK-AIX32-NEXT: lxv 1, 16(3)
329 ; CHECK-AIX32-NEXT: lxv 4, 32(3)
330 ; CHECK-AIX32-NEXT: lxv 0, 0(3)
331 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 32, 36, 0
332 ; CHECK-AIX32-NEXT: xvi4ger8pp 0, 2, 2
333 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
334 ; CHECK-AIX32-NEXT: stxv 5, 48(5)
335 ; CHECK-AIX32-NEXT: stxv 4, 32(5)
336 ; CHECK-AIX32-NEXT: stxv 3, 16(5)
337 ; CHECK-AIX32-NEXT: stxv 2, 0(5)
338 ; CHECK-AIX32-NEXT: blr
339 entry:
340 %0 = load <512 x i1>, ptr %vqp, align 64
341 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
342 %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
343 store <512 x i1> %2, ptr %resp, align 64
344 ret void
345 }
347 declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>)
349 ; xxmfacc with a loaded and stored vector quad.
350 define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
351 ; CHECK-LABEL: ld_st_xxmfacc:
352 ; CHECK: # %bb.0: # %entry
353 ; CHECK-NEXT: lxv v3, 0(r3)
354 ; CHECK-NEXT: lxv v5, 32(r3)
355 ; CHECK-NEXT: lxv v2, 16(r3)
356 ; CHECK-NEXT: lxv v4, 48(r3)
357 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
358 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
359 ; CHECK-NEXT: stxv v4, 48(r3)
360 ; CHECK-NEXT: stxv v5, 32(r3)
361 ; CHECK-NEXT: stxv v2, 16(r3)
362 ; CHECK-NEXT: stxv v3, 0(r3)
363 ; CHECK-NEXT: stxv v4, 48(r7)
364 ; CHECK-NEXT: stxv v5, 32(r7)
365 ; CHECK-NEXT: stxv v2, 16(r7)
366 ; CHECK-NEXT: stxv v3, 0(r7)
367 ; CHECK-NEXT: blr
368 ;
369 ; CHECK-BE-LABEL: ld_st_xxmfacc:
370 ; CHECK-BE: # %bb.0: # %entry
371 ; CHECK-BE-NEXT: lxv v3, 48(r3)
372 ; CHECK-BE-NEXT: lxv v5, 16(r3)
373 ; CHECK-BE-NEXT: lxv v2, 32(r3)
374 ; CHECK-BE-NEXT: lxv v4, 0(r3)
375 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
376 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
377 ; CHECK-BE-NEXT: stxv v5, 48(r3)
378 ; CHECK-BE-NEXT: stxv v4, 32(r3)
379 ; CHECK-BE-NEXT: stxv v3, 16(r3)
380 ; CHECK-BE-NEXT: stxv v2, 0(r3)
381 ; CHECK-BE-NEXT: stxv v5, 48(r7)
382 ; CHECK-BE-NEXT: stxv v4, 32(r7)
383 ; CHECK-BE-NEXT: stxv v3, 16(r7)
384 ; CHECK-BE-NEXT: stxv v2, 0(r7)
385 ; CHECK-BE-NEXT: blr
386 ;
387 ; CHECK-O0-LABEL: ld_st_xxmfacc:
388 ; CHECK-O0: # %bb.0: # %entry
389 ; CHECK-O0-NEXT: lxv vs0, 0(r3)
390 ; CHECK-O0-NEXT: # implicit-def: $vsrp18
391 ; CHECK-O0-NEXT: xxlor v5, vs0, vs0
392 ; CHECK-O0-NEXT: lxv vs0, 16(r3)
393 ; CHECK-O0-NEXT: xxlor v4, vs0, vs0
394 ; CHECK-O0-NEXT: lxv vs0, 32(r3)
395 ; CHECK-O0-NEXT: # implicit-def: $vsrp17
396 ; CHECK-O0-NEXT: xxlor v3, vs0, vs0
397 ; CHECK-O0-NEXT: lxv vs0, 48(r3)
398 ; CHECK-O0-NEXT: xxlor v2, vs0, vs0
399 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
400 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
401 ; CHECK-O0-NEXT: xxlor vs3, v4, v4
402 ; CHECK-O0-NEXT: stxv vs3, 48(r3)
403 ; CHECK-O0-NEXT: xxlor vs2, v5, v5
404 ; CHECK-O0-NEXT: stxv vs2, 32(r3)
405 ; CHECK-O0-NEXT: xxlor vs1, v2, v2
406 ; CHECK-O0-NEXT: stxv vs1, 16(r3)
407 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
408 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
409 ; CHECK-O0-NEXT: stxv vs3, 48(r7)
410 ; CHECK-O0-NEXT: stxv vs2, 32(r7)
411 ; CHECK-O0-NEXT: stxv vs1, 16(r7)
412 ; CHECK-O0-NEXT: stxv vs0, 0(r7)
413 ; CHECK-O0-NEXT: blr
414 ;
415 ; CHECK-O0-BE-LABEL: ld_st_xxmfacc:
416 ; CHECK-O0-BE: # %bb.0: # %entry
417 ; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)
418 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18
419 ; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0
420 ; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)
421 ; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0
422 ; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)
423 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17
424 ; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0
425 ; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
426 ; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0
427 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
428 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
429 ; CHECK-O0-BE-NEXT: xxlor vs3, v5, v5
430 ; CHECK-O0-BE-NEXT: stxv vs3, 48(r3)
431 ; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4
432 ; CHECK-O0-BE-NEXT: stxv vs2, 32(r3)
433 ; CHECK-O0-BE-NEXT: xxlor vs1, v3, v3
434 ; CHECK-O0-BE-NEXT: stxv vs1, 16(r3)
435 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
436 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
437 ; CHECK-O0-BE-NEXT: stxv vs3, 48(r7)
438 ; CHECK-O0-BE-NEXT: stxv vs2, 32(r7)
439 ; CHECK-O0-BE-NEXT: stxv vs1, 16(r7)
440 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)
441 ; CHECK-O0-BE-NEXT: blr
442 ;
443 ; CHECK-AIX64-LABEL: ld_st_xxmfacc:
444 ; CHECK-AIX64: # %bb.0: # %entry
445 ; CHECK-AIX64-NEXT: lxv 3, 48(3)
446 ; CHECK-AIX64-NEXT: lxv 5, 16(3)
447 ; CHECK-AIX64-NEXT: lxv 2, 32(3)
448 ; CHECK-AIX64-NEXT: lxv 4, 0(3)
449 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 36, 34, 0
450 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
451 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
452 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
453 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
454 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
455 ; CHECK-AIX64-NEXT: stxv 5, 48(5)
456 ; CHECK-AIX64-NEXT: stxv 4, 32(5)
457 ; CHECK-AIX64-NEXT: stxv 3, 16(5)
458 ; CHECK-AIX64-NEXT: stxv 2, 0(5)
459 ; CHECK-AIX64-NEXT: blr
460 ;
461 ; CHECK-AIX32-LABEL: ld_st_xxmfacc:
462 ; CHECK-AIX32: # %bb.0: # %entry
463 ; CHECK-AIX32-NEXT: lxv 3, 48(3)
464 ; CHECK-AIX32-NEXT: lxv 5, 16(3)
465 ; CHECK-AIX32-NEXT: lxv 2, 32(3)
466 ; CHECK-AIX32-NEXT: lxv 4, 0(3)
467 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 36, 34, 0
468 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
469 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
470 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
471 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
472 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
473 ; CHECK-AIX32-NEXT: stxv 5, 48(5)
474 ; CHECK-AIX32-NEXT: stxv 4, 32(5)
475 ; CHECK-AIX32-NEXT: stxv 3, 16(5)
476 ; CHECK-AIX32-NEXT: stxv 2, 0(5)
477 ; CHECK-AIX32-NEXT: blr
478 entry:
479 %0 = load <512 x i1>, ptr %vqp, align 64
480 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %0)
481 store <512 x i1> %1, ptr %vqp, align 64
482 store <512 x i1> %1, ptr %resp, align 64
483 ret void
484 }
486 declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
488 ; xxmfacc used with an instruction that is not a load or store.
489 define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
490 ; CHECK-LABEL: ld_op_st_xxmfacc:
491 ; CHECK: # %bb.0: # %entry
492 ; CHECK-NEXT: lxv v5, 0(r3)
493 ; CHECK-NEXT: lxv v1, 32(r3)
494 ; CHECK-NEXT: lxv v4, 16(r3)
495 ; CHECK-NEXT: lxv v0, 48(r3)
496 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
497 ; CHECK-NEXT: xvi4ger8pp wacc0, v2, v2
498 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
499 ; CHECK-NEXT: stxv v4, 48(r7)
500 ; CHECK-NEXT: stxv v5, 32(r7)
501 ; CHECK-NEXT: stxv v2, 16(r7)
502 ; CHECK-NEXT: stxv v3, 0(r7)
503 ; CHECK-NEXT: blr
504 ;
505 ; CHECK-BE-LABEL: ld_op_st_xxmfacc:
506 ; CHECK-BE: # %bb.0: # %entry
507 ; CHECK-BE-NEXT: lxv v5, 48(r3)
508 ; CHECK-BE-NEXT: lxv v1, 16(r3)
509 ; CHECK-BE-NEXT: lxv v4, 32(r3)
510 ; CHECK-BE-NEXT: lxv v0, 0(r3)
511 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
512 ; CHECK-BE-NEXT: xvi4ger8pp wacc0, v2, v2
513 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
514 ; CHECK-BE-NEXT: stxv v5, 48(r7)
515 ; CHECK-BE-NEXT: stxv v4, 32(r7)
516 ; CHECK-BE-NEXT: stxv v3, 16(r7)
517 ; CHECK-BE-NEXT: stxv v2, 0(r7)
518 ; CHECK-BE-NEXT: blr
519 ;
520 ; CHECK-O0-LABEL: ld_op_st_xxmfacc:
521 ; CHECK-O0: # %bb.0: # %entry
522 ; CHECK-O0-NEXT: lxv vs0, 0(r3)
523 ; CHECK-O0-NEXT: # implicit-def: $vsrp16
524 ; CHECK-O0-NEXT: xxlor v1, vs0, vs0
525 ; CHECK-O0-NEXT: lxv vs0, 16(r3)
526 ; CHECK-O0-NEXT: xxlor v0, vs0, vs0
527 ; CHECK-O0-NEXT: lxv vs0, 32(r3)
528 ; CHECK-O0-NEXT: # implicit-def: $vsrp18
529 ; CHECK-O0-NEXT: xxlor v5, vs0, vs0
530 ; CHECK-O0-NEXT: lxv vs0, 48(r3)
531 ; CHECK-O0-NEXT: xxlor v4, vs0, vs0
532 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
533 ; CHECK-O0-NEXT: xvi4ger8pp wacc0, v2, v2
534 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
535 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
536 ; CHECK-O0-NEXT: stxv vs0, 48(r7)
537 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
538 ; CHECK-O0-NEXT: stxv vs0, 32(r7)
539 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
540 ; CHECK-O0-NEXT: stxv vs0, 16(r7)
541 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
542 ; CHECK-O0-NEXT: stxv vs0, 0(r7)
543 ; CHECK-O0-NEXT: blr
544 ;
545 ; CHECK-O0-BE-LABEL: ld_op_st_xxmfacc:
546 ; CHECK-O0-BE: # %bb.0: # %entry
547 ; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)
548 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp16
549 ; CHECK-O0-BE-NEXT: xxlor v1, vs0, vs0
550 ; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)
551 ; CHECK-O0-BE-NEXT: xxlor v0, vs0, vs0
552 ; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)
553 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18
554 ; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0
555 ; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
556 ; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0
557 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
558 ; CHECK-O0-BE-NEXT: xvi4ger8pp wacc0, v2, v2
559 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
560 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
561 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)
562 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
563 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)
564 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
565 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)
566 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
567 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)
568 ; CHECK-O0-BE-NEXT: blr
569 ;
570 ; CHECK-AIX64-LABEL: ld_op_st_xxmfacc:
571 ; CHECK-AIX64: # %bb.0: # %entry
572 ; CHECK-AIX64-NEXT: lxv 5, 48(3)
573 ; CHECK-AIX64-NEXT: lxv 1, 16(3)
574 ; CHECK-AIX64-NEXT: lxv 4, 32(3)
575 ; CHECK-AIX64-NEXT: lxv 0, 0(3)
576 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 32, 36, 0
577 ; CHECK-AIX64-NEXT: xvi4ger8pp 0, 2, 2
578 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
579 ; CHECK-AIX64-NEXT: stxv 5, 48(5)
580 ; CHECK-AIX64-NEXT: stxv 4, 32(5)
581 ; CHECK-AIX64-NEXT: stxv 3, 16(5)
582 ; CHECK-AIX64-NEXT: stxv 2, 0(5)
583 ; CHECK-AIX64-NEXT: blr
584 ;
585 ; CHECK-AIX32-LABEL: ld_op_st_xxmfacc:
586 ; CHECK-AIX32: # %bb.0: # %entry
587 ; CHECK-AIX32-NEXT: lxv 5, 48(3)
588 ; CHECK-AIX32-NEXT: lxv 1, 16(3)
589 ; CHECK-AIX32-NEXT: lxv 4, 32(3)
590 ; CHECK-AIX32-NEXT: lxv 0, 0(3)
591 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 32, 36, 0
592 ; CHECK-AIX32-NEXT: xvi4ger8pp 0, 2, 2
593 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
594 ; CHECK-AIX32-NEXT: stxv 5, 48(5)
595 ; CHECK-AIX32-NEXT: stxv 4, 32(5)
596 ; CHECK-AIX32-NEXT: stxv 3, 16(5)
597 ; CHECK-AIX32-NEXT: stxv 2, 0(5)
598 ; CHECK-AIX32-NEXT: blr
599 entry:
600 %0 = load <512 x i1>, ptr %vqp, align 64
601 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
602 %2 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %1)
603 store <512 x i1> %2, ptr %resp, align 64
604 ret void
605 }
607 ; xxmtacc and xxmfacc used interleaved in more complexed mma code.
608 define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2) {
609 ; CHECK-LABEL: cmplx_xxmacc:
610 ; CHECK: # %bb.0: # %entry
611 ; CHECK-NEXT: lxv v1, 0(r3)
612 ; CHECK-NEXT: lxv v7, 32(r3)
613 ; CHECK-NEXT: lxv v0, 16(r3)
614 ; CHECK-NEXT: lxv v6, 48(r3)
615 ; CHECK-NEXT: vmr v4, v3
616 ; CHECK-NEXT: vmr v5, v2
617 ; CHECK-NEXT: xxlor v2, v4, v4
618 ; CHECK-NEXT: vmr v2, v5
619 ; CHECK-NEXT: xxlor v3, v5, v5
620 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp32, 0
621 ; CHECK-NEXT: xvf64gerpp wacc0, vsp34, v5
622 ; CHECK-NEXT: xvf64gerpp wacc0, vsp36, v4
623 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
624 ; CHECK-NEXT: stxv v4, 48(r3)
625 ; CHECK-NEXT: stxv v5, 32(r3)
626 ; CHECK-NEXT: stxv v2, 16(r3)
627 ; CHECK-NEXT: stxv v3, 0(r3)
628 ; CHECK-NEXT: blr
629 ;
630 ; CHECK-BE-LABEL: cmplx_xxmacc:
631 ; CHECK-BE: # %bb.0: # %entry
632 ; CHECK-BE-NEXT: lxv v1, 48(r3)
633 ; CHECK-BE-NEXT: lxv v7, 16(r3)
634 ; CHECK-BE-NEXT: lxv v0, 32(r3)
635 ; CHECK-BE-NEXT: lxv v6, 0(r3)
636 ; CHECK-BE-NEXT: vmr v4, v3
637 ; CHECK-BE-NEXT: vmr v5, v2
638 ; CHECK-BE-NEXT: xxlor v2, v4, v4
639 ; CHECK-BE-NEXT: vmr v2, v5
640 ; CHECK-BE-NEXT: xxlor v3, v5, v5
641 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp32, 0
642 ; CHECK-BE-NEXT: xvf64gerpp wacc0, vsp34, v5
643 ; CHECK-BE-NEXT: xvf64gerpp wacc0, vsp36, v4
644 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
645 ; CHECK-BE-NEXT: stxv v5, 48(r3)
646 ; CHECK-BE-NEXT: stxv v4, 32(r3)
647 ; CHECK-BE-NEXT: stxv v3, 16(r3)
648 ; CHECK-BE-NEXT: stxv v2, 0(r3)
649 ; CHECK-BE-NEXT: blr
650 ;
651 ; CHECK-O0-LABEL: cmplx_xxmacc:
652 ; CHECK-O0: # %bb.0: # %entry
653 ; CHECK-O0-NEXT: vmr v4, v3
654 ; CHECK-O0-NEXT: vmr v5, v2
655 ; CHECK-O0-NEXT: # implicit-def: $vsrp16
656 ; CHECK-O0-NEXT: vmr v1, v5
657 ; CHECK-O0-NEXT: xxlor v2, v0, v0
658 ; CHECK-O0-NEXT: xxlor v3, v1, v1
659 ; CHECK-O0-NEXT: vmr v2, v4
660 ; CHECK-O0-NEXT: vmr v0, v5
661 ; CHECK-O0-NEXT: lxv vs0, 0(r3)
662 ; CHECK-O0-NEXT: # implicit-def: $vsrp20
663 ; CHECK-O0-NEXT: xxlor v9, vs0, vs0
664 ; CHECK-O0-NEXT: lxv vs0, 16(r3)
665 ; CHECK-O0-NEXT: xxlor v8, vs0, vs0
666 ; CHECK-O0-NEXT: lxv vs0, 32(r3)
667 ; CHECK-O0-NEXT: # implicit-def: $vsrp19
668 ; CHECK-O0-NEXT: xxlor v7, vs0, vs0
669 ; CHECK-O0-NEXT: lxv vs0, 48(r3)
670 ; CHECK-O0-NEXT: xxlor v6, vs0, vs0
671 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp40, 0
672 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
673 ; CHECK-O0-NEXT: xvf64gerpp wacc0, vsp32, vs0
674 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
675 ; CHECK-O0-NEXT: xvf64gerpp wacc0, vsp34, vs0
676 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
677 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
678 ; CHECK-O0-NEXT: stxv vs0, 48(r3)
679 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
680 ; CHECK-O0-NEXT: stxv vs0, 32(r3)
681 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
682 ; CHECK-O0-NEXT: stxv vs0, 16(r3)
683 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
684 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
685 ; CHECK-O0-NEXT: blr
686 ;
687 ; CHECK-O0-BE-LABEL: cmplx_xxmacc:
688 ; CHECK-O0-BE: # %bb.0: # %entry
689 ; CHECK-O0-BE-NEXT: vmr v4, v3
690 ; CHECK-O0-BE-NEXT: vmr v5, v2
691 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp16
692 ; CHECK-O0-BE-NEXT: vmr v1, v5
693 ; CHECK-O0-BE-NEXT: xxlor v2, v0, v0
694 ; CHECK-O0-BE-NEXT: xxlor v3, v1, v1
695 ; CHECK-O0-BE-NEXT: vmr v2, v4
696 ; CHECK-O0-BE-NEXT: vmr v0, v5
697 ; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)
698 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp20
699 ; CHECK-O0-BE-NEXT: xxlor v9, vs0, vs0
700 ; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)
701 ; CHECK-O0-BE-NEXT: xxlor v8, vs0, vs0
702 ; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)
703 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp19
704 ; CHECK-O0-BE-NEXT: xxlor v7, vs0, vs0
705 ; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
706 ; CHECK-O0-BE-NEXT: xxlor v6, vs0, vs0
707 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp40, 0
708 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
709 ; CHECK-O0-BE-NEXT: xvf64gerpp wacc0, vsp32, vs0
710 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
711 ; CHECK-O0-BE-NEXT: xvf64gerpp wacc0, vsp34, vs0
712 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
713 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
714 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
715 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
716 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)
717 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
718 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)
719 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
720 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
721 ; CHECK-O0-BE-NEXT: blr
722 ;
723 ; CHECK-AIX64-LABEL: cmplx_xxmacc:
724 ; CHECK-AIX64: # %bb.0: # %entry
725 ; CHECK-AIX64-NEXT: lxv 1, 48(3)
726 ; CHECK-AIX64-NEXT: lxv 7, 16(3)
727 ; CHECK-AIX64-NEXT: lxv 0, 32(3)
728 ; CHECK-AIX64-NEXT: lxv 6, 0(3)
729 ; CHECK-AIX64-NEXT: vmr 4, 3
730 ; CHECK-AIX64-NEXT: vmr 5, 2
731 ; CHECK-AIX64-NEXT: xxlor 2, 4, 4
732 ; CHECK-AIX64-NEXT: vmr 2, 5
733 ; CHECK-AIX64-NEXT: xxlor 3, 5, 5
734 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 38, 32, 0
735 ; CHECK-AIX64-NEXT: xvf64gerpp 0, 34, 5
736 ; CHECK-AIX64-NEXT: xvf64gerpp 0, 36, 4
737 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
738 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
739 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
740 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
741 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
742 ; CHECK-AIX64-NEXT: blr
743 ;
744 ; CHECK-AIX32-LABEL: cmplx_xxmacc:
745 ; CHECK-AIX32: # %bb.0: # %entry
746 ; CHECK-AIX32-NEXT: lxv 1, 48(3)
747 ; CHECK-AIX32-NEXT: lxv 7, 16(3)
748 ; CHECK-AIX32-NEXT: lxv 0, 32(3)
749 ; CHECK-AIX32-NEXT: lxv 6, 0(3)
750 ; CHECK-AIX32-NEXT: vmr 4, 3
751 ; CHECK-AIX32-NEXT: vmr 5, 2
752 ; CHECK-AIX32-NEXT: xxlor 2, 4, 4
753 ; CHECK-AIX32-NEXT: vmr 2, 5
754 ; CHECK-AIX32-NEXT: xxlor 3, 5, 5
755 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 38, 32, 0
756 ; CHECK-AIX32-NEXT: xvf64gerpp 0, 34, 5
757 ; CHECK-AIX32-NEXT: xvf64gerpp 0, 36, 4
758 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
759 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
760 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
761 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
762 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
763 ; CHECK-AIX32-NEXT: blr
764 entry:
765 %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc2, <16 x i8> %vc1)
766 %1 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc1, <16 x i8> %vc1)
767 %2 = load <512 x i1>, ptr %ptr1, align 64
768 %3 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %2)
769 %4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %3, <256 x i1> %1, <16 x i8> %vc1)
770 %5 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %4)
771 %6 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %5, <256 x i1> %0, <16 x i8> %vc2)
772 store <512 x i1> %6, ptr %ptr1, align 64
773 ret void
774 }
776 declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
777 declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
779 ; xxsetaccz
780 declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
781 define void @int_xxsetaccz(ptr %ptr) {
782 ; CHECK-LABEL: int_xxsetaccz:
783 ; CHECK: # %bb.0: # %entry
784 ; CHECK-NEXT: xxsetaccz wacc0
785 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
786 ; CHECK-NEXT: stxv v4, 48(r3)
787 ; CHECK-NEXT: stxv v5, 32(r3)
788 ; CHECK-NEXT: stxv v2, 16(r3)
789 ; CHECK-NEXT: stxv v3, 0(r3)
790 ; CHECK-NEXT: blr
791 ;
792 ; CHECK-BE-LABEL: int_xxsetaccz:
793 ; CHECK-BE: # %bb.0: # %entry
794 ; CHECK-BE-NEXT: xxsetaccz wacc0
795 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
796 ; CHECK-BE-NEXT: stxv v5, 48(r3)
797 ; CHECK-BE-NEXT: stxv v4, 32(r3)
798 ; CHECK-BE-NEXT: stxv v3, 16(r3)
799 ; CHECK-BE-NEXT: stxv v2, 0(r3)
800 ; CHECK-BE-NEXT: blr
801 ;
802 ; CHECK-O0-LABEL: int_xxsetaccz:
803 ; CHECK-O0: # %bb.0: # %entry
804 ; CHECK-O0-NEXT: xxsetaccz wacc0
805 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
806 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
807 ; CHECK-O0-NEXT: stxv vs0, 48(r3)
808 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
809 ; CHECK-O0-NEXT: stxv vs0, 32(r3)
810 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
811 ; CHECK-O0-NEXT: stxv vs0, 16(r3)
812 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
813 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
814 ; CHECK-O0-NEXT: blr
815 ;
816 ; CHECK-O0-BE-LABEL: int_xxsetaccz:
817 ; CHECK-O0-BE: # %bb.0: # %entry
818 ; CHECK-O0-BE-NEXT: xxsetaccz wacc0
819 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
820 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
821 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
822 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
823 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)
824 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
825 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)
826 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
827 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
828 ; CHECK-O0-BE-NEXT: blr
829 ;
830 ; CHECK-AIX64-LABEL: int_xxsetaccz:
831 ; CHECK-AIX64: # %bb.0: # %entry
832 ; CHECK-AIX64-NEXT: xxsetaccz 0
833 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
834 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
835 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
836 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
837 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
838 ; CHECK-AIX64-NEXT: blr
839 ;
840 ; CHECK-AIX32-LABEL: int_xxsetaccz:
841 ; CHECK-AIX32: # %bb.0: # %entry
842 ; CHECK-AIX32-NEXT: xxsetaccz 0
843 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
844 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
845 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
846 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
847 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
848 ; CHECK-AIX32-NEXT: blr
849 entry:
850 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
851 store <512 x i1> %0, ptr %ptr, align 64
852 ret void
853 }
855 ; disassemble_acc
856 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
857 define void @disass_acc(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
858 ; CHECK-LABEL: disass_acc:
859 ; CHECK: # %bb.0: # %entry
860 ; CHECK-NEXT: xxsetaccz wacc0
861 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
862 ; CHECK-NEXT: stxv v5, 0(r3)
863 ; CHECK-NEXT: stxv v4, 0(r4)
864 ; CHECK-NEXT: stxv v3, 0(r5)
865 ; CHECK-NEXT: stxv v2, 0(r6)
866 ; CHECK-NEXT: blr
867 ;
868 ; CHECK-BE-LABEL: disass_acc:
869 ; CHECK-BE: # %bb.0: # %entry
870 ; CHECK-BE-NEXT: xxsetaccz wacc0
871 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
872 ; CHECK-BE-NEXT: stxv v2, 0(r3)
873 ; CHECK-BE-NEXT: stxv v3, 0(r4)
874 ; CHECK-BE-NEXT: stxv v4, 0(r5)
875 ; CHECK-BE-NEXT: stxv v5, 0(r6)
876 ; CHECK-BE-NEXT: blr
877 ;
878 ; CHECK-O0-LABEL: disass_acc:
879 ; CHECK-O0: # %bb.0: # %entry
880 ; CHECK-O0-NEXT: xxsetaccz wacc0
881 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp32, vsp36, 0
882 ; CHECK-O0-NEXT: vmr v2, v0
883 ; CHECK-O0-NEXT: xxlor vs0, v1, v1
884 ; CHECK-O0-NEXT: xxlor vs1, v4, v4
885 ; CHECK-O0-NEXT: xxlor vs2, v5, v5
886 ; CHECK-O0-NEXT: stxv vs2, 0(r3)
887 ; CHECK-O0-NEXT: stxv vs1, 0(r4)
888 ; CHECK-O0-NEXT: stxv vs0, 0(r5)
889 ; CHECK-O0-NEXT: stxv v2, 0(r6)
890 ; CHECK-O0-NEXT: blr
891 ;
892 ; CHECK-O0-BE-LABEL: disass_acc:
893 ; CHECK-O0-BE: # %bb.0: # %entry
894 ; CHECK-O0-BE-NEXT: xxsetaccz wacc0
895 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp32, 0
896 ; CHECK-O0-BE-NEXT: vmr v2, v1
897 ; CHECK-O0-BE-NEXT: xxlor vs0, v0, v0
898 ; CHECK-O0-BE-NEXT: xxlor vs1, v5, v5
899 ; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4
900 ; CHECK-O0-BE-NEXT: stxv vs2, 0(r3)
901 ; CHECK-O0-BE-NEXT: stxv vs1, 0(r4)
902 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r5)
903 ; CHECK-O0-BE-NEXT: stxv v2, 0(r6)
904 ; CHECK-O0-BE-NEXT: blr
905 ;
906 ; CHECK-AIX64-LABEL: disass_acc:
907 ; CHECK-AIX64: # %bb.0: # %entry
908 ; CHECK-AIX64-NEXT: xxsetaccz 0
909 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
910 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
911 ; CHECK-AIX64-NEXT: stxv 3, 0(4)
912 ; CHECK-AIX64-NEXT: stxv 4, 0(5)
913 ; CHECK-AIX64-NEXT: stxv 5, 0(6)
914 ; CHECK-AIX64-NEXT: blr
915 ;
916 ; CHECK-AIX32-LABEL: disass_acc:
917 ; CHECK-AIX32: # %bb.0: # %entry
918 ; CHECK-AIX32-NEXT: xxsetaccz 0
919 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
920 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
921 ; CHECK-AIX32-NEXT: stxv 3, 0(4)
922 ; CHECK-AIX32-NEXT: stxv 4, 0(5)
923 ; CHECK-AIX32-NEXT: stxv 5, 0(6)
924 ; CHECK-AIX32-NEXT: blr
925 entry:
926 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
927 %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
928 %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
929 %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
930 %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
931 %5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
932 store <16 x i8> %2, ptr %ptr1, align 16
933 store <16 x i8> %3, ptr %ptr2, align 16
934 store <16 x i8> %4, ptr %ptr3, align 16
935 store <16 x i8> %5, ptr %ptr4, align 16
936 ret void
937 }
939 declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)
940 declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)
941 declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
943 define void @testcse(ptr %res, <16 x i8> %vc) {
944 ; CHECK-LABEL: testcse:
945 ; CHECK: # %bb.0: # %entry
946 ; CHECK-NEXT: xxsetaccz wacc0
947 ; CHECK-NEXT: xvf32gerpp wacc0, v2, v2
948 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
949 ; CHECK-NEXT: stxv v4, 48(r3)
950 ; CHECK-NEXT: stxv v5, 32(r3)
951 ; CHECK-NEXT: stxv v2, 16(r3)
952 ; CHECK-NEXT: stxv v3, 0(r3)
953 ; CHECK-NEXT: stxv v4, 112(r3)
954 ; CHECK-NEXT: stxv v5, 96(r3)
955 ; CHECK-NEXT: stxv v2, 80(r3)
956 ; CHECK-NEXT: stxv v3, 64(r3)
957 ; CHECK-NEXT: blr
958 ;
959 ; CHECK-BE-LABEL: testcse:
960 ; CHECK-BE: # %bb.0: # %entry
961 ; CHECK-BE-NEXT: xxsetaccz wacc0
962 ; CHECK-BE-NEXT: xvf32gerpp wacc0, v2, v2
963 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
964 ; CHECK-BE-NEXT: stxv v5, 48(r3)
965 ; CHECK-BE-NEXT: stxv v4, 32(r3)
966 ; CHECK-BE-NEXT: stxv v3, 16(r3)
967 ; CHECK-BE-NEXT: stxv v2, 0(r3)
968 ; CHECK-BE-NEXT: stxv v5, 112(r3)
969 ; CHECK-BE-NEXT: stxv v4, 96(r3)
970 ; CHECK-BE-NEXT: stxv v3, 80(r3)
971 ; CHECK-BE-NEXT: stxv v2, 64(r3)
972 ; CHECK-BE-NEXT: blr
973 ;
974 ; CHECK-O0-LABEL: testcse:
975 ; CHECK-O0: # %bb.0: # %entry
976 ; CHECK-O0-NEXT: xxsetaccz wacc0
977 ; CHECK-O0-NEXT: xvf32gerpp wacc0, v2, v2
978 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
979 ; CHECK-O0-NEXT: xxlor vs3, v4, v4
980 ; CHECK-O0-NEXT: stxv vs3, 48(r3)
981 ; CHECK-O0-NEXT: xxlor vs2, v5, v5
982 ; CHECK-O0-NEXT: stxv vs2, 32(r3)
983 ; CHECK-O0-NEXT: xxlor vs1, v2, v2
984 ; CHECK-O0-NEXT: stxv vs1, 16(r3)
985 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
986 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
987 ; CHECK-O0-NEXT: stxv vs3, 112(r3)
988 ; CHECK-O0-NEXT: stxv vs2, 96(r3)
989 ; CHECK-O0-NEXT: stxv vs1, 80(r3)
990 ; CHECK-O0-NEXT: stxv vs0, 64(r3)
991 ; CHECK-O0-NEXT: blr
992 ;
993 ; CHECK-O0-BE-LABEL: testcse:
994 ; CHECK-O0-BE: # %bb.0: # %entry
995 ; CHECK-O0-BE-NEXT: xxsetaccz wacc0
996 ; CHECK-O0-BE-NEXT: xvf32gerpp wacc0, v2, v2
997 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
998 ; CHECK-O0-BE-NEXT: xxlor vs3, v5, v5
999 ; CHECK-O0-BE-NEXT: stxv vs3, 48(r3)
1000 ; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4
1001 ; CHECK-O0-BE-NEXT: stxv vs2, 32(r3)
1002 ; CHECK-O0-BE-NEXT: xxlor vs1, v3, v3
1003 ; CHECK-O0-BE-NEXT: stxv vs1, 16(r3)
1004 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
1005 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
1006 ; CHECK-O0-BE-NEXT: stxv vs3, 112(r3)
1007 ; CHECK-O0-BE-NEXT: stxv vs2, 96(r3)
1008 ; CHECK-O0-BE-NEXT: stxv vs1, 80(r3)
1009 ; CHECK-O0-BE-NEXT: stxv vs0, 64(r3)
1010 ; CHECK-O0-BE-NEXT: blr
1011 ;
1012 ; CHECK-AIX64-LABEL: testcse:
1013 ; CHECK-AIX64: # %bb.0: # %entry
1014 ; CHECK-AIX64-NEXT: xxsetaccz 0
1015 ; CHECK-AIX64-NEXT: xvf32gerpp 0, 2, 2
1016 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
1017 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
1018 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
1019 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
1020 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
1021 ; CHECK-AIX64-NEXT: stxv 5, 112(3)
1022 ; CHECK-AIX64-NEXT: stxv 4, 96(3)
1023 ; CHECK-AIX64-NEXT: stxv 3, 80(3)
1024 ; CHECK-AIX64-NEXT: stxv 2, 64(3)
1025 ; CHECK-AIX64-NEXT: blr
1026 ;
1027 ; CHECK-AIX32-LABEL: testcse:
1028 ; CHECK-AIX32: # %bb.0: # %entry
1029 ; CHECK-AIX32-NEXT: xxsetaccz 0
1030 ; CHECK-AIX32-NEXT: xvf32gerpp 0, 2, 2
1031 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
1032 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
1033 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
1034 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
1035 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
1036 ; CHECK-AIX32-NEXT: stxv 5, 112(3)
1037 ; CHECK-AIX32-NEXT: stxv 4, 96(3)
1038 ; CHECK-AIX32-NEXT: stxv 3, 80(3)
1039 ; CHECK-AIX32-NEXT: stxv 2, 64(3)
1040 ; CHECK-AIX32-NEXT: blr
1041 entry:
1042 %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
1043 %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
1044 %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
1045 %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
1046 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 0
1047 %5 = getelementptr inbounds <512 x i1>, ptr %res, i64 1
1048 store <512 x i1> %2, ptr %4, align 64
1049 store <512 x i1> %3, ptr %5, align 64
1050 ret void
1051 }
1053 declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)
1054 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, ptr)
1056 ; Function Attrs: nofree nounwind
1057 define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {
1058 ; CHECK-LABEL: test_ldst_1:
1059 ; CHECK: # %bb.0: # %entry
1060 ; CHECK-NEXT: lxv v5, 0(r3)
1061 ; CHECK-NEXT: lxv v1, 32(r3)
1062 ; CHECK-NEXT: lxv v4, 16(r3)
1063 ; CHECK-NEXT: lxv v0, 48(r3)
1064 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
1065 ; CHECK-NEXT: plxvp vsp36, 8(r4), 0
1066 ; CHECK-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 0
1067 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
1068 ; CHECK-NEXT: stxv v4, 48(r7)
1069 ; CHECK-NEXT: stxv v5, 32(r7)
1070 ; CHECK-NEXT: stxv v2, 16(r7)
1071 ; CHECK-NEXT: stxv v3, 0(r7)
1072 ; CHECK-NEXT: blr
1073 ;
1074 ; CHECK-BE-LABEL: test_ldst_1:
1075 ; CHECK-BE: # %bb.0: # %entry
1076 ; CHECK-BE-NEXT: lxv v5, 48(r3)
1077 ; CHECK-BE-NEXT: lxv v1, 16(r3)
1078 ; CHECK-BE-NEXT: lxv v4, 32(r3)
1079 ; CHECK-BE-NEXT: lxv v0, 0(r3)
1080 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
1081 ; CHECK-BE-NEXT: plxvp vsp36, 8(r4), 0
1082 ; CHECK-BE-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 0
1083 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
1084 ; CHECK-BE-NEXT: stxv v5, 48(r7)
1085 ; CHECK-BE-NEXT: stxv v4, 32(r7)
1086 ; CHECK-BE-NEXT: stxv v3, 16(r7)
1087 ; CHECK-BE-NEXT: stxv v2, 0(r7)
1088 ; CHECK-BE-NEXT: blr
1089 ;
1090 ; CHECK-O0-LABEL: test_ldst_1:
1091 ; CHECK-O0: # %bb.0: # %entry
1092 ; CHECK-O0-NEXT: vmr v4, v2
1093 ; CHECK-O0-NEXT: lxv vs0, 0(r3)
1094 ; CHECK-O0-NEXT: # implicit-def: $vsrp16
1095 ; CHECK-O0-NEXT: xxlor v1, vs0, vs0
1096 ; CHECK-O0-NEXT: lxv vs0, 16(r3)
1097 ; CHECK-O0-NEXT: xxlor v0, vs0, vs0
1098 ; CHECK-O0-NEXT: lxv vs0, 32(r3)
1099 ; CHECK-O0-NEXT: # implicit-def: $vsrp17
1100 ; CHECK-O0-NEXT: xxlor v3, vs0, vs0
1101 ; CHECK-O0-NEXT: lxv vs0, 48(r3)
1102 ; CHECK-O0-NEXT: xxlor v2, vs0, vs0
1103 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp32, 0
1104 ; CHECK-O0-NEXT: plxvp vsp34, 8(r4), 0
1105 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
1106 ; CHECK-O0-NEXT: pmxvf64gernn wacc0, vsp34, vs0, 0, 0
1107 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
1108 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
1109 ; CHECK-O0-NEXT: stxv vs0, 48(r7)
1110 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
1111 ; CHECK-O0-NEXT: stxv vs0, 32(r7)
1112 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
1113 ; CHECK-O0-NEXT: stxv vs0, 16(r7)
1114 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
1115 ; CHECK-O0-NEXT: stxv vs0, 0(r7)
1116 ; CHECK-O0-NEXT: blr
1117 ;
1118 ; CHECK-O0-BE-LABEL: test_ldst_1:
1119 ; CHECK-O0-BE: # %bb.0: # %entry
1120 ; CHECK-O0-BE-NEXT: vmr v4, v2
1121 ; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)
1122 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp16
1123 ; CHECK-O0-BE-NEXT: xxlor v1, vs0, vs0
1124 ; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)
1125 ; CHECK-O0-BE-NEXT: xxlor v0, vs0, vs0
1126 ; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)
1127 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17
1128 ; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0
1129 ; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
1130 ; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0
1131 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp32, 0
1132 ; CHECK-O0-BE-NEXT: plxvp vsp34, 8(r4), 0
1133 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
1134 ; CHECK-O0-BE-NEXT: pmxvf64gernn wacc0, vsp34, vs0, 0, 0
1135 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
1136 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
1137 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)
1138 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
1139 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)
1140 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
1141 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)
1142 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
1143 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)
1144 ; CHECK-O0-BE-NEXT: blr
1145 ;
1146 ; CHECK-AIX64-LABEL: test_ldst_1:
1147 ; CHECK-AIX64: # %bb.0: # %entry
1148 ; CHECK-AIX64-NEXT: lxv 5, 48(3)
1149 ; CHECK-AIX64-NEXT: lxv 1, 16(3)
1150 ; CHECK-AIX64-NEXT: lxv 4, 32(3)
1151 ; CHECK-AIX64-NEXT: lxv 0, 0(3)
1152 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 32, 36, 0
1153 ; CHECK-AIX64-NEXT: plxvp 36, 8(4), 0
1154 ; CHECK-AIX64-NEXT: pmxvf64gernn 0, 36, 2, 0, 0
1155 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
1156 ; CHECK-AIX64-NEXT: stxv 5, 48(5)
1157 ; CHECK-AIX64-NEXT: stxv 4, 32(5)
1158 ; CHECK-AIX64-NEXT: stxv 3, 16(5)
1159 ; CHECK-AIX64-NEXT: stxv 2, 0(5)
1160 ; CHECK-AIX64-NEXT: blr
1161 ;
1162 ; CHECK-AIX32-LABEL: test_ldst_1:
1163 ; CHECK-AIX32: # %bb.0: # %entry
1164 ; CHECK-AIX32-NEXT: lxv 5, 48(3)
1165 ; CHECK-AIX32-NEXT: lxv 1, 16(3)
1166 ; CHECK-AIX32-NEXT: lxv 4, 32(3)
1167 ; CHECK-AIX32-NEXT: lxv 0, 0(3)
1168 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 32, 36, 0
1169 ; CHECK-AIX32-NEXT: plxvp 36, 8(4), 0
1170 ; CHECK-AIX32-NEXT: pmxvf64gernn 0, 36, 2, 0, 0
1171 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
1172 ; CHECK-AIX32-NEXT: stxv 5, 48(5)
1173 ; CHECK-AIX32-NEXT: stxv 4, 32(5)
1174 ; CHECK-AIX32-NEXT: stxv 3, 16(5)
1175 ; CHECK-AIX32-NEXT: stxv 2, 0(5)
1176 ; CHECK-AIX32-NEXT: blr
1177 entry:
1178 %0 = load <512 x i1>, ptr %vqp, align 64
1179 %1 = getelementptr i8, ptr %vpp, i64 8
1180 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %1)
1181 %3 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %0, <256 x i1> %2, <16 x i8> %vc, i32 0, i32 0)
1182 store <512 x i1> %3, ptr %resp, align 64
1183 ret void
1184 }
1186 declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
1187 declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)