| blob | 7a09d5a5e8bb2e241c78f389a91ca9ba23b3c6dc |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6 ; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-BE
9 define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
10 ; CHECK-LABEL: test8x32:
11 ; CHECK: # %bb.0:
12 ; CHECK-NEXT: rldimi r3, r4, 32, 0
13 ; CHECK-NEXT: rldimi r5, r6, 32, 0
14 ; CHECK-NEXT: mtfprd f0, r3
15 ; CHECK-NEXT: mtfprd f1, r5
16 ; CHECK-NEXT: rldimi r7, r8, 32, 0
17 ; CHECK-NEXT: rldimi r9, r10, 32, 0
18 ; CHECK-NEXT: mtfprd f2, r7
19 ; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha
20 ; CHECK-NEXT: addi r3, r3, .LCPI0_0@toc@l
21 ; CHECK-NEXT: xxmrghd v2, vs1, vs0
22 ; CHECK-NEXT: mtfprd f0, r9
23 ; CHECK-NEXT: xxmrghd v3, vs0, vs2
24 ; CHECK-NEXT: lxvd2x vs0, 0, r3
25 ; CHECK-NEXT: xxswapd v4, vs0
26 ; CHECK-NEXT: vperm v2, v3, v2, v4
27 ; CHECK-NEXT: blr
28 ;
29 ; CHECK-BE-LABEL: test8x32:
30 ; CHECK-BE: # %bb.0:
31 ; CHECK-BE-NEXT: stw r10, -80(r1)
32 ; CHECK-BE-NEXT: stw r9, -96(r1)
33 ; CHECK-BE-NEXT: stw r8, -112(r1)
34 ; CHECK-BE-NEXT: stw r7, -128(r1)
35 ; CHECK-BE-NEXT: stw r6, -16(r1)
36 ; CHECK-BE-NEXT: stw r5, -32(r1)
37 ; CHECK-BE-NEXT: stw r4, -48(r1)
38 ; CHECK-BE-NEXT: stw r3, -64(r1)
39 ; CHECK-BE-NEXT: addi r3, r1, -80
40 ; CHECK-BE-NEXT: lxvw4x vs0, 0, r3
41 ; CHECK-BE-NEXT: addi r3, r1, -96
42 ; CHECK-BE-NEXT: lxvw4x vs1, 0, r3
43 ; CHECK-BE-NEXT: addi r3, r1, -112
44 ; CHECK-BE-NEXT: lxvw4x vs2, 0, r3
45 ; CHECK-BE-NEXT: addi r3, r1, -128
46 ; CHECK-BE-NEXT: lxvw4x vs3, 0, r3
47 ; CHECK-BE-NEXT: addi r3, r1, -16
48 ; CHECK-BE-NEXT: lxvw4x vs4, 0, r3
49 ; CHECK-BE-NEXT: addi r3, r1, -32
50 ; CHECK-BE-NEXT: lxvw4x vs5, 0, r3
51 ; CHECK-BE-NEXT: addi r3, r1, -48
52 ; CHECK-BE-NEXT: lxvw4x vs6, 0, r3
53 ; CHECK-BE-NEXT: addi r3, r1, -64
54 ; CHECK-BE-NEXT: lxvw4x vs7, 0, r3
55 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
56 ; CHECK-BE-NEXT: xxmrghw vs0, vs1, vs0
57 ; CHECK-BE-NEXT: xxmrghw vs1, vs3, vs2
58 ; CHECK-BE-NEXT: xxmrghw vs2, vs5, vs4
59 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
60 ; CHECK-BE-NEXT: xxmrghd v3, vs1, vs0
61 ; CHECK-BE-NEXT: lxvw4x v2, 0, r3
62 ; CHECK-BE-NEXT: xxmrghw vs3, vs7, vs6
63 ; CHECK-BE-NEXT: xxmrghd v4, vs3, vs2
64 ; CHECK-BE-NEXT: vperm v2, v4, v3, v2
65 ; CHECK-BE-NEXT: blr
66 %v10 = insertelement <8 x i32> undef, i32 %i1, i32 0
67 %v11 = insertelement <8 x i32> %v10, i32 %i2, i32 1
68 %v12 = insertelement <8 x i32> %v11, i32 %i3, i32 2
69 %v13 = insertelement <8 x i32> %v12, i32 %i4, i32 3
70 %v14 = insertelement <8 x i32> %v13, i32 %i5, i32 4
71 %v15 = insertelement <8 x i32> %v14, i32 %i6, i32 5
72 %v16 = insertelement <8 x i32> %v15, i32 %i7, i32 6
73 %v17 = insertelement <8 x i32> %v16, i32 %i8, i32 7
74 %v2 = trunc <8 x i32> %v17 to <8 x i8>
75 ret <8 x i8> %v2
76 }
78 define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) {
79 ; CHECK-LABEL: test4x64:
80 ; CHECK: # %bb.0:
81 ; CHECK-NEXT: mtfprd f0, r5
82 ; CHECK-NEXT: mtfprd f1, r6
83 ; CHECK-NEXT: xxmrghd v2, vs1, vs0
84 ; CHECK-NEXT: mtfprd f0, r3
85 ; CHECK-NEXT: mtfprd f1, r4
86 ; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
87 ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
88 ; CHECK-NEXT: xxmrghd v3, vs1, vs0
89 ; CHECK-NEXT: lxvd2x vs0, 0, r3
90 ; CHECK-NEXT: xxswapd v4, vs0
91 ; CHECK-NEXT: vperm v2, v2, v3, v4
92 ; CHECK-NEXT: blr
93 ;
94 ; CHECK-BE-LABEL: test4x64:
95 ; CHECK-BE: # %bb.0:
96 ; CHECK-BE-NEXT: std r6, -8(r1)
97 ; CHECK-BE-NEXT: std r5, -16(r1)
98 ; CHECK-BE-NEXT: std r4, -24(r1)
99 ; CHECK-BE-NEXT: std r3, -32(r1)
100 ; CHECK-BE-NEXT: addi r3, r1, -32
101 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
102 ; CHECK-BE-NEXT: addi r7, r1, -16
103 ; CHECK-BE-NEXT: lxvd2x v3, 0, r3
104 ; CHECK-BE-NEXT: addi r3, r4, .LCPI1_0@toc@l
105 ; CHECK-BE-NEXT: lxvd2x v2, 0, r7
106 ; CHECK-BE-NEXT: lxvw4x v4, 0, r3
107 ; CHECK-BE-NEXT: vperm v2, v3, v2, v4
108 ; CHECK-BE-NEXT: blr
109 %v10 = insertelement <4 x i64> undef, i64 %i1, i32 0
110 %v11 = insertelement <4 x i64> %v10, i64 %i2, i32 1
111 %v12 = insertelement <4 x i64> %v11, i64 %i3, i32 2
112 %v13 = insertelement <4 x i64> %v12, i64 %i4, i32 3
113 %v2 = trunc <4 x i64> %v13 to <4 x i16>
114 ret <4 x i16> %v2
115 }
117 define dso_local <8 x i16> @test8x24(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
118 ; CHECK-LABEL: test8x24:
119 ; CHECK: # %bb.0:
120 ; CHECK-NEXT: mtvsrd v2, r3
121 ; CHECK-NEXT: mtvsrd v3, r4
122 ; CHECK-NEXT: mtvsrd v4, r5
123 ; CHECK-NEXT: mtvsrd v5, r6
124 ; CHECK-NEXT: mtvsrd v0, r7
125 ; CHECK-NEXT: vmrghh v2, v3, v2
126 ; CHECK-NEXT: mtvsrd v3, r8
127 ; CHECK-NEXT: vmrghh v4, v5, v4
128 ; CHECK-NEXT: mtvsrd v5, r9
129 ; CHECK-NEXT: xxmrglw vs0, v4, v2
130 ; CHECK-NEXT: vmrghh v3, v3, v0
131 ; CHECK-NEXT: mtvsrd v0, r10
132 ; CHECK-NEXT: vmrghh v5, v0, v5
133 ; CHECK-NEXT: xxmrglw vs1, v5, v3
134 ; CHECK-NEXT: xxmrgld v2, vs1, vs0
135 ; CHECK-NEXT: blr
136 ;
137 ; CHECK-BE-LABEL: test8x24:
138 ; CHECK-BE: # %bb.0:
139 ; CHECK-BE-NEXT: sth r10, -16(r1)
140 ; CHECK-BE-NEXT: sth r9, -32(r1)
141 ; CHECK-BE-NEXT: sth r8, -48(r1)
142 ; CHECK-BE-NEXT: sth r7, -64(r1)
143 ; CHECK-BE-NEXT: sth r6, -80(r1)
144 ; CHECK-BE-NEXT: sth r5, -96(r1)
145 ; CHECK-BE-NEXT: sth r4, -112(r1)
146 ; CHECK-BE-NEXT: sth r3, -128(r1)
147 ; CHECK-BE-NEXT: addi r3, r1, -16
148 ; CHECK-BE-NEXT: lxvw4x v2, 0, r3
149 ; CHECK-BE-NEXT: addi r3, r1, -32
150 ; CHECK-BE-NEXT: lxvw4x v3, 0, r3
151 ; CHECK-BE-NEXT: addi r3, r1, -48
152 ; CHECK-BE-NEXT: lxvw4x v4, 0, r3
153 ; CHECK-BE-NEXT: addi r3, r1, -64
154 ; CHECK-BE-NEXT: lxvw4x v5, 0, r3
155 ; CHECK-BE-NEXT: addi r3, r1, -80
156 ; CHECK-BE-NEXT: lxvw4x v0, 0, r3
157 ; CHECK-BE-NEXT: addi r3, r1, -96
158 ; CHECK-BE-NEXT: lxvw4x v1, 0, r3
159 ; CHECK-BE-NEXT: addi r3, r1, -112
160 ; CHECK-BE-NEXT: lxvw4x v6, 0, r3
161 ; CHECK-BE-NEXT: addi r3, r1, -128
162 ; CHECK-BE-NEXT: lxvw4x v7, 0, r3
163 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
164 ; CHECK-BE-NEXT: vmrghh v3, v5, v4
165 ; CHECK-BE-NEXT: vmrghh v4, v1, v0
166 ; CHECK-BE-NEXT: xxmrghw vs0, v3, v2
167 ; CHECK-BE-NEXT: vmrghh v5, v7, v6
168 ; CHECK-BE-NEXT: xxmrghw vs1, v5, v4
169 ; CHECK-BE-NEXT: xxmrghd v2, vs1, vs0
170 ; CHECK-BE-NEXT: blr
171 %i11 = trunc i32 %i1 to i24
172 %i21 = trunc i32 %i2 to i24
173 %i31 = trunc i32 %i3 to i24
174 %i41 = trunc i32 %i4 to i24
175 %i51 = trunc i32 %i5 to i24
176 %i61 = trunc i32 %i6 to i24
177 %i71 = trunc i32 %i7 to i24
178 %i81 = trunc i32 %i8 to i24
179 %v10 = insertelement <8 x i24> undef, i24 %i11, i32 0
180 %v11 = insertelement <8 x i24> %v10, i24 %i21, i32 1
181 %v12 = insertelement <8 x i24> %v11, i24 %i31, i32 2
182 %v13 = insertelement <8 x i24> %v12, i24 %i41, i32 3
183 %v14 = insertelement <8 x i24> %v13, i24 %i51, i32 4
184 %v15 = insertelement <8 x i24> %v14, i24 %i61, i32 5
185 %v16 = insertelement <8 x i24> %v15, i24 %i71, i32 6
186 %v17 = insertelement <8 x i24> %v16, i24 %i81, i32 7
187 %v2 = trunc <8 x i24> %v17 to <8 x i16>
188 ret <8 x i16> %v2
189 }