| blob | 1cd78ecd5cede4a21f7196cd96650d1e83cf9f54 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: xxswapd vs0, v2
16 ; CHECK-P8-NEXT: xscvdpuxws f1, v2
17 ; CHECK-P8-NEXT: xscvdpuxws f0, f0
18 ; CHECK-P8-NEXT: xxmrghw vs0, vs1, vs0
19 ; CHECK-P8-NEXT: xxswapd vs0, vs0
20 ; CHECK-P8-NEXT: mffprd r3, f0
21 ; CHECK-P8-NEXT: blr
22 ;
23 ; CHECK-P9-LABEL: test2elt:
24 ; CHECK-P9: # %bb.0: # %entry
25 ; CHECK-P9-NEXT: xxswapd vs1, v2
26 ; CHECK-P9-NEXT: xscvdpuxws f0, v2
27 ; CHECK-P9-NEXT: xscvdpuxws f1, f1
28 ; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs1
29 ; CHECK-P9-NEXT: mfvsrld r3, vs0
30 ; CHECK-P9-NEXT: blr
31 ;
32 ; CHECK-BE-LABEL: test2elt:
33 ; CHECK-BE: # %bb.0: # %entry
34 ; CHECK-BE-NEXT: xxswapd vs0, v2
35 ; CHECK-BE-NEXT: xscvdpuxws v3, v2
36 ; CHECK-BE-NEXT: xscvdpuxws v2, f0
37 ; CHECK-BE-NEXT: vmrgow v2, v3, v2
38 ; CHECK-BE-NEXT: mfvsrd r3, v2
39 ; CHECK-BE-NEXT: blr
40 entry:
41 %0 = fptoui <2 x double> %a to <2 x i32>
42 %1 = bitcast <2 x i32> %0 to i64
43 ret i64 %1
44 }
46 define <4 x i32> @test4elt(ptr nocapture readonly) local_unnamed_addr #1 {
47 ; CHECK-P8-LABEL: test4elt:
48 ; CHECK-P8: # %bb.0: # %entry
49 ; CHECK-P8-NEXT: li r4, 16
50 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
51 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
52 ; CHECK-P8-NEXT: xxswapd vs1, vs1
53 ; CHECK-P8-NEXT: xxswapd vs0, vs0
54 ; CHECK-P8-NEXT: xxmrgld vs2, vs0, vs1
55 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs1
56 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs2
57 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs0
58 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
59 ; CHECK-P8-NEXT: blr
60 ;
61 ; CHECK-P9-LABEL: test4elt:
62 ; CHECK-P9: # %bb.0: # %entry
63 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
64 ; CHECK-P9-NEXT: lxv vs1, 16(r3)
65 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
66 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
67 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs2
68 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs0
69 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
70 ; CHECK-P9-NEXT: blr
71 ;
72 ; CHECK-BE-LABEL: test4elt:
73 ; CHECK-BE: # %bb.0: # %entry
74 ; CHECK-BE-NEXT: lxv vs0, 16(r3)
75 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
76 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
77 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
78 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs2
79 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs0
80 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
81 ; CHECK-BE-NEXT: blr
82 entry:
83 %a = load <4 x double>, ptr %0, align 32
84 %1 = fptoui <4 x double> %a to <4 x i32>
85 ret <4 x i32> %1
86 }
88 define void @test8elt(ptr noalias nocapture sret(<8 x i32>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
89 ; CHECK-P8-LABEL: test8elt:
90 ; CHECK-P8: # %bb.0: # %entry
91 ; CHECK-P8-NEXT: li r6, 32
92 ; CHECK-P8-NEXT: li r5, 16
93 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
94 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
95 ; CHECK-P8-NEXT: li r6, 48
96 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
97 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
98 ; CHECK-P8-NEXT: xxmrghd vs4, vs1, vs2
99 ; CHECK-P8-NEXT: xxmrgld vs1, vs1, vs2
100 ; CHECK-P8-NEXT: xxmrghd vs2, vs3, vs0
101 ; CHECK-P8-NEXT: xxmrgld vs0, vs3, vs0
102 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs4
103 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs1
104 ; CHECK-P8-NEXT: xvcvdpuxws v4, vs0
105 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
106 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs2
107 ; CHECK-P8-NEXT: stxvd2x v2, r3, r5
108 ; CHECK-P8-NEXT: vmrgew v3, v4, v3
109 ; CHECK-P8-NEXT: stxvd2x v3, 0, r3
110 ; CHECK-P8-NEXT: blr
111 ;
112 ; CHECK-P9-LABEL: test8elt:
113 ; CHECK-P9: # %bb.0: # %entry
114 ; CHECK-P9-NEXT: lxv vs2, 0(r4)
115 ; CHECK-P9-NEXT: lxv vs3, 16(r4)
116 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
117 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
118 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
119 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
120 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs4
121 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
122 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
123 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
124 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs0
125 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
126 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs2
127 ; CHECK-P9-NEXT: stxv v2, 0(r3)
128 ; CHECK-P9-NEXT: vmrgew v3, v4, v3
129 ; CHECK-P9-NEXT: stxv v3, 16(r3)
130 ; CHECK-P9-NEXT: blr
131 ;
132 ; CHECK-BE-LABEL: test8elt:
133 ; CHECK-BE: # %bb.0: # %entry
134 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
135 ; CHECK-BE-NEXT: lxv vs3, 0(r4)
136 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
137 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
138 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
139 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
140 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs4
141 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
142 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
143 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
144 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs0
145 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
146 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs2
147 ; CHECK-BE-NEXT: stxv v2, 0(r3)
148 ; CHECK-BE-NEXT: vmrgew v3, v4, v3
149 ; CHECK-BE-NEXT: stxv v3, 16(r3)
150 ; CHECK-BE-NEXT: blr
151 entry:
152 %a = load <8 x double>, ptr %0, align 64
153 %1 = fptoui <8 x double> %a to <8 x i32>
154 store <8 x i32> %1, ptr %agg.result, align 32
155 ret void
156 }
158 define void @test16elt(ptr noalias nocapture sret(<16 x i32>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
159 ; CHECK-P8-LABEL: test16elt:
160 ; CHECK-P8: # %bb.0: # %entry
161 ; CHECK-P8-NEXT: li r6, 96
162 ; CHECK-P8-NEXT: li r7, 112
163 ; CHECK-P8-NEXT: li r5, 16
164 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
165 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r6
166 ; CHECK-P8-NEXT: li r6, 64
167 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r7
168 ; CHECK-P8-NEXT: li r7, 80
169 ; CHECK-P8-NEXT: lxvd2x vs4, r4, r5
170 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
171 ; CHECK-P8-NEXT: li r6, 32
172 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r7
173 ; CHECK-P8-NEXT: li r7, 48
174 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r6
175 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r7
176 ; CHECK-P8-NEXT: xxmrghd vs8, vs5, vs6
177 ; CHECK-P8-NEXT: xxmrgld vs5, vs5, vs6
178 ; CHECK-P8-NEXT: xxmrghd vs6, vs2, vs3
179 ; CHECK-P8-NEXT: xxmrgld vs2, vs2, vs3
180 ; CHECK-P8-NEXT: xxmrghd vs3, vs0, vs1
181 ; CHECK-P8-NEXT: xxmrgld vs0, vs0, vs1
182 ; CHECK-P8-NEXT: xxmrghd vs1, vs7, vs4
183 ; CHECK-P8-NEXT: xxmrgld vs4, vs7, vs4
184 ; CHECK-P8-NEXT: xvcvdpuxws v2, vs8
185 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs5
186 ; CHECK-P8-NEXT: xvcvdpuxws v4, vs6
187 ; CHECK-P8-NEXT: xvcvdpuxws v5, vs2
188 ; CHECK-P8-NEXT: xvcvdpuxws v0, vs3
189 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
190 ; CHECK-P8-NEXT: xvcvdpuxws v3, vs0
191 ; CHECK-P8-NEXT: vmrgew v4, v5, v4
192 ; CHECK-P8-NEXT: xvcvdpuxws v5, vs1
193 ; CHECK-P8-NEXT: vmrgew v3, v3, v0
194 ; CHECK-P8-NEXT: xvcvdpuxws v0, vs4
195 ; CHECK-P8-NEXT: stxvd2x v3, r3, r7
196 ; CHECK-P8-NEXT: stxvd2x v4, r3, r6
197 ; CHECK-P8-NEXT: stxvd2x v2, r3, r5
198 ; CHECK-P8-NEXT: vmrgew v5, v0, v5
199 ; CHECK-P8-NEXT: stxvd2x v5, 0, r3
200 ; CHECK-P8-NEXT: blr
201 ;
202 ; CHECK-P9-LABEL: test16elt:
203 ; CHECK-P9: # %bb.0: # %entry
204 ; CHECK-P9-NEXT: lxv vs6, 0(r4)
205 ; CHECK-P9-NEXT: lxv vs7, 16(r4)
206 ; CHECK-P9-NEXT: lxv vs4, 32(r4)
207 ; CHECK-P9-NEXT: lxv vs5, 48(r4)
208 ; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
209 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
210 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
211 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
212 ; CHECK-P9-NEXT: lxv vs2, 64(r4)
213 ; CHECK-P9-NEXT: lxv vs3, 80(r4)
214 ; CHECK-P9-NEXT: lxv vs0, 96(r4)
215 ; CHECK-P9-NEXT: lxv vs1, 112(r4)
216 ; CHECK-P9-NEXT: xvcvdpuxws v2, vs8
217 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs6
218 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs7
219 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
220 ; CHECK-P9-NEXT: xvcvdpuxws v3, vs4
221 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
222 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
223 ; CHECK-P9-NEXT: stxv v2, 0(r3)
224 ; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
225 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
226 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
227 ; CHECK-P9-NEXT: xvcvdpuxws v0, vs0
228 ; CHECK-P9-NEXT: vmrgew v3, v3, v4
229 ; CHECK-P9-NEXT: xvcvdpuxws v4, vs4
230 ; CHECK-P9-NEXT: stxv v3, 16(r3)
231 ; CHECK-P9-NEXT: vmrgew v4, v5, v4
232 ; CHECK-P9-NEXT: stxv v4, 32(r3)
233 ; CHECK-P9-NEXT: xvcvdpuxws v5, vs2
234 ; CHECK-P9-NEXT: vmrgew v5, v0, v5
235 ; CHECK-P9-NEXT: stxv v5, 48(r3)
236 ; CHECK-P9-NEXT: blr
237 ;
238 ; CHECK-BE-LABEL: test16elt:
239 ; CHECK-BE: # %bb.0: # %entry
240 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
241 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
242 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
243 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
244 ; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
245 ; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
246 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
247 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
248 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
249 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
250 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
251 ; CHECK-BE-NEXT: lxv vs1, 96(r4)
252 ; CHECK-BE-NEXT: xvcvdpuxws v2, vs8
253 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs6
254 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs7
255 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
256 ; CHECK-BE-NEXT: xvcvdpuxws v3, vs4
257 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
258 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
259 ; CHECK-BE-NEXT: stxv v2, 0(r3)
260 ; CHECK-BE-NEXT: xvcvdpuxws v5, vs2
261 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
262 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
263 ; CHECK-BE-NEXT: xvcvdpuxws v0, vs0
264 ; CHECK-BE-NEXT: vmrgew v3, v3, v4
265 ; CHECK-BE-NEXT: xvcvdpuxws v4, vs4
266 ; CHECK-BE-NEXT: stxv v3, 16(r3)
267 ; CHECK-BE-NEXT: vmrgew v4, v5, v4
268 ; CHECK-BE-NEXT: stxv v4, 32(r3)
269 ; CHECK-BE-NEXT: xvcvdpuxws v5, vs2
270 ; CHECK-BE-NEXT: vmrgew v5, v0, v5
271 ; CHECK-BE-NEXT: stxv v5, 48(r3)
272 ; CHECK-BE-NEXT: blr
273 entry:
274 %a = load <16 x double>, ptr %0, align 128
275 %1 = fptoui <16 x double> %a to <16 x i32>
276 store <16 x i32> %1, ptr %agg.result, align 64
277 ret void
278 }
280 define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
281 ; CHECK-P8-LABEL: test2elt_signed:
282 ; CHECK-P8: # %bb.0: # %entry
283 ; CHECK-P8-NEXT: xxswapd vs0, v2
284 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
285 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
286 ; CHECK-P8-NEXT: xxmrghw vs0, vs1, vs0
287 ; CHECK-P8-NEXT: xxswapd vs0, vs0
288 ; CHECK-P8-NEXT: mffprd r3, f0
289 ; CHECK-P8-NEXT: blr
290 ;
291 ; CHECK-P9-LABEL: test2elt_signed:
292 ; CHECK-P9: # %bb.0: # %entry
293 ; CHECK-P9-NEXT: xxswapd vs1, v2
294 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
295 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
296 ; CHECK-P9-NEXT: xxmrghw vs0, vs0, vs1
297 ; CHECK-P9-NEXT: mfvsrld r3, vs0
298 ; CHECK-P9-NEXT: blr
299 ;
300 ; CHECK-BE-LABEL: test2elt_signed:
301 ; CHECK-BE: # %bb.0: # %entry
302 ; CHECK-BE-NEXT: xxswapd vs0, v2
303 ; CHECK-BE-NEXT: xscvdpsxws v3, v2
304 ; CHECK-BE-NEXT: xscvdpsxws v2, f0
305 ; CHECK-BE-NEXT: vmrgow v2, v3, v2
306 ; CHECK-BE-NEXT: mfvsrd r3, v2
307 ; CHECK-BE-NEXT: blr
308 entry:
309 %0 = fptosi <2 x double> %a to <2 x i32>
310 %1 = bitcast <2 x i32> %0 to i64
311 ret i64 %1
312 }
314 define <4 x i32> @test4elt_signed(ptr nocapture readonly) local_unnamed_addr #1 {
315 ; CHECK-P8-LABEL: test4elt_signed:
316 ; CHECK-P8: # %bb.0: # %entry
317 ; CHECK-P8-NEXT: li r4, 16
318 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r3
319 ; CHECK-P8-NEXT: lxvd2x vs0, r3, r4
320 ; CHECK-P8-NEXT: xxswapd vs1, vs1
321 ; CHECK-P8-NEXT: xxswapd vs0, vs0
322 ; CHECK-P8-NEXT: xxmrgld vs2, vs0, vs1
323 ; CHECK-P8-NEXT: xxmrghd vs0, vs0, vs1
324 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs2
325 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs0
326 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
327 ; CHECK-P8-NEXT: blr
328 ;
329 ; CHECK-P9-LABEL: test4elt_signed:
330 ; CHECK-P9: # %bb.0: # %entry
331 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
332 ; CHECK-P9-NEXT: lxv vs1, 16(r3)
333 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
334 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
335 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs2
336 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs0
337 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
338 ; CHECK-P9-NEXT: blr
339 ;
340 ; CHECK-BE-LABEL: test4elt_signed:
341 ; CHECK-BE: # %bb.0: # %entry
342 ; CHECK-BE-NEXT: lxv vs0, 16(r3)
343 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
344 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
345 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
346 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs2
347 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs0
348 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
349 ; CHECK-BE-NEXT: blr
350 entry:
351 %a = load <4 x double>, ptr %0, align 32
352 %1 = fptosi <4 x double> %a to <4 x i32>
353 ret <4 x i32> %1
354 }
356 define void @test8elt_signed(ptr noalias nocapture sret(<8 x i32>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
357 ; CHECK-P8-LABEL: test8elt_signed:
358 ; CHECK-P8: # %bb.0: # %entry
359 ; CHECK-P8-NEXT: li r6, 32
360 ; CHECK-P8-NEXT: li r5, 16
361 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
362 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r6
363 ; CHECK-P8-NEXT: li r6, 48
364 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
365 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
366 ; CHECK-P8-NEXT: xxmrghd vs4, vs1, vs2
367 ; CHECK-P8-NEXT: xxmrgld vs1, vs1, vs2
368 ; CHECK-P8-NEXT: xxmrghd vs2, vs3, vs0
369 ; CHECK-P8-NEXT: xxmrgld vs0, vs3, vs0
370 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs4
371 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs1
372 ; CHECK-P8-NEXT: xvcvdpsxws v4, vs0
373 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
374 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs2
375 ; CHECK-P8-NEXT: stxvd2x v2, r3, r5
376 ; CHECK-P8-NEXT: vmrgew v3, v4, v3
377 ; CHECK-P8-NEXT: stxvd2x v3, 0, r3
378 ; CHECK-P8-NEXT: blr
379 ;
380 ; CHECK-P9-LABEL: test8elt_signed:
381 ; CHECK-P9: # %bb.0: # %entry
382 ; CHECK-P9-NEXT: lxv vs2, 0(r4)
383 ; CHECK-P9-NEXT: lxv vs3, 16(r4)
384 ; CHECK-P9-NEXT: lxv vs0, 32(r4)
385 ; CHECK-P9-NEXT: lxv vs1, 48(r4)
386 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
387 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
388 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs4
389 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
390 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
391 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
392 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs0
393 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
394 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs2
395 ; CHECK-P9-NEXT: stxv v2, 0(r3)
396 ; CHECK-P9-NEXT: vmrgew v3, v4, v3
397 ; CHECK-P9-NEXT: stxv v3, 16(r3)
398 ; CHECK-P9-NEXT: blr
399 ;
400 ; CHECK-BE-LABEL: test8elt_signed:
401 ; CHECK-BE: # %bb.0: # %entry
402 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
403 ; CHECK-BE-NEXT: lxv vs3, 0(r4)
404 ; CHECK-BE-NEXT: lxv vs0, 48(r4)
405 ; CHECK-BE-NEXT: lxv vs1, 32(r4)
406 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
407 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
408 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs4
409 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
410 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
411 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
412 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs0
413 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
414 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs2
415 ; CHECK-BE-NEXT: stxv v2, 0(r3)
416 ; CHECK-BE-NEXT: vmrgew v3, v4, v3
417 ; CHECK-BE-NEXT: stxv v3, 16(r3)
418 ; CHECK-BE-NEXT: blr
419 entry:
420 %a = load <8 x double>, ptr %0, align 64
421 %1 = fptosi <8 x double> %a to <8 x i32>
422 store <8 x i32> %1, ptr %agg.result, align 32
423 ret void
424 }
426 define void @test16elt_signed(ptr noalias nocapture sret(<16 x i32>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
427 ; CHECK-P8-LABEL: test16elt_signed:
428 ; CHECK-P8: # %bb.0: # %entry
429 ; CHECK-P8-NEXT: li r6, 96
430 ; CHECK-P8-NEXT: li r7, 112
431 ; CHECK-P8-NEXT: li r5, 16
432 ; CHECK-P8-NEXT: lxvd2x vs7, 0, r4
433 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r6
434 ; CHECK-P8-NEXT: li r6, 64
435 ; CHECK-P8-NEXT: lxvd2x vs1, r4, r7
436 ; CHECK-P8-NEXT: li r7, 80
437 ; CHECK-P8-NEXT: lxvd2x vs4, r4, r5
438 ; CHECK-P8-NEXT: lxvd2x vs2, r4, r6
439 ; CHECK-P8-NEXT: li r6, 32
440 ; CHECK-P8-NEXT: lxvd2x vs3, r4, r7
441 ; CHECK-P8-NEXT: li r7, 48
442 ; CHECK-P8-NEXT: lxvd2x vs5, r4, r6
443 ; CHECK-P8-NEXT: lxvd2x vs6, r4, r7
444 ; CHECK-P8-NEXT: xxmrghd vs8, vs5, vs6
445 ; CHECK-P8-NEXT: xxmrgld vs5, vs5, vs6
446 ; CHECK-P8-NEXT: xxmrghd vs6, vs2, vs3
447 ; CHECK-P8-NEXT: xxmrgld vs2, vs2, vs3
448 ; CHECK-P8-NEXT: xxmrghd vs3, vs0, vs1
449 ; CHECK-P8-NEXT: xxmrgld vs0, vs0, vs1
450 ; CHECK-P8-NEXT: xxmrghd vs1, vs7, vs4
451 ; CHECK-P8-NEXT: xxmrgld vs4, vs7, vs4
452 ; CHECK-P8-NEXT: xvcvdpsxws v2, vs8
453 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs5
454 ; CHECK-P8-NEXT: xvcvdpsxws v4, vs6
455 ; CHECK-P8-NEXT: xvcvdpsxws v5, vs2
456 ; CHECK-P8-NEXT: xvcvdpsxws v0, vs3
457 ; CHECK-P8-NEXT: vmrgew v2, v3, v2
458 ; CHECK-P8-NEXT: xvcvdpsxws v3, vs0
459 ; CHECK-P8-NEXT: vmrgew v4, v5, v4
460 ; CHECK-P8-NEXT: xvcvdpsxws v5, vs1
461 ; CHECK-P8-NEXT: vmrgew v3, v3, v0
462 ; CHECK-P8-NEXT: xvcvdpsxws v0, vs4
463 ; CHECK-P8-NEXT: stxvd2x v3, r3, r7
464 ; CHECK-P8-NEXT: stxvd2x v4, r3, r6
465 ; CHECK-P8-NEXT: stxvd2x v2, r3, r5
466 ; CHECK-P8-NEXT: vmrgew v5, v0, v5
467 ; CHECK-P8-NEXT: stxvd2x v5, 0, r3
468 ; CHECK-P8-NEXT: blr
469 ;
470 ; CHECK-P9-LABEL: test16elt_signed:
471 ; CHECK-P9: # %bb.0: # %entry
472 ; CHECK-P9-NEXT: lxv vs6, 0(r4)
473 ; CHECK-P9-NEXT: lxv vs7, 16(r4)
474 ; CHECK-P9-NEXT: lxv vs4, 32(r4)
475 ; CHECK-P9-NEXT: lxv vs5, 48(r4)
476 ; CHECK-P9-NEXT: xxmrgld vs8, vs7, vs6
477 ; CHECK-P9-NEXT: xxmrghd vs6, vs7, vs6
478 ; CHECK-P9-NEXT: xxmrgld vs7, vs5, vs4
479 ; CHECK-P9-NEXT: xxmrghd vs4, vs5, vs4
480 ; CHECK-P9-NEXT: lxv vs2, 64(r4)
481 ; CHECK-P9-NEXT: lxv vs3, 80(r4)
482 ; CHECK-P9-NEXT: lxv vs0, 96(r4)
483 ; CHECK-P9-NEXT: lxv vs1, 112(r4)
484 ; CHECK-P9-NEXT: xvcvdpsxws v2, vs8
485 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs6
486 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs7
487 ; CHECK-P9-NEXT: vmrgew v2, v3, v2
488 ; CHECK-P9-NEXT: xvcvdpsxws v3, vs4
489 ; CHECK-P9-NEXT: xxmrgld vs4, vs3, vs2
490 ; CHECK-P9-NEXT: xxmrghd vs2, vs3, vs2
491 ; CHECK-P9-NEXT: stxv v2, 0(r3)
492 ; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
493 ; CHECK-P9-NEXT: xxmrgld vs2, vs1, vs0
494 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
495 ; CHECK-P9-NEXT: xvcvdpsxws v0, vs0
496 ; CHECK-P9-NEXT: vmrgew v3, v3, v4
497 ; CHECK-P9-NEXT: xvcvdpsxws v4, vs4
498 ; CHECK-P9-NEXT: stxv v3, 16(r3)
499 ; CHECK-P9-NEXT: vmrgew v4, v5, v4
500 ; CHECK-P9-NEXT: stxv v4, 32(r3)
501 ; CHECK-P9-NEXT: xvcvdpsxws v5, vs2
502 ; CHECK-P9-NEXT: vmrgew v5, v0, v5
503 ; CHECK-P9-NEXT: stxv v5, 48(r3)
504 ; CHECK-P9-NEXT: blr
505 ;
506 ; CHECK-BE-LABEL: test16elt_signed:
507 ; CHECK-BE: # %bb.0: # %entry
508 ; CHECK-BE-NEXT: lxv vs6, 16(r4)
509 ; CHECK-BE-NEXT: lxv vs7, 0(r4)
510 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
511 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
512 ; CHECK-BE-NEXT: xxmrgld vs8, vs7, vs6
513 ; CHECK-BE-NEXT: xxmrghd vs6, vs7, vs6
514 ; CHECK-BE-NEXT: xxmrgld vs7, vs5, vs4
515 ; CHECK-BE-NEXT: xxmrghd vs4, vs5, vs4
516 ; CHECK-BE-NEXT: lxv vs2, 80(r4)
517 ; CHECK-BE-NEXT: lxv vs3, 64(r4)
518 ; CHECK-BE-NEXT: lxv vs0, 112(r4)
519 ; CHECK-BE-NEXT: lxv vs1, 96(r4)
520 ; CHECK-BE-NEXT: xvcvdpsxws v2, vs8
521 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs6
522 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs7
523 ; CHECK-BE-NEXT: vmrgew v2, v3, v2
524 ; CHECK-BE-NEXT: xvcvdpsxws v3, vs4
525 ; CHECK-BE-NEXT: xxmrgld vs4, vs3, vs2
526 ; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2
527 ; CHECK-BE-NEXT: stxv v2, 0(r3)
528 ; CHECK-BE-NEXT: xvcvdpsxws v5, vs2
529 ; CHECK-BE-NEXT: xxmrgld vs2, vs1, vs0
530 ; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0
531 ; CHECK-BE-NEXT: xvcvdpsxws v0, vs0
532 ; CHECK-BE-NEXT: vmrgew v3, v3, v4
533 ; CHECK-BE-NEXT: xvcvdpsxws v4, vs4
534 ; CHECK-BE-NEXT: stxv v3, 16(r3)
535 ; CHECK-BE-NEXT: vmrgew v4, v5, v4
536 ; CHECK-BE-NEXT: stxv v4, 32(r3)
537 ; CHECK-BE-NEXT: xvcvdpsxws v5, vs2
538 ; CHECK-BE-NEXT: vmrgew v5, v0, v5
539 ; CHECK-BE-NEXT: stxv v5, 48(r3)
540 ; CHECK-BE-NEXT: blr
541 entry:
542 %a = load <16 x double>, ptr %0, align 128
543 %1 = fptosi <16 x double> %a to <16 x i32>
544 store <16 x i32> %1, ptr %agg.result, align 64
545 ret void
546 }