| blob | bfb8b72327f5a6f1a545d78bcb892918c38f70c9 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
16 ; CHECK-P8-NEXT: mtvsrwz v3, r3
17 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
18 ; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l
19 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
20 ; CHECK-P8-NEXT: xxswapd v2, vs0
21 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
22 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
23 ; CHECK-P8-NEXT: blr
24 ;
25 ; CHECK-P9-LABEL: test2elt:
26 ; CHECK-P9: # %bb.0: # %entry
27 ; CHECK-P9-NEXT: mtfprwz f0, r3
28 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
29 ; CHECK-P9-NEXT: xxlxor vs2, vs2, vs2
30 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
31 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
32 ; CHECK-P9-NEXT: xxperm vs0, vs2, vs1
33 ; CHECK-P9-NEXT: xvcvuxddp v2, vs0
34 ; CHECK-P9-NEXT: blr
35 ;
36 ; CHECK-BE-LABEL: test2elt:
37 ; CHECK-BE: # %bb.0: # %entry
38 ; CHECK-BE-NEXT: mtfprwz f0, r3
39 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
40 ; CHECK-BE-NEXT: xxlxor vs2, vs2, vs2
41 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
42 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
43 ; CHECK-BE-NEXT: xxperm vs0, vs2, vs1
44 ; CHECK-BE-NEXT: xvcvuxddp v2, vs0
45 ; CHECK-BE-NEXT: blr
46 entry:
47 %0 = bitcast i32 %a.coerce to <2 x i16>
48 %1 = uitofp <2 x i16> %0 to <2 x double>
49 ret <2 x double> %1
50 }
52 define void @test4elt(ptr noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
53 ; CHECK-P8-LABEL: test4elt:
54 ; CHECK-P8: # %bb.0: # %entry
55 ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
56 ; CHECK-P8-NEXT: mtvsrd v4, r4
57 ; CHECK-P8-NEXT: xxlxor v5, v5, v5
58 ; CHECK-P8-NEXT: li r4, 16
59 ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
60 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
61 ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_1@toc@ha
62 ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_1@toc@l
63 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
64 ; CHECK-P8-NEXT: xxswapd v2, vs0
65 ; CHECK-P8-NEXT: vperm v2, v5, v4, v2
66 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2
67 ; CHECK-P8-NEXT: xxswapd v3, vs1
68 ; CHECK-P8-NEXT: vperm v3, v5, v4, v3
69 ; CHECK-P8-NEXT: xvcvuxddp vs1, v3
70 ; CHECK-P8-NEXT: xxswapd vs0, vs0
71 ; CHECK-P8-NEXT: xxswapd vs1, vs1
72 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
73 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
74 ; CHECK-P8-NEXT: blr
75 ;
76 ; CHECK-P9-LABEL: test4elt:
77 ; CHECK-P9: # %bb.0: # %entry
78 ; CHECK-P9-NEXT: mtvsrd v2, r4
79 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
80 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
81 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
82 ; CHECK-P9-NEXT: lxv v3, 0(r4)
83 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
84 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
85 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
86 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
87 ; CHECK-P9-NEXT: lxv v3, 0(r4)
88 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
89 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
90 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
91 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
92 ; CHECK-P9-NEXT: blr
93 ;
94 ; CHECK-BE-LABEL: test4elt:
95 ; CHECK-BE: # %bb.0: # %entry
96 ; CHECK-BE-NEXT: mtvsrd v2, r4
97 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
98 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
99 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
100 ; CHECK-BE-NEXT: lxv v3, 0(r4)
101 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
102 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
103 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
104 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
105 ; CHECK-BE-NEXT: lxv v3, 0(r4)
106 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
107 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
108 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
109 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
110 ; CHECK-BE-NEXT: blr
111 entry:
112 %0 = bitcast i64 %a.coerce to <4 x i16>
113 %1 = uitofp <4 x i16> %0 to <4 x double>
114 store <4 x double> %1, ptr %agg.result, align 32
115 ret void
116 }
118 define void @test8elt(ptr noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
119 ; CHECK-P8-LABEL: test8elt:
120 ; CHECK-P8: # %bb.0: # %entry
121 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha
122 ; CHECK-P8-NEXT: xxlxor v1, v1, v1
123 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l
124 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
125 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
126 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_1@toc@l
127 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
128 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha
129 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l
130 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
131 ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_2@toc@ha
132 ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_2@toc@l
133 ; CHECK-P8-NEXT: xxswapd v4, vs0
134 ; CHECK-P8-NEXT: vperm v4, v1, v2, v4
135 ; CHECK-P8-NEXT: xvcvuxddp vs0, v4
136 ; CHECK-P8-NEXT: xxswapd v5, vs1
137 ; CHECK-P8-NEXT: vperm v5, v1, v2, v5
138 ; CHECK-P8-NEXT: xvcvuxddp vs1, v5
139 ; CHECK-P8-NEXT: xxswapd v3, vs2
140 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
141 ; CHECK-P8-NEXT: li r4, 48
142 ; CHECK-P8-NEXT: vperm v3, v1, v2, v3
143 ; CHECK-P8-NEXT: xxswapd vs0, vs0
144 ; CHECK-P8-NEXT: xxswapd v0, vs2
145 ; CHECK-P8-NEXT: xvcvuxddp vs2, v3
146 ; CHECK-P8-NEXT: xxswapd vs1, vs1
147 ; CHECK-P8-NEXT: vperm v2, v1, v2, v0
148 ; CHECK-P8-NEXT: xvcvuxddp vs3, v2
149 ; CHECK-P8-NEXT: xxswapd vs2, vs2
150 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
151 ; CHECK-P8-NEXT: li r4, 32
152 ; CHECK-P8-NEXT: xxswapd vs3, vs3
153 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
154 ; CHECK-P8-NEXT: li r4, 16
155 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
156 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
157 ; CHECK-P8-NEXT: blr
158 ;
159 ; CHECK-P9-LABEL: test8elt:
160 ; CHECK-P9: # %bb.0: # %entry
161 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
162 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
163 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
164 ; CHECK-P9-NEXT: lxv v3, 0(r4)
165 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
166 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
167 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
168 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
169 ; CHECK-P9-NEXT: lxv v3, 0(r4)
170 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
171 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
172 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
173 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
174 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
175 ; CHECK-P9-NEXT: lxv v3, 0(r4)
176 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
177 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
178 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
179 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
180 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
181 ; CHECK-P9-NEXT: lxv v3, 0(r4)
182 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
183 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
184 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
185 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
186 ; CHECK-P9-NEXT: blr
187 ;
188 ; CHECK-BE-LABEL: test8elt:
189 ; CHECK-BE: # %bb.0: # %entry
190 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
191 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
192 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
193 ; CHECK-BE-NEXT: lxv v3, 0(r4)
194 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
195 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
196 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
197 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
198 ; CHECK-BE-NEXT: lxv v3, 0(r4)
199 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
200 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
201 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
202 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
203 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
204 ; CHECK-BE-NEXT: lxv v3, 0(r4)
205 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
206 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
207 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
208 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
209 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
210 ; CHECK-BE-NEXT: lxv v3, 0(r4)
211 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
212 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
213 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
214 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
215 ; CHECK-BE-NEXT: blr
216 entry:
217 %0 = uitofp <8 x i16> %a to <8 x double>
218 store <8 x double> %0, ptr %agg.result, align 64
219 ret void
220 }
222 define void @test16elt(ptr noalias nocapture sret(<16 x double>) %agg.result, ptr nocapture readonly) local_unnamed_addr #3 {
223 ; CHECK-P8-LABEL: test16elt:
224 ; CHECK-P8: # %bb.0: # %entry
225 ; CHECK-P8-NEXT: li r5, 16
226 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
227 ; CHECK-P8-NEXT: xxlxor v5, v5, v5
228 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
229 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1@toc@ha
230 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1@toc@l
231 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
232 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha
233 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l
234 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
235 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_2@toc@ha
236 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_2@toc@l
237 ; CHECK-P8-NEXT: xxswapd v6, vs1
238 ; CHECK-P8-NEXT: xxswapd v2, vs0
239 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
240 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha
241 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l
242 ; CHECK-P8-NEXT: xxswapd v0, vs2
243 ; CHECK-P8-NEXT: vperm v9, v5, v2, v0
244 ; CHECK-P8-NEXT: xvcvuxddp vs6, v9
245 ; CHECK-P8-NEXT: vperm v0, v5, v6, v0
246 ; CHECK-P8-NEXT: xvcvuxddp vs1, v0
247 ; CHECK-P8-NEXT: xxswapd v3, vs3
248 ; CHECK-P8-NEXT: vperm v1, v5, v2, v3
249 ; CHECK-P8-NEXT: vperm v3, v5, v6, v3
250 ; CHECK-P8-NEXT: xvcvuxddp vs4, v1
251 ; CHECK-P8-NEXT: xvcvuxddp vs3, v3
252 ; CHECK-P8-NEXT: xxswapd v4, vs0
253 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
254 ; CHECK-P8-NEXT: li r4, 112
255 ; CHECK-P8-NEXT: vperm v8, v5, v2, v4
256 ; CHECK-P8-NEXT: vperm v4, v5, v6, v4
257 ; CHECK-P8-NEXT: xxswapd vs1, vs1
258 ; CHECK-P8-NEXT: xvcvuxddp vs7, v8
259 ; CHECK-P8-NEXT: xvcvuxddp vs2, v4
260 ; CHECK-P8-NEXT: xxswapd v7, vs0
261 ; CHECK-P8-NEXT: xxswapd vs4, vs4
262 ; CHECK-P8-NEXT: xxswapd vs3, vs3
263 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
264 ; CHECK-P8-NEXT: li r4, 96
265 ; CHECK-P8-NEXT: vperm v2, v5, v2, v7
266 ; CHECK-P8-NEXT: vperm v7, v5, v6, v7
267 ; CHECK-P8-NEXT: xvcvuxddp vs5, v2
268 ; CHECK-P8-NEXT: xvcvuxddp vs0, v7
269 ; CHECK-P8-NEXT: xxswapd vs4, vs6
270 ; CHECK-P8-NEXT: xxswapd vs7, vs7
271 ; CHECK-P8-NEXT: xxswapd vs2, vs2
272 ; CHECK-P8-NEXT: stxvd2x vs7, r3, r4
273 ; CHECK-P8-NEXT: li r4, 80
274 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
275 ; CHECK-P8-NEXT: li r4, 64
276 ; CHECK-P8-NEXT: xxswapd vs5, vs5
277 ; CHECK-P8-NEXT: xxswapd vs0, vs0
278 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
279 ; CHECK-P8-NEXT: li r4, 48
280 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
281 ; CHECK-P8-NEXT: li r4, 32
282 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
283 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
284 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
285 ; CHECK-P8-NEXT: blr
286 ;
287 ; CHECK-P9-LABEL: test16elt:
288 ; CHECK-P9: # %bb.0: # %entry
289 ; CHECK-P9-NEXT: lxv v2, 16(r4)
290 ; CHECK-P9-NEXT: lxv v3, 0(r4)
291 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
292 ; CHECK-P9-NEXT: xxlxor v5, v5, v5
293 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
294 ; CHECK-P9-NEXT: lxv v4, 0(r4)
295 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
296 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
297 ; CHECK-P9-NEXT: vperm v0, v5, v3, v4
298 ; CHECK-P9-NEXT: xvcvuxddp vs0, v0
299 ; CHECK-P9-NEXT: lxv v0, 0(r4)
300 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
301 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
302 ; CHECK-P9-NEXT: vperm v1, v5, v3, v0
303 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
304 ; CHECK-P9-NEXT: xvcvuxddp vs1, v1
305 ; CHECK-P9-NEXT: lxv v1, 0(r4)
306 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
307 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
308 ; CHECK-P9-NEXT: vperm v6, v5, v3, v1
309 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
310 ; CHECK-P9-NEXT: xvcvuxddp vs2, v6
311 ; CHECK-P9-NEXT: lxv v6, 0(r4)
312 ; CHECK-P9-NEXT: vperm v3, v5, v3, v6
313 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
314 ; CHECK-P9-NEXT: xvcvuxddp vs3, v3
315 ; CHECK-P9-NEXT: vperm v3, v5, v2, v4
316 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
317 ; CHECK-P9-NEXT: vperm v3, v5, v2, v0
318 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
319 ; CHECK-P9-NEXT: vperm v3, v5, v2, v1
320 ; CHECK-P9-NEXT: vperm v2, v5, v2, v6
321 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
322 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
323 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
324 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
325 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
326 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
327 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
328 ; CHECK-P9-NEXT: blr
329 ;
330 ; CHECK-BE-LABEL: test16elt:
331 ; CHECK-BE: # %bb.0: # %entry
332 ; CHECK-BE-NEXT: lxv v2, 16(r4)
333 ; CHECK-BE-NEXT: lxv v3, 0(r4)
334 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
335 ; CHECK-BE-NEXT: xxlxor v5, v5, v5
336 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
337 ; CHECK-BE-NEXT: lxv v4, 0(r4)
338 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
339 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
340 ; CHECK-BE-NEXT: vperm v0, v5, v3, v4
341 ; CHECK-BE-NEXT: xvcvuxddp vs0, v0
342 ; CHECK-BE-NEXT: lxv v0, 0(r4)
343 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
344 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
345 ; CHECK-BE-NEXT: vperm v1, v5, v3, v0
346 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
347 ; CHECK-BE-NEXT: xvcvuxddp vs1, v1
348 ; CHECK-BE-NEXT: lxv v1, 0(r4)
349 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
350 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
351 ; CHECK-BE-NEXT: vperm v6, v5, v3, v1
352 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
353 ; CHECK-BE-NEXT: xvcvuxddp vs2, v6
354 ; CHECK-BE-NEXT: lxv v6, 0(r4)
355 ; CHECK-BE-NEXT: vperm v3, v5, v3, v6
356 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
357 ; CHECK-BE-NEXT: xvcvuxddp vs3, v3
358 ; CHECK-BE-NEXT: vperm v3, v5, v2, v4
359 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
360 ; CHECK-BE-NEXT: vperm v3, v5, v2, v0
361 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
362 ; CHECK-BE-NEXT: vperm v3, v5, v2, v1
363 ; CHECK-BE-NEXT: vperm v2, v5, v2, v6
364 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
365 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
366 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
367 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
368 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
369 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
370 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
371 ; CHECK-BE-NEXT: blr
372 entry:
373 %a = load <16 x i16>, ptr %0, align 32
374 %1 = uitofp <16 x i16> %a to <16 x double>
375 store <16 x double> %1, ptr %agg.result, align 128
376 ret void
377 }
379 define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
380 ; CHECK-P8-LABEL: test2elt_signed:
381 ; CHECK-P8: # %bb.0: # %entry
382 ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
383 ; CHECK-P8-NEXT: mtvsrwz v3, r3
384 ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
385 ; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l
386 ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
387 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
388 ; CHECK-P8-NEXT: xxswapd v2, vs0
389 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
390 ; CHECK-P8-NEXT: lxvd2x v3, 0, r3
391 ; CHECK-P8-NEXT: vsld v2, v2, v3
392 ; CHECK-P8-NEXT: vsrad v2, v2, v3
393 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
394 ; CHECK-P8-NEXT: blr
395 ;
396 ; CHECK-P9-LABEL: test2elt_signed:
397 ; CHECK-P9: # %bb.0: # %entry
398 ; CHECK-P9-NEXT: mtvsrwz v2, r3
399 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
400 ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
401 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
402 ; CHECK-P9-NEXT: xxperm v2, v2, vs0
403 ; CHECK-P9-NEXT: vextsh2d v2, v2
404 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
405 ; CHECK-P9-NEXT: blr
406 ;
407 ; CHECK-BE-LABEL: test2elt_signed:
408 ; CHECK-BE: # %bb.0: # %entry
409 ; CHECK-BE-NEXT: mtvsrwz v2, r3
410 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
411 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
412 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
413 ; CHECK-BE-NEXT: xxperm v2, v2, vs0
414 ; CHECK-BE-NEXT: vextsh2d v2, v2
415 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
416 ; CHECK-BE-NEXT: blr
417 entry:
418 %0 = bitcast i32 %a.coerce to <2 x i16>
419 %1 = sitofp <2 x i16> %0 to <2 x double>
420 ret <2 x double> %1
421 }
423 define void @test4elt_signed(ptr noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
424 ; CHECK-P8-LABEL: test4elt_signed:
425 ; CHECK-P8: # %bb.0: # %entry
426 ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
427 ; CHECK-P8-NEXT: mtvsrd v4, r4
428 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
429 ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
430 ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
431 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
432 ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_2@toc@ha
433 ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_2@toc@l
434 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
435 ; CHECK-P8-NEXT: xxswapd v2, vs0
436 ; CHECK-P8-NEXT: vperm v2, v4, v4, v2
437 ; CHECK-P8-NEXT: xxswapd v3, vs1
438 ; CHECK-P8-NEXT: vperm v3, v4, v4, v3
439 ; CHECK-P8-NEXT: lxvd2x v4, 0, r4
440 ; CHECK-P8-NEXT: li r4, 16
441 ; CHECK-P8-NEXT: vsld v2, v2, v4
442 ; CHECK-P8-NEXT: vsrad v2, v2, v4
443 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
444 ; CHECK-P8-NEXT: vsld v2, v3, v4
445 ; CHECK-P8-NEXT: vsrad v2, v2, v4
446 ; CHECK-P8-NEXT: xvcvsxddp vs1, v2
447 ; CHECK-P8-NEXT: xxswapd vs0, vs0
448 ; CHECK-P8-NEXT: xxswapd vs1, vs1
449 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
450 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
451 ; CHECK-P8-NEXT: blr
452 ;
453 ; CHECK-P9-LABEL: test4elt_signed:
454 ; CHECK-P9: # %bb.0: # %entry
455 ; CHECK-P9-NEXT: mtvsrd v2, r4
456 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
457 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
458 ; CHECK-P9-NEXT: lxv v3, 0(r4)
459 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
460 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
461 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
462 ; CHECK-P9-NEXT: vextsh2d v3, v3
463 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
464 ; CHECK-P9-NEXT: lxv v3, 0(r4)
465 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
466 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
467 ; CHECK-P9-NEXT: vextsh2d v2, v2
468 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
469 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
470 ; CHECK-P9-NEXT: blr
471 ;
472 ; CHECK-BE-LABEL: test4elt_signed:
473 ; CHECK-BE: # %bb.0: # %entry
474 ; CHECK-BE-NEXT: mtvsrd v2, r4
475 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
476 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
477 ; CHECK-BE-NEXT: lxv v3, 0(r4)
478 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
479 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
480 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
481 ; CHECK-BE-NEXT: vextsh2d v3, v3
482 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
483 ; CHECK-BE-NEXT: lxv v3, 0(r4)
484 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
485 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
486 ; CHECK-BE-NEXT: vextsh2d v2, v2
487 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
488 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
489 ; CHECK-BE-NEXT: blr
490 entry:
491 %0 = bitcast i64 %a.coerce to <4 x i16>
492 %1 = sitofp <4 x i16> %0 to <4 x double>
493 store <4 x double> %1, ptr %agg.result, align 32
494 ret void
495 }
497 define void @test8elt_signed(ptr noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {
498 ; CHECK-P8-LABEL: test8elt_signed:
499 ; CHECK-P8: # %bb.0: # %entry
500 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha
501 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l
502 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
503 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_2@toc@ha
504 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_2@toc@l
505 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
506 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_4@toc@ha
507 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_4@toc@l
508 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
509 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_3@toc@ha
510 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_3@toc@l
511 ; CHECK-P8-NEXT: xxswapd v4, vs0
512 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
513 ; CHECK-P8-NEXT: xxswapd v5, vs1
514 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
515 ; CHECK-P8-NEXT: xxswapd v3, vs2
516 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
517 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
518 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l
519 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
520 ; CHECK-P8-NEXT: xxswapd v0, vs2
521 ; CHECK-P8-NEXT: vperm v2, v2, v2, v0
522 ; CHECK-P8-NEXT: lxvd2x v0, 0, r4
523 ; CHECK-P8-NEXT: li r4, 48
524 ; CHECK-P8-NEXT: vsld v3, v3, v0
525 ; CHECK-P8-NEXT: vsld v2, v2, v0
526 ; CHECK-P8-NEXT: vsld v4, v4, v0
527 ; CHECK-P8-NEXT: vsld v5, v5, v0
528 ; CHECK-P8-NEXT: vsrad v3, v3, v0
529 ; CHECK-P8-NEXT: vsrad v2, v2, v0
530 ; CHECK-P8-NEXT: vsrad v4, v4, v0
531 ; CHECK-P8-NEXT: vsrad v5, v5, v0
532 ; CHECK-P8-NEXT: xvcvsxddp vs2, v3
533 ; CHECK-P8-NEXT: xvcvsxddp vs3, v2
534 ; CHECK-P8-NEXT: xvcvsxddp vs0, v4
535 ; CHECK-P8-NEXT: xvcvsxddp vs1, v5
536 ; CHECK-P8-NEXT: xxswapd vs2, vs2
537 ; CHECK-P8-NEXT: xxswapd vs3, vs3
538 ; CHECK-P8-NEXT: xxswapd vs1, vs1
539 ; CHECK-P8-NEXT: xxswapd vs0, vs0
540 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
541 ; CHECK-P8-NEXT: li r4, 32
542 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
543 ; CHECK-P8-NEXT: li r4, 16
544 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
545 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
546 ; CHECK-P8-NEXT: blr
547 ;
548 ; CHECK-P9-LABEL: test8elt_signed:
549 ; CHECK-P9: # %bb.0: # %entry
550 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
551 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
552 ; CHECK-P9-NEXT: lxv v3, 0(r4)
553 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
554 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
555 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
556 ; CHECK-P9-NEXT: vextsh2d v3, v3
557 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
558 ; CHECK-P9-NEXT: lxv v3, 0(r4)
559 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
560 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
561 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
562 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
563 ; CHECK-P9-NEXT: vextsh2d v3, v3
564 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
565 ; CHECK-P9-NEXT: lxv v3, 0(r4)
566 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
567 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
568 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
569 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
570 ; CHECK-P9-NEXT: vextsh2d v3, v3
571 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
572 ; CHECK-P9-NEXT: lxv v3, 0(r4)
573 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
574 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
575 ; CHECK-P9-NEXT: vextsh2d v2, v2
576 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
577 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
578 ; CHECK-P9-NEXT: blr
579 ;
580 ; CHECK-BE-LABEL: test8elt_signed:
581 ; CHECK-BE: # %bb.0: # %entry
582 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
583 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
584 ; CHECK-BE-NEXT: lxv v3, 0(r4)
585 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
586 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
587 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
588 ; CHECK-BE-NEXT: vextsh2d v3, v3
589 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
590 ; CHECK-BE-NEXT: lxv v3, 0(r4)
591 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
592 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
593 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
594 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
595 ; CHECK-BE-NEXT: vextsh2d v3, v3
596 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
597 ; CHECK-BE-NEXT: lxv v3, 0(r4)
598 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
599 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
600 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
601 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
602 ; CHECK-BE-NEXT: vextsh2d v3, v3
603 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
604 ; CHECK-BE-NEXT: lxv v3, 0(r4)
605 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
606 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
607 ; CHECK-BE-NEXT: vextsh2d v2, v2
608 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
609 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
610 ; CHECK-BE-NEXT: blr
611 entry:
612 %0 = sitofp <8 x i16> %a to <8 x double>
613 store <8 x double> %0, ptr %agg.result, align 64
614 ret void
615 }
617 define void @test16elt_signed(ptr noalias nocapture sret(<16 x double>) %agg.result, ptr nocapture readonly) local_unnamed_addr #3 {
618 ; CHECK-P8-LABEL: test16elt_signed:
619 ; CHECK-P8: # %bb.0: # %entry
620 ; CHECK-P8-NEXT: li r5, 16
621 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
622 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
623 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_2@toc@ha
624 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_2@toc@l
625 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
626 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_4@toc@ha
627 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_4@toc@l
628 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
629 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha
630 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l
631 ; CHECK-P8-NEXT: xxswapd v1, vs1
632 ; CHECK-P8-NEXT: xxswapd v2, vs0
633 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
634 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha
635 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l
636 ; CHECK-P8-NEXT: xxswapd v5, vs2
637 ; CHECK-P8-NEXT: vperm v8, v2, v2, v5
638 ; CHECK-P8-NEXT: vperm v5, v1, v1, v5
639 ; CHECK-P8-NEXT: xxswapd v3, vs3
640 ; CHECK-P8-NEXT: vperm v0, v2, v2, v3
641 ; CHECK-P8-NEXT: vperm v3, v1, v1, v3
642 ; CHECK-P8-NEXT: xxswapd v4, vs0
643 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
644 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_1@toc@ha
645 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_1@toc@l
646 ; CHECK-P8-NEXT: vperm v7, v2, v2, v4
647 ; CHECK-P8-NEXT: vperm v4, v1, v1, v4
648 ; CHECK-P8-NEXT: xxswapd v6, vs0
649 ; CHECK-P8-NEXT: vperm v2, v2, v2, v6
650 ; CHECK-P8-NEXT: vperm v6, v1, v1, v6
651 ; CHECK-P8-NEXT: lxvd2x v1, 0, r4
652 ; CHECK-P8-NEXT: li r4, 112
653 ; CHECK-P8-NEXT: vsld v0, v0, v1
654 ; CHECK-P8-NEXT: vsld v7, v7, v1
655 ; CHECK-P8-NEXT: vsld v8, v8, v1
656 ; CHECK-P8-NEXT: vsld v2, v2, v1
657 ; CHECK-P8-NEXT: vsld v3, v3, v1
658 ; CHECK-P8-NEXT: vsld v6, v6, v1
659 ; CHECK-P8-NEXT: vsld v5, v5, v1
660 ; CHECK-P8-NEXT: vsld v4, v4, v1
661 ; CHECK-P8-NEXT: vsrad v0, v0, v1
662 ; CHECK-P8-NEXT: vsrad v7, v7, v1
663 ; CHECK-P8-NEXT: vsrad v8, v8, v1
664 ; CHECK-P8-NEXT: vsrad v2, v2, v1
665 ; CHECK-P8-NEXT: vsrad v3, v3, v1
666 ; CHECK-P8-NEXT: vsrad v6, v6, v1
667 ; CHECK-P8-NEXT: vsrad v5, v5, v1
668 ; CHECK-P8-NEXT: vsrad v4, v4, v1
669 ; CHECK-P8-NEXT: xvcvsxddp vs4, v0
670 ; CHECK-P8-NEXT: xvcvsxddp vs7, v7
671 ; CHECK-P8-NEXT: xvcvsxddp vs6, v8
672 ; CHECK-P8-NEXT: xvcvsxddp vs5, v2
673 ; CHECK-P8-NEXT: xvcvsxddp vs3, v3
674 ; CHECK-P8-NEXT: xvcvsxddp vs0, v6
675 ; CHECK-P8-NEXT: xvcvsxddp vs1, v5
676 ; CHECK-P8-NEXT: xvcvsxddp vs2, v4
677 ; CHECK-P8-NEXT: xxswapd vs4, vs4
678 ; CHECK-P8-NEXT: xxswapd vs7, vs7
679 ; CHECK-P8-NEXT: xxswapd vs5, vs5
680 ; CHECK-P8-NEXT: xxswapd vs3, vs3
681 ; CHECK-P8-NEXT: xxswapd vs2, vs2
682 ; CHECK-P8-NEXT: xxswapd vs1, vs1
683 ; CHECK-P8-NEXT: xxswapd vs0, vs0
684 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
685 ; CHECK-P8-NEXT: li r4, 96
686 ; CHECK-P8-NEXT: xxswapd vs4, vs6
687 ; CHECK-P8-NEXT: stxvd2x vs7, r3, r4
688 ; CHECK-P8-NEXT: li r4, 80
689 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
690 ; CHECK-P8-NEXT: li r4, 64
691 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
692 ; CHECK-P8-NEXT: li r4, 48
693 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
694 ; CHECK-P8-NEXT: li r4, 32
695 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
696 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
697 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
698 ; CHECK-P8-NEXT: blr
699 ;
700 ; CHECK-P9-LABEL: test16elt_signed:
701 ; CHECK-P9: # %bb.0: # %entry
702 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha
703 ; CHECK-P9-NEXT: lxv v2, 0(r4)
704 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l
705 ; CHECK-P9-NEXT: lxv v3, 0(r5)
706 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha
707 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l
708 ; CHECK-P9-NEXT: lxv v5, 0(r5)
709 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha
710 ; CHECK-P9-NEXT: vperm v4, v2, v2, v3
711 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l
712 ; CHECK-P9-NEXT: vextsh2d v4, v4
713 ; CHECK-P9-NEXT: lxv v0, 0(r5)
714 ; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha
715 ; CHECK-P9-NEXT: xvcvsxddp vs0, v4
716 ; CHECK-P9-NEXT: vperm v4, v2, v2, v5
717 ; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l
718 ; CHECK-P9-NEXT: lxv v1, 0(r5)
719 ; CHECK-P9-NEXT: vextsh2d v4, v4
720 ; CHECK-P9-NEXT: xvcvsxddp vs1, v4
721 ; CHECK-P9-NEXT: vperm v4, v2, v2, v0
722 ; CHECK-P9-NEXT: vperm v2, v2, v2, v1
723 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
724 ; CHECK-P9-NEXT: vextsh2d v4, v4
725 ; CHECK-P9-NEXT: xvcvsxddp vs2, v4
726 ; CHECK-P9-NEXT: lxv v4, 16(r4)
727 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
728 ; CHECK-P9-NEXT: vextsh2d v2, v2
729 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
730 ; CHECK-P9-NEXT: vperm v2, v4, v4, v3
731 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
732 ; CHECK-P9-NEXT: vextsh2d v2, v2
733 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
734 ; CHECK-P9-NEXT: xvcvsxddp vs4, v2
735 ; CHECK-P9-NEXT: vperm v2, v4, v4, v5
736 ; CHECK-P9-NEXT: vextsh2d v2, v2
737 ; CHECK-P9-NEXT: xvcvsxddp vs5, v2
738 ; CHECK-P9-NEXT: vperm v2, v4, v4, v0
739 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
740 ; CHECK-P9-NEXT: vextsh2d v2, v2
741 ; CHECK-P9-NEXT: xvcvsxddp vs6, v2
742 ; CHECK-P9-NEXT: vperm v2, v4, v4, v1
743 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
744 ; CHECK-P9-NEXT: vextsh2d v2, v2
745 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
746 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
747 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
748 ; CHECK-P9-NEXT: blr
749 ;
750 ; CHECK-BE-LABEL: test16elt_signed:
751 ; CHECK-BE: # %bb.0: # %entry
752 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
753 ; CHECK-BE-NEXT: lxv v2, 0(r4)
754 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
755 ; CHECK-BE-NEXT: lxv v3, 0(r5)
756 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
757 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l
758 ; CHECK-BE-NEXT: lxv v5, 0(r5)
759 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_2@toc@ha
760 ; CHECK-BE-NEXT: vperm v4, v2, v2, v3
761 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_2@toc@l
762 ; CHECK-BE-NEXT: vextsh2d v4, v4
763 ; CHECK-BE-NEXT: lxv v0, 0(r5)
764 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_3@toc@ha
765 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4
766 ; CHECK-BE-NEXT: vperm v4, v2, v2, v5
767 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_3@toc@l
768 ; CHECK-BE-NEXT: lxv v1, 0(r5)
769 ; CHECK-BE-NEXT: vextsh2d v4, v4
770 ; CHECK-BE-NEXT: xvcvsxddp vs1, v4
771 ; CHECK-BE-NEXT: vperm v4, v2, v2, v0
772 ; CHECK-BE-NEXT: vperm v2, v2, v2, v1
773 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
774 ; CHECK-BE-NEXT: vextsh2d v4, v4
775 ; CHECK-BE-NEXT: xvcvsxddp vs2, v4
776 ; CHECK-BE-NEXT: lxv v4, 16(r4)
777 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
778 ; CHECK-BE-NEXT: vextsh2d v2, v2
779 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
780 ; CHECK-BE-NEXT: vperm v2, v4, v4, v3
781 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
782 ; CHECK-BE-NEXT: vextsh2d v2, v2
783 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
784 ; CHECK-BE-NEXT: xvcvsxddp vs4, v2
785 ; CHECK-BE-NEXT: vperm v2, v4, v4, v5
786 ; CHECK-BE-NEXT: vextsh2d v2, v2
787 ; CHECK-BE-NEXT: xvcvsxddp vs5, v2
788 ; CHECK-BE-NEXT: vperm v2, v4, v4, v0
789 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
790 ; CHECK-BE-NEXT: vextsh2d v2, v2
791 ; CHECK-BE-NEXT: xvcvsxddp vs6, v2
792 ; CHECK-BE-NEXT: vperm v2, v4, v4, v1
793 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
794 ; CHECK-BE-NEXT: vextsh2d v2, v2
795 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
796 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
797 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
798 ; CHECK-BE-NEXT: blr
799 entry:
800 %a = load <16 x i16>, ptr %0, align 32
801 %1 = sitofp <16 x i16> %a to <16 x double>
802 store <16 x double> %1, ptr %agg.result, align 128
803 ret void
804 }