| blob | c001f2ff51bf6f07ebbfeb418463b54430342037 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: mtfprd f0, r3
16 ; CHECK-P8-NEXT: xxswapd v2, vs0
17 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
18 ; CHECK-P8-NEXT: xvcvuxwdp v2, v2
19 ; CHECK-P8-NEXT: blr
20 ;
21 ; CHECK-P9-LABEL: test2elt:
22 ; CHECK-P9: # %bb.0: # %entry
23 ; CHECK-P9-NEXT: mtfprd f0, r3
24 ; CHECK-P9-NEXT: xxswapd v2, vs0
25 ; CHECK-P9-NEXT: xxmrglw v2, v2, v2
26 ; CHECK-P9-NEXT: xvcvuxwdp v2, v2
27 ; CHECK-P9-NEXT: blr
28 ;
29 ; CHECK-BE-LABEL: test2elt:
30 ; CHECK-BE: # %bb.0: # %entry
31 ; CHECK-BE-NEXT: mtfprd f0, r3
32 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
33 ; CHECK-BE-NEXT: xvcvuxwdp v2, v2
34 ; CHECK-BE-NEXT: blr
35 entry:
36 %0 = bitcast i64 %a.coerce to <2 x i32>
37 %1 = uitofp <2 x i32> %0 to <2 x double>
38 ret <2 x double> %1
39 }
41 define void @test4elt(ptr noalias nocapture sret(<4 x double>) %agg.result, <4 x i32> %a) local_unnamed_addr #1 {
42 ; CHECK-P8-LABEL: test4elt:
43 ; CHECK-P8: # %bb.0: # %entry
44 ; CHECK-P8-NEXT: xxmrglw v3, v2, v2
45 ; CHECK-P8-NEXT: xxmrghw v2, v2, v2
46 ; CHECK-P8-NEXT: li r4, 16
47 ; CHECK-P8-NEXT: xvcvuxwdp vs0, v3
48 ; CHECK-P8-NEXT: xvcvuxwdp vs1, v2
49 ; CHECK-P8-NEXT: xxswapd vs1, vs1
50 ; CHECK-P8-NEXT: xxswapd vs0, vs0
51 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
52 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
53 ; CHECK-P8-NEXT: blr
54 ;
55 ; CHECK-P9-LABEL: test4elt:
56 ; CHECK-P9: # %bb.0: # %entry
57 ; CHECK-P9-NEXT: xxmrglw v3, v2, v2
58 ; CHECK-P9-NEXT: xxmrghw v2, v2, v2
59 ; CHECK-P9-NEXT: xvcvuxwdp vs0, v3
60 ; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
61 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
62 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
63 ; CHECK-P9-NEXT: blr
64 ;
65 ; CHECK-BE-LABEL: test4elt:
66 ; CHECK-BE: # %bb.0: # %entry
67 ; CHECK-BE-NEXT: xxmrghw v3, v2, v2
68 ; CHECK-BE-NEXT: xxmrglw v2, v2, v2
69 ; CHECK-BE-NEXT: xvcvuxwdp vs0, v3
70 ; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
71 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
72 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
73 ; CHECK-BE-NEXT: blr
74 entry:
75 %0 = uitofp <4 x i32> %a to <4 x double>
76 store <4 x double> %0, ptr %agg.result, align 32
77 ret void
78 }
80 define void @test8elt(ptr noalias nocapture sret(<8 x double>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
81 ; CHECK-P8-LABEL: test8elt:
82 ; CHECK-P8: # %bb.0: # %entry
83 ; CHECK-P8-NEXT: li r5, 16
84 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
85 ; CHECK-P8-NEXT: xxswapd v2, vs0
86 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
87 ; CHECK-P8-NEXT: li r4, 48
88 ; CHECK-P8-NEXT: xxmrghw v4, v2, v2
89 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
90 ; CHECK-P8-NEXT: xvcvuxwdp vs1, v4
91 ; CHECK-P8-NEXT: xxswapd v3, vs0
92 ; CHECK-P8-NEXT: xvcvuxwdp vs0, v2
93 ; CHECK-P8-NEXT: xxmrglw v5, v3, v3
94 ; CHECK-P8-NEXT: xxmrghw v3, v3, v3
95 ; CHECK-P8-NEXT: xvcvuxwdp vs2, v5
96 ; CHECK-P8-NEXT: xvcvuxwdp vs3, v3
97 ; CHECK-P8-NEXT: xxswapd vs1, vs1
98 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
99 ; CHECK-P8-NEXT: li r4, 32
100 ; CHECK-P8-NEXT: xxswapd vs0, vs0
101 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
102 ; CHECK-P8-NEXT: xxswapd vs3, vs3
103 ; CHECK-P8-NEXT: xxswapd vs2, vs2
104 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
105 ; CHECK-P8-NEXT: stxvd2x vs2, 0, r3
106 ; CHECK-P8-NEXT: blr
107 ;
108 ; CHECK-P9-LABEL: test8elt:
109 ; CHECK-P9: # %bb.0: # %entry
110 ; CHECK-P9-NEXT: lxv vs1, 0(r4)
111 ; CHECK-P9-NEXT: lxv vs0, 16(r4)
112 ; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
113 ; CHECK-P9-NEXT: xvcvuxwdp vs2, v2
114 ; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1
115 ; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
116 ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
117 ; CHECK-P9-NEXT: xvcvuxwdp vs3, v2
118 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
119 ; CHECK-P9-NEXT: stxv vs2, 0(r3)
120 ; CHECK-P9-NEXT: xvcvuxwdp vs0, v2
121 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
122 ; CHECK-P9-NEXT: stxv vs3, 32(r3)
123 ; CHECK-P9-NEXT: stxv vs0, 48(r3)
124 ; CHECK-P9-NEXT: blr
125 ;
126 ; CHECK-BE-LABEL: test8elt:
127 ; CHECK-BE: # %bb.0: # %entry
128 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
129 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
130 ; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
131 ; CHECK-BE-NEXT: xvcvuxwdp vs2, v2
132 ; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1
133 ; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
134 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
135 ; CHECK-BE-NEXT: xvcvuxwdp vs3, v2
136 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
137 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
138 ; CHECK-BE-NEXT: xvcvuxwdp vs0, v2
139 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
140 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
141 ; CHECK-BE-NEXT: stxv vs0, 48(r3)
142 ; CHECK-BE-NEXT: blr
143 entry:
144 %a = load <8 x i32>, ptr %0, align 32
145 %1 = uitofp <8 x i32> %a to <8 x double>
146 store <8 x double> %1, ptr %agg.result, align 64
147 ret void
148 }
150 define void @test16elt(ptr noalias nocapture sret(<16 x double>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
151 ; CHECK-P8-LABEL: test16elt:
152 ; CHECK-P8: # %bb.0: # %entry
153 ; CHECK-P8-NEXT: li r5, 48
154 ; CHECK-P8-NEXT: li r6, 32
155 ; CHECK-P8-NEXT: li r7, 16
156 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
157 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
158 ; CHECK-P8-NEXT: xxswapd v0, vs1
159 ; CHECK-P8-NEXT: xxswapd v2, vs0
160 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r6
161 ; CHECK-P8-NEXT: xxmrglw v7, v0, v0
162 ; CHECK-P8-NEXT: xxmrghw v0, v0, v0
163 ; CHECK-P8-NEXT: xvcvuxwdp vs6, v7
164 ; CHECK-P8-NEXT: xvcvuxwdp vs7, v0
165 ; CHECK-P8-NEXT: xxmrghw v3, v2, v2
166 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
167 ; CHECK-P8-NEXT: xvcvuxwdp vs2, v3
168 ; CHECK-P8-NEXT: xvcvuxwdp vs5, v2
169 ; CHECK-P8-NEXT: xxswapd v4, vs0
170 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r7
171 ; CHECK-P8-NEXT: li r4, 112
172 ; CHECK-P8-NEXT: xxmrglw v1, v4, v4
173 ; CHECK-P8-NEXT: xxmrghw v4, v4, v4
174 ; CHECK-P8-NEXT: xvcvuxwdp vs4, v4
175 ; CHECK-P8-NEXT: xvcvuxwdp vs3, v1
176 ; CHECK-P8-NEXT: xxswapd v5, vs0
177 ; CHECK-P8-NEXT: xxswapd vs2, vs2
178 ; CHECK-P8-NEXT: xxswapd vs5, vs5
179 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
180 ; CHECK-P8-NEXT: li r4, 96
181 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
182 ; CHECK-P8-NEXT: li r4, 80
183 ; CHECK-P8-NEXT: xxmrglw v6, v5, v5
184 ; CHECK-P8-NEXT: xxmrghw v5, v5, v5
185 ; CHECK-P8-NEXT: xvcvuxwdp vs0, v6
186 ; CHECK-P8-NEXT: xvcvuxwdp vs1, v5
187 ; CHECK-P8-NEXT: xxswapd vs5, vs6
188 ; CHECK-P8-NEXT: xxswapd vs2, vs4
189 ; CHECK-P8-NEXT: xxswapd vs3, vs3
190 ; CHECK-P8-NEXT: xxswapd vs4, vs7
191 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
192 ; CHECK-P8-NEXT: li r4, 64
193 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
194 ; CHECK-P8-NEXT: xxswapd vs1, vs1
195 ; CHECK-P8-NEXT: xxswapd vs0, vs0
196 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
197 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
198 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r7
199 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
200 ; CHECK-P8-NEXT: blr
201 ;
202 ; CHECK-P9-LABEL: test16elt:
203 ; CHECK-P9: # %bb.0: # %entry
204 ; CHECK-P9-NEXT: lxv vs0, 0(r4)
205 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
206 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
207 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
208 ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
209 ; CHECK-P9-NEXT: xvcvuxwdp vs1, v2
210 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
211 ; CHECK-P9-NEXT: xvcvuxwdp vs0, v2
212 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
213 ; CHECK-P9-NEXT: xvcvuxwdp vs3, v2
214 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
215 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
216 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
217 ; CHECK-P9-NEXT: xvcvuxwdp vs2, v2
218 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
219 ; CHECK-P9-NEXT: xvcvuxwdp vs6, v2
220 ; CHECK-P9-NEXT: xxmrghw v2, vs5, vs5
221 ; CHECK-P9-NEXT: stxv vs3, 32(r3)
222 ; CHECK-P9-NEXT: stxv vs2, 48(r3)
223 ; CHECK-P9-NEXT: xvcvuxwdp vs5, v2
224 ; CHECK-P9-NEXT: xxmrglw v2, vs4, vs4
225 ; CHECK-P9-NEXT: xvcvuxwdp vs7, v2
226 ; CHECK-P9-NEXT: xxmrghw v2, vs4, vs4
227 ; CHECK-P9-NEXT: stxv vs6, 64(r3)
228 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
229 ; CHECK-P9-NEXT: xvcvuxwdp vs4, v2
230 ; CHECK-P9-NEXT: stxv vs7, 96(r3)
231 ; CHECK-P9-NEXT: stxv vs4, 112(r3)
232 ; CHECK-P9-NEXT: blr
233 ;
234 ; CHECK-BE-LABEL: test16elt:
235 ; CHECK-BE: # %bb.0: # %entry
236 ; CHECK-BE-NEXT: lxv vs0, 0(r4)
237 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
238 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
239 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
240 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
241 ; CHECK-BE-NEXT: xvcvuxwdp vs1, v2
242 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
243 ; CHECK-BE-NEXT: xvcvuxwdp vs0, v2
244 ; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2
245 ; CHECK-BE-NEXT: xvcvuxwdp vs3, v2
246 ; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2
247 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
248 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
249 ; CHECK-BE-NEXT: xvcvuxwdp vs2, v2
250 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
251 ; CHECK-BE-NEXT: xvcvuxwdp vs6, v2
252 ; CHECK-BE-NEXT: xxmrglw v2, vs5, vs5
253 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
254 ; CHECK-BE-NEXT: stxv vs2, 48(r3)
255 ; CHECK-BE-NEXT: xvcvuxwdp vs5, v2
256 ; CHECK-BE-NEXT: xxmrghw v2, vs4, vs4
257 ; CHECK-BE-NEXT: xvcvuxwdp vs7, v2
258 ; CHECK-BE-NEXT: xxmrglw v2, vs4, vs4
259 ; CHECK-BE-NEXT: stxv vs6, 64(r3)
260 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
261 ; CHECK-BE-NEXT: xvcvuxwdp vs4, v2
262 ; CHECK-BE-NEXT: stxv vs7, 96(r3)
263 ; CHECK-BE-NEXT: stxv vs4, 112(r3)
264 ; CHECK-BE-NEXT: blr
265 entry:
266 %a = load <16 x i32>, ptr %0, align 64
267 %1 = uitofp <16 x i32> %a to <16 x double>
268 store <16 x double> %1, ptr %agg.result, align 128
269 ret void
270 }
272 define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
273 ; CHECK-P8-LABEL: test2elt_signed:
274 ; CHECK-P8: # %bb.0: # %entry
275 ; CHECK-P8-NEXT: mtfprd f0, r3
276 ; CHECK-P8-NEXT: xxswapd v2, vs0
277 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
278 ; CHECK-P8-NEXT: xvcvsxwdp v2, v2
279 ; CHECK-P8-NEXT: blr
280 ;
281 ; CHECK-P9-LABEL: test2elt_signed:
282 ; CHECK-P9: # %bb.0: # %entry
283 ; CHECK-P9-NEXT: mtfprd f0, r3
284 ; CHECK-P9-NEXT: xxswapd v2, vs0
285 ; CHECK-P9-NEXT: xxmrglw v2, v2, v2
286 ; CHECK-P9-NEXT: xvcvsxwdp v2, v2
287 ; CHECK-P9-NEXT: blr
288 ;
289 ; CHECK-BE-LABEL: test2elt_signed:
290 ; CHECK-BE: # %bb.0: # %entry
291 ; CHECK-BE-NEXT: mtfprd f0, r3
292 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
293 ; CHECK-BE-NEXT: xvcvsxwdp v2, v2
294 ; CHECK-BE-NEXT: blr
295 entry:
296 %0 = bitcast i64 %a.coerce to <2 x i32>
297 %1 = sitofp <2 x i32> %0 to <2 x double>
298 ret <2 x double> %1
299 }
301 define void @test4elt_signed(ptr noalias nocapture sret(<4 x double>) %agg.result, <4 x i32> %a) local_unnamed_addr #1 {
302 ; CHECK-P8-LABEL: test4elt_signed:
303 ; CHECK-P8: # %bb.0: # %entry
304 ; CHECK-P8-NEXT: xxmrglw v3, v2, v2
305 ; CHECK-P8-NEXT: xxmrghw v2, v2, v2
306 ; CHECK-P8-NEXT: li r4, 16
307 ; CHECK-P8-NEXT: xvcvsxwdp vs0, v3
308 ; CHECK-P8-NEXT: xvcvsxwdp vs1, v2
309 ; CHECK-P8-NEXT: xxswapd vs1, vs1
310 ; CHECK-P8-NEXT: xxswapd vs0, vs0
311 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
312 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
313 ; CHECK-P8-NEXT: blr
314 ;
315 ; CHECK-P9-LABEL: test4elt_signed:
316 ; CHECK-P9: # %bb.0: # %entry
317 ; CHECK-P9-NEXT: xxmrglw v3, v2, v2
318 ; CHECK-P9-NEXT: xxmrghw v2, v2, v2
319 ; CHECK-P9-NEXT: xvcvsxwdp vs0, v3
320 ; CHECK-P9-NEXT: xvcvsxwdp vs1, v2
321 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
322 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
323 ; CHECK-P9-NEXT: blr
324 ;
325 ; CHECK-BE-LABEL: test4elt_signed:
326 ; CHECK-BE: # %bb.0: # %entry
327 ; CHECK-BE-NEXT: xxmrghw v3, v2, v2
328 ; CHECK-BE-NEXT: xxmrglw v2, v2, v2
329 ; CHECK-BE-NEXT: xvcvsxwdp vs0, v3
330 ; CHECK-BE-NEXT: xvcvsxwdp vs1, v2
331 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
332 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
333 ; CHECK-BE-NEXT: blr
334 entry:
335 %0 = sitofp <4 x i32> %a to <4 x double>
336 store <4 x double> %0, ptr %agg.result, align 32
337 ret void
338 }
340 define void @test8elt_signed(ptr noalias nocapture sret(<8 x double>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
341 ; CHECK-P8-LABEL: test8elt_signed:
342 ; CHECK-P8: # %bb.0: # %entry
343 ; CHECK-P8-NEXT: li r5, 16
344 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
345 ; CHECK-P8-NEXT: xxswapd v2, vs0
346 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
347 ; CHECK-P8-NEXT: li r4, 48
348 ; CHECK-P8-NEXT: xxmrghw v4, v2, v2
349 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
350 ; CHECK-P8-NEXT: xvcvsxwdp vs1, v4
351 ; CHECK-P8-NEXT: xxswapd v3, vs0
352 ; CHECK-P8-NEXT: xvcvsxwdp vs0, v2
353 ; CHECK-P8-NEXT: xxmrglw v5, v3, v3
354 ; CHECK-P8-NEXT: xxmrghw v3, v3, v3
355 ; CHECK-P8-NEXT: xvcvsxwdp vs2, v5
356 ; CHECK-P8-NEXT: xvcvsxwdp vs3, v3
357 ; CHECK-P8-NEXT: xxswapd vs1, vs1
358 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
359 ; CHECK-P8-NEXT: li r4, 32
360 ; CHECK-P8-NEXT: xxswapd vs0, vs0
361 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r4
362 ; CHECK-P8-NEXT: xxswapd vs3, vs3
363 ; CHECK-P8-NEXT: xxswapd vs2, vs2
364 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r5
365 ; CHECK-P8-NEXT: stxvd2x vs2, 0, r3
366 ; CHECK-P8-NEXT: blr
367 ;
368 ; CHECK-P9-LABEL: test8elt_signed:
369 ; CHECK-P9: # %bb.0: # %entry
370 ; CHECK-P9-NEXT: lxv vs1, 0(r4)
371 ; CHECK-P9-NEXT: lxv vs0, 16(r4)
372 ; CHECK-P9-NEXT: xxmrglw v2, vs1, vs1
373 ; CHECK-P9-NEXT: xvcvsxwdp vs2, v2
374 ; CHECK-P9-NEXT: xxmrghw v2, vs1, vs1
375 ; CHECK-P9-NEXT: xvcvsxwdp vs1, v2
376 ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
377 ; CHECK-P9-NEXT: xvcvsxwdp vs3, v2
378 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
379 ; CHECK-P9-NEXT: stxv vs2, 0(r3)
380 ; CHECK-P9-NEXT: xvcvsxwdp vs0, v2
381 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
382 ; CHECK-P9-NEXT: stxv vs3, 32(r3)
383 ; CHECK-P9-NEXT: stxv vs0, 48(r3)
384 ; CHECK-P9-NEXT: blr
385 ;
386 ; CHECK-BE-LABEL: test8elt_signed:
387 ; CHECK-BE: # %bb.0: # %entry
388 ; CHECK-BE-NEXT: lxv vs1, 0(r4)
389 ; CHECK-BE-NEXT: lxv vs0, 16(r4)
390 ; CHECK-BE-NEXT: xxmrghw v2, vs1, vs1
391 ; CHECK-BE-NEXT: xvcvsxwdp vs2, v2
392 ; CHECK-BE-NEXT: xxmrglw v2, vs1, vs1
393 ; CHECK-BE-NEXT: xvcvsxwdp vs1, v2
394 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
395 ; CHECK-BE-NEXT: xvcvsxwdp vs3, v2
396 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
397 ; CHECK-BE-NEXT: stxv vs2, 0(r3)
398 ; CHECK-BE-NEXT: xvcvsxwdp vs0, v2
399 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
400 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
401 ; CHECK-BE-NEXT: stxv vs0, 48(r3)
402 ; CHECK-BE-NEXT: blr
403 entry:
404 %a = load <8 x i32>, ptr %0, align 32
405 %1 = sitofp <8 x i32> %a to <8 x double>
406 store <8 x double> %1, ptr %agg.result, align 64
407 ret void
408 }
410 define void @test16elt_signed(ptr noalias nocapture sret(<16 x double>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 {
411 ; CHECK-P8-LABEL: test16elt_signed:
412 ; CHECK-P8: # %bb.0: # %entry
413 ; CHECK-P8-NEXT: li r5, 48
414 ; CHECK-P8-NEXT: li r6, 32
415 ; CHECK-P8-NEXT: li r7, 16
416 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
417 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r5
418 ; CHECK-P8-NEXT: xxswapd v0, vs1
419 ; CHECK-P8-NEXT: xxswapd v2, vs0
420 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r6
421 ; CHECK-P8-NEXT: xxmrglw v7, v0, v0
422 ; CHECK-P8-NEXT: xxmrghw v0, v0, v0
423 ; CHECK-P8-NEXT: xvcvsxwdp vs6, v7
424 ; CHECK-P8-NEXT: xvcvsxwdp vs7, v0
425 ; CHECK-P8-NEXT: xxmrghw v3, v2, v2
426 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
427 ; CHECK-P8-NEXT: xvcvsxwdp vs2, v3
428 ; CHECK-P8-NEXT: xvcvsxwdp vs5, v2
429 ; CHECK-P8-NEXT: xxswapd v4, vs0
430 ; CHECK-P8-NEXT: lxvd2x vs0, r4, r7
431 ; CHECK-P8-NEXT: li r4, 112
432 ; CHECK-P8-NEXT: xxmrglw v1, v4, v4
433 ; CHECK-P8-NEXT: xxmrghw v4, v4, v4
434 ; CHECK-P8-NEXT: xvcvsxwdp vs4, v4
435 ; CHECK-P8-NEXT: xvcvsxwdp vs3, v1
436 ; CHECK-P8-NEXT: xxswapd v5, vs0
437 ; CHECK-P8-NEXT: xxswapd vs2, vs2
438 ; CHECK-P8-NEXT: xxswapd vs5, vs5
439 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
440 ; CHECK-P8-NEXT: li r4, 96
441 ; CHECK-P8-NEXT: stxvd2x vs5, r3, r4
442 ; CHECK-P8-NEXT: li r4, 80
443 ; CHECK-P8-NEXT: xxmrglw v6, v5, v5
444 ; CHECK-P8-NEXT: xxmrghw v5, v5, v5
445 ; CHECK-P8-NEXT: xvcvsxwdp vs0, v6
446 ; CHECK-P8-NEXT: xvcvsxwdp vs1, v5
447 ; CHECK-P8-NEXT: xxswapd vs5, vs6
448 ; CHECK-P8-NEXT: xxswapd vs2, vs4
449 ; CHECK-P8-NEXT: xxswapd vs3, vs3
450 ; CHECK-P8-NEXT: xxswapd vs4, vs7
451 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
452 ; CHECK-P8-NEXT: li r4, 64
453 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
454 ; CHECK-P8-NEXT: xxswapd vs1, vs1
455 ; CHECK-P8-NEXT: xxswapd vs0, vs0
456 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
457 ; CHECK-P8-NEXT: stxvd2x vs0, r3, r6
458 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r7
459 ; CHECK-P8-NEXT: stxvd2x vs5, 0, r3
460 ; CHECK-P8-NEXT: blr
461 ;
462 ; CHECK-P9-LABEL: test16elt_signed:
463 ; CHECK-P9: # %bb.0: # %entry
464 ; CHECK-P9-NEXT: lxv vs0, 0(r4)
465 ; CHECK-P9-NEXT: lxv vs2, 16(r4)
466 ; CHECK-P9-NEXT: lxv vs5, 32(r4)
467 ; CHECK-P9-NEXT: lxv vs4, 48(r4)
468 ; CHECK-P9-NEXT: xxmrglw v2, vs0, vs0
469 ; CHECK-P9-NEXT: xvcvsxwdp vs1, v2
470 ; CHECK-P9-NEXT: xxmrghw v2, vs0, vs0
471 ; CHECK-P9-NEXT: xvcvsxwdp vs0, v2
472 ; CHECK-P9-NEXT: xxmrglw v2, vs2, vs2
473 ; CHECK-P9-NEXT: xvcvsxwdp vs3, v2
474 ; CHECK-P9-NEXT: xxmrghw v2, vs2, vs2
475 ; CHECK-P9-NEXT: stxv vs1, 0(r3)
476 ; CHECK-P9-NEXT: stxv vs0, 16(r3)
477 ; CHECK-P9-NEXT: xvcvsxwdp vs2, v2
478 ; CHECK-P9-NEXT: xxmrglw v2, vs5, vs5
479 ; CHECK-P9-NEXT: xvcvsxwdp vs6, v2
480 ; CHECK-P9-NEXT: xxmrghw v2, vs5, vs5
481 ; CHECK-P9-NEXT: stxv vs3, 32(r3)
482 ; CHECK-P9-NEXT: stxv vs2, 48(r3)
483 ; CHECK-P9-NEXT: xvcvsxwdp vs5, v2
484 ; CHECK-P9-NEXT: xxmrglw v2, vs4, vs4
485 ; CHECK-P9-NEXT: xvcvsxwdp vs7, v2
486 ; CHECK-P9-NEXT: xxmrghw v2, vs4, vs4
487 ; CHECK-P9-NEXT: stxv vs6, 64(r3)
488 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
489 ; CHECK-P9-NEXT: xvcvsxwdp vs4, v2
490 ; CHECK-P9-NEXT: stxv vs7, 96(r3)
491 ; CHECK-P9-NEXT: stxv vs4, 112(r3)
492 ; CHECK-P9-NEXT: blr
493 ;
494 ; CHECK-BE-LABEL: test16elt_signed:
495 ; CHECK-BE: # %bb.0: # %entry
496 ; CHECK-BE-NEXT: lxv vs0, 0(r4)
497 ; CHECK-BE-NEXT: lxv vs2, 16(r4)
498 ; CHECK-BE-NEXT: lxv vs5, 32(r4)
499 ; CHECK-BE-NEXT: lxv vs4, 48(r4)
500 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
501 ; CHECK-BE-NEXT: xvcvsxwdp vs1, v2
502 ; CHECK-BE-NEXT: xxmrglw v2, vs0, vs0
503 ; CHECK-BE-NEXT: xvcvsxwdp vs0, v2
504 ; CHECK-BE-NEXT: xxmrghw v2, vs2, vs2
505 ; CHECK-BE-NEXT: xvcvsxwdp vs3, v2
506 ; CHECK-BE-NEXT: xxmrglw v2, vs2, vs2
507 ; CHECK-BE-NEXT: stxv vs1, 0(r3)
508 ; CHECK-BE-NEXT: stxv vs0, 16(r3)
509 ; CHECK-BE-NEXT: xvcvsxwdp vs2, v2
510 ; CHECK-BE-NEXT: xxmrghw v2, vs5, vs5
511 ; CHECK-BE-NEXT: xvcvsxwdp vs6, v2
512 ; CHECK-BE-NEXT: xxmrglw v2, vs5, vs5
513 ; CHECK-BE-NEXT: stxv vs3, 32(r3)
514 ; CHECK-BE-NEXT: stxv vs2, 48(r3)
515 ; CHECK-BE-NEXT: xvcvsxwdp vs5, v2
516 ; CHECK-BE-NEXT: xxmrghw v2, vs4, vs4
517 ; CHECK-BE-NEXT: xvcvsxwdp vs7, v2
518 ; CHECK-BE-NEXT: xxmrglw v2, vs4, vs4
519 ; CHECK-BE-NEXT: stxv vs6, 64(r3)
520 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
521 ; CHECK-BE-NEXT: xvcvsxwdp vs4, v2
522 ; CHECK-BE-NEXT: stxv vs7, 96(r3)
523 ; CHECK-BE-NEXT: stxv vs4, 112(r3)
524 ; CHECK-BE-NEXT: blr
525 entry:
526 %a = load <16 x i32>, ptr %0, align 64
527 %1 = sitofp <16 x i32> %a to <16 x double>
528 store <16 x double> %1, ptr %agg.result, align 128
529 ret void
530 }