| blob | 540a00fa84c5d5dc02f7d9e77854b01b96c48e20 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
5 ; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
6 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
7 ; RUN: -mcpu=pwr9 -mattr=-altivec < %s | FileCheck %s \
8 ; RUN: --check-prefix=CHECK-P9-NOALTIVEC
9 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
10 ; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-P8
12 define <4 x i32> @test_vextsh2w(<4 x i32> %m) {
13 ; CHECK-P9-LABEL: test_vextsh2w:
14 ; CHECK-P9: # %bb.0: # %entry
15 ; CHECK-P9-NEXT: vextsh2w 2, 2
16 ; CHECK-P9-NEXT: blr
17 ;
18 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2w:
19 ; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
20 ; CHECK-P9-NOALTIVEC-NEXT: extsh 6, 6
21 ; CHECK-P9-NOALTIVEC-NEXT: extsh 5, 5
22 ; CHECK-P9-NOALTIVEC-NEXT: extsh 4, 4
23 ; CHECK-P9-NOALTIVEC-NEXT: extsh 3, 3
24 ; CHECK-P9-NOALTIVEC-NEXT: blr
25 ;
26 ; CHECK-P8-LABEL: test_vextsh2w:
27 ; CHECK-P8: # %bb.0: # %entry
28 ; CHECK-P8-NEXT: vspltisw 3, 8
29 ; CHECK-P8-NEXT: vadduwm 3, 3, 3
30 ; CHECK-P8-NEXT: vslw 2, 2, 3
31 ; CHECK-P8-NEXT: vsraw 2, 2, 3
32 ; CHECK-P8-NEXT: blr
33 entry:
34 %shl = shl <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>
35 %shr = ashr exact <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
36 ret <4 x i32> %shr
37 }
39 define <4 x i32> @test_vextsb2w(<4 x i32> %m) {
40 ; CHECK-P9-LABEL: test_vextsb2w:
41 ; CHECK-P9: # %bb.0: # %entry
42 ; CHECK-P9-NEXT: vextsb2w 2, 2
43 ; CHECK-P9-NEXT: blr
44 ;
45 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2w:
46 ; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
47 ; CHECK-P9-NOALTIVEC-NEXT: extsb 6, 6
48 ; CHECK-P9-NOALTIVEC-NEXT: extsb 5, 5
49 ; CHECK-P9-NOALTIVEC-NEXT: extsb 4, 4
50 ; CHECK-P9-NOALTIVEC-NEXT: extsb 3, 3
51 ; CHECK-P9-NOALTIVEC-NEXT: blr
52 ;
53 ; CHECK-P8-LABEL: test_vextsb2w:
54 ; CHECK-P8: # %bb.0: # %entry
55 ; CHECK-P8-NEXT: vspltisw 3, 12
56 ; CHECK-P8-NEXT: vadduwm 3, 3, 3
57 ; CHECK-P8-NEXT: vslw 2, 2, 3
58 ; CHECK-P8-NEXT: vsraw 2, 2, 3
59 ; CHECK-P8-NEXT: blr
60 entry:
61 %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
62 %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
63 ret <4 x i32> %shr
64 }
66 define <2 x i64> @test_vextsb2d(<2 x i64> %m) {
67 ; CHECK-P9-LABEL: test_vextsb2d:
68 ; CHECK-P9: # %bb.0: # %entry
69 ; CHECK-P9-NEXT: vextsb2d 2, 2
70 ; CHECK-P9-NEXT: blr
71 ;
72 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2d:
73 ; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
74 ; CHECK-P9-NOALTIVEC-NEXT: extsb 3, 3
75 ; CHECK-P9-NOALTIVEC-NEXT: extsb 4, 4
76 ; CHECK-P9-NOALTIVEC-NEXT: blr
77 ;
78 ; CHECK-P8-LABEL: test_vextsb2d:
79 ; CHECK-P8: # %bb.0: # %entry
80 ; CHECK-P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha
81 ; CHECK-P8-NEXT: addi 3, 3, .LCPI2_0@toc@l
82 ; CHECK-P8-NEXT: lxvd2x 35, 0, 3
83 ; CHECK-P8-NEXT: vsld 2, 2, 3
84 ; CHECK-P8-NEXT: vsrad 2, 2, 3
85 ; CHECK-P8-NEXT: blr
86 entry:
87 %shl = shl <2 x i64> %m, <i64 56, i64 56>
88 %shr = ashr exact <2 x i64> %shl, <i64 56, i64 56>
89 ret <2 x i64> %shr
90 }
92 define <2 x i64> @test_vextsh2d(<2 x i64> %m) {
93 ; CHECK-P9-LABEL: test_vextsh2d:
94 ; CHECK-P9: # %bb.0: # %entry
95 ; CHECK-P9-NEXT: vextsh2d 2, 2
96 ; CHECK-P9-NEXT: blr
97 ;
98 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2d:
99 ; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
100 ; CHECK-P9-NOALTIVEC-NEXT: extsh 3, 3
101 ; CHECK-P9-NOALTIVEC-NEXT: extsh 4, 4
102 ; CHECK-P9-NOALTIVEC-NEXT: blr
103 ;
104 ; CHECK-P8-LABEL: test_vextsh2d:
105 ; CHECK-P8: # %bb.0: # %entry
106 ; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha
107 ; CHECK-P8-NEXT: addi 3, 3, .LCPI3_0@toc@l
108 ; CHECK-P8-NEXT: lxvd2x 35, 0, 3
109 ; CHECK-P8-NEXT: vsld 2, 2, 3
110 ; CHECK-P8-NEXT: vsrad 2, 2, 3
111 ; CHECK-P8-NEXT: blr
112 entry:
113 %shl = shl <2 x i64> %m, <i64 48, i64 48>
114 %shr = ashr exact <2 x i64> %shl, <i64 48, i64 48>
115 ret <2 x i64> %shr
116 }
118 define <2 x i64> @test_vextsw2d(<2 x i64> %m) {
119 ; CHECK-P9-LABEL: test_vextsw2d:
120 ; CHECK-P9: # %bb.0: # %entry
121 ; CHECK-P9-NEXT: vextsw2d 2, 2
122 ; CHECK-P9-NEXT: blr
123 ;
124 ; CHECK-P9-NOALTIVEC-LABEL: test_vextsw2d:
125 ; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
126 ; CHECK-P9-NOALTIVEC-NEXT: extsw 3, 3
127 ; CHECK-P9-NOALTIVEC-NEXT: extsw 4, 4
128 ; CHECK-P9-NOALTIVEC-NEXT: blr
129 ;
130 ; CHECK-P8-LABEL: test_vextsw2d:
131 ; CHECK-P8: # %bb.0: # %entry
132 ; CHECK-P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha
133 ; CHECK-P8-NEXT: addi 3, 3, .LCPI4_0@toc@l
134 ; CHECK-P8-NEXT: lxvd2x 35, 0, 3
135 ; CHECK-P8-NEXT: vsld 2, 2, 3
136 ; CHECK-P8-NEXT: vsrad 2, 2, 3
137 ; CHECK-P8-NEXT: blr
138 entry:
139 %shl = shl <2 x i64> %m, <i64 32, i64 32>
140 %shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>
141 ret <2 x i64> %shr
142 }
144 define <2 x i64> @test_none(<2 x i64> %m) {
145 ; CHECK-P9-LABEL: test_none:
146 ; CHECK-P9: # %bb.0: # %entry
147 ; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha
148 ; CHECK-P9-NEXT: addi 3, 3, .LCPI5_0@toc@l
149 ; CHECK-P9-NEXT: lxv 35, 0(3)
150 ; CHECK-P9-NEXT: vsld 2, 2, 3
151 ; CHECK-P9-NEXT: vsrad 2, 2, 3
152 ; CHECK-P9-NEXT: blr
153 ;
154 ; CHECK-P9-NOALTIVEC-LABEL: test_none:
155 ; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
156 ; CHECK-P9-NOALTIVEC-NEXT: sldi 3, 3, 16
157 ; CHECK-P9-NOALTIVEC-NEXT: sldi 4, 4, 16
158 ; CHECK-P9-NOALTIVEC-NEXT: sradi 3, 3, 16
159 ; CHECK-P9-NOALTIVEC-NEXT: sradi 4, 4, 16
160 ; CHECK-P9-NOALTIVEC-NEXT: blr
161 ;
162 ; CHECK-P8-LABEL: test_none:
163 ; CHECK-P8: # %bb.0: # %entry
164 ; CHECK-P8-NEXT: addis 3, 2, .LCPI5_0@toc@ha
165 ; CHECK-P8-NEXT: addi 3, 3, .LCPI5_0@toc@l
166 ; CHECK-P8-NEXT: lxvd2x 35, 0, 3
167 ; CHECK-P8-NEXT: vsld 2, 2, 3
168 ; CHECK-P8-NEXT: vsrad 2, 2, 3
169 ; CHECK-P8-NEXT: blr
170 entry:
171 %shl = shl <2 x i64> %m, <i64 16, i64 16>
172 %shr = ashr exact <2 x i64> %shl, <i64 16, i64 16>
173 ret <2 x i64> %shr
174 }