1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select %s -o - \
3 # RUN: -code-model=small | FileCheck %s --check-prefix=RV32-SMALL
4 # RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=instruction-select %s -o - \
5 # RUN: -code-model=medium | FileCheck %s --check-prefix=RV32-MEDIUM
8 define i32 @jt_test(i32 signext %in) {
10 switch i32 %in, label %default [
37 default: ; preds = %entry
46 tracksRegLiveness: true
51 blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.6', '%bb.7' ]
53 ; RV32-SMALL-LABEL: name: jt_test
54 ; RV32-SMALL: bb.0.entry:
55 ; RV32-SMALL-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
56 ; RV32-SMALL-NEXT: liveins: $x10
57 ; RV32-SMALL-NEXT: {{ $}}
58 ; RV32-SMALL-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
59 ; RV32-SMALL-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
60 ; RV32-SMALL-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 200
61 ; RV32-SMALL-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 100
62 ; RV32-SMALL-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 1
63 ; RV32-SMALL-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 2
64 ; RV32-SMALL-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 3
65 ; RV32-SMALL-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 4
66 ; RV32-SMALL-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 1000
67 ; RV32-SMALL-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI [[COPY]], -1
68 ; RV32-SMALL-NEXT: BLTU [[ADDI]], [[ADDI8]], %bb.8
69 ; RV32-SMALL-NEXT: {{ $}}
70 ; RV32-SMALL-NEXT: bb.1.entry:
71 ; RV32-SMALL-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
72 ; RV32-SMALL-NEXT: {{ $}}
73 ; RV32-SMALL-NEXT: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %jump-table.0
74 ; RV32-SMALL-NEXT: [[ADDI9:%[0-9]+]]:gpr = ADDI [[LUI]], target-flags(riscv-lo) %jump-table.0
75 ; RV32-SMALL-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI8]], 2
76 ; RV32-SMALL-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[ADDI9]], [[SLLI]]
77 ; RV32-SMALL-NEXT: [[LW:%[0-9]+]]:gprjalr = LW [[ADD]], 0 :: (load (s32) from jump-table)
78 ; RV32-SMALL-NEXT: PseudoBRIND [[LW]], 0
79 ; RV32-SMALL-NEXT: {{ $}}
80 ; RV32-SMALL-NEXT: bb.2.bb1:
81 ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI6]]
82 ; RV32-SMALL-NEXT: PseudoRET implicit $x10
83 ; RV32-SMALL-NEXT: {{ $}}
84 ; RV32-SMALL-NEXT: bb.3.bb2:
85 ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI5]]
86 ; RV32-SMALL-NEXT: PseudoRET implicit $x10
87 ; RV32-SMALL-NEXT: {{ $}}
88 ; RV32-SMALL-NEXT: bb.4.bb3:
89 ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI4]]
90 ; RV32-SMALL-NEXT: PseudoRET implicit $x10
91 ; RV32-SMALL-NEXT: {{ $}}
92 ; RV32-SMALL-NEXT: bb.5.bb4:
93 ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI3]]
94 ; RV32-SMALL-NEXT: PseudoRET implicit $x10
95 ; RV32-SMALL-NEXT: {{ $}}
96 ; RV32-SMALL-NEXT: bb.6.bb5:
97 ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI2]]
98 ; RV32-SMALL-NEXT: PseudoRET implicit $x10
99 ; RV32-SMALL-NEXT: {{ $}}
100 ; RV32-SMALL-NEXT: bb.7.bb6:
101 ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI1]]
102 ; RV32-SMALL-NEXT: PseudoRET implicit $x10
103 ; RV32-SMALL-NEXT: {{ $}}
104 ; RV32-SMALL-NEXT: bb.8.default:
105 ; RV32-SMALL-NEXT: $x10 = COPY [[ADDI7]]
106 ; RV32-SMALL-NEXT: PseudoRET implicit $x10
108 ; RV32-MEDIUM-LABEL: name: jt_test
109 ; RV32-MEDIUM: bb.0.entry:
110 ; RV32-MEDIUM-NEXT: successors: %bb.8(0x40000000), %bb.1(0x40000000)
111 ; RV32-MEDIUM-NEXT: liveins: $x10
112 ; RV32-MEDIUM-NEXT: {{ $}}
113 ; RV32-MEDIUM-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
114 ; RV32-MEDIUM-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5
115 ; RV32-MEDIUM-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 200
116 ; RV32-MEDIUM-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 100
117 ; RV32-MEDIUM-NEXT: [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 1
118 ; RV32-MEDIUM-NEXT: [[ADDI4:%[0-9]+]]:gpr = ADDI $x0, 2
119 ; RV32-MEDIUM-NEXT: [[ADDI5:%[0-9]+]]:gpr = ADDI $x0, 3
120 ; RV32-MEDIUM-NEXT: [[ADDI6:%[0-9]+]]:gpr = ADDI $x0, 4
121 ; RV32-MEDIUM-NEXT: [[ADDI7:%[0-9]+]]:gpr = ADDI $x0, 1000
122 ; RV32-MEDIUM-NEXT: [[ADDI8:%[0-9]+]]:gpr = ADDI [[COPY]], -1
123 ; RV32-MEDIUM-NEXT: BLTU [[ADDI]], [[ADDI8]], %bb.8
124 ; RV32-MEDIUM-NEXT: {{ $}}
125 ; RV32-MEDIUM-NEXT: bb.1.entry:
126 ; RV32-MEDIUM-NEXT: successors: %bb.2(0x15555555), %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.6(0x15555555), %bb.7(0x15555555)
127 ; RV32-MEDIUM-NEXT: {{ $}}
128 ; RV32-MEDIUM-NEXT: [[PseudoLLA:%[0-9]+]]:gpr = PseudoLLA %jump-table.0
129 ; RV32-MEDIUM-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI8]], 2
130 ; RV32-MEDIUM-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PseudoLLA]], [[SLLI]]
131 ; RV32-MEDIUM-NEXT: [[LW:%[0-9]+]]:gprjalr = LW [[ADD]], 0 :: (load (s32) from jump-table)
132 ; RV32-MEDIUM-NEXT: PseudoBRIND [[LW]], 0
133 ; RV32-MEDIUM-NEXT: {{ $}}
134 ; RV32-MEDIUM-NEXT: bb.2.bb1:
135 ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI6]]
136 ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
137 ; RV32-MEDIUM-NEXT: {{ $}}
138 ; RV32-MEDIUM-NEXT: bb.3.bb2:
139 ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI5]]
140 ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
141 ; RV32-MEDIUM-NEXT: {{ $}}
142 ; RV32-MEDIUM-NEXT: bb.4.bb3:
143 ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI4]]
144 ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
145 ; RV32-MEDIUM-NEXT: {{ $}}
146 ; RV32-MEDIUM-NEXT: bb.5.bb4:
147 ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI3]]
148 ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
149 ; RV32-MEDIUM-NEXT: {{ $}}
150 ; RV32-MEDIUM-NEXT: bb.6.bb5:
151 ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI2]]
152 ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
153 ; RV32-MEDIUM-NEXT: {{ $}}
154 ; RV32-MEDIUM-NEXT: bb.7.bb6:
155 ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI1]]
156 ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
157 ; RV32-MEDIUM-NEXT: {{ $}}
158 ; RV32-MEDIUM-NEXT: bb.8.default:
159 ; RV32-MEDIUM-NEXT: $x10 = COPY [[ADDI7]]
160 ; RV32-MEDIUM-NEXT: PseudoRET implicit $x10
162 successors: %bb.8, %bb.9
165 %0:gprb(s32) = COPY $x10
166 %4:gprb(s32) = G_CONSTANT i32 5
167 %8:gprb(s32) = G_CONSTANT i32 200
168 %9:gprb(s32) = G_CONSTANT i32 100
169 %10:gprb(s32) = G_CONSTANT i32 1
170 %11:gprb(s32) = G_CONSTANT i32 2
171 %12:gprb(s32) = G_CONSTANT i32 3
172 %13:gprb(s32) = G_CONSTANT i32 4
173 %14:gprb(s32) = G_CONSTANT i32 1000
174 %1:gprb(s32) = G_CONSTANT i32 1
175 %2:gprb(s32) = G_SUB %0, %1
176 %16:gprb(s32) = G_ICMP intpred(ugt), %2(s32), %4
177 G_BRCOND %16(s32), %bb.8
180 successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.6, %bb.7
182 %7:gprb(p0) = G_JUMP_TABLE %jump-table.0
183 G_BRJT %7(p0), %jump-table.0, %2(s32)
187 PseudoRET implicit $x10
191 PseudoRET implicit $x10
195 PseudoRET implicit $x10
199 PseudoRET implicit $x10
203 PseudoRET implicit $x10
207 PseudoRET implicit $x10
211 PseudoRET implicit $x10