[llvm-project.git] / llvm / test / CodeGen / RISCV / GlobalISel / irtranslator / calling-conv-half.ll
| blob | 04fa62b195076334a18fce229b8ab0f8348bdd2f |
1 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2 ; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV32I %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+f -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefix=RV32IF %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
7 ; RUN: | FileCheck -check-prefix=RV32IZFH %s
8 ; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefix=RV64I %s
10 ; RUN: llc -mtriple=riscv64 -mattr=+f -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
11 ; RUN: | FileCheck -check-prefix=RV64IF %s
12 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
13 ; RUN: | FileCheck -check-prefix=RV64IZFH %s
15 define half @callee_half_in_regs(half %x) nounwind {
16 ; RV32I-LABEL: name: callee_half_in_regs
17 ; RV32I: bb.1 (%ir-block.0):
18 ; RV32I-NEXT: liveins: $x10
19 ; RV32I-NEXT: {{ $}}
20 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
21 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
22 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
23 ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
24 ; RV32I-NEXT: PseudoRET implicit $x10
25 ;
26 ; RV32IF-LABEL: name: callee_half_in_regs
27 ; RV32IF: bb.1 (%ir-block.0):
28 ; RV32IF-NEXT: liveins: $f10_f
29 ; RV32IF-NEXT: {{ $}}
30 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
31 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
32 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
33 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
34 ; RV32IF-NEXT: PseudoRET implicit $f10_f
35 ;
36 ; RV32IZFH-LABEL: name: callee_half_in_regs
37 ; RV32IZFH: bb.1 (%ir-block.0):
38 ; RV32IZFH-NEXT: liveins: $f10_h
39 ; RV32IZFH-NEXT: {{ $}}
40 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
41 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
42 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
43 ;
44 ; RV64I-LABEL: name: callee_half_in_regs
45 ; RV64I: bb.1 (%ir-block.0):
46 ; RV64I-NEXT: liveins: $x10
47 ; RV64I-NEXT: {{ $}}
48 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
49 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
50 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
51 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
52 ; RV64I-NEXT: PseudoRET implicit $x10
53 ;
54 ; RV64IF-LABEL: name: callee_half_in_regs
55 ; RV64IF: bb.1 (%ir-block.0):
56 ; RV64IF-NEXT: liveins: $f10_f
57 ; RV64IF-NEXT: {{ $}}
58 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
59 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
60 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
61 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
62 ; RV64IF-NEXT: PseudoRET implicit $f10_f
63 ;
64 ; RV64IZFH-LABEL: name: callee_half_in_regs
65 ; RV64IZFH: bb.1 (%ir-block.0):
66 ; RV64IZFH-NEXT: liveins: $f10_h
67 ; RV64IZFH-NEXT: {{ $}}
68 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
69 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
70 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
71 ret half %x
72 }
74 define half @caller_half_in_regs(half %x) nounwind {
75 ; RV32I-LABEL: name: caller_half_in_regs
76 ; RV32I: bb.1 (%ir-block.0):
77 ; RV32I-NEXT: liveins: $x10
78 ; RV32I-NEXT: {{ $}}
79 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
80 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
81 ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
82 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
83 ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
84 ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10
85 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
86 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
87 ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
88 ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
89 ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
90 ; RV32I-NEXT: PseudoRET implicit $x10
91 ;
92 ; RV32IF-LABEL: name: caller_half_in_regs
93 ; RV32IF: bb.1 (%ir-block.0):
94 ; RV32IF-NEXT: liveins: $f10_f
95 ; RV32IF-NEXT: {{ $}}
96 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
97 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
98 ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
99 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
100 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
101 ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit-def $f10_f
102 ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
103 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
104 ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
105 ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
106 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
107 ; RV32IF-NEXT: PseudoRET implicit $f10_f
108 ;
109 ; RV32IZFH-LABEL: name: caller_half_in_regs
110 ; RV32IZFH: bb.1 (%ir-block.0):
111 ; RV32IZFH-NEXT: liveins: $f10_h
112 ; RV32IZFH-NEXT: {{ $}}
113 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
114 ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
115 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
116 ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit-def $f10_h
117 ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
118 ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
119 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
120 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
121 ;
122 ; RV64I-LABEL: name: caller_half_in_regs
123 ; RV64I: bb.1 (%ir-block.0):
124 ; RV64I-NEXT: liveins: $x10
125 ; RV64I-NEXT: {{ $}}
126 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
127 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
128 ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
129 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
130 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
131 ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10
132 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
133 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
134 ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
135 ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
136 ; RV64I-NEXT: $x10 = COPY [[ANYEXT1]](s64)
137 ; RV64I-NEXT: PseudoRET implicit $x10
138 ;
139 ; RV64IF-LABEL: name: caller_half_in_regs
140 ; RV64IF: bb.1 (%ir-block.0):
141 ; RV64IF-NEXT: liveins: $f10_f
142 ; RV64IF-NEXT: {{ $}}
143 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
144 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
145 ; RV64IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
146 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
147 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
148 ; RV64IF-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit-def $f10_f
149 ; RV64IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
150 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
151 ; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
152 ; RV64IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
153 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
154 ; RV64IF-NEXT: PseudoRET implicit $f10_f
155 ;
156 ; RV64IZFH-LABEL: name: caller_half_in_regs
157 ; RV64IZFH: bb.1 (%ir-block.0):
158 ; RV64IZFH-NEXT: liveins: $f10_h
159 ; RV64IZFH-NEXT: {{ $}}
160 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
161 ; RV64IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
162 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
163 ; RV64IZFH-NEXT: PseudoCALL target-flags(riscv-call) @caller_half_in_regs, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit-def $f10_h
164 ; RV64IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
165 ; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
166 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
167 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
168 %y = call half @caller_half_in_regs(half %x)
169 ret half %y
170 }
172 define half @callee_half_mixed_with_int(i32 %x0, half %x) nounwind {
173 ; RV32I-LABEL: name: callee_half_mixed_with_int
174 ; RV32I: bb.1 (%ir-block.0):
175 ; RV32I-NEXT: liveins: $x10, $x11
176 ; RV32I-NEXT: {{ $}}
177 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
178 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
179 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
180 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
181 ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
182 ; RV32I-NEXT: PseudoRET implicit $x10
183 ;
184 ; RV32IF-LABEL: name: callee_half_mixed_with_int
185 ; RV32IF: bb.1 (%ir-block.0):
186 ; RV32IF-NEXT: liveins: $x10, $f10_f
187 ; RV32IF-NEXT: {{ $}}
188 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
189 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
190 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
191 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
192 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
193 ; RV32IF-NEXT: PseudoRET implicit $f10_f
194 ;
195 ; RV32IZFH-LABEL: name: callee_half_mixed_with_int
196 ; RV32IZFH: bb.1 (%ir-block.0):
197 ; RV32IZFH-NEXT: liveins: $x10, $f10_h
198 ; RV32IZFH-NEXT: {{ $}}
199 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
200 ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
201 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
202 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
203 ;
204 ; RV64I-LABEL: name: callee_half_mixed_with_int
205 ; RV64I: bb.1 (%ir-block.0):
206 ; RV64I-NEXT: liveins: $x10, $x11
207 ; RV64I-NEXT: {{ $}}
208 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
209 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
210 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
211 ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
212 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
213 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
214 ; RV64I-NEXT: PseudoRET implicit $x10
215 ;
216 ; RV64IF-LABEL: name: callee_half_mixed_with_int
217 ; RV64IF: bb.1 (%ir-block.0):
218 ; RV64IF-NEXT: liveins: $x10, $f10_f
219 ; RV64IF-NEXT: {{ $}}
220 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
221 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
222 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
223 ; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
224 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
225 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
226 ; RV64IF-NEXT: PseudoRET implicit $f10_f
227 ;
228 ; RV64IZFH-LABEL: name: callee_half_mixed_with_int
229 ; RV64IZFH: bb.1 (%ir-block.0):
230 ; RV64IZFH-NEXT: liveins: $x10, $f10_h
231 ; RV64IZFH-NEXT: {{ $}}
232 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
233 ; RV64IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
234 ; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
235 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
236 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
237 ret half %x
238 }
240 define half @caller_half_mixed_with_int(half %x, i32 %x0) nounwind {
241 ; RV32I-LABEL: name: caller_half_mixed_with_int
242 ; RV32I: bb.1 (%ir-block.0):
243 ; RV32I-NEXT: liveins: $x10, $x11
244 ; RV32I-NEXT: {{ $}}
245 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
246 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
247 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
248 ; RV32I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
249 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
250 ; RV32I-NEXT: $x10 = COPY [[COPY1]](s32)
251 ; RV32I-NEXT: $x11 = COPY [[ANYEXT]](s32)
252 ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
253 ; RV32I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
254 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
255 ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
256 ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
257 ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
258 ; RV32I-NEXT: PseudoRET implicit $x10
259 ;
260 ; RV32IF-LABEL: name: caller_half_mixed_with_int
261 ; RV32IF: bb.1 (%ir-block.0):
262 ; RV32IF-NEXT: liveins: $x10, $f10_f
263 ; RV32IF-NEXT: {{ $}}
264 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
265 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
266 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
267 ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
268 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
269 ; RV32IF-NEXT: $x10 = COPY [[COPY1]](s32)
270 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
271 ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $f10_f
272 ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
273 ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
274 ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
275 ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
276 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
277 ; RV32IF-NEXT: PseudoRET implicit $f10_f
278 ;
279 ; RV32IZFH-LABEL: name: caller_half_mixed_with_int
280 ; RV32IZFH: bb.1 (%ir-block.0):
281 ; RV32IZFH-NEXT: liveins: $x10, $f10_h
282 ; RV32IZFH-NEXT: {{ $}}
283 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
284 ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
285 ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
286 ; RV32IZFH-NEXT: $x10 = COPY [[COPY1]](s32)
287 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
288 ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_h, implicit-def $f10_h
289 ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
290 ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
291 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
292 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
293 ;
294 ; RV64I-LABEL: name: caller_half_mixed_with_int
295 ; RV64I: bb.1 (%ir-block.0):
296 ; RV64I-NEXT: liveins: $x10, $x11
297 ; RV64I-NEXT: {{ $}}
298 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
299 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
300 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
301 ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
302 ; RV64I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
303 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s32)
304 ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
305 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
306 ; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64)
307 ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
308 ; RV64I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
309 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
310 ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s64)
311 ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s16)
312 ; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
313 ; RV64I-NEXT: PseudoRET implicit $x10
314 ;
315 ; RV64IF-LABEL: name: caller_half_mixed_with_int
316 ; RV64IF: bb.1 (%ir-block.0):
317 ; RV64IF-NEXT: liveins: $x10, $f10_f
318 ; RV64IF-NEXT: {{ $}}
319 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
320 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
321 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
322 ; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
323 ; RV64IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
324 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s32)
325 ; RV64IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
326 ; RV64IF-NEXT: $x10 = COPY [[ANYEXT]](s64)
327 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
328 ; RV64IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_f, implicit-def $f10_f
329 ; RV64IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
330 ; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
331 ; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
332 ; RV64IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
333 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT2]](s32)
334 ; RV64IF-NEXT: PseudoRET implicit $f10_f
335 ;
336 ; RV64IZFH-LABEL: name: caller_half_mixed_with_int
337 ; RV64IZFH: bb.1 (%ir-block.0):
338 ; RV64IZFH-NEXT: liveins: $x10, $f10_h
339 ; RV64IZFH-NEXT: {{ $}}
340 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
341 ; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
342 ; RV64IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
343 ; RV64IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
344 ; RV64IZFH-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
345 ; RV64IZFH-NEXT: $x10 = COPY [[ANYEXT]](s64)
346 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
347 ; RV64IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_mixed_with_int, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $f10_h, implicit-def $f10_h
348 ; RV64IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
349 ; RV64IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
350 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
351 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
352 %y = call half @callee_half_mixed_with_int(i32 %x0, half %x)
353 ret half %y
354 }
356 define half @callee_half_return_stack1(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, i32 %v6, i32 %v7, i32 %v8, half %x) nounwind {
357 ; RV32I-LABEL: name: callee_half_return_stack1
358 ; RV32I: bb.1 (%ir-block.0):
359 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
360 ; RV32I-NEXT: {{ $}}
361 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
362 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
363 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
364 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
365 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
366 ; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
367 ; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
368 ; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
369 ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
370 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)
371 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
372 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
373 ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
374 ; RV32I-NEXT: PseudoRET implicit $x10
375 ;
376 ; RV32IF-LABEL: name: callee_half_return_stack1
377 ; RV32IF: bb.1 (%ir-block.0):
378 ; RV32IF-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f
379 ; RV32IF-NEXT: {{ $}}
380 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
381 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
382 ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
383 ; RV32IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
384 ; RV32IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
385 ; RV32IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
386 ; RV32IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
387 ; RV32IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
388 ; RV32IF-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $f10_f
389 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
390 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
391 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
392 ; RV32IF-NEXT: PseudoRET implicit $f10_f
393 ;
394 ; RV32IZFH-LABEL: name: callee_half_return_stack1
395 ; RV32IZFH: bb.1 (%ir-block.0):
396 ; RV32IZFH-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_h
397 ; RV32IZFH-NEXT: {{ $}}
398 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
399 ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
400 ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
401 ; RV32IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
402 ; RV32IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
403 ; RV32IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
404 ; RV32IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
405 ; RV32IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
406 ; RV32IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s16) = COPY $f10_h
407 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY8]](s16)
408 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
409 ;
410 ; RV64I-LABEL: name: callee_half_return_stack1
411 ; RV64I: bb.1 (%ir-block.0):
412 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
413 ; RV64I-NEXT: {{ $}}
414 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
415 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
416 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
417 ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
418 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
419 ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
420 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
421 ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
422 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
423 ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
424 ; RV64I-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
425 ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY5]](s64)
426 ; RV64I-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
427 ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY6]](s64)
428 ; RV64I-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
429 ; RV64I-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY7]](s64)
430 ; RV64I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
431 ; RV64I-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0, align 16)
432 ; RV64I-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s64)
433 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC8]](s16)
434 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
435 ; RV64I-NEXT: PseudoRET implicit $x10
436 ;
437 ; RV64IF-LABEL: name: callee_half_return_stack1
438 ; RV64IF: bb.1 (%ir-block.0):
439 ; RV64IF-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_f
440 ; RV64IF-NEXT: {{ $}}
441 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
442 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
443 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
444 ; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
445 ; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
446 ; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
447 ; RV64IF-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
448 ; RV64IF-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
449 ; RV64IF-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
450 ; RV64IF-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
451 ; RV64IF-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
452 ; RV64IF-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY5]](s64)
453 ; RV64IF-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
454 ; RV64IF-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY6]](s64)
455 ; RV64IF-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
456 ; RV64IF-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY7]](s64)
457 ; RV64IF-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $f10_f
458 ; RV64IF-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
459 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16)
460 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
461 ; RV64IF-NEXT: PseudoRET implicit $f10_f
462 ;
463 ; RV64IZFH-LABEL: name: callee_half_return_stack1
464 ; RV64IZFH: bb.1 (%ir-block.0):
465 ; RV64IZFH-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_h
466 ; RV64IZFH-NEXT: {{ $}}
467 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
468 ; RV64IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
469 ; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
470 ; RV64IZFH-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
471 ; RV64IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
472 ; RV64IZFH-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
473 ; RV64IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
474 ; RV64IZFH-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
475 ; RV64IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
476 ; RV64IZFH-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
477 ; RV64IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
478 ; RV64IZFH-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY5]](s64)
479 ; RV64IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
480 ; RV64IZFH-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY6]](s64)
481 ; RV64IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
482 ; RV64IZFH-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY7]](s64)
483 ; RV64IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s16) = COPY $f10_h
484 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY8]](s16)
485 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
486 ret half %x
487 }
489 define half @caller_half_return_stack1(i32 %v1, half %x) nounwind {
490 ; RV32I-LABEL: name: caller_half_return_stack1
491 ; RV32I: bb.1 (%ir-block.0):
492 ; RV32I-NEXT: liveins: $x10, $x11
493 ; RV32I-NEXT: {{ $}}
494 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
495 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
496 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
497 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
498 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
499 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
500 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
501 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
502 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
503 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
504 ; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2
505 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
506 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
507 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
508 ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C7]](s32)
509 ; RV32I-NEXT: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
510 ; RV32I-NEXT: $x10 = COPY [[C]](s32)
511 ; RV32I-NEXT: $x11 = COPY [[C1]](s32)
512 ; RV32I-NEXT: $x12 = COPY [[C2]](s32)
513 ; RV32I-NEXT: $x13 = COPY [[COPY]](s32)
514 ; RV32I-NEXT: $x14 = COPY [[C3]](s32)
515 ; RV32I-NEXT: $x15 = COPY [[C4]](s32)
516 ; RV32I-NEXT: $x16 = COPY [[C5]](s32)
517 ; RV32I-NEXT: $x17 = COPY [[C6]](s32)
518 ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
519 ; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2
520 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
521 ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
522 ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
523 ; RV32I-NEXT: $x10 = COPY [[ANYEXT1]](s32)
524 ; RV32I-NEXT: PseudoRET implicit $x10
525 ;
526 ; RV32IF-LABEL: name: caller_half_return_stack1
527 ; RV32IF: bb.1 (%ir-block.0):
528 ; RV32IF-NEXT: liveins: $x10, $f10_f
529 ; RV32IF-NEXT: {{ $}}
530 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
531 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
532 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
533 ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
534 ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
535 ; RV32IF-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
536 ; RV32IF-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
537 ; RV32IF-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
538 ; RV32IF-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
539 ; RV32IF-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
540 ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
541 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
542 ; RV32IF-NEXT: $x10 = COPY [[C]](s32)
543 ; RV32IF-NEXT: $x11 = COPY [[C1]](s32)
544 ; RV32IF-NEXT: $x12 = COPY [[C2]](s32)
545 ; RV32IF-NEXT: $x13 = COPY [[COPY]](s32)
546 ; RV32IF-NEXT: $x14 = COPY [[C3]](s32)
547 ; RV32IF-NEXT: $x15 = COPY [[C4]](s32)
548 ; RV32IF-NEXT: $x16 = COPY [[C5]](s32)
549 ; RV32IF-NEXT: $x17 = COPY [[C6]](s32)
550 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
551 ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $f10_f
552 ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
553 ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
554 ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
555 ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
556 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT1]](s32)
557 ; RV32IF-NEXT: PseudoRET implicit $f10_f
558 ;
559 ; RV32IZFH-LABEL: name: caller_half_return_stack1
560 ; RV32IZFH: bb.1 (%ir-block.0):
561 ; RV32IZFH-NEXT: liveins: $x10, $f10_h
562 ; RV32IZFH-NEXT: {{ $}}
563 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
564 ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
565 ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
566 ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
567 ; RV32IZFH-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
568 ; RV32IZFH-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
569 ; RV32IZFH-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
570 ; RV32IZFH-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
571 ; RV32IZFH-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
572 ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
573 ; RV32IZFH-NEXT: $x10 = COPY [[C]](s32)
574 ; RV32IZFH-NEXT: $x11 = COPY [[C1]](s32)
575 ; RV32IZFH-NEXT: $x12 = COPY [[C2]](s32)
576 ; RV32IZFH-NEXT: $x13 = COPY [[COPY]](s32)
577 ; RV32IZFH-NEXT: $x14 = COPY [[C3]](s32)
578 ; RV32IZFH-NEXT: $x15 = COPY [[C4]](s32)
579 ; RV32IZFH-NEXT: $x16 = COPY [[C5]](s32)
580 ; RV32IZFH-NEXT: $x17 = COPY [[C6]](s32)
581 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
582 ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_h, implicit-def $f10_h
583 ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
584 ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
585 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
586 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
587 ;
588 ; RV64I-LABEL: name: caller_half_return_stack1
589 ; RV64I: bb.1 (%ir-block.0):
590 ; RV64I-NEXT: liveins: $x10, $x11
591 ; RV64I-NEXT: {{ $}}
592 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
593 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
594 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
595 ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
596 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
597 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
598 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
599 ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
600 ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
601 ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
602 ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
603 ; RV64I-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2
604 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
605 ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
606 ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32)
607 ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
608 ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32)
609 ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32)
610 ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
611 ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32)
612 ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
613 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
614 ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
615 ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C7]](s64)
616 ; RV64I-NEXT: G_STORE [[ANYEXT8]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
617 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
618 ; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64)
619 ; RV64I-NEXT: $x12 = COPY [[ANYEXT2]](s64)
620 ; RV64I-NEXT: $x13 = COPY [[ANYEXT3]](s64)
621 ; RV64I-NEXT: $x14 = COPY [[ANYEXT4]](s64)
622 ; RV64I-NEXT: $x15 = COPY [[ANYEXT5]](s64)
623 ; RV64I-NEXT: $x16 = COPY [[ANYEXT6]](s64)
624 ; RV64I-NEXT: $x17 = COPY [[ANYEXT7]](s64)
625 ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
626 ; RV64I-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2
627 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
628 ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s64)
629 ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s16)
630 ; RV64I-NEXT: $x10 = COPY [[ANYEXT9]](s64)
631 ; RV64I-NEXT: PseudoRET implicit $x10
632 ;
633 ; RV64IF-LABEL: name: caller_half_return_stack1
634 ; RV64IF: bb.1 (%ir-block.0):
635 ; RV64IF-NEXT: liveins: $x10, $f10_f
636 ; RV64IF-NEXT: {{ $}}
637 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
638 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
639 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f10_f
640 ; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
641 ; RV64IF-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
642 ; RV64IF-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
643 ; RV64IF-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
644 ; RV64IF-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
645 ; RV64IF-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
646 ; RV64IF-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
647 ; RV64IF-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
648 ; RV64IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
649 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
650 ; RV64IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
651 ; RV64IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32)
652 ; RV64IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
653 ; RV64IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32)
654 ; RV64IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32)
655 ; RV64IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
656 ; RV64IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32)
657 ; RV64IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
658 ; RV64IF-NEXT: $x10 = COPY [[ANYEXT]](s64)
659 ; RV64IF-NEXT: $x11 = COPY [[ANYEXT1]](s64)
660 ; RV64IF-NEXT: $x12 = COPY [[ANYEXT2]](s64)
661 ; RV64IF-NEXT: $x13 = COPY [[ANYEXT3]](s64)
662 ; RV64IF-NEXT: $x14 = COPY [[ANYEXT4]](s64)
663 ; RV64IF-NEXT: $x15 = COPY [[ANYEXT5]](s64)
664 ; RV64IF-NEXT: $x16 = COPY [[ANYEXT6]](s64)
665 ; RV64IF-NEXT: $x17 = COPY [[ANYEXT7]](s64)
666 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT8]](s32)
667 ; RV64IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_f, implicit-def $f10_f
668 ; RV64IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
669 ; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
670 ; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
671 ; RV64IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
672 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT9]](s32)
673 ; RV64IF-NEXT: PseudoRET implicit $f10_f
674 ;
675 ; RV64IZFH-LABEL: name: caller_half_return_stack1
676 ; RV64IZFH: bb.1 (%ir-block.0):
677 ; RV64IZFH-NEXT: liveins: $x10, $f10_h
678 ; RV64IZFH-NEXT: {{ $}}
679 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
680 ; RV64IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
681 ; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f10_h
682 ; RV64IZFH-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
683 ; RV64IZFH-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
684 ; RV64IZFH-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
685 ; RV64IZFH-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
686 ; RV64IZFH-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
687 ; RV64IZFH-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
688 ; RV64IZFH-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
689 ; RV64IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
690 ; RV64IZFH-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
691 ; RV64IZFH-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)
692 ; RV64IZFH-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32)
693 ; RV64IZFH-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s32)
694 ; RV64IZFH-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32)
695 ; RV64IZFH-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32)
696 ; RV64IZFH-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32)
697 ; RV64IZFH-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32)
698 ; RV64IZFH-NEXT: $x10 = COPY [[ANYEXT]](s64)
699 ; RV64IZFH-NEXT: $x11 = COPY [[ANYEXT1]](s64)
700 ; RV64IZFH-NEXT: $x12 = COPY [[ANYEXT2]](s64)
701 ; RV64IZFH-NEXT: $x13 = COPY [[ANYEXT3]](s64)
702 ; RV64IZFH-NEXT: $x14 = COPY [[ANYEXT4]](s64)
703 ; RV64IZFH-NEXT: $x15 = COPY [[ANYEXT5]](s64)
704 ; RV64IZFH-NEXT: $x16 = COPY [[ANYEXT6]](s64)
705 ; RV64IZFH-NEXT: $x17 = COPY [[ANYEXT7]](s64)
706 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY1]](s16)
707 ; RV64IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_h, implicit-def $f10_h
708 ; RV64IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
709 ; RV64IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
710 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
711 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
712 %y = call half @callee_half_return_stack1(i32 0, i32 1, i32 2, i32 %v1, i32 5, i32 6, i32 7, i32 8, half %x)
713 ret half %y
714 }
716 define half @callee_half_return_stack2(half %v1, half %v2, half %v3, half %v4, half %v5, half %v6, half %v7, half %v8, half %x) nounwind {
717 ; RV32I-LABEL: name: callee_half_return_stack2
718 ; RV32I: bb.1 (%ir-block.0):
719 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
720 ; RV32I-NEXT: {{ $}}
721 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
722 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
723 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
724 ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
725 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
726 ; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
727 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
728 ; RV32I-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
729 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
730 ; RV32I-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
731 ; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
732 ; RV32I-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
733 ; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
734 ; RV32I-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
735 ; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
736 ; RV32I-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32)
737 ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
738 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)
739 ; RV32I-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s32)
740 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16)
741 ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
742 ; RV32I-NEXT: PseudoRET implicit $x10
743 ;
744 ; RV32IF-LABEL: name: callee_half_return_stack2
745 ; RV32IF: bb.1 (%ir-block.0):
746 ; RV32IF-NEXT: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
747 ; RV32IF-NEXT: {{ $}}
748 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
749 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
750 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
751 ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
752 ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
753 ; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
754 ; RV32IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
755 ; RV32IF-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
756 ; RV32IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
757 ; RV32IF-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
758 ; RV32IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
759 ; RV32IF-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
760 ; RV32IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
761 ; RV32IF-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
762 ; RV32IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
763 ; RV32IF-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32)
764 ; RV32IF-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
765 ; RV32IF-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
766 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16)
767 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
768 ; RV32IF-NEXT: PseudoRET implicit $f10_f
769 ;
770 ; RV32IZFH-LABEL: name: callee_half_return_stack2
771 ; RV32IZFH: bb.1 (%ir-block.0):
772 ; RV32IZFH-NEXT: liveins: $x10, $f10_h, $f11_h, $f12_h, $f13_h, $f14_h, $f15_h, $f16_h, $f17_h
773 ; RV32IZFH-NEXT: {{ $}}
774 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
775 ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
776 ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f12_h
777 ; RV32IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY $f13_h
778 ; RV32IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s16) = COPY $f14_h
779 ; RV32IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s16) = COPY $f15_h
780 ; RV32IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s16) = COPY $f16_h
781 ; RV32IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s16) = COPY $f17_h
782 ; RV32IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
783 ; RV32IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s32)
784 ; RV32IZFH-NEXT: $f10_h = COPY [[TRUNC]](s16)
785 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
786 ;
787 ; RV64I-LABEL: name: callee_half_return_stack2
788 ; RV64I: bb.1 (%ir-block.0):
789 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17
790 ; RV64I-NEXT: {{ $}}
791 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
792 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
793 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
794 ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
795 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12
796 ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s64)
797 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13
798 ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s64)
799 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14
800 ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s64)
801 ; RV64I-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15
802 ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s64)
803 ; RV64I-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16
804 ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s64)
805 ; RV64I-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17
806 ; RV64I-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s64)
807 ; RV64I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
808 ; RV64I-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0, align 16)
809 ; RV64I-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD]](s64)
810 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC8]](s16)
811 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
812 ; RV64I-NEXT: PseudoRET implicit $x10
813 ;
814 ; RV64IF-LABEL: name: callee_half_return_stack2
815 ; RV64IF: bb.1 (%ir-block.0):
816 ; RV64IF-NEXT: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f, $f14_f, $f15_f, $f16_f, $f17_f
817 ; RV64IF-NEXT: {{ $}}
818 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
819 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
820 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
821 ; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
822 ; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f12_f
823 ; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
824 ; RV64IF-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $f13_f
825 ; RV64IF-NEXT: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
826 ; RV64IF-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $f14_f
827 ; RV64IF-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
828 ; RV64IF-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $f15_f
829 ; RV64IF-NEXT: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
830 ; RV64IF-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $f16_f
831 ; RV64IF-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
832 ; RV64IF-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $f17_f
833 ; RV64IF-NEXT: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s32)
834 ; RV64IF-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
835 ; RV64IF-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s64)
836 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC8]](s16)
837 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
838 ; RV64IF-NEXT: PseudoRET implicit $f10_f
839 ;
840 ; RV64IZFH-LABEL: name: callee_half_return_stack2
841 ; RV64IZFH: bb.1 (%ir-block.0):
842 ; RV64IZFH-NEXT: liveins: $x10, $f10_h, $f11_h, $f12_h, $f13_h, $f14_h, $f15_h, $f16_h, $f17_h
843 ; RV64IZFH-NEXT: {{ $}}
844 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
845 ; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
846 ; RV64IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f12_h
847 ; RV64IZFH-NEXT: [[COPY3:%[0-9]+]]:_(s16) = COPY $f13_h
848 ; RV64IZFH-NEXT: [[COPY4:%[0-9]+]]:_(s16) = COPY $f14_h
849 ; RV64IZFH-NEXT: [[COPY5:%[0-9]+]]:_(s16) = COPY $f15_h
850 ; RV64IZFH-NEXT: [[COPY6:%[0-9]+]]:_(s16) = COPY $f16_h
851 ; RV64IZFH-NEXT: [[COPY7:%[0-9]+]]:_(s16) = COPY $f17_h
852 ; RV64IZFH-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $x10
853 ; RV64IZFH-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY8]](s64)
854 ; RV64IZFH-NEXT: $f10_h = COPY [[TRUNC]](s16)
855 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
856 ret half %x
857 }
859 define half @caller_half_return_stack2(half %x, half %y) nounwind {
860 ; RV32I-LABEL: name: caller_half_return_stack2
861 ; RV32I: bb.1 (%ir-block.0):
862 ; RV32I-NEXT: liveins: $x10, $x11
863 ; RV32I-NEXT: {{ $}}
864 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
865 ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
866 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
867 ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
868 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
869 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
870 ; RV32I-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2
871 ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
872 ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
873 ; RV32I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
874 ; RV32I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
875 ; RV32I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
876 ; RV32I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
877 ; RV32I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
878 ; RV32I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
879 ; RV32I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
880 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
881 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
882 ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s32)
883 ; RV32I-NEXT: G_STORE [[ANYEXT8]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
884 ; RV32I-NEXT: $x10 = COPY [[ANYEXT]](s32)
885 ; RV32I-NEXT: $x11 = COPY [[ANYEXT1]](s32)
886 ; RV32I-NEXT: $x12 = COPY [[ANYEXT2]](s32)
887 ; RV32I-NEXT: $x13 = COPY [[ANYEXT3]](s32)
888 ; RV32I-NEXT: $x14 = COPY [[ANYEXT4]](s32)
889 ; RV32I-NEXT: $x15 = COPY [[ANYEXT5]](s32)
890 ; RV32I-NEXT: $x16 = COPY [[ANYEXT6]](s32)
891 ; RV32I-NEXT: $x17 = COPY [[ANYEXT7]](s32)
892 ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
893 ; RV32I-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2
894 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x10
895 ; RV32I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
896 ; RV32I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
897 ; RV32I-NEXT: $x10 = COPY [[ANYEXT9]](s32)
898 ; RV32I-NEXT: PseudoRET implicit $x10
899 ;
900 ; RV32IF-LABEL: name: caller_half_return_stack2
901 ; RV32IF: bb.1 (%ir-block.0):
902 ; RV32IF-NEXT: liveins: $f10_f, $f11_f
903 ; RV32IF-NEXT: {{ $}}
904 ; RV32IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
905 ; RV32IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
906 ; RV32IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
907 ; RV32IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
908 ; RV32IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
909 ; RV32IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
910 ; RV32IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
911 ; RV32IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
912 ; RV32IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
913 ; RV32IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
914 ; RV32IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
915 ; RV32IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
916 ; RV32IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
917 ; RV32IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
918 ; RV32IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
919 ; RV32IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
920 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
921 ; RV32IF-NEXT: $f11_f = COPY [[ANYEXT1]](s32)
922 ; RV32IF-NEXT: $f12_f = COPY [[ANYEXT2]](s32)
923 ; RV32IF-NEXT: $f13_f = COPY [[ANYEXT3]](s32)
924 ; RV32IF-NEXT: $f14_f = COPY [[ANYEXT4]](s32)
925 ; RV32IF-NEXT: $f15_f = COPY [[ANYEXT5]](s32)
926 ; RV32IF-NEXT: $f16_f = COPY [[ANYEXT6]](s32)
927 ; RV32IF-NEXT: $f17_f = COPY [[ANYEXT7]](s32)
928 ; RV32IF-NEXT: $x10 = COPY [[ANYEXT8]](s32)
929 ; RV32IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $f10_f
930 ; RV32IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
931 ; RV32IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
932 ; RV32IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
933 ; RV32IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
934 ; RV32IF-NEXT: $f10_f = COPY [[ANYEXT9]](s32)
935 ; RV32IF-NEXT: PseudoRET implicit $f10_f
936 ;
937 ; RV32IZFH-LABEL: name: caller_half_return_stack2
938 ; RV32IZFH: bb.1 (%ir-block.0):
939 ; RV32IZFH-NEXT: liveins: $f10_h, $f11_h
940 ; RV32IZFH-NEXT: {{ $}}
941 ; RV32IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
942 ; RV32IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
943 ; RV32IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
944 ; RV32IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
945 ; RV32IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
946 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
947 ; RV32IZFH-NEXT: $f11_h = COPY [[C]](s16)
948 ; RV32IZFH-NEXT: $f12_h = COPY [[COPY]](s16)
949 ; RV32IZFH-NEXT: $f13_h = COPY [[C1]](s16)
950 ; RV32IZFH-NEXT: $f14_h = COPY [[COPY]](s16)
951 ; RV32IZFH-NEXT: $f15_h = COPY [[COPY1]](s16)
952 ; RV32IZFH-NEXT: $f16_h = COPY [[COPY1]](s16)
953 ; RV32IZFH-NEXT: $f17_h = COPY [[COPY1]](s16)
954 ; RV32IZFH-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
955 ; RV32IZFH-NEXT: $x10 = COPY [[ANYEXT]](s32)
956 ; RV32IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit $f11_h, implicit $f12_h, implicit $f13_h, implicit $f14_h, implicit $f15_h, implicit $f16_h, implicit $f17_h, implicit $x10, implicit-def $f10_h
957 ; RV32IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
958 ; RV32IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
959 ; RV32IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
960 ; RV32IZFH-NEXT: PseudoRET implicit $f10_h
961 ;
962 ; RV64I-LABEL: name: caller_half_return_stack2
963 ; RV64I: bb.1 (%ir-block.0):
964 ; RV64I-NEXT: liveins: $x10, $x11
965 ; RV64I-NEXT: {{ $}}
966 ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
967 ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
968 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
969 ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
970 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
971 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
972 ; RV64I-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2
973 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
974 ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s16)
975 ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
976 ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s16)
977 ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
978 ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
979 ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
980 ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC1]](s16)
981 ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s16)
982 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
983 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
984 ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
985 ; RV64I-NEXT: G_STORE [[ANYEXT8]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
986 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
987 ; RV64I-NEXT: $x11 = COPY [[ANYEXT1]](s64)
988 ; RV64I-NEXT: $x12 = COPY [[ANYEXT2]](s64)
989 ; RV64I-NEXT: $x13 = COPY [[ANYEXT3]](s64)
990 ; RV64I-NEXT: $x14 = COPY [[ANYEXT4]](s64)
991 ; RV64I-NEXT: $x15 = COPY [[ANYEXT5]](s64)
992 ; RV64I-NEXT: $x16 = COPY [[ANYEXT6]](s64)
993 ; RV64I-NEXT: $x17 = COPY [[ANYEXT7]](s64)
994 ; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10
995 ; RV64I-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2
996 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x10
997 ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s64)
998 ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s16)
999 ; RV64I-NEXT: $x10 = COPY [[ANYEXT9]](s64)
1000 ; RV64I-NEXT: PseudoRET implicit $x10
1001 ;
1002 ; RV64IF-LABEL: name: caller_half_return_stack2
1003 ; RV64IF: bb.1 (%ir-block.0):
1004 ; RV64IF-NEXT: liveins: $f10_f, $f11_f
1005 ; RV64IF-NEXT: {{ $}}
1006 ; RV64IF-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
1007 ; RV64IF-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
1008 ; RV64IF-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $f11_f
1009 ; RV64IF-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
1010 ; RV64IF-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
1011 ; RV64IF-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
1012 ; RV64IF-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
1013 ; RV64IF-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
1014 ; RV64IF-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
1015 ; RV64IF-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
1016 ; RV64IF-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[C1]](s16)
1017 ; RV64IF-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
1018 ; RV64IF-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
1019 ; RV64IF-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
1020 ; RV64IF-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s16)
1021 ; RV64IF-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
1022 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT]](s32)
1023 ; RV64IF-NEXT: $f11_f = COPY [[ANYEXT1]](s32)
1024 ; RV64IF-NEXT: $f12_f = COPY [[ANYEXT2]](s32)
1025 ; RV64IF-NEXT: $f13_f = COPY [[ANYEXT3]](s32)
1026 ; RV64IF-NEXT: $f14_f = COPY [[ANYEXT4]](s32)
1027 ; RV64IF-NEXT: $f15_f = COPY [[ANYEXT5]](s32)
1028 ; RV64IF-NEXT: $f16_f = COPY [[ANYEXT6]](s32)
1029 ; RV64IF-NEXT: $f17_f = COPY [[ANYEXT7]](s32)
1030 ; RV64IF-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[ANYEXT8]](s32)
1031 ; RV64IF-NEXT: $x10 = COPY [[ANYEXT9]](s64)
1032 ; RV64IF-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_f, implicit $f11_f, implicit $f12_f, implicit $f13_f, implicit $f14_f, implicit $f15_f, implicit $f16_f, implicit $f17_f, implicit $x10, implicit-def $f10_f
1033 ; RV64IF-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
1034 ; RV64IF-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $f10_f
1035 ; RV64IF-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
1036 ; RV64IF-NEXT: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s16)
1037 ; RV64IF-NEXT: $f10_f = COPY [[ANYEXT10]](s32)
1038 ; RV64IF-NEXT: PseudoRET implicit $f10_f
1039 ;
1040 ; RV64IZFH-LABEL: name: caller_half_return_stack2
1041 ; RV64IZFH: bb.1 (%ir-block.0):
1042 ; RV64IZFH-NEXT: liveins: $f10_h, $f11_h
1043 ; RV64IZFH-NEXT: {{ $}}
1044 ; RV64IZFH-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
1045 ; RV64IZFH-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
1046 ; RV64IZFH-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
1047 ; RV64IZFH-NEXT: [[C1:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH4200
1048 ; RV64IZFH-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
1049 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY]](s16)
1050 ; RV64IZFH-NEXT: $f11_h = COPY [[C]](s16)
1051 ; RV64IZFH-NEXT: $f12_h = COPY [[COPY]](s16)
1052 ; RV64IZFH-NEXT: $f13_h = COPY [[C1]](s16)
1053 ; RV64IZFH-NEXT: $f14_h = COPY [[COPY]](s16)
1054 ; RV64IZFH-NEXT: $f15_h = COPY [[COPY1]](s16)
1055 ; RV64IZFH-NEXT: $f16_h = COPY [[COPY1]](s16)
1056 ; RV64IZFH-NEXT: $f17_h = COPY [[COPY1]](s16)
1057 ; RV64IZFH-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
1058 ; RV64IZFH-NEXT: $x10 = COPY [[ANYEXT]](s64)
1059 ; RV64IZFH-NEXT: PseudoCALL target-flags(riscv-call) @callee_half_return_stack2, csr_ilp32f_lp64f, implicit-def $x1, implicit $f10_h, implicit $f11_h, implicit $f12_h, implicit $f13_h, implicit $f14_h, implicit $f15_h, implicit $f16_h, implicit $f17_h, implicit $x10, implicit-def $f10_h
1060 ; RV64IZFH-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
1061 ; RV64IZFH-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f10_h
1062 ; RV64IZFH-NEXT: $f10_h = COPY [[COPY2]](s16)
1063 ; RV64IZFH-NEXT: PseudoRET implicit $f10_h
1064 %z = call half @callee_half_return_stack2(half %x, half 1.0, half %x, half 3.0, half %x, half %y, half %y, half %y, half %x)
1065 ret half %z
1066 }