| blob | 6d90def954bdb04c0a314d0025f86d7c2649d743 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \
3 ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECK32ZFBFMIN,RV32IZFBFMIN %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfbfmin -verify-machineinstrs \
5 ; RUN: -target-abi ilp32d < %s | FileCheck -check-prefixes=CHECK32ZFBFMIN,R32IDZFBFMIN %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs \
7 ; RUN: -target-abi ilp32d < %s | FileCheck -check-prefixes=RV32ID %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \
9 ; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECK64ZFBFMIN,RV64IZFBFMIN %s
10 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfbfmin -verify-machineinstrs \
11 ; RUN: -target-abi lp64d < %s | FileCheck -check-prefixes=CHECK64ZFBFMIN,RV64IDZFBFMIN %s
12 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs \
13 ; RUN: -target-abi lp64d < %s | FileCheck -check-prefixes=RV64ID %s
15 ; These tests descend from float-arith.ll, where each function was targeted at
16 ; a particular RISC-V FPU instruction.
18 define i16 @fcvt_si_bf16(bfloat %a) nounwind {
19 ; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16:
20 ; CHECK32ZFBFMIN: # %bb.0:
21 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
22 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
23 ; CHECK32ZFBFMIN-NEXT: ret
24 ;
25 ; RV32ID-LABEL: fcvt_si_bf16:
26 ; RV32ID: # %bb.0:
27 ; RV32ID-NEXT: fmv.x.w a0, fa0
28 ; RV32ID-NEXT: slli a0, a0, 16
29 ; RV32ID-NEXT: fmv.w.x fa5, a0
30 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
31 ; RV32ID-NEXT: ret
32 ;
33 ; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16:
34 ; CHECK64ZFBFMIN: # %bb.0:
35 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
36 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
37 ; CHECK64ZFBFMIN-NEXT: ret
38 ;
39 ; RV64ID-LABEL: fcvt_si_bf16:
40 ; RV64ID: # %bb.0:
41 ; RV64ID-NEXT: fmv.x.w a0, fa0
42 ; RV64ID-NEXT: slli a0, a0, 16
43 ; RV64ID-NEXT: fmv.w.x fa5, a0
44 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
45 ; RV64ID-NEXT: ret
46 %1 = fptosi bfloat %a to i16
47 ret i16 %1
48 }
50 define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
51 ; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16_sat:
52 ; CHECK32ZFBFMIN: # %bb.0: # %start
53 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
54 ; CHECK32ZFBFMIN-NEXT: feq.s a0, fa5, fa5
55 ; CHECK32ZFBFMIN-NEXT: neg a0, a0
56 ; CHECK32ZFBFMIN-NEXT: lui a1, %hi(.LCPI1_0)
57 ; CHECK32ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
58 ; CHECK32ZFBFMIN-NEXT: lui a1, 815104
59 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa3, a1
60 ; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
61 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
62 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a1, fa5, rtz
63 ; CHECK32ZFBFMIN-NEXT: and a0, a0, a1
64 ; CHECK32ZFBFMIN-NEXT: ret
65 ;
66 ; RV32ID-LABEL: fcvt_si_bf16_sat:
67 ; RV32ID: # %bb.0: # %start
68 ; RV32ID-NEXT: fmv.x.w a0, fa0
69 ; RV32ID-NEXT: slli a0, a0, 16
70 ; RV32ID-NEXT: fmv.w.x fa5, a0
71 ; RV32ID-NEXT: feq.s a0, fa5, fa5
72 ; RV32ID-NEXT: lui a1, %hi(.LCPI1_0)
73 ; RV32ID-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
74 ; RV32ID-NEXT: lui a1, 815104
75 ; RV32ID-NEXT: fmv.w.x fa3, a1
76 ; RV32ID-NEXT: fmax.s fa5, fa5, fa3
77 ; RV32ID-NEXT: neg a0, a0
78 ; RV32ID-NEXT: fmin.s fa5, fa5, fa4
79 ; RV32ID-NEXT: fcvt.w.s a1, fa5, rtz
80 ; RV32ID-NEXT: and a0, a0, a1
81 ; RV32ID-NEXT: ret
82 ;
83 ; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16_sat:
84 ; CHECK64ZFBFMIN: # %bb.0: # %start
85 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
86 ; CHECK64ZFBFMIN-NEXT: feq.s a0, fa5, fa5
87 ; CHECK64ZFBFMIN-NEXT: neg a0, a0
88 ; CHECK64ZFBFMIN-NEXT: lui a1, %hi(.LCPI1_0)
89 ; CHECK64ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
90 ; CHECK64ZFBFMIN-NEXT: lui a1, 815104
91 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, a1
92 ; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
93 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
94 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a1, fa5, rtz
95 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
96 ; CHECK64ZFBFMIN-NEXT: ret
97 ;
98 ; RV64ID-LABEL: fcvt_si_bf16_sat:
99 ; RV64ID: # %bb.0: # %start
100 ; RV64ID-NEXT: fmv.x.w a0, fa0
101 ; RV64ID-NEXT: slli a0, a0, 16
102 ; RV64ID-NEXT: fmv.w.x fa5, a0
103 ; RV64ID-NEXT: feq.s a0, fa5, fa5
104 ; RV64ID-NEXT: lui a1, %hi(.LCPI1_0)
105 ; RV64ID-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
106 ; RV64ID-NEXT: lui a1, 815104
107 ; RV64ID-NEXT: fmv.w.x fa3, a1
108 ; RV64ID-NEXT: fmax.s fa5, fa5, fa3
109 ; RV64ID-NEXT: neg a0, a0
110 ; RV64ID-NEXT: fmin.s fa5, fa5, fa4
111 ; RV64ID-NEXT: fcvt.l.s a1, fa5, rtz
112 ; RV64ID-NEXT: and a0, a0, a1
113 ; RV64ID-NEXT: ret
114 start:
115 %0 = tail call i16 @llvm.fptosi.sat.i16.bf16(bfloat %a)
116 ret i16 %0
117 }
118 declare i16 @llvm.fptosi.sat.i16.bf16(bfloat)
120 define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
121 ; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
122 ; CHECK32ZFBFMIN: # %bb.0:
123 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
124 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
125 ; CHECK32ZFBFMIN-NEXT: ret
126 ;
127 ; RV32ID-LABEL: fcvt_ui_bf16:
128 ; RV32ID: # %bb.0:
129 ; RV32ID-NEXT: fmv.x.w a0, fa0
130 ; RV32ID-NEXT: slli a0, a0, 16
131 ; RV32ID-NEXT: fmv.w.x fa5, a0
132 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
133 ; RV32ID-NEXT: ret
134 ;
135 ; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
136 ; CHECK64ZFBFMIN: # %bb.0:
137 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
138 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
139 ; CHECK64ZFBFMIN-NEXT: ret
140 ;
141 ; RV64ID-LABEL: fcvt_ui_bf16:
142 ; RV64ID: # %bb.0:
143 ; RV64ID-NEXT: fmv.x.w a0, fa0
144 ; RV64ID-NEXT: slli a0, a0, 16
145 ; RV64ID-NEXT: fmv.w.x fa5, a0
146 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
147 ; RV64ID-NEXT: ret
148 %1 = fptoui bfloat %a to i16
149 ret i16 %1
150 }
152 define i16 @fcvt_ui_bf16_sat(bfloat %a) nounwind {
153 ; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16_sat:
154 ; CHECK32ZFBFMIN: # %bb.0: # %start
155 ; CHECK32ZFBFMIN-NEXT: lui a0, %hi(.LCPI3_0)
156 ; CHECK32ZFBFMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
157 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
158 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa3, zero
159 ; CHECK32ZFBFMIN-NEXT: fmax.s fa4, fa4, fa3
160 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa4, fa5
161 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
162 ; CHECK32ZFBFMIN-NEXT: ret
163 ;
164 ; RV32ID-LABEL: fcvt_ui_bf16_sat:
165 ; RV32ID: # %bb.0: # %start
166 ; RV32ID-NEXT: fmv.x.w a0, fa0
167 ; RV32ID-NEXT: slli a0, a0, 16
168 ; RV32ID-NEXT: lui a1, %hi(.LCPI3_0)
169 ; RV32ID-NEXT: flw fa5, %lo(.LCPI3_0)(a1)
170 ; RV32ID-NEXT: fmv.w.x fa4, a0
171 ; RV32ID-NEXT: fmv.w.x fa3, zero
172 ; RV32ID-NEXT: fmax.s fa4, fa4, fa3
173 ; RV32ID-NEXT: fmin.s fa5, fa4, fa5
174 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
175 ; RV32ID-NEXT: ret
176 ;
177 ; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16_sat:
178 ; CHECK64ZFBFMIN: # %bb.0: # %start
179 ; CHECK64ZFBFMIN-NEXT: lui a0, %hi(.LCPI3_0)
180 ; CHECK64ZFBFMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
181 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
182 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, zero
183 ; CHECK64ZFBFMIN-NEXT: fmax.s fa4, fa4, fa3
184 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa4, fa5
185 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
186 ; CHECK64ZFBFMIN-NEXT: ret
187 ;
188 ; RV64ID-LABEL: fcvt_ui_bf16_sat:
189 ; RV64ID: # %bb.0: # %start
190 ; RV64ID-NEXT: fmv.x.w a0, fa0
191 ; RV64ID-NEXT: slli a0, a0, 16
192 ; RV64ID-NEXT: lui a1, %hi(.LCPI3_0)
193 ; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a1)
194 ; RV64ID-NEXT: fmv.w.x fa4, a0
195 ; RV64ID-NEXT: fmv.w.x fa3, zero
196 ; RV64ID-NEXT: fmax.s fa4, fa4, fa3
197 ; RV64ID-NEXT: fmin.s fa5, fa4, fa5
198 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
199 ; RV64ID-NEXT: ret
200 start:
201 %0 = tail call i16 @llvm.fptoui.sat.i16.bf16(bfloat %a)
202 ret i16 %0
203 }
204 declare i16 @llvm.fptoui.sat.i16.bf16(bfloat)
206 define i32 @fcvt_w_bf16(bfloat %a) nounwind {
207 ; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16:
208 ; CHECK32ZFBFMIN: # %bb.0:
209 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
210 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
211 ; CHECK32ZFBFMIN-NEXT: ret
212 ;
213 ; RV32ID-LABEL: fcvt_w_bf16:
214 ; RV32ID: # %bb.0:
215 ; RV32ID-NEXT: fmv.x.w a0, fa0
216 ; RV32ID-NEXT: slli a0, a0, 16
217 ; RV32ID-NEXT: fmv.w.x fa5, a0
218 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
219 ; RV32ID-NEXT: ret
220 ;
221 ; CHECK64ZFBFMIN-LABEL: fcvt_w_bf16:
222 ; CHECK64ZFBFMIN: # %bb.0:
223 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
224 ; CHECK64ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
225 ; CHECK64ZFBFMIN-NEXT: ret
226 ;
227 ; RV64ID-LABEL: fcvt_w_bf16:
228 ; RV64ID: # %bb.0:
229 ; RV64ID-NEXT: fmv.x.w a0, fa0
230 ; RV64ID-NEXT: slli a0, a0, 16
231 ; RV64ID-NEXT: fmv.w.x fa5, a0
232 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
233 ; RV64ID-NEXT: ret
234 %1 = fptosi bfloat %a to i32
235 ret i32 %1
236 }
238 define i32 @fcvt_w_bf16_sat(bfloat %a) nounwind {
239 ; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16_sat:
240 ; CHECK32ZFBFMIN: # %bb.0: # %start
241 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
242 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
243 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
244 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
245 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
246 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
247 ; CHECK32ZFBFMIN-NEXT: ret
248 ;
249 ; RV32ID-LABEL: fcvt_w_bf16_sat:
250 ; RV32ID: # %bb.0: # %start
251 ; RV32ID-NEXT: fmv.x.w a0, fa0
252 ; RV32ID-NEXT: slli a0, a0, 16
253 ; RV32ID-NEXT: fmv.w.x fa5, a0
254 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
255 ; RV32ID-NEXT: feq.s a1, fa5, fa5
256 ; RV32ID-NEXT: seqz a1, a1
257 ; RV32ID-NEXT: addi a1, a1, -1
258 ; RV32ID-NEXT: and a0, a1, a0
259 ; RV32ID-NEXT: ret
260 ;
261 ; CHECK64ZFBFMIN-LABEL: fcvt_w_bf16_sat:
262 ; CHECK64ZFBFMIN: # %bb.0: # %start
263 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
264 ; CHECK64ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
265 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
266 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
267 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
268 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
269 ; CHECK64ZFBFMIN-NEXT: ret
270 ;
271 ; RV64ID-LABEL: fcvt_w_bf16_sat:
272 ; RV64ID: # %bb.0: # %start
273 ; RV64ID-NEXT: fmv.x.w a0, fa0
274 ; RV64ID-NEXT: slli a0, a0, 16
275 ; RV64ID-NEXT: fmv.w.x fa5, a0
276 ; RV64ID-NEXT: fcvt.w.s a0, fa5, rtz
277 ; RV64ID-NEXT: feq.s a1, fa5, fa5
278 ; RV64ID-NEXT: seqz a1, a1
279 ; RV64ID-NEXT: addi a1, a1, -1
280 ; RV64ID-NEXT: and a0, a1, a0
281 ; RV64ID-NEXT: ret
282 start:
283 %0 = tail call i32 @llvm.fptosi.sat.i32.bf16(bfloat %a)
284 ret i32 %0
285 }
286 declare i32 @llvm.fptosi.sat.i32.bf16(bfloat)
288 define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
289 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16:
290 ; CHECK32ZFBFMIN: # %bb.0:
291 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
292 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
293 ; CHECK32ZFBFMIN-NEXT: ret
294 ;
295 ; RV32ID-LABEL: fcvt_wu_bf16:
296 ; RV32ID: # %bb.0:
297 ; RV32ID-NEXT: fmv.x.w a0, fa0
298 ; RV32ID-NEXT: slli a0, a0, 16
299 ; RV32ID-NEXT: fmv.w.x fa5, a0
300 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
301 ; RV32ID-NEXT: ret
302 ;
303 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16:
304 ; CHECK64ZFBFMIN: # %bb.0:
305 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
306 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
307 ; CHECK64ZFBFMIN-NEXT: ret
308 ;
309 ; RV64ID-LABEL: fcvt_wu_bf16:
310 ; RV64ID: # %bb.0:
311 ; RV64ID-NEXT: fmv.x.w a0, fa0
312 ; RV64ID-NEXT: slli a0, a0, 16
313 ; RV64ID-NEXT: fmv.w.x fa5, a0
314 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
315 ; RV64ID-NEXT: ret
316 %1 = fptoui bfloat %a to i32
317 ret i32 %1
318 }
320 define i32 @fcvt_wu_bf16_multiple_use(bfloat %x, ptr %y) nounwind {
321 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
322 ; CHECK32ZFBFMIN: # %bb.0:
323 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
324 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
325 ; CHECK32ZFBFMIN-NEXT: seqz a1, a0
326 ; CHECK32ZFBFMIN-NEXT: add a0, a0, a1
327 ; CHECK32ZFBFMIN-NEXT: ret
328 ;
329 ; RV32ID-LABEL: fcvt_wu_bf16_multiple_use:
330 ; RV32ID: # %bb.0:
331 ; RV32ID-NEXT: fmv.x.w a0, fa0
332 ; RV32ID-NEXT: slli a0, a0, 16
333 ; RV32ID-NEXT: fmv.w.x fa5, a0
334 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
335 ; RV32ID-NEXT: seqz a1, a0
336 ; RV32ID-NEXT: add a0, a0, a1
337 ; RV32ID-NEXT: ret
338 ;
339 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
340 ; CHECK64ZFBFMIN: # %bb.0:
341 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
342 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
343 ; CHECK64ZFBFMIN-NEXT: seqz a1, a0
344 ; CHECK64ZFBFMIN-NEXT: add a0, a0, a1
345 ; CHECK64ZFBFMIN-NEXT: ret
346 ;
347 ; RV64ID-LABEL: fcvt_wu_bf16_multiple_use:
348 ; RV64ID: # %bb.0:
349 ; RV64ID-NEXT: fmv.x.w a0, fa0
350 ; RV64ID-NEXT: slli a0, a0, 16
351 ; RV64ID-NEXT: fmv.w.x fa5, a0
352 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
353 ; RV64ID-NEXT: seqz a1, a0
354 ; RV64ID-NEXT: add a0, a0, a1
355 ; RV64ID-NEXT: ret
356 %a = fptoui bfloat %x to i32
357 %b = icmp eq i32 %a, 0
358 %c = select i1 %b, i32 1, i32 %a
359 ret i32 %c
360 }
362 define i32 @fcvt_wu_bf16_sat(bfloat %a) nounwind {
363 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_sat:
364 ; CHECK32ZFBFMIN: # %bb.0: # %start
365 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
366 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
367 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
368 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
369 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
370 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
371 ; CHECK32ZFBFMIN-NEXT: ret
372 ;
373 ; RV32ID-LABEL: fcvt_wu_bf16_sat:
374 ; RV32ID: # %bb.0: # %start
375 ; RV32ID-NEXT: fmv.x.w a0, fa0
376 ; RV32ID-NEXT: slli a0, a0, 16
377 ; RV32ID-NEXT: fmv.w.x fa5, a0
378 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
379 ; RV32ID-NEXT: feq.s a1, fa5, fa5
380 ; RV32ID-NEXT: seqz a1, a1
381 ; RV32ID-NEXT: addi a1, a1, -1
382 ; RV32ID-NEXT: and a0, a1, a0
383 ; RV32ID-NEXT: ret
384 ;
385 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16_sat:
386 ; CHECK64ZFBFMIN: # %bb.0: # %start
387 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
388 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
389 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
390 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
391 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
392 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
393 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
394 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
395 ; CHECK64ZFBFMIN-NEXT: ret
396 ;
397 ; RV64ID-LABEL: fcvt_wu_bf16_sat:
398 ; RV64ID: # %bb.0: # %start
399 ; RV64ID-NEXT: fmv.x.w a0, fa0
400 ; RV64ID-NEXT: slli a0, a0, 16
401 ; RV64ID-NEXT: fmv.w.x fa5, a0
402 ; RV64ID-NEXT: fcvt.wu.s a0, fa5, rtz
403 ; RV64ID-NEXT: feq.s a1, fa5, fa5
404 ; RV64ID-NEXT: seqz a1, a1
405 ; RV64ID-NEXT: addi a1, a1, -1
406 ; RV64ID-NEXT: and a0, a0, a1
407 ; RV64ID-NEXT: slli a0, a0, 32
408 ; RV64ID-NEXT: srli a0, a0, 32
409 ; RV64ID-NEXT: ret
410 start:
411 %0 = tail call i32 @llvm.fptoui.sat.i32.bf16(bfloat %a)
412 ret i32 %0
413 }
414 declare i32 @llvm.fptoui.sat.i32.bf16(bfloat)
416 define i64 @fcvt_l_bf16(bfloat %a) nounwind {
417 ; CHECK32ZFBFMIN-LABEL: fcvt_l_bf16:
418 ; CHECK32ZFBFMIN: # %bb.0:
419 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
420 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
421 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
422 ; CHECK32ZFBFMIN-NEXT: call __fixsfdi
423 ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
424 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
425 ; CHECK32ZFBFMIN-NEXT: ret
426 ;
427 ; RV32ID-LABEL: fcvt_l_bf16:
428 ; RV32ID: # %bb.0:
429 ; RV32ID-NEXT: addi sp, sp, -16
430 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
431 ; RV32ID-NEXT: fmv.x.w a0, fa0
432 ; RV32ID-NEXT: slli a0, a0, 16
433 ; RV32ID-NEXT: fmv.w.x fa0, a0
434 ; RV32ID-NEXT: call __fixsfdi
435 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
436 ; RV32ID-NEXT: addi sp, sp, 16
437 ; RV32ID-NEXT: ret
438 ;
439 ; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16:
440 ; CHECK64ZFBFMIN: # %bb.0:
441 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
442 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
443 ; CHECK64ZFBFMIN-NEXT: ret
444 ;
445 ; RV64ID-LABEL: fcvt_l_bf16:
446 ; RV64ID: # %bb.0:
447 ; RV64ID-NEXT: fmv.x.w a0, fa0
448 ; RV64ID-NEXT: slli a0, a0, 16
449 ; RV64ID-NEXT: fmv.w.x fa5, a0
450 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
451 ; RV64ID-NEXT: ret
452 %1 = fptosi bfloat %a to i64
453 ret i64 %1
454 }
456 define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind {
457 ; RV32IZFBFMIN-LABEL: fcvt_l_bf16_sat:
458 ; RV32IZFBFMIN: # %bb.0: # %start
459 ; RV32IZFBFMIN-NEXT: addi sp, sp, -16
460 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
461 ; RV32IZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
462 ; RV32IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
463 ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0
464 ; RV32IZFBFMIN-NEXT: lui a0, 913408
465 ; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a0
466 ; RV32IZFBFMIN-NEXT: fle.s s0, fa5, fs0
467 ; RV32IZFBFMIN-NEXT: fmv.s fa0, fs0
468 ; RV32IZFBFMIN-NEXT: call __fixsfdi
469 ; RV32IZFBFMIN-NEXT: lui a4, 524288
470 ; RV32IZFBFMIN-NEXT: lui a2, 524288
471 ; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_2
472 ; RV32IZFBFMIN-NEXT: # %bb.1: # %start
473 ; RV32IZFBFMIN-NEXT: mv a2, a1
474 ; RV32IZFBFMIN-NEXT: .LBB10_2: # %start
475 ; RV32IZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0)
476 ; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
477 ; RV32IZFBFMIN-NEXT: flt.s a3, fa5, fs0
478 ; RV32IZFBFMIN-NEXT: beqz a3, .LBB10_4
479 ; RV32IZFBFMIN-NEXT: # %bb.3:
480 ; RV32IZFBFMIN-NEXT: addi a2, a4, -1
481 ; RV32IZFBFMIN-NEXT: .LBB10_4: # %start
482 ; RV32IZFBFMIN-NEXT: feq.s a1, fs0, fs0
483 ; RV32IZFBFMIN-NEXT: neg a4, a1
484 ; RV32IZFBFMIN-NEXT: and a1, a4, a2
485 ; RV32IZFBFMIN-NEXT: neg a2, a3
486 ; RV32IZFBFMIN-NEXT: neg a3, s0
487 ; RV32IZFBFMIN-NEXT: and a0, a3, a0
488 ; RV32IZFBFMIN-NEXT: or a0, a2, a0
489 ; RV32IZFBFMIN-NEXT: and a0, a4, a0
490 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
491 ; RV32IZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
492 ; RV32IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
493 ; RV32IZFBFMIN-NEXT: addi sp, sp, 16
494 ; RV32IZFBFMIN-NEXT: ret
495 ;
496 ; R32IDZFBFMIN-LABEL: fcvt_l_bf16_sat:
497 ; R32IDZFBFMIN: # %bb.0: # %start
498 ; R32IDZFBFMIN-NEXT: addi sp, sp, -16
499 ; R32IDZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
500 ; R32IDZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
501 ; R32IDZFBFMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
502 ; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0
503 ; R32IDZFBFMIN-NEXT: lui a0, 913408
504 ; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a0
505 ; R32IDZFBFMIN-NEXT: fle.s s0, fa5, fs0
506 ; R32IDZFBFMIN-NEXT: fmv.s fa0, fs0
507 ; R32IDZFBFMIN-NEXT: call __fixsfdi
508 ; R32IDZFBFMIN-NEXT: lui a4, 524288
509 ; R32IDZFBFMIN-NEXT: lui a2, 524288
510 ; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_2
511 ; R32IDZFBFMIN-NEXT: # %bb.1: # %start
512 ; R32IDZFBFMIN-NEXT: mv a2, a1
513 ; R32IDZFBFMIN-NEXT: .LBB10_2: # %start
514 ; R32IDZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0)
515 ; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
516 ; R32IDZFBFMIN-NEXT: flt.s a3, fa5, fs0
517 ; R32IDZFBFMIN-NEXT: beqz a3, .LBB10_4
518 ; R32IDZFBFMIN-NEXT: # %bb.3:
519 ; R32IDZFBFMIN-NEXT: addi a2, a4, -1
520 ; R32IDZFBFMIN-NEXT: .LBB10_4: # %start
521 ; R32IDZFBFMIN-NEXT: feq.s a1, fs0, fs0
522 ; R32IDZFBFMIN-NEXT: neg a4, a1
523 ; R32IDZFBFMIN-NEXT: and a1, a4, a2
524 ; R32IDZFBFMIN-NEXT: neg a2, a3
525 ; R32IDZFBFMIN-NEXT: neg a3, s0
526 ; R32IDZFBFMIN-NEXT: and a0, a3, a0
527 ; R32IDZFBFMIN-NEXT: or a0, a2, a0
528 ; R32IDZFBFMIN-NEXT: and a0, a4, a0
529 ; R32IDZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
530 ; R32IDZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
531 ; R32IDZFBFMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
532 ; R32IDZFBFMIN-NEXT: addi sp, sp, 16
533 ; R32IDZFBFMIN-NEXT: ret
534 ;
535 ; RV32ID-LABEL: fcvt_l_bf16_sat:
536 ; RV32ID: # %bb.0: # %start
537 ; RV32ID-NEXT: addi sp, sp, -16
538 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
539 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
540 ; RV32ID-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
541 ; RV32ID-NEXT: fmv.x.w a0, fa0
542 ; RV32ID-NEXT: slli a0, a0, 16
543 ; RV32ID-NEXT: fmv.w.x fs0, a0
544 ; RV32ID-NEXT: lui a0, 913408
545 ; RV32ID-NEXT: fmv.w.x fa5, a0
546 ; RV32ID-NEXT: fle.s s0, fa5, fs0
547 ; RV32ID-NEXT: fmv.s fa0, fs0
548 ; RV32ID-NEXT: call __fixsfdi
549 ; RV32ID-NEXT: lui a4, 524288
550 ; RV32ID-NEXT: lui a2, 524288
551 ; RV32ID-NEXT: beqz s0, .LBB10_2
552 ; RV32ID-NEXT: # %bb.1: # %start
553 ; RV32ID-NEXT: mv a2, a1
554 ; RV32ID-NEXT: .LBB10_2: # %start
555 ; RV32ID-NEXT: lui a1, %hi(.LCPI10_0)
556 ; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
557 ; RV32ID-NEXT: flt.s a3, fa5, fs0
558 ; RV32ID-NEXT: beqz a3, .LBB10_4
559 ; RV32ID-NEXT: # %bb.3:
560 ; RV32ID-NEXT: addi a2, a4, -1
561 ; RV32ID-NEXT: .LBB10_4: # %start
562 ; RV32ID-NEXT: feq.s a1, fs0, fs0
563 ; RV32ID-NEXT: neg a4, a1
564 ; RV32ID-NEXT: and a1, a4, a2
565 ; RV32ID-NEXT: neg a2, a3
566 ; RV32ID-NEXT: neg a3, s0
567 ; RV32ID-NEXT: and a0, a3, a0
568 ; RV32ID-NEXT: or a0, a2, a0
569 ; RV32ID-NEXT: and a0, a4, a0
570 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
571 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
572 ; RV32ID-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
573 ; RV32ID-NEXT: addi sp, sp, 16
574 ; RV32ID-NEXT: ret
575 ;
576 ; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16_sat:
577 ; CHECK64ZFBFMIN: # %bb.0: # %start
578 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
579 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
580 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
581 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
582 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
583 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
584 ; CHECK64ZFBFMIN-NEXT: ret
585 ;
586 ; RV64ID-LABEL: fcvt_l_bf16_sat:
587 ; RV64ID: # %bb.0: # %start
588 ; RV64ID-NEXT: fmv.x.w a0, fa0
589 ; RV64ID-NEXT: slli a0, a0, 16
590 ; RV64ID-NEXT: fmv.w.x fa5, a0
591 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
592 ; RV64ID-NEXT: feq.s a1, fa5, fa5
593 ; RV64ID-NEXT: seqz a1, a1
594 ; RV64ID-NEXT: addi a1, a1, -1
595 ; RV64ID-NEXT: and a0, a1, a0
596 ; RV64ID-NEXT: ret
597 start:
598 %0 = tail call i64 @llvm.fptosi.sat.i64.bf16(bfloat %a)
599 ret i64 %0
600 }
601 declare i64 @llvm.fptosi.sat.i64.bf16(bfloat)
603 define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
604 ; CHECK32ZFBFMIN-LABEL: fcvt_lu_bf16:
605 ; CHECK32ZFBFMIN: # %bb.0:
606 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
607 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
608 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
609 ; CHECK32ZFBFMIN-NEXT: call __fixunssfdi
610 ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
611 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
612 ; CHECK32ZFBFMIN-NEXT: ret
613 ;
614 ; RV32ID-LABEL: fcvt_lu_bf16:
615 ; RV32ID: # %bb.0:
616 ; RV32ID-NEXT: addi sp, sp, -16
617 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
618 ; RV32ID-NEXT: fmv.x.w a0, fa0
619 ; RV32ID-NEXT: slli a0, a0, 16
620 ; RV32ID-NEXT: fmv.w.x fa0, a0
621 ; RV32ID-NEXT: call __fixunssfdi
622 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
623 ; RV32ID-NEXT: addi sp, sp, 16
624 ; RV32ID-NEXT: ret
625 ;
626 ; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16:
627 ; CHECK64ZFBFMIN: # %bb.0:
628 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
629 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
630 ; CHECK64ZFBFMIN-NEXT: ret
631 ;
632 ; RV64ID-LABEL: fcvt_lu_bf16:
633 ; RV64ID: # %bb.0:
634 ; RV64ID-NEXT: fmv.x.w a0, fa0
635 ; RV64ID-NEXT: slli a0, a0, 16
636 ; RV64ID-NEXT: fmv.w.x fa5, a0
637 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
638 ; RV64ID-NEXT: ret
639 %1 = fptoui bfloat %a to i64
640 ret i64 %1
641 }
643 define i64 @fcvt_lu_bf16_sat(bfloat %a) nounwind {
644 ; CHECK32ZFBFMIN-LABEL: fcvt_lu_bf16_sat:
645 ; CHECK32ZFBFMIN: # %bb.0: # %start
646 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
647 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
648 ; CHECK32ZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
649 ; CHECK32ZFBFMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
650 ; CHECK32ZFBFMIN-NEXT: lui a0, %hi(.LCPI12_0)
651 ; CHECK32ZFBFMIN-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
652 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
653 ; CHECK32ZFBFMIN-NEXT: flt.s a0, fa5, fa0
654 ; CHECK32ZFBFMIN-NEXT: neg s0, a0
655 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa5, zero
656 ; CHECK32ZFBFMIN-NEXT: fle.s a0, fa5, fa0
657 ; CHECK32ZFBFMIN-NEXT: neg s1, a0
658 ; CHECK32ZFBFMIN-NEXT: call __fixunssfdi
659 ; CHECK32ZFBFMIN-NEXT: and a0, s1, a0
660 ; CHECK32ZFBFMIN-NEXT: or a0, s0, a0
661 ; CHECK32ZFBFMIN-NEXT: and a1, s1, a1
662 ; CHECK32ZFBFMIN-NEXT: or a1, s0, a1
663 ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
664 ; CHECK32ZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
665 ; CHECK32ZFBFMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
666 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
667 ; CHECK32ZFBFMIN-NEXT: ret
668 ;
669 ; RV32ID-LABEL: fcvt_lu_bf16_sat:
670 ; RV32ID: # %bb.0: # %start
671 ; RV32ID-NEXT: addi sp, sp, -16
672 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
673 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
674 ; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
675 ; RV32ID-NEXT: lui a0, %hi(.LCPI12_0)
676 ; RV32ID-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
677 ; RV32ID-NEXT: fmv.x.w a0, fa0
678 ; RV32ID-NEXT: slli a0, a0, 16
679 ; RV32ID-NEXT: fmv.w.x fa0, a0
680 ; RV32ID-NEXT: flt.s a0, fa5, fa0
681 ; RV32ID-NEXT: neg s0, a0
682 ; RV32ID-NEXT: fmv.w.x fa5, zero
683 ; RV32ID-NEXT: fle.s a0, fa5, fa0
684 ; RV32ID-NEXT: neg s1, a0
685 ; RV32ID-NEXT: call __fixunssfdi
686 ; RV32ID-NEXT: and a0, s1, a0
687 ; RV32ID-NEXT: or a0, s0, a0
688 ; RV32ID-NEXT: and a1, s1, a1
689 ; RV32ID-NEXT: or a1, s0, a1
690 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
691 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
692 ; RV32ID-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
693 ; RV32ID-NEXT: addi sp, sp, 16
694 ; RV32ID-NEXT: ret
695 ;
696 ; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16_sat:
697 ; CHECK64ZFBFMIN: # %bb.0: # %start
698 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
699 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
700 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
701 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
702 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
703 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
704 ; CHECK64ZFBFMIN-NEXT: ret
705 ;
706 ; RV64ID-LABEL: fcvt_lu_bf16_sat:
707 ; RV64ID: # %bb.0: # %start
708 ; RV64ID-NEXT: fmv.x.w a0, fa0
709 ; RV64ID-NEXT: slli a0, a0, 16
710 ; RV64ID-NEXT: fmv.w.x fa5, a0
711 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
712 ; RV64ID-NEXT: feq.s a1, fa5, fa5
713 ; RV64ID-NEXT: seqz a1, a1
714 ; RV64ID-NEXT: addi a1, a1, -1
715 ; RV64ID-NEXT: and a0, a1, a0
716 ; RV64ID-NEXT: ret
717 start:
718 %0 = tail call i64 @llvm.fptoui.sat.i64.bf16(bfloat %a)
719 ret i64 %0
720 }
721 declare i64 @llvm.fptoui.sat.i64.bf16(bfloat)
723 define bfloat @fcvt_bf16_si(i16 %a) nounwind {
724 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_si:
725 ; CHECK32ZFBFMIN: # %bb.0:
726 ; CHECK32ZFBFMIN-NEXT: slli a0, a0, 16
727 ; CHECK32ZFBFMIN-NEXT: srai a0, a0, 16
728 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
729 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
730 ; CHECK32ZFBFMIN-NEXT: ret
731 ;
732 ; RV32ID-LABEL: fcvt_bf16_si:
733 ; RV32ID: # %bb.0:
734 ; RV32ID-NEXT: addi sp, sp, -16
735 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
736 ; RV32ID-NEXT: slli a0, a0, 16
737 ; RV32ID-NEXT: srai a0, a0, 16
738 ; RV32ID-NEXT: fcvt.s.w fa0, a0
739 ; RV32ID-NEXT: call __truncsfbf2
740 ; RV32ID-NEXT: fmv.x.w a0, fa0
741 ; RV32ID-NEXT: lui a1, 1048560
742 ; RV32ID-NEXT: or a0, a0, a1
743 ; RV32ID-NEXT: fmv.w.x fa0, a0
744 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
745 ; RV32ID-NEXT: addi sp, sp, 16
746 ; RV32ID-NEXT: ret
747 ;
748 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_si:
749 ; CHECK64ZFBFMIN: # %bb.0:
750 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 48
751 ; CHECK64ZFBFMIN-NEXT: srai a0, a0, 48
752 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
753 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
754 ; CHECK64ZFBFMIN-NEXT: ret
755 ;
756 ; RV64ID-LABEL: fcvt_bf16_si:
757 ; RV64ID: # %bb.0:
758 ; RV64ID-NEXT: addi sp, sp, -16
759 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
760 ; RV64ID-NEXT: slli a0, a0, 48
761 ; RV64ID-NEXT: srai a0, a0, 48
762 ; RV64ID-NEXT: fcvt.s.w fa0, a0
763 ; RV64ID-NEXT: call __truncsfbf2
764 ; RV64ID-NEXT: fmv.x.w a0, fa0
765 ; RV64ID-NEXT: lui a1, 1048560
766 ; RV64ID-NEXT: or a0, a0, a1
767 ; RV64ID-NEXT: fmv.w.x fa0, a0
768 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
769 ; RV64ID-NEXT: addi sp, sp, 16
770 ; RV64ID-NEXT: ret
771 %1 = sitofp i16 %a to bfloat
772 ret bfloat %1
773 }
775 define bfloat @fcvt_bf16_si_signext(i16 signext %a) nounwind {
776 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_si_signext:
777 ; CHECK32ZFBFMIN: # %bb.0:
778 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
779 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
780 ; CHECK32ZFBFMIN-NEXT: ret
781 ;
782 ; RV32ID-LABEL: fcvt_bf16_si_signext:
783 ; RV32ID: # %bb.0:
784 ; RV32ID-NEXT: addi sp, sp, -16
785 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
786 ; RV32ID-NEXT: fcvt.s.w fa0, a0
787 ; RV32ID-NEXT: call __truncsfbf2
788 ; RV32ID-NEXT: fmv.x.w a0, fa0
789 ; RV32ID-NEXT: lui a1, 1048560
790 ; RV32ID-NEXT: or a0, a0, a1
791 ; RV32ID-NEXT: fmv.w.x fa0, a0
792 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
793 ; RV32ID-NEXT: addi sp, sp, 16
794 ; RV32ID-NEXT: ret
795 ;
796 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_si_signext:
797 ; CHECK64ZFBFMIN: # %bb.0:
798 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
799 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
800 ; CHECK64ZFBFMIN-NEXT: ret
801 ;
802 ; RV64ID-LABEL: fcvt_bf16_si_signext:
803 ; RV64ID: # %bb.0:
804 ; RV64ID-NEXT: addi sp, sp, -16
805 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
806 ; RV64ID-NEXT: fcvt.s.w fa0, a0
807 ; RV64ID-NEXT: call __truncsfbf2
808 ; RV64ID-NEXT: fmv.x.w a0, fa0
809 ; RV64ID-NEXT: lui a1, 1048560
810 ; RV64ID-NEXT: or a0, a0, a1
811 ; RV64ID-NEXT: fmv.w.x fa0, a0
812 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
813 ; RV64ID-NEXT: addi sp, sp, 16
814 ; RV64ID-NEXT: ret
815 %1 = sitofp i16 %a to bfloat
816 ret bfloat %1
817 }
819 define bfloat @fcvt_bf16_ui(i16 %a) nounwind {
820 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_ui:
821 ; CHECK32ZFBFMIN: # %bb.0:
822 ; CHECK32ZFBFMIN-NEXT: slli a0, a0, 16
823 ; CHECK32ZFBFMIN-NEXT: srli a0, a0, 16
824 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
825 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
826 ; CHECK32ZFBFMIN-NEXT: ret
827 ;
828 ; RV32ID-LABEL: fcvt_bf16_ui:
829 ; RV32ID: # %bb.0:
830 ; RV32ID-NEXT: addi sp, sp, -16
831 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
832 ; RV32ID-NEXT: slli a0, a0, 16
833 ; RV32ID-NEXT: srli a0, a0, 16
834 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
835 ; RV32ID-NEXT: call __truncsfbf2
836 ; RV32ID-NEXT: fmv.x.w a0, fa0
837 ; RV32ID-NEXT: lui a1, 1048560
838 ; RV32ID-NEXT: or a0, a0, a1
839 ; RV32ID-NEXT: fmv.w.x fa0, a0
840 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
841 ; RV32ID-NEXT: addi sp, sp, 16
842 ; RV32ID-NEXT: ret
843 ;
844 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_ui:
845 ; CHECK64ZFBFMIN: # %bb.0:
846 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 48
847 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 48
848 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
849 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
850 ; CHECK64ZFBFMIN-NEXT: ret
851 ;
852 ; RV64ID-LABEL: fcvt_bf16_ui:
853 ; RV64ID: # %bb.0:
854 ; RV64ID-NEXT: addi sp, sp, -16
855 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
856 ; RV64ID-NEXT: slli a0, a0, 48
857 ; RV64ID-NEXT: srli a0, a0, 48
858 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
859 ; RV64ID-NEXT: call __truncsfbf2
860 ; RV64ID-NEXT: fmv.x.w a0, fa0
861 ; RV64ID-NEXT: lui a1, 1048560
862 ; RV64ID-NEXT: or a0, a0, a1
863 ; RV64ID-NEXT: fmv.w.x fa0, a0
864 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
865 ; RV64ID-NEXT: addi sp, sp, 16
866 ; RV64ID-NEXT: ret
867 %1 = uitofp i16 %a to bfloat
868 ret bfloat %1
869 }
871 define bfloat @fcvt_bf16_ui_zeroext(i16 zeroext %a) nounwind {
872 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_ui_zeroext:
873 ; CHECK32ZFBFMIN: # %bb.0:
874 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
875 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
876 ; CHECK32ZFBFMIN-NEXT: ret
877 ;
878 ; RV32ID-LABEL: fcvt_bf16_ui_zeroext:
879 ; RV32ID: # %bb.0:
880 ; RV32ID-NEXT: addi sp, sp, -16
881 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
882 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
883 ; RV32ID-NEXT: call __truncsfbf2
884 ; RV32ID-NEXT: fmv.x.w a0, fa0
885 ; RV32ID-NEXT: lui a1, 1048560
886 ; RV32ID-NEXT: or a0, a0, a1
887 ; RV32ID-NEXT: fmv.w.x fa0, a0
888 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
889 ; RV32ID-NEXT: addi sp, sp, 16
890 ; RV32ID-NEXT: ret
891 ;
892 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_ui_zeroext:
893 ; CHECK64ZFBFMIN: # %bb.0:
894 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
895 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
896 ; CHECK64ZFBFMIN-NEXT: ret
897 ;
898 ; RV64ID-LABEL: fcvt_bf16_ui_zeroext:
899 ; RV64ID: # %bb.0:
900 ; RV64ID-NEXT: addi sp, sp, -16
901 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
902 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
903 ; RV64ID-NEXT: call __truncsfbf2
904 ; RV64ID-NEXT: fmv.x.w a0, fa0
905 ; RV64ID-NEXT: lui a1, 1048560
906 ; RV64ID-NEXT: or a0, a0, a1
907 ; RV64ID-NEXT: fmv.w.x fa0, a0
908 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
909 ; RV64ID-NEXT: addi sp, sp, 16
910 ; RV64ID-NEXT: ret
911 %1 = uitofp i16 %a to bfloat
912 ret bfloat %1
913 }
915 define bfloat @fcvt_bf16_w(i32 %a) nounwind {
916 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_w:
917 ; CHECK32ZFBFMIN: # %bb.0:
918 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
919 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
920 ; CHECK32ZFBFMIN-NEXT: ret
921 ;
922 ; RV32ID-LABEL: fcvt_bf16_w:
923 ; RV32ID: # %bb.0:
924 ; RV32ID-NEXT: addi sp, sp, -16
925 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
926 ; RV32ID-NEXT: fcvt.s.w fa0, a0
927 ; RV32ID-NEXT: call __truncsfbf2
928 ; RV32ID-NEXT: fmv.x.w a0, fa0
929 ; RV32ID-NEXT: lui a1, 1048560
930 ; RV32ID-NEXT: or a0, a0, a1
931 ; RV32ID-NEXT: fmv.w.x fa0, a0
932 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
933 ; RV32ID-NEXT: addi sp, sp, 16
934 ; RV32ID-NEXT: ret
935 ;
936 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w:
937 ; CHECK64ZFBFMIN: # %bb.0:
938 ; CHECK64ZFBFMIN-NEXT: sext.w a0, a0
939 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
940 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
941 ; CHECK64ZFBFMIN-NEXT: ret
942 ;
943 ; RV64ID-LABEL: fcvt_bf16_w:
944 ; RV64ID: # %bb.0:
945 ; RV64ID-NEXT: addi sp, sp, -16
946 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
947 ; RV64ID-NEXT: fcvt.s.w fa0, a0
948 ; RV64ID-NEXT: call __truncsfbf2
949 ; RV64ID-NEXT: fmv.x.w a0, fa0
950 ; RV64ID-NEXT: lui a1, 1048560
951 ; RV64ID-NEXT: or a0, a0, a1
952 ; RV64ID-NEXT: fmv.w.x fa0, a0
953 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
954 ; RV64ID-NEXT: addi sp, sp, 16
955 ; RV64ID-NEXT: ret
956 %1 = sitofp i32 %a to bfloat
957 ret bfloat %1
958 }
960 define bfloat @fcvt_bf16_w_load(ptr %p) nounwind {
961 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_w_load:
962 ; CHECK32ZFBFMIN: # %bb.0:
963 ; CHECK32ZFBFMIN-NEXT: lw a0, 0(a0)
964 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
965 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
966 ; CHECK32ZFBFMIN-NEXT: ret
967 ;
968 ; RV32ID-LABEL: fcvt_bf16_w_load:
969 ; RV32ID: # %bb.0:
970 ; RV32ID-NEXT: addi sp, sp, -16
971 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
972 ; RV32ID-NEXT: lw a0, 0(a0)
973 ; RV32ID-NEXT: fcvt.s.w fa0, a0
974 ; RV32ID-NEXT: call __truncsfbf2
975 ; RV32ID-NEXT: fmv.x.w a0, fa0
976 ; RV32ID-NEXT: lui a1, 1048560
977 ; RV32ID-NEXT: or a0, a0, a1
978 ; RV32ID-NEXT: fmv.w.x fa0, a0
979 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
980 ; RV32ID-NEXT: addi sp, sp, 16
981 ; RV32ID-NEXT: ret
982 ;
983 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w_load:
984 ; CHECK64ZFBFMIN: # %bb.0:
985 ; CHECK64ZFBFMIN-NEXT: lw a0, 0(a0)
986 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
987 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
988 ; CHECK64ZFBFMIN-NEXT: ret
989 ;
990 ; RV64ID-LABEL: fcvt_bf16_w_load:
991 ; RV64ID: # %bb.0:
992 ; RV64ID-NEXT: addi sp, sp, -16
993 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
994 ; RV64ID-NEXT: lw a0, 0(a0)
995 ; RV64ID-NEXT: fcvt.s.w fa0, a0
996 ; RV64ID-NEXT: call __truncsfbf2
997 ; RV64ID-NEXT: fmv.x.w a0, fa0
998 ; RV64ID-NEXT: lui a1, 1048560
999 ; RV64ID-NEXT: or a0, a0, a1
1000 ; RV64ID-NEXT: fmv.w.x fa0, a0
1001 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1002 ; RV64ID-NEXT: addi sp, sp, 16
1003 ; RV64ID-NEXT: ret
1004 %a = load i32, ptr %p
1005 %1 = sitofp i32 %a to bfloat
1006 ret bfloat %1
1007 }
1009 define bfloat @fcvt_bf16_wu(i32 %a) nounwind {
1010 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_wu:
1011 ; CHECK32ZFBFMIN: # %bb.0:
1012 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
1013 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1014 ; CHECK32ZFBFMIN-NEXT: ret
1015 ;
1016 ; RV32ID-LABEL: fcvt_bf16_wu:
1017 ; RV32ID: # %bb.0:
1018 ; RV32ID-NEXT: addi sp, sp, -16
1019 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1020 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
1021 ; RV32ID-NEXT: call __truncsfbf2
1022 ; RV32ID-NEXT: fmv.x.w a0, fa0
1023 ; RV32ID-NEXT: lui a1, 1048560
1024 ; RV32ID-NEXT: or a0, a0, a1
1025 ; RV32ID-NEXT: fmv.w.x fa0, a0
1026 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1027 ; RV32ID-NEXT: addi sp, sp, 16
1028 ; RV32ID-NEXT: ret
1029 ;
1030 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu:
1031 ; CHECK64ZFBFMIN: # %bb.0:
1032 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
1033 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
1034 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
1035 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1036 ; CHECK64ZFBFMIN-NEXT: ret
1037 ;
1038 ; RV64ID-LABEL: fcvt_bf16_wu:
1039 ; RV64ID: # %bb.0:
1040 ; RV64ID-NEXT: addi sp, sp, -16
1041 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1042 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
1043 ; RV64ID-NEXT: call __truncsfbf2
1044 ; RV64ID-NEXT: fmv.x.w a0, fa0
1045 ; RV64ID-NEXT: lui a1, 1048560
1046 ; RV64ID-NEXT: or a0, a0, a1
1047 ; RV64ID-NEXT: fmv.w.x fa0, a0
1048 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1049 ; RV64ID-NEXT: addi sp, sp, 16
1050 ; RV64ID-NEXT: ret
1051 %1 = uitofp i32 %a to bfloat
1052 ret bfloat %1
1053 }
1055 define bfloat @fcvt_bf16_wu_load(ptr %p) nounwind {
1056 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_wu_load:
1057 ; CHECK32ZFBFMIN: # %bb.0:
1058 ; CHECK32ZFBFMIN-NEXT: lw a0, 0(a0)
1059 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
1060 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1061 ; CHECK32ZFBFMIN-NEXT: ret
1062 ;
1063 ; RV32ID-LABEL: fcvt_bf16_wu_load:
1064 ; RV32ID: # %bb.0:
1065 ; RV32ID-NEXT: addi sp, sp, -16
1066 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1067 ; RV32ID-NEXT: lw a0, 0(a0)
1068 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
1069 ; RV32ID-NEXT: call __truncsfbf2
1070 ; RV32ID-NEXT: fmv.x.w a0, fa0
1071 ; RV32ID-NEXT: lui a1, 1048560
1072 ; RV32ID-NEXT: or a0, a0, a1
1073 ; RV32ID-NEXT: fmv.w.x fa0, a0
1074 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1075 ; RV32ID-NEXT: addi sp, sp, 16
1076 ; RV32ID-NEXT: ret
1077 ;
1078 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu_load:
1079 ; CHECK64ZFBFMIN: # %bb.0:
1080 ; CHECK64ZFBFMIN-NEXT: lwu a0, 0(a0)
1081 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
1082 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1083 ; CHECK64ZFBFMIN-NEXT: ret
1084 ;
1085 ; RV64ID-LABEL: fcvt_bf16_wu_load:
1086 ; RV64ID: # %bb.0:
1087 ; RV64ID-NEXT: addi sp, sp, -16
1088 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1089 ; RV64ID-NEXT: lwu a0, 0(a0)
1090 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
1091 ; RV64ID-NEXT: call __truncsfbf2
1092 ; RV64ID-NEXT: fmv.x.w a0, fa0
1093 ; RV64ID-NEXT: lui a1, 1048560
1094 ; RV64ID-NEXT: or a0, a0, a1
1095 ; RV64ID-NEXT: fmv.w.x fa0, a0
1096 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1097 ; RV64ID-NEXT: addi sp, sp, 16
1098 ; RV64ID-NEXT: ret
1099 %a = load i32, ptr %p
1100 %1 = uitofp i32 %a to bfloat
1101 ret bfloat %1
1102 }
1104 ; TODO: The following tests error on rv32 with zfbfmin enabled.
1106 ; define bfloat @fcvt_bf16_l(i64 %a) nounwind {
1107 ; %1 = sitofp i64 %a to bfloat
1108 ; ret bfloat %1
1109 ; }
1111 ; define bfloat @fcvt_bf16_lu(i64 %a) nounwind {
1112 ; %1 = uitofp i64 %a to bfloat
1113 ; ret bfloat %1
1114 ; }
1116 define bfloat @fcvt_bf16_s(float %a) nounwind {
1117 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_s:
1118 ; CHECK32ZFBFMIN: # %bb.0:
1119 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0
1120 ; CHECK32ZFBFMIN-NEXT: ret
1121 ;
1122 ; RV32ID-LABEL: fcvt_bf16_s:
1123 ; RV32ID: # %bb.0:
1124 ; RV32ID-NEXT: addi sp, sp, -16
1125 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1126 ; RV32ID-NEXT: call __truncsfbf2
1127 ; RV32ID-NEXT: fmv.x.w a0, fa0
1128 ; RV32ID-NEXT: lui a1, 1048560
1129 ; RV32ID-NEXT: or a0, a0, a1
1130 ; RV32ID-NEXT: fmv.w.x fa0, a0
1131 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1132 ; RV32ID-NEXT: addi sp, sp, 16
1133 ; RV32ID-NEXT: ret
1134 ;
1135 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_s:
1136 ; CHECK64ZFBFMIN: # %bb.0:
1137 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0
1138 ; CHECK64ZFBFMIN-NEXT: ret
1139 ;
1140 ; RV64ID-LABEL: fcvt_bf16_s:
1141 ; RV64ID: # %bb.0:
1142 ; RV64ID-NEXT: addi sp, sp, -16
1143 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1144 ; RV64ID-NEXT: call __truncsfbf2
1145 ; RV64ID-NEXT: fmv.x.w a0, fa0
1146 ; RV64ID-NEXT: lui a1, 1048560
1147 ; RV64ID-NEXT: or a0, a0, a1
1148 ; RV64ID-NEXT: fmv.w.x fa0, a0
1149 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1150 ; RV64ID-NEXT: addi sp, sp, 16
1151 ; RV64ID-NEXT: ret
1152 %1 = fptrunc float %a to bfloat
1153 ret bfloat %1
1154 }
1156 define float @fcvt_s_bf16(bfloat %a) nounwind {
1157 ; CHECK32ZFBFMIN-LABEL: fcvt_s_bf16:
1158 ; CHECK32ZFBFMIN: # %bb.0:
1159 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1160 ; CHECK32ZFBFMIN-NEXT: ret
1161 ;
1162 ; RV32ID-LABEL: fcvt_s_bf16:
1163 ; RV32ID: # %bb.0:
1164 ; RV32ID-NEXT: fmv.x.w a0, fa0
1165 ; RV32ID-NEXT: slli a0, a0, 16
1166 ; RV32ID-NEXT: fmv.w.x fa0, a0
1167 ; RV32ID-NEXT: ret
1168 ;
1169 ; CHECK64ZFBFMIN-LABEL: fcvt_s_bf16:
1170 ; CHECK64ZFBFMIN: # %bb.0:
1171 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1172 ; CHECK64ZFBFMIN-NEXT: ret
1173 ;
1174 ; RV64ID-LABEL: fcvt_s_bf16:
1175 ; RV64ID: # %bb.0:
1176 ; RV64ID-NEXT: fmv.x.w a0, fa0
1177 ; RV64ID-NEXT: slli a0, a0, 16
1178 ; RV64ID-NEXT: fmv.w.x fa0, a0
1179 ; RV64ID-NEXT: ret
1180 %1 = fpext bfloat %a to float
1181 ret float %1
1182 }
1184 define bfloat @fcvt_bf16_d(double %a) nounwind {
1185 ; RV32IZFBFMIN-LABEL: fcvt_bf16_d:
1186 ; RV32IZFBFMIN: # %bb.0:
1187 ; RV32IZFBFMIN-NEXT: addi sp, sp, -16
1188 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1189 ; RV32IZFBFMIN-NEXT: call __truncdfbf2
1190 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1191 ; RV32IZFBFMIN-NEXT: addi sp, sp, 16
1192 ; RV32IZFBFMIN-NEXT: ret
1193 ;
1194 ; R32IDZFBFMIN-LABEL: fcvt_bf16_d:
1195 ; R32IDZFBFMIN: # %bb.0:
1196 ; R32IDZFBFMIN-NEXT: fcvt.s.d fa5, fa0
1197 ; R32IDZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1198 ; R32IDZFBFMIN-NEXT: ret
1199 ;
1200 ; RV32ID-LABEL: fcvt_bf16_d:
1201 ; RV32ID: # %bb.0:
1202 ; RV32ID-NEXT: addi sp, sp, -16
1203 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1204 ; RV32ID-NEXT: call __truncdfbf2
1205 ; RV32ID-NEXT: fmv.x.w a0, fa0
1206 ; RV32ID-NEXT: lui a1, 1048560
1207 ; RV32ID-NEXT: or a0, a0, a1
1208 ; RV32ID-NEXT: fmv.w.x fa0, a0
1209 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1210 ; RV32ID-NEXT: addi sp, sp, 16
1211 ; RV32ID-NEXT: ret
1212 ;
1213 ; RV64IZFBFMIN-LABEL: fcvt_bf16_d:
1214 ; RV64IZFBFMIN: # %bb.0:
1215 ; RV64IZFBFMIN-NEXT: addi sp, sp, -16
1216 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1217 ; RV64IZFBFMIN-NEXT: call __truncdfbf2
1218 ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1219 ; RV64IZFBFMIN-NEXT: addi sp, sp, 16
1220 ; RV64IZFBFMIN-NEXT: ret
1221 ;
1222 ; RV64IDZFBFMIN-LABEL: fcvt_bf16_d:
1223 ; RV64IDZFBFMIN: # %bb.0:
1224 ; RV64IDZFBFMIN-NEXT: fcvt.s.d fa5, fa0
1225 ; RV64IDZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1226 ; RV64IDZFBFMIN-NEXT: ret
1227 ;
1228 ; RV64ID-LABEL: fcvt_bf16_d:
1229 ; RV64ID: # %bb.0:
1230 ; RV64ID-NEXT: addi sp, sp, -16
1231 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1232 ; RV64ID-NEXT: call __truncdfbf2
1233 ; RV64ID-NEXT: fmv.x.w a0, fa0
1234 ; RV64ID-NEXT: lui a1, 1048560
1235 ; RV64ID-NEXT: or a0, a0, a1
1236 ; RV64ID-NEXT: fmv.w.x fa0, a0
1237 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1238 ; RV64ID-NEXT: addi sp, sp, 16
1239 ; RV64ID-NEXT: ret
1240 %1 = fptrunc double %a to bfloat
1241 ret bfloat %1
1242 }
1244 define double @fcvt_d_bf16(bfloat %a) nounwind {
1245 ; RV32IZFBFMIN-LABEL: fcvt_d_bf16:
1246 ; RV32IZFBFMIN: # %bb.0:
1247 ; RV32IZFBFMIN-NEXT: addi sp, sp, -16
1248 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1249 ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1250 ; RV32IZFBFMIN-NEXT: call __extendsfdf2
1251 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1252 ; RV32IZFBFMIN-NEXT: addi sp, sp, 16
1253 ; RV32IZFBFMIN-NEXT: ret
1254 ;
1255 ; R32IDZFBFMIN-LABEL: fcvt_d_bf16:
1256 ; R32IDZFBFMIN: # %bb.0:
1257 ; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1258 ; R32IDZFBFMIN-NEXT: fcvt.d.s fa0, fa5
1259 ; R32IDZFBFMIN-NEXT: ret
1260 ;
1261 ; RV32ID-LABEL: fcvt_d_bf16:
1262 ; RV32ID: # %bb.0:
1263 ; RV32ID-NEXT: fmv.x.w a0, fa0
1264 ; RV32ID-NEXT: slli a0, a0, 16
1265 ; RV32ID-NEXT: fmv.w.x fa5, a0
1266 ; RV32ID-NEXT: fcvt.d.s fa0, fa5
1267 ; RV32ID-NEXT: ret
1268 ;
1269 ; RV64IZFBFMIN-LABEL: fcvt_d_bf16:
1270 ; RV64IZFBFMIN: # %bb.0:
1271 ; RV64IZFBFMIN-NEXT: addi sp, sp, -16
1272 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1273 ; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1274 ; RV64IZFBFMIN-NEXT: call __extendsfdf2
1275 ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1276 ; RV64IZFBFMIN-NEXT: addi sp, sp, 16
1277 ; RV64IZFBFMIN-NEXT: ret
1278 ;
1279 ; RV64IDZFBFMIN-LABEL: fcvt_d_bf16:
1280 ; RV64IDZFBFMIN: # %bb.0:
1281 ; RV64IDZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1282 ; RV64IDZFBFMIN-NEXT: fcvt.d.s fa0, fa5
1283 ; RV64IDZFBFMIN-NEXT: ret
1284 ;
1285 ; RV64ID-LABEL: fcvt_d_bf16:
1286 ; RV64ID: # %bb.0:
1287 ; RV64ID-NEXT: fmv.x.w a0, fa0
1288 ; RV64ID-NEXT: slli a0, a0, 16
1289 ; RV64ID-NEXT: fmv.w.x fa5, a0
1290 ; RV64ID-NEXT: fcvt.d.s fa0, fa5
1291 ; RV64ID-NEXT: ret
1292 %1 = fpext bfloat %a to double
1293 ret double %1
1294 }
1296 define bfloat @bitcast_bf16_i16(i16 %a) nounwind {
1297 ; CHECK32ZFBFMIN-LABEL: bitcast_bf16_i16:
1298 ; CHECK32ZFBFMIN: # %bb.0:
1299 ; CHECK32ZFBFMIN-NEXT: fmv.h.x fa0, a0
1300 ; CHECK32ZFBFMIN-NEXT: ret
1301 ;
1302 ; RV32ID-LABEL: bitcast_bf16_i16:
1303 ; RV32ID: # %bb.0:
1304 ; RV32ID-NEXT: lui a1, 1048560
1305 ; RV32ID-NEXT: or a0, a0, a1
1306 ; RV32ID-NEXT: fmv.w.x fa0, a0
1307 ; RV32ID-NEXT: ret
1308 ;
1309 ; CHECK64ZFBFMIN-LABEL: bitcast_bf16_i16:
1310 ; CHECK64ZFBFMIN: # %bb.0:
1311 ; CHECK64ZFBFMIN-NEXT: fmv.h.x fa0, a0
1312 ; CHECK64ZFBFMIN-NEXT: ret
1313 ;
1314 ; RV64ID-LABEL: bitcast_bf16_i16:
1315 ; RV64ID: # %bb.0:
1316 ; RV64ID-NEXT: lui a1, 1048560
1317 ; RV64ID-NEXT: or a0, a0, a1
1318 ; RV64ID-NEXT: fmv.w.x fa0, a0
1319 ; RV64ID-NEXT: ret
1320 %1 = bitcast i16 %a to bfloat
1321 ret bfloat %1
1322 }
1324 define i16 @bitcast_i16_bf16(bfloat %a) nounwind {
1325 ; CHECK32ZFBFMIN-LABEL: bitcast_i16_bf16:
1326 ; CHECK32ZFBFMIN: # %bb.0:
1327 ; CHECK32ZFBFMIN-NEXT: fmv.x.h a0, fa0
1328 ; CHECK32ZFBFMIN-NEXT: ret
1329 ;
1330 ; RV32ID-LABEL: bitcast_i16_bf16:
1331 ; RV32ID: # %bb.0:
1332 ; RV32ID-NEXT: fmv.x.w a0, fa0
1333 ; RV32ID-NEXT: ret
1334 ;
1335 ; CHECK64ZFBFMIN-LABEL: bitcast_i16_bf16:
1336 ; CHECK64ZFBFMIN: # %bb.0:
1337 ; CHECK64ZFBFMIN-NEXT: fmv.x.h a0, fa0
1338 ; CHECK64ZFBFMIN-NEXT: ret
1339 ;
1340 ; RV64ID-LABEL: bitcast_i16_bf16:
1341 ; RV64ID: # %bb.0:
1342 ; RV64ID-NEXT: fmv.x.w a0, fa0
1343 ; RV64ID-NEXT: ret
1344 %1 = bitcast bfloat %a to i16
1345 ret i16 %1
1346 }
1348 define signext i32 @fcvt_bf16_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
1349 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_w_demanded_bits:
1350 ; CHECK32ZFBFMIN: # %bb.0:
1351 ; CHECK32ZFBFMIN-NEXT: addi a0, a0, 1
1352 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
1353 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1354 ; CHECK32ZFBFMIN-NEXT: fsh fa5, 0(a1)
1355 ; CHECK32ZFBFMIN-NEXT: ret
1356 ;
1357 ; RV32ID-LABEL: fcvt_bf16_w_demanded_bits:
1358 ; RV32ID: # %bb.0:
1359 ; RV32ID-NEXT: addi sp, sp, -16
1360 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1361 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1362 ; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1363 ; RV32ID-NEXT: mv s0, a1
1364 ; RV32ID-NEXT: addi s1, a0, 1
1365 ; RV32ID-NEXT: fcvt.s.w fa0, s1
1366 ; RV32ID-NEXT: call __truncsfbf2
1367 ; RV32ID-NEXT: fmv.x.w a0, fa0
1368 ; RV32ID-NEXT: sh a0, 0(s0)
1369 ; RV32ID-NEXT: mv a0, s1
1370 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1371 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1372 ; RV32ID-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1373 ; RV32ID-NEXT: addi sp, sp, 16
1374 ; RV32ID-NEXT: ret
1375 ;
1376 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w_demanded_bits:
1377 ; CHECK64ZFBFMIN: # %bb.0:
1378 ; CHECK64ZFBFMIN-NEXT: addiw a0, a0, 1
1379 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
1380 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1381 ; CHECK64ZFBFMIN-NEXT: fsh fa5, 0(a1)
1382 ; CHECK64ZFBFMIN-NEXT: ret
1383 ;
1384 ; RV64ID-LABEL: fcvt_bf16_w_demanded_bits:
1385 ; RV64ID: # %bb.0:
1386 ; RV64ID-NEXT: addi sp, sp, -32
1387 ; RV64ID-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1388 ; RV64ID-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1389 ; RV64ID-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1390 ; RV64ID-NEXT: mv s0, a1
1391 ; RV64ID-NEXT: addiw s1, a0, 1
1392 ; RV64ID-NEXT: fcvt.s.w fa0, s1
1393 ; RV64ID-NEXT: call __truncsfbf2
1394 ; RV64ID-NEXT: fmv.x.w a0, fa0
1395 ; RV64ID-NEXT: sh a0, 0(s0)
1396 ; RV64ID-NEXT: mv a0, s1
1397 ; RV64ID-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1398 ; RV64ID-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1399 ; RV64ID-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1400 ; RV64ID-NEXT: addi sp, sp, 32
1401 ; RV64ID-NEXT: ret
1402 %3 = add i32 %0, 1
1403 %4 = sitofp i32 %3 to bfloat
1404 store bfloat %4, ptr %1, align 2
1405 ret i32 %3
1406 }
1408 define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
1409 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_wu_demanded_bits:
1410 ; CHECK32ZFBFMIN: # %bb.0:
1411 ; CHECK32ZFBFMIN-NEXT: addi a0, a0, 1
1412 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
1413 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1414 ; CHECK32ZFBFMIN-NEXT: fsh fa5, 0(a1)
1415 ; CHECK32ZFBFMIN-NEXT: ret
1416 ;
1417 ; RV32ID-LABEL: fcvt_bf16_wu_demanded_bits:
1418 ; RV32ID: # %bb.0:
1419 ; RV32ID-NEXT: addi sp, sp, -16
1420 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1421 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1422 ; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1423 ; RV32ID-NEXT: mv s0, a1
1424 ; RV32ID-NEXT: addi s1, a0, 1
1425 ; RV32ID-NEXT: fcvt.s.wu fa0, s1
1426 ; RV32ID-NEXT: call __truncsfbf2
1427 ; RV32ID-NEXT: fmv.x.w a0, fa0
1428 ; RV32ID-NEXT: sh a0, 0(s0)
1429 ; RV32ID-NEXT: mv a0, s1
1430 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1431 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1432 ; RV32ID-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1433 ; RV32ID-NEXT: addi sp, sp, 16
1434 ; RV32ID-NEXT: ret
1435 ;
1436 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu_demanded_bits:
1437 ; CHECK64ZFBFMIN: # %bb.0:
1438 ; CHECK64ZFBFMIN-NEXT: addiw a0, a0, 1
1439 ; CHECK64ZFBFMIN-NEXT: slli a2, a0, 32
1440 ; CHECK64ZFBFMIN-NEXT: srli a2, a2, 32
1441 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a2
1442 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1443 ; CHECK64ZFBFMIN-NEXT: fsh fa5, 0(a1)
1444 ; CHECK64ZFBFMIN-NEXT: ret
1445 ;
1446 ; RV64ID-LABEL: fcvt_bf16_wu_demanded_bits:
1447 ; RV64ID: # %bb.0:
1448 ; RV64ID-NEXT: addi sp, sp, -32
1449 ; RV64ID-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1450 ; RV64ID-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1451 ; RV64ID-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1452 ; RV64ID-NEXT: mv s0, a1
1453 ; RV64ID-NEXT: addiw s1, a0, 1
1454 ; RV64ID-NEXT: fcvt.s.wu fa0, s1
1455 ; RV64ID-NEXT: call __truncsfbf2
1456 ; RV64ID-NEXT: fmv.x.w a0, fa0
1457 ; RV64ID-NEXT: sh a0, 0(s0)
1458 ; RV64ID-NEXT: mv a0, s1
1459 ; RV64ID-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1460 ; RV64ID-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1461 ; RV64ID-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1462 ; RV64ID-NEXT: addi sp, sp, 32
1463 ; RV64ID-NEXT: ret
1464 %3 = add i32 %0, 1
1465 %4 = uitofp i32 %3 to bfloat
1466 store bfloat %4, ptr %1, align 2
1467 ret i32 %3
1468 }
1470 define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
1471 ; CHECK32ZFBFMIN-LABEL: fcvt_w_s_i8:
1472 ; CHECK32ZFBFMIN: # %bb.0:
1473 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1474 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
1475 ; CHECK32ZFBFMIN-NEXT: ret
1476 ;
1477 ; RV32ID-LABEL: fcvt_w_s_i8:
1478 ; RV32ID: # %bb.0:
1479 ; RV32ID-NEXT: fmv.x.w a0, fa0
1480 ; RV32ID-NEXT: slli a0, a0, 16
1481 ; RV32ID-NEXT: fmv.w.x fa5, a0
1482 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
1483 ; RV32ID-NEXT: ret
1484 ;
1485 ; CHECK64ZFBFMIN-LABEL: fcvt_w_s_i8:
1486 ; CHECK64ZFBFMIN: # %bb.0:
1487 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1488 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
1489 ; CHECK64ZFBFMIN-NEXT: ret
1490 ;
1491 ; RV64ID-LABEL: fcvt_w_s_i8:
1492 ; RV64ID: # %bb.0:
1493 ; RV64ID-NEXT: fmv.x.w a0, fa0
1494 ; RV64ID-NEXT: slli a0, a0, 16
1495 ; RV64ID-NEXT: fmv.w.x fa5, a0
1496 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
1497 ; RV64ID-NEXT: ret
1498 %1 = fptosi bfloat %a to i8
1499 ret i8 %1
1500 }
1502 define signext i8 @fcvt_w_s_sat_i8(bfloat %a) nounwind {
1503 ; CHECK32ZFBFMIN-LABEL: fcvt_w_s_sat_i8:
1504 ; CHECK32ZFBFMIN: # %bb.0: # %start
1505 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1506 ; CHECK32ZFBFMIN-NEXT: feq.s a0, fa5, fa5
1507 ; CHECK32ZFBFMIN-NEXT: neg a0, a0
1508 ; CHECK32ZFBFMIN-NEXT: lui a1, 798720
1509 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a1
1510 ; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1511 ; CHECK32ZFBFMIN-NEXT: lui a1, 274400
1512 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a1
1513 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1514 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a1, fa5, rtz
1515 ; CHECK32ZFBFMIN-NEXT: and a0, a0, a1
1516 ; CHECK32ZFBFMIN-NEXT: ret
1517 ;
1518 ; RV32ID-LABEL: fcvt_w_s_sat_i8:
1519 ; RV32ID: # %bb.0: # %start
1520 ; RV32ID-NEXT: fmv.x.w a0, fa0
1521 ; RV32ID-NEXT: slli a0, a0, 16
1522 ; RV32ID-NEXT: fmv.w.x fa5, a0
1523 ; RV32ID-NEXT: feq.s a0, fa5, fa5
1524 ; RV32ID-NEXT: neg a0, a0
1525 ; RV32ID-NEXT: lui a1, 798720
1526 ; RV32ID-NEXT: fmv.w.x fa4, a1
1527 ; RV32ID-NEXT: fmax.s fa5, fa5, fa4
1528 ; RV32ID-NEXT: lui a1, 274400
1529 ; RV32ID-NEXT: fmv.w.x fa4, a1
1530 ; RV32ID-NEXT: fmin.s fa5, fa5, fa4
1531 ; RV32ID-NEXT: fcvt.w.s a1, fa5, rtz
1532 ; RV32ID-NEXT: and a0, a0, a1
1533 ; RV32ID-NEXT: ret
1534 ;
1535 ; CHECK64ZFBFMIN-LABEL: fcvt_w_s_sat_i8:
1536 ; CHECK64ZFBFMIN: # %bb.0: # %start
1537 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1538 ; CHECK64ZFBFMIN-NEXT: feq.s a0, fa5, fa5
1539 ; CHECK64ZFBFMIN-NEXT: neg a0, a0
1540 ; CHECK64ZFBFMIN-NEXT: lui a1, 798720
1541 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a1
1542 ; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1543 ; CHECK64ZFBFMIN-NEXT: lui a1, 274400
1544 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a1
1545 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1546 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a1, fa5, rtz
1547 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
1548 ; CHECK64ZFBFMIN-NEXT: ret
1549 ;
1550 ; RV64ID-LABEL: fcvt_w_s_sat_i8:
1551 ; RV64ID: # %bb.0: # %start
1552 ; RV64ID-NEXT: fmv.x.w a0, fa0
1553 ; RV64ID-NEXT: slli a0, a0, 16
1554 ; RV64ID-NEXT: fmv.w.x fa5, a0
1555 ; RV64ID-NEXT: feq.s a0, fa5, fa5
1556 ; RV64ID-NEXT: neg a0, a0
1557 ; RV64ID-NEXT: lui a1, 798720
1558 ; RV64ID-NEXT: fmv.w.x fa4, a1
1559 ; RV64ID-NEXT: fmax.s fa5, fa5, fa4
1560 ; RV64ID-NEXT: lui a1, 274400
1561 ; RV64ID-NEXT: fmv.w.x fa4, a1
1562 ; RV64ID-NEXT: fmin.s fa5, fa5, fa4
1563 ; RV64ID-NEXT: fcvt.l.s a1, fa5, rtz
1564 ; RV64ID-NEXT: and a0, a0, a1
1565 ; RV64ID-NEXT: ret
1566 start:
1567 %0 = tail call i8 @llvm.fptosi.sat.i8.bf16(bfloat %a)
1568 ret i8 %0
1569 }
1570 declare i8 @llvm.fptosi.sat.i8.bf16(bfloat)
1572 define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
1573 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
1574 ; CHECK32ZFBFMIN: # %bb.0:
1575 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1576 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1577 ; CHECK32ZFBFMIN-NEXT: ret
1578 ;
1579 ; RV32ID-LABEL: fcvt_wu_s_i8:
1580 ; RV32ID: # %bb.0:
1581 ; RV32ID-NEXT: fmv.x.w a0, fa0
1582 ; RV32ID-NEXT: slli a0, a0, 16
1583 ; RV32ID-NEXT: fmv.w.x fa5, a0
1584 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
1585 ; RV32ID-NEXT: ret
1586 ;
1587 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_i8:
1588 ; CHECK64ZFBFMIN: # %bb.0:
1589 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1590 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1591 ; CHECK64ZFBFMIN-NEXT: ret
1592 ;
1593 ; RV64ID-LABEL: fcvt_wu_s_i8:
1594 ; RV64ID: # %bb.0:
1595 ; RV64ID-NEXT: fmv.x.w a0, fa0
1596 ; RV64ID-NEXT: slli a0, a0, 16
1597 ; RV64ID-NEXT: fmv.w.x fa5, a0
1598 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
1599 ; RV64ID-NEXT: ret
1600 %1 = fptoui bfloat %a to i8
1601 ret i8 %1
1602 }
1604 define zeroext i8 @fcvt_wu_s_sat_i8(bfloat %a) nounwind {
1605 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_sat_i8:
1606 ; CHECK32ZFBFMIN: # %bb.0: # %start
1607 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1608 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, zero
1609 ; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1610 ; CHECK32ZFBFMIN-NEXT: lui a0, 276464
1611 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a0
1612 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1613 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1614 ; CHECK32ZFBFMIN-NEXT: ret
1615 ;
1616 ; RV32ID-LABEL: fcvt_wu_s_sat_i8:
1617 ; RV32ID: # %bb.0: # %start
1618 ; RV32ID-NEXT: fmv.x.w a0, fa0
1619 ; RV32ID-NEXT: slli a0, a0, 16
1620 ; RV32ID-NEXT: fmv.w.x fa5, a0
1621 ; RV32ID-NEXT: fmv.w.x fa4, zero
1622 ; RV32ID-NEXT: fmax.s fa5, fa5, fa4
1623 ; RV32ID-NEXT: lui a0, 276464
1624 ; RV32ID-NEXT: fmv.w.x fa4, a0
1625 ; RV32ID-NEXT: fmin.s fa5, fa5, fa4
1626 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
1627 ; RV32ID-NEXT: ret
1628 ;
1629 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_sat_i8:
1630 ; CHECK64ZFBFMIN: # %bb.0: # %start
1631 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1632 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, zero
1633 ; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1634 ; CHECK64ZFBFMIN-NEXT: lui a0, 276464
1635 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a0
1636 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1637 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1638 ; CHECK64ZFBFMIN-NEXT: ret
1639 ;
1640 ; RV64ID-LABEL: fcvt_wu_s_sat_i8:
1641 ; RV64ID: # %bb.0: # %start
1642 ; RV64ID-NEXT: fmv.x.w a0, fa0
1643 ; RV64ID-NEXT: slli a0, a0, 16
1644 ; RV64ID-NEXT: fmv.w.x fa5, a0
1645 ; RV64ID-NEXT: fmv.w.x fa4, zero
1646 ; RV64ID-NEXT: fmax.s fa5, fa5, fa4
1647 ; RV64ID-NEXT: lui a0, 276464
1648 ; RV64ID-NEXT: fmv.w.x fa4, a0
1649 ; RV64ID-NEXT: fmin.s fa5, fa5, fa4
1650 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
1651 ; RV64ID-NEXT: ret
1652 start:
1653 %0 = tail call i8 @llvm.fptoui.sat.i8.bf16(bfloat %a)
1654 ret i8 %0
1655 }
1656 declare i8 @llvm.fptoui.sat.i8.bf16(bfloat)
1658 define zeroext i32 @fcvt_wu_bf16_sat_zext(bfloat %a) nounwind {
1659 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_sat_zext:
1660 ; CHECK32ZFBFMIN: # %bb.0: # %start
1661 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1662 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1663 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1664 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
1665 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
1666 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
1667 ; CHECK32ZFBFMIN-NEXT: ret
1668 ;
1669 ; RV32ID-LABEL: fcvt_wu_bf16_sat_zext:
1670 ; RV32ID: # %bb.0: # %start
1671 ; RV32ID-NEXT: fmv.x.w a0, fa0
1672 ; RV32ID-NEXT: slli a0, a0, 16
1673 ; RV32ID-NEXT: fmv.w.x fa5, a0
1674 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
1675 ; RV32ID-NEXT: feq.s a1, fa5, fa5
1676 ; RV32ID-NEXT: seqz a1, a1
1677 ; RV32ID-NEXT: addi a1, a1, -1
1678 ; RV32ID-NEXT: and a0, a1, a0
1679 ; RV32ID-NEXT: ret
1680 ;
1681 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16_sat_zext:
1682 ; CHECK64ZFBFMIN: # %bb.0: # %start
1683 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1684 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1685 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1686 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
1687 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
1688 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
1689 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
1690 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
1691 ; CHECK64ZFBFMIN-NEXT: ret
1692 ;
1693 ; RV64ID-LABEL: fcvt_wu_bf16_sat_zext:
1694 ; RV64ID: # %bb.0: # %start
1695 ; RV64ID-NEXT: fmv.x.w a0, fa0
1696 ; RV64ID-NEXT: slli a0, a0, 16
1697 ; RV64ID-NEXT: fmv.w.x fa5, a0
1698 ; RV64ID-NEXT: fcvt.wu.s a0, fa5, rtz
1699 ; RV64ID-NEXT: feq.s a1, fa5, fa5
1700 ; RV64ID-NEXT: seqz a1, a1
1701 ; RV64ID-NEXT: addi a1, a1, -1
1702 ; RV64ID-NEXT: and a0, a0, a1
1703 ; RV64ID-NEXT: slli a0, a0, 32
1704 ; RV64ID-NEXT: srli a0, a0, 32
1705 ; RV64ID-NEXT: ret
1706 start:
1707 %0 = tail call i32 @llvm.fptoui.sat.i32.bf16(bfloat %a)
1708 ret i32 %0
1709 }
1711 define signext i32 @fcvt_w_bf16_sat_sext(bfloat %a) nounwind {
1712 ; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16_sat_sext:
1713 ; CHECK32ZFBFMIN: # %bb.0: # %start
1714 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1715 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
1716 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1717 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
1718 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
1719 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
1720 ; CHECK32ZFBFMIN-NEXT: ret
1721 ;
1722 ; RV32ID-LABEL: fcvt_w_bf16_sat_sext:
1723 ; RV32ID: # %bb.0: # %start
1724 ; RV32ID-NEXT: fmv.x.w a0, fa0
1725 ; RV32ID-NEXT: slli a0, a0, 16
1726 ; RV32ID-NEXT: fmv.w.x fa5, a0
1727 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
1728 ; RV32ID-NEXT: feq.s a1, fa5, fa5
1729 ; RV32ID-NEXT: seqz a1, a1
1730 ; RV32ID-NEXT: addi a1, a1, -1
1731 ; RV32ID-NEXT: and a0, a1, a0
1732 ; RV32ID-NEXT: ret
1733 ;
1734 ; CHECK64ZFBFMIN-LABEL: fcvt_w_bf16_sat_sext:
1735 ; CHECK64ZFBFMIN: # %bb.0: # %start
1736 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1737 ; CHECK64ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
1738 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1739 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
1740 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
1741 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
1742 ; CHECK64ZFBFMIN-NEXT: ret
1743 ;
1744 ; RV64ID-LABEL: fcvt_w_bf16_sat_sext:
1745 ; RV64ID: # %bb.0: # %start
1746 ; RV64ID-NEXT: fmv.x.w a0, fa0
1747 ; RV64ID-NEXT: slli a0, a0, 16
1748 ; RV64ID-NEXT: fmv.w.x fa5, a0
1749 ; RV64ID-NEXT: fcvt.w.s a0, fa5, rtz
1750 ; RV64ID-NEXT: feq.s a1, fa5, fa5
1751 ; RV64ID-NEXT: seqz a1, a1
1752 ; RV64ID-NEXT: addi a1, a1, -1
1753 ; RV64ID-NEXT: and a0, a1, a0
1754 ; RV64ID-NEXT: ret
1755 start:
1756 %0 = tail call i32 @llvm.fptosi.sat.i32.bf16(bfloat %a)
1757 ret i32 %0
1758 }