| blob | 70d3291d3a8402920658a5113ef6c8b54dcabb1b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV32I %s
4 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -mattr=+d -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefix=RV32IFD %s
6 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -mattr=+zdinx -verify-machineinstrs < %s \
7 ; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
8 ; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefix=RV64I %s
10 ; RUN: llc -mtriple=riscv64 -target-abi=lp64 -mattr=+d -verify-machineinstrs < %s \
11 ; RUN: | FileCheck -check-prefix=RV64IFD %s
12 ; RUN: llc -mtriple=riscv64 -target-abi=lp64 -mattr=+zdinx -verify-machineinstrs < %s \
13 ; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
14 ;
15 ; This file tests cases where simple floating point operations can be
16 ; profitably handled though bit manipulation if a soft-float ABI is being used
17 ; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
18 ; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
19 ; in cases where we perform custom legalisation (e.g. RV32IFD).
21 ; TODO: Add an appropriate target-specific DAG combine that can handle
22 ; RISCVISD::SplitF64/BuildPairF64 used for RV32IFD.
24 define double @fneg(double %a) nounwind {
25 ; RV32I-LABEL: fneg:
26 ; RV32I: # %bb.0:
27 ; RV32I-NEXT: lui a2, 524288
28 ; RV32I-NEXT: xor a1, a1, a2
29 ; RV32I-NEXT: ret
30 ;
31 ; RV32IFD-LABEL: fneg:
32 ; RV32IFD: # %bb.0:
33 ; RV32IFD-NEXT: lui a2, 524288
34 ; RV32IFD-NEXT: xor a1, a1, a2
35 ; RV32IFD-NEXT: ret
36 ;
37 ; RV32IZFINXZDINX-LABEL: fneg:
38 ; RV32IZFINXZDINX: # %bb.0:
39 ; RV32IZFINXZDINX-NEXT: lui a2, 524288
40 ; RV32IZFINXZDINX-NEXT: xor a1, a1, a2
41 ; RV32IZFINXZDINX-NEXT: ret
42 ;
43 ; RV64I-LABEL: fneg:
44 ; RV64I: # %bb.0:
45 ; RV64I-NEXT: li a1, -1
46 ; RV64I-NEXT: slli a1, a1, 63
47 ; RV64I-NEXT: xor a0, a0, a1
48 ; RV64I-NEXT: ret
49 ;
50 ; RV64IFD-LABEL: fneg:
51 ; RV64IFD: # %bb.0:
52 ; RV64IFD-NEXT: li a1, -1
53 ; RV64IFD-NEXT: slli a1, a1, 63
54 ; RV64IFD-NEXT: xor a0, a0, a1
55 ; RV64IFD-NEXT: ret
56 ;
57 ; RV64IZFINXZDINX-LABEL: fneg:
58 ; RV64IZFINXZDINX: # %bb.0:
59 ; RV64IZFINXZDINX-NEXT: li a1, -1
60 ; RV64IZFINXZDINX-NEXT: slli a1, a1, 63
61 ; RV64IZFINXZDINX-NEXT: xor a0, a0, a1
62 ; RV64IZFINXZDINX-NEXT: ret
63 %1 = fneg double %a
64 ret double %1
65 }
67 declare double @llvm.fabs.f64(double)
69 define double @fabs(double %a) nounwind {
70 ; RV32I-LABEL: fabs:
71 ; RV32I: # %bb.0:
72 ; RV32I-NEXT: slli a1, a1, 1
73 ; RV32I-NEXT: srli a1, a1, 1
74 ; RV32I-NEXT: ret
75 ;
76 ; RV32IFD-LABEL: fabs:
77 ; RV32IFD: # %bb.0:
78 ; RV32IFD-NEXT: slli a1, a1, 1
79 ; RV32IFD-NEXT: srli a1, a1, 1
80 ; RV32IFD-NEXT: ret
81 ;
82 ; RV32IZFINXZDINX-LABEL: fabs:
83 ; RV32IZFINXZDINX: # %bb.0:
84 ; RV32IZFINXZDINX-NEXT: slli a1, a1, 1
85 ; RV32IZFINXZDINX-NEXT: srli a1, a1, 1
86 ; RV32IZFINXZDINX-NEXT: ret
87 ;
88 ; RV64I-LABEL: fabs:
89 ; RV64I: # %bb.0:
90 ; RV64I-NEXT: slli a0, a0, 1
91 ; RV64I-NEXT: srli a0, a0, 1
92 ; RV64I-NEXT: ret
93 ;
94 ; RV64IFD-LABEL: fabs:
95 ; RV64IFD: # %bb.0:
96 ; RV64IFD-NEXT: slli a0, a0, 1
97 ; RV64IFD-NEXT: srli a0, a0, 1
98 ; RV64IFD-NEXT: ret
99 ;
100 ; RV64IZFINXZDINX-LABEL: fabs:
101 ; RV64IZFINXZDINX: # %bb.0:
102 ; RV64IZFINXZDINX-NEXT: slli a0, a0, 1
103 ; RV64IZFINXZDINX-NEXT: srli a0, a0, 1
104 ; RV64IZFINXZDINX-NEXT: ret
105 %1 = call double @llvm.fabs.f64(double %a)
106 ret double %1
107 }
109 declare double @llvm.copysign.f64(double, double)
111 ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
112 ; operations if floating point isn't supported. A combine could be written to
113 ; do the same even when f64 is legal.
115 define double @fcopysign_fneg(double %a, double %b) nounwind {
116 ; RV32I-LABEL: fcopysign_fneg:
117 ; RV32I: # %bb.0:
118 ; RV32I-NEXT: not a2, a3
119 ; RV32I-NEXT: lui a3, 524288
120 ; RV32I-NEXT: and a2, a2, a3
121 ; RV32I-NEXT: slli a1, a1, 1
122 ; RV32I-NEXT: srli a1, a1, 1
123 ; RV32I-NEXT: or a1, a1, a2
124 ; RV32I-NEXT: ret
125 ;
126 ; RV32IFD-LABEL: fcopysign_fneg:
127 ; RV32IFD: # %bb.0:
128 ; RV32IFD-NEXT: addi sp, sp, -16
129 ; RV32IFD-NEXT: sw a2, 8(sp)
130 ; RV32IFD-NEXT: sw a3, 12(sp)
131 ; RV32IFD-NEXT: fld fa5, 8(sp)
132 ; RV32IFD-NEXT: sw a0, 8(sp)
133 ; RV32IFD-NEXT: sw a1, 12(sp)
134 ; RV32IFD-NEXT: fld fa4, 8(sp)
135 ; RV32IFD-NEXT: fsgnjn.d fa5, fa4, fa5
136 ; RV32IFD-NEXT: fsd fa5, 8(sp)
137 ; RV32IFD-NEXT: lw a0, 8(sp)
138 ; RV32IFD-NEXT: lw a1, 12(sp)
139 ; RV32IFD-NEXT: addi sp, sp, 16
140 ; RV32IFD-NEXT: ret
141 ;
142 ; RV32IZFINXZDINX-LABEL: fcopysign_fneg:
143 ; RV32IZFINXZDINX: # %bb.0:
144 ; RV32IZFINXZDINX-NEXT: fsgnjn.d a0, a0, a2
145 ; RV32IZFINXZDINX-NEXT: ret
146 ;
147 ; RV64I-LABEL: fcopysign_fneg:
148 ; RV64I: # %bb.0:
149 ; RV64I-NEXT: not a1, a1
150 ; RV64I-NEXT: slli a0, a0, 1
151 ; RV64I-NEXT: srli a0, a0, 1
152 ; RV64I-NEXT: srli a1, a1, 63
153 ; RV64I-NEXT: slli a1, a1, 63
154 ; RV64I-NEXT: or a0, a0, a1
155 ; RV64I-NEXT: ret
156 ;
157 ; RV64IFD-LABEL: fcopysign_fneg:
158 ; RV64IFD: # %bb.0:
159 ; RV64IFD-NEXT: fmv.d.x fa5, a0
160 ; RV64IFD-NEXT: not a0, a1
161 ; RV64IFD-NEXT: fmv.d.x fa4, a0
162 ; RV64IFD-NEXT: fsgnj.d fa5, fa5, fa4
163 ; RV64IFD-NEXT: fmv.x.d a0, fa5
164 ; RV64IFD-NEXT: ret
165 ;
166 ; RV64IZFINXZDINX-LABEL: fcopysign_fneg:
167 ; RV64IZFINXZDINX: # %bb.0:
168 ; RV64IZFINXZDINX-NEXT: not a1, a1
169 ; RV64IZFINXZDINX-NEXT: fsgnj.d a0, a0, a1
170 ; RV64IZFINXZDINX-NEXT: ret
171 %1 = fneg double %b
172 %2 = call double @llvm.copysign.f64(double %a, double %1)
173 ret double %2
174 }