| blob | feea4f19720b0ba40d8bccbde87b6d4d6dca5544 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=RV32IZFINXZDINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=RV64IZFINXZDINX %s
10 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
11 ; RUN: | FileCheck -check-prefix=RV32I %s
12 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
13 ; RUN: | FileCheck -check-prefix=RV64I %s
15 define float @fcvt_s_d(double %a) nounwind {
16 ; CHECKIFD-LABEL: fcvt_s_d:
17 ; CHECKIFD: # %bb.0:
18 ; CHECKIFD-NEXT: fcvt.s.d fa0, fa0
19 ; CHECKIFD-NEXT: ret
20 ;
21 ; RV32IZFINXZDINX-LABEL: fcvt_s_d:
22 ; RV32IZFINXZDINX: # %bb.0:
23 ; RV32IZFINXZDINX-NEXT: fcvt.s.d a0, a0
24 ; RV32IZFINXZDINX-NEXT: ret
25 ;
26 ; RV64IZFINXZDINX-LABEL: fcvt_s_d:
27 ; RV64IZFINXZDINX: # %bb.0:
28 ; RV64IZFINXZDINX-NEXT: fcvt.s.d a0, a0
29 ; RV64IZFINXZDINX-NEXT: ret
30 ;
31 ; RV32I-LABEL: fcvt_s_d:
32 ; RV32I: # %bb.0:
33 ; RV32I-NEXT: addi sp, sp, -16
34 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
35 ; RV32I-NEXT: call __truncdfsf2
36 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
37 ; RV32I-NEXT: addi sp, sp, 16
38 ; RV32I-NEXT: ret
39 ;
40 ; RV64I-LABEL: fcvt_s_d:
41 ; RV64I: # %bb.0:
42 ; RV64I-NEXT: addi sp, sp, -16
43 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
44 ; RV64I-NEXT: call __truncdfsf2
45 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
46 ; RV64I-NEXT: addi sp, sp, 16
47 ; RV64I-NEXT: ret
48 %1 = fptrunc double %a to float
49 ret float %1
50 }
52 define double @fcvt_d_s(float %a) nounwind {
53 ; CHECKIFD-LABEL: fcvt_d_s:
54 ; CHECKIFD: # %bb.0:
55 ; CHECKIFD-NEXT: fcvt.d.s fa0, fa0
56 ; CHECKIFD-NEXT: ret
57 ;
58 ; RV32IZFINXZDINX-LABEL: fcvt_d_s:
59 ; RV32IZFINXZDINX: # %bb.0:
60 ; RV32IZFINXZDINX-NEXT: fcvt.d.s a0, a0
61 ; RV32IZFINXZDINX-NEXT: ret
62 ;
63 ; RV64IZFINXZDINX-LABEL: fcvt_d_s:
64 ; RV64IZFINXZDINX: # %bb.0:
65 ; RV64IZFINXZDINX-NEXT: fcvt.d.s a0, a0
66 ; RV64IZFINXZDINX-NEXT: ret
67 ;
68 ; RV32I-LABEL: fcvt_d_s:
69 ; RV32I: # %bb.0:
70 ; RV32I-NEXT: addi sp, sp, -16
71 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
72 ; RV32I-NEXT: call __extendsfdf2
73 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
74 ; RV32I-NEXT: addi sp, sp, 16
75 ; RV32I-NEXT: ret
76 ;
77 ; RV64I-LABEL: fcvt_d_s:
78 ; RV64I: # %bb.0:
79 ; RV64I-NEXT: addi sp, sp, -16
80 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
81 ; RV64I-NEXT: call __extendsfdf2
82 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
83 ; RV64I-NEXT: addi sp, sp, 16
84 ; RV64I-NEXT: ret
85 %1 = fpext float %a to double
86 ret double %1
87 }
89 define i32 @fcvt_w_d(double %a) nounwind {
90 ; CHECKIFD-LABEL: fcvt_w_d:
91 ; CHECKIFD: # %bb.0:
92 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
93 ; CHECKIFD-NEXT: ret
94 ;
95 ; RV32IZFINXZDINX-LABEL: fcvt_w_d:
96 ; RV32IZFINXZDINX: # %bb.0:
97 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
98 ; RV32IZFINXZDINX-NEXT: ret
99 ;
100 ; RV64IZFINXZDINX-LABEL: fcvt_w_d:
101 ; RV64IZFINXZDINX: # %bb.0:
102 ; RV64IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
103 ; RV64IZFINXZDINX-NEXT: ret
104 ;
105 ; RV32I-LABEL: fcvt_w_d:
106 ; RV32I: # %bb.0:
107 ; RV32I-NEXT: addi sp, sp, -16
108 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
109 ; RV32I-NEXT: call __fixdfsi
110 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
111 ; RV32I-NEXT: addi sp, sp, 16
112 ; RV32I-NEXT: ret
113 ;
114 ; RV64I-LABEL: fcvt_w_d:
115 ; RV64I: # %bb.0:
116 ; RV64I-NEXT: addi sp, sp, -16
117 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
118 ; RV64I-NEXT: call __fixdfsi
119 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
120 ; RV64I-NEXT: addi sp, sp, 16
121 ; RV64I-NEXT: ret
122 %1 = fptosi double %a to i32
123 ret i32 %1
124 }
126 define i32 @fcvt_w_d_sat(double %a) nounwind {
127 ; CHECKIFD-LABEL: fcvt_w_d_sat:
128 ; CHECKIFD: # %bb.0: # %start
129 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
130 ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
131 ; CHECKIFD-NEXT: seqz a1, a1
132 ; CHECKIFD-NEXT: addi a1, a1, -1
133 ; CHECKIFD-NEXT: and a0, a1, a0
134 ; CHECKIFD-NEXT: ret
135 ;
136 ; RV32IZFINXZDINX-LABEL: fcvt_w_d_sat:
137 ; RV32IZFINXZDINX: # %bb.0: # %start
138 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rtz
139 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
140 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
141 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
142 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
143 ; RV32IZFINXZDINX-NEXT: ret
144 ;
145 ; RV64IZFINXZDINX-LABEL: fcvt_w_d_sat:
146 ; RV64IZFINXZDINX: # %bb.0: # %start
147 ; RV64IZFINXZDINX-NEXT: fcvt.w.d a1, a0, rtz
148 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
149 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
150 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
151 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
152 ; RV64IZFINXZDINX-NEXT: ret
153 ;
154 ; RV32I-LABEL: fcvt_w_d_sat:
155 ; RV32I: # %bb.0: # %start
156 ; RV32I-NEXT: addi sp, sp, -32
157 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
158 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
159 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
160 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
161 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
162 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
163 ; RV32I-NEXT: mv s0, a1
164 ; RV32I-NEXT: mv s1, a0
165 ; RV32I-NEXT: lui a3, 269824
166 ; RV32I-NEXT: addi a3, a3, -1
167 ; RV32I-NEXT: lui a2, 1047552
168 ; RV32I-NEXT: call __gtdf2
169 ; RV32I-NEXT: mv s2, a0
170 ; RV32I-NEXT: lui a3, 794112
171 ; RV32I-NEXT: mv a0, s1
172 ; RV32I-NEXT: mv a1, s0
173 ; RV32I-NEXT: li a2, 0
174 ; RV32I-NEXT: call __gedf2
175 ; RV32I-NEXT: mv s4, a0
176 ; RV32I-NEXT: mv a0, s1
177 ; RV32I-NEXT: mv a1, s0
178 ; RV32I-NEXT: call __fixdfsi
179 ; RV32I-NEXT: mv s3, a0
180 ; RV32I-NEXT: lui a0, 524288
181 ; RV32I-NEXT: bgez s4, .LBB3_2
182 ; RV32I-NEXT: # %bb.1: # %start
183 ; RV32I-NEXT: lui s3, 524288
184 ; RV32I-NEXT: .LBB3_2: # %start
185 ; RV32I-NEXT: blez s2, .LBB3_4
186 ; RV32I-NEXT: # %bb.3: # %start
187 ; RV32I-NEXT: addi s3, a0, -1
188 ; RV32I-NEXT: .LBB3_4: # %start
189 ; RV32I-NEXT: mv a0, s1
190 ; RV32I-NEXT: mv a1, s0
191 ; RV32I-NEXT: mv a2, s1
192 ; RV32I-NEXT: mv a3, s0
193 ; RV32I-NEXT: call __unorddf2
194 ; RV32I-NEXT: snez a0, a0
195 ; RV32I-NEXT: addi a0, a0, -1
196 ; RV32I-NEXT: and a0, a0, s3
197 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
198 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
199 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
200 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
201 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
202 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
203 ; RV32I-NEXT: addi sp, sp, 32
204 ; RV32I-NEXT: ret
205 ;
206 ; RV64I-LABEL: fcvt_w_d_sat:
207 ; RV64I: # %bb.0: # %start
208 ; RV64I-NEXT: addi sp, sp, -48
209 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
210 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
211 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
212 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
213 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
214 ; RV64I-NEXT: mv s0, a0
215 ; RV64I-NEXT: li a1, -497
216 ; RV64I-NEXT: slli a1, a1, 53
217 ; RV64I-NEXT: call __gedf2
218 ; RV64I-NEXT: mv s2, a0
219 ; RV64I-NEXT: mv a0, s0
220 ; RV64I-NEXT: call __fixdfdi
221 ; RV64I-NEXT: mv s1, a0
222 ; RV64I-NEXT: lui s3, 524288
223 ; RV64I-NEXT: bgez s2, .LBB3_2
224 ; RV64I-NEXT: # %bb.1: # %start
225 ; RV64I-NEXT: lui s1, 524288
226 ; RV64I-NEXT: .LBB3_2: # %start
227 ; RV64I-NEXT: li a0, 527
228 ; RV64I-NEXT: slli a0, a0, 31
229 ; RV64I-NEXT: addi a0, a0, -1
230 ; RV64I-NEXT: slli a1, a0, 22
231 ; RV64I-NEXT: mv a0, s0
232 ; RV64I-NEXT: call __gtdf2
233 ; RV64I-NEXT: blez a0, .LBB3_4
234 ; RV64I-NEXT: # %bb.3: # %start
235 ; RV64I-NEXT: addiw s1, s3, -1
236 ; RV64I-NEXT: .LBB3_4: # %start
237 ; RV64I-NEXT: mv a0, s0
238 ; RV64I-NEXT: mv a1, s0
239 ; RV64I-NEXT: call __unorddf2
240 ; RV64I-NEXT: snez a0, a0
241 ; RV64I-NEXT: addi a0, a0, -1
242 ; RV64I-NEXT: and a0, a0, s1
243 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
244 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
245 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
246 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
247 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
248 ; RV64I-NEXT: addi sp, sp, 48
249 ; RV64I-NEXT: ret
250 start:
251 %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
252 ret i32 %0
253 }
254 declare i32 @llvm.fptosi.sat.i32.f64(double)
256 ; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
257 ; because fptosi will produce poison if the result doesn't fit into an i32.
258 define i32 @fcvt_wu_d(double %a) nounwind {
259 ; CHECKIFD-LABEL: fcvt_wu_d:
260 ; CHECKIFD: # %bb.0:
261 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
262 ; CHECKIFD-NEXT: ret
263 ;
264 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d:
265 ; RV32IZFINXZDINX: # %bb.0:
266 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
267 ; RV32IZFINXZDINX-NEXT: ret
268 ;
269 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d:
270 ; RV64IZFINXZDINX: # %bb.0:
271 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
272 ; RV64IZFINXZDINX-NEXT: ret
273 ;
274 ; RV32I-LABEL: fcvt_wu_d:
275 ; RV32I: # %bb.0:
276 ; RV32I-NEXT: addi sp, sp, -16
277 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
278 ; RV32I-NEXT: call __fixunsdfsi
279 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
280 ; RV32I-NEXT: addi sp, sp, 16
281 ; RV32I-NEXT: ret
282 ;
283 ; RV64I-LABEL: fcvt_wu_d:
284 ; RV64I: # %bb.0:
285 ; RV64I-NEXT: addi sp, sp, -16
286 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
287 ; RV64I-NEXT: call __fixunsdfsi
288 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
289 ; RV64I-NEXT: addi sp, sp, 16
290 ; RV64I-NEXT: ret
291 %1 = fptoui double %a to i32
292 ret i32 %1
293 }
295 ; Test where the fptoui has multiple uses, one of which causes a sext to be
296 ; inserted on RV64.
297 define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
298 ; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
299 ; CHECKIFD: # %bb.0:
300 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
301 ; CHECKIFD-NEXT: seqz a1, a0
302 ; CHECKIFD-NEXT: add a0, a0, a1
303 ; CHECKIFD-NEXT: ret
304 ;
305 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
306 ; RV32IZFINXZDINX: # %bb.0:
307 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
308 ; RV32IZFINXZDINX-NEXT: seqz a1, a0
309 ; RV32IZFINXZDINX-NEXT: add a0, a0, a1
310 ; RV32IZFINXZDINX-NEXT: ret
311 ;
312 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d_multiple_use:
313 ; RV64IZFINXZDINX: # %bb.0:
314 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
315 ; RV64IZFINXZDINX-NEXT: seqz a1, a0
316 ; RV64IZFINXZDINX-NEXT: add a0, a0, a1
317 ; RV64IZFINXZDINX-NEXT: ret
318 ;
319 ; RV32I-LABEL: fcvt_wu_d_multiple_use:
320 ; RV32I: # %bb.0:
321 ; RV32I-NEXT: addi sp, sp, -16
322 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
323 ; RV32I-NEXT: call __fixunsdfsi
324 ; RV32I-NEXT: seqz a1, a0
325 ; RV32I-NEXT: add a0, a0, a1
326 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
327 ; RV32I-NEXT: addi sp, sp, 16
328 ; RV32I-NEXT: ret
329 ;
330 ; RV64I-LABEL: fcvt_wu_d_multiple_use:
331 ; RV64I: # %bb.0:
332 ; RV64I-NEXT: addi sp, sp, -16
333 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
334 ; RV64I-NEXT: call __fixunsdfsi
335 ; RV64I-NEXT: seqz a1, a0
336 ; RV64I-NEXT: add a0, a0, a1
337 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
338 ; RV64I-NEXT: addi sp, sp, 16
339 ; RV64I-NEXT: ret
340 %a = fptoui double %x to i32
341 %b = icmp eq i32 %a, 0
342 %c = select i1 %b, i32 1, i32 %a
343 ret i32 %c
344 }
346 define i32 @fcvt_wu_d_sat(double %a) nounwind {
347 ; RV32IFD-LABEL: fcvt_wu_d_sat:
348 ; RV32IFD: # %bb.0: # %start
349 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
350 ; RV32IFD-NEXT: feq.d a1, fa0, fa0
351 ; RV32IFD-NEXT: seqz a1, a1
352 ; RV32IFD-NEXT: addi a1, a1, -1
353 ; RV32IFD-NEXT: and a0, a1, a0
354 ; RV32IFD-NEXT: ret
355 ;
356 ; RV64IFD-LABEL: fcvt_wu_d_sat:
357 ; RV64IFD: # %bb.0: # %start
358 ; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
359 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
360 ; RV64IFD-NEXT: seqz a1, a1
361 ; RV64IFD-NEXT: addi a1, a1, -1
362 ; RV64IFD-NEXT: and a0, a0, a1
363 ; RV64IFD-NEXT: slli a0, a0, 32
364 ; RV64IFD-NEXT: srli a0, a0, 32
365 ; RV64IFD-NEXT: ret
366 ;
367 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d_sat:
368 ; RV32IZFINXZDINX: # %bb.0: # %start
369 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rtz
370 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
371 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
372 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
373 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
374 ; RV32IZFINXZDINX-NEXT: ret
375 ;
376 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d_sat:
377 ; RV64IZFINXZDINX: # %bb.0: # %start
378 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a1, a0, rtz
379 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
380 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
381 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
382 ; RV64IZFINXZDINX-NEXT: and a0, a1, a0
383 ; RV64IZFINXZDINX-NEXT: slli a0, a0, 32
384 ; RV64IZFINXZDINX-NEXT: srli a0, a0, 32
385 ; RV64IZFINXZDINX-NEXT: ret
386 ;
387 ; RV32I-LABEL: fcvt_wu_d_sat:
388 ; RV32I: # %bb.0: # %start
389 ; RV32I-NEXT: addi sp, sp, -32
390 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
391 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
392 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
393 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
394 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
395 ; RV32I-NEXT: mv s0, a1
396 ; RV32I-NEXT: mv s1, a0
397 ; RV32I-NEXT: lui a3, 270080
398 ; RV32I-NEXT: addi a3, a3, -1
399 ; RV32I-NEXT: lui a2, 1048064
400 ; RV32I-NEXT: call __gtdf2
401 ; RV32I-NEXT: sgtz a0, a0
402 ; RV32I-NEXT: neg s2, a0
403 ; RV32I-NEXT: mv a0, s1
404 ; RV32I-NEXT: mv a1, s0
405 ; RV32I-NEXT: li a2, 0
406 ; RV32I-NEXT: li a3, 0
407 ; RV32I-NEXT: call __gedf2
408 ; RV32I-NEXT: slti a0, a0, 0
409 ; RV32I-NEXT: addi s3, a0, -1
410 ; RV32I-NEXT: mv a0, s1
411 ; RV32I-NEXT: mv a1, s0
412 ; RV32I-NEXT: call __fixunsdfsi
413 ; RV32I-NEXT: and a0, s3, a0
414 ; RV32I-NEXT: or a0, s2, a0
415 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
416 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
417 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
418 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
419 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
420 ; RV32I-NEXT: addi sp, sp, 32
421 ; RV32I-NEXT: ret
422 ;
423 ; RV64I-LABEL: fcvt_wu_d_sat:
424 ; RV64I: # %bb.0: # %start
425 ; RV64I-NEXT: addi sp, sp, -32
426 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
427 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
428 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
429 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
430 ; RV64I-NEXT: mv s2, a0
431 ; RV64I-NEXT: li a1, 0
432 ; RV64I-NEXT: call __gedf2
433 ; RV64I-NEXT: mv s0, a0
434 ; RV64I-NEXT: mv a0, s2
435 ; RV64I-NEXT: call __fixunsdfdi
436 ; RV64I-NEXT: mv s1, a0
437 ; RV64I-NEXT: li a0, 1055
438 ; RV64I-NEXT: slli a0, a0, 31
439 ; RV64I-NEXT: addi a0, a0, -1
440 ; RV64I-NEXT: slli a1, a0, 21
441 ; RV64I-NEXT: mv a0, s2
442 ; RV64I-NEXT: call __gtdf2
443 ; RV64I-NEXT: blez a0, .LBB6_2
444 ; RV64I-NEXT: # %bb.1: # %start
445 ; RV64I-NEXT: li a0, -1
446 ; RV64I-NEXT: srli a0, a0, 32
447 ; RV64I-NEXT: j .LBB6_3
448 ; RV64I-NEXT: .LBB6_2:
449 ; RV64I-NEXT: slti a0, s0, 0
450 ; RV64I-NEXT: addi a0, a0, -1
451 ; RV64I-NEXT: and a0, a0, s1
452 ; RV64I-NEXT: .LBB6_3: # %start
453 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
454 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
455 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
456 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
457 ; RV64I-NEXT: addi sp, sp, 32
458 ; RV64I-NEXT: ret
459 start:
460 %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
461 ret i32 %0
462 }
463 declare i32 @llvm.fptoui.sat.i32.f64(double)
465 define double @fcvt_d_w(i32 %a) nounwind {
466 ; CHECKIFD-LABEL: fcvt_d_w:
467 ; CHECKIFD: # %bb.0:
468 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
469 ; CHECKIFD-NEXT: ret
470 ;
471 ; RV32IZFINXZDINX-LABEL: fcvt_d_w:
472 ; RV32IZFINXZDINX: # %bb.0:
473 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
474 ; RV32IZFINXZDINX-NEXT: ret
475 ;
476 ; RV64IZFINXZDINX-LABEL: fcvt_d_w:
477 ; RV64IZFINXZDINX: # %bb.0:
478 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
479 ; RV64IZFINXZDINX-NEXT: ret
480 ;
481 ; RV32I-LABEL: fcvt_d_w:
482 ; RV32I: # %bb.0:
483 ; RV32I-NEXT: addi sp, sp, -16
484 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
485 ; RV32I-NEXT: call __floatsidf
486 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
487 ; RV32I-NEXT: addi sp, sp, 16
488 ; RV32I-NEXT: ret
489 ;
490 ; RV64I-LABEL: fcvt_d_w:
491 ; RV64I: # %bb.0:
492 ; RV64I-NEXT: addi sp, sp, -16
493 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
494 ; RV64I-NEXT: sext.w a0, a0
495 ; RV64I-NEXT: call __floatsidf
496 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
497 ; RV64I-NEXT: addi sp, sp, 16
498 ; RV64I-NEXT: ret
499 %1 = sitofp i32 %a to double
500 ret double %1
501 }
503 define double @fcvt_d_w_load(ptr %p) nounwind {
504 ; CHECKIFD-LABEL: fcvt_d_w_load:
505 ; CHECKIFD: # %bb.0:
506 ; CHECKIFD-NEXT: lw a0, 0(a0)
507 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
508 ; CHECKIFD-NEXT: ret
509 ;
510 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_load:
511 ; RV32IZFINXZDINX: # %bb.0:
512 ; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
513 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
514 ; RV32IZFINXZDINX-NEXT: ret
515 ;
516 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_load:
517 ; RV64IZFINXZDINX: # %bb.0:
518 ; RV64IZFINXZDINX-NEXT: lw a0, 0(a0)
519 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
520 ; RV64IZFINXZDINX-NEXT: ret
521 ;
522 ; RV32I-LABEL: fcvt_d_w_load:
523 ; RV32I: # %bb.0:
524 ; RV32I-NEXT: addi sp, sp, -16
525 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
526 ; RV32I-NEXT: lw a0, 0(a0)
527 ; RV32I-NEXT: call __floatsidf
528 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
529 ; RV32I-NEXT: addi sp, sp, 16
530 ; RV32I-NEXT: ret
531 ;
532 ; RV64I-LABEL: fcvt_d_w_load:
533 ; RV64I: # %bb.0:
534 ; RV64I-NEXT: addi sp, sp, -16
535 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
536 ; RV64I-NEXT: lw a0, 0(a0)
537 ; RV64I-NEXT: call __floatsidf
538 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
539 ; RV64I-NEXT: addi sp, sp, 16
540 ; RV64I-NEXT: ret
541 %a = load i32, ptr %p
542 %1 = sitofp i32 %a to double
543 ret double %1
544 }
546 define double @fcvt_d_wu(i32 %a) nounwind {
547 ; CHECKIFD-LABEL: fcvt_d_wu:
548 ; CHECKIFD: # %bb.0:
549 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
550 ; CHECKIFD-NEXT: ret
551 ;
552 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu:
553 ; RV32IZFINXZDINX: # %bb.0:
554 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
555 ; RV32IZFINXZDINX-NEXT: ret
556 ;
557 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu:
558 ; RV64IZFINXZDINX: # %bb.0:
559 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
560 ; RV64IZFINXZDINX-NEXT: ret
561 ;
562 ; RV32I-LABEL: fcvt_d_wu:
563 ; RV32I: # %bb.0:
564 ; RV32I-NEXT: addi sp, sp, -16
565 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
566 ; RV32I-NEXT: call __floatunsidf
567 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
568 ; RV32I-NEXT: addi sp, sp, 16
569 ; RV32I-NEXT: ret
570 ;
571 ; RV64I-LABEL: fcvt_d_wu:
572 ; RV64I: # %bb.0:
573 ; RV64I-NEXT: addi sp, sp, -16
574 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
575 ; RV64I-NEXT: sext.w a0, a0
576 ; RV64I-NEXT: call __floatunsidf
577 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
578 ; RV64I-NEXT: addi sp, sp, 16
579 ; RV64I-NEXT: ret
580 %1 = uitofp i32 %a to double
581 ret double %1
582 }
584 define double @fcvt_d_wu_load(ptr %p) nounwind {
585 ; RV32IFD-LABEL: fcvt_d_wu_load:
586 ; RV32IFD: # %bb.0:
587 ; RV32IFD-NEXT: lw a0, 0(a0)
588 ; RV32IFD-NEXT: fcvt.d.wu fa0, a0
589 ; RV32IFD-NEXT: ret
590 ;
591 ; RV64IFD-LABEL: fcvt_d_wu_load:
592 ; RV64IFD: # %bb.0:
593 ; RV64IFD-NEXT: lwu a0, 0(a0)
594 ; RV64IFD-NEXT: fcvt.d.wu fa0, a0
595 ; RV64IFD-NEXT: ret
596 ;
597 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_load:
598 ; RV32IZFINXZDINX: # %bb.0:
599 ; RV32IZFINXZDINX-NEXT: lw a0, 0(a0)
600 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
601 ; RV32IZFINXZDINX-NEXT: ret
602 ;
603 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_load:
604 ; RV64IZFINXZDINX: # %bb.0:
605 ; RV64IZFINXZDINX-NEXT: lwu a0, 0(a0)
606 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
607 ; RV64IZFINXZDINX-NEXT: ret
608 ;
609 ; RV32I-LABEL: fcvt_d_wu_load:
610 ; RV32I: # %bb.0:
611 ; RV32I-NEXT: addi sp, sp, -16
612 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
613 ; RV32I-NEXT: lw a0, 0(a0)
614 ; RV32I-NEXT: call __floatunsidf
615 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
616 ; RV32I-NEXT: addi sp, sp, 16
617 ; RV32I-NEXT: ret
618 ;
619 ; RV64I-LABEL: fcvt_d_wu_load:
620 ; RV64I: # %bb.0:
621 ; RV64I-NEXT: addi sp, sp, -16
622 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
623 ; RV64I-NEXT: lw a0, 0(a0)
624 ; RV64I-NEXT: call __floatunsidf
625 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
626 ; RV64I-NEXT: addi sp, sp, 16
627 ; RV64I-NEXT: ret
628 %a = load i32, ptr %p
629 %1 = uitofp i32 %a to double
630 ret double %1
631 }
633 define i64 @fcvt_l_d(double %a) nounwind {
634 ; RV32IFD-LABEL: fcvt_l_d:
635 ; RV32IFD: # %bb.0:
636 ; RV32IFD-NEXT: addi sp, sp, -16
637 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
638 ; RV32IFD-NEXT: call __fixdfdi
639 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
640 ; RV32IFD-NEXT: addi sp, sp, 16
641 ; RV32IFD-NEXT: ret
642 ;
643 ; RV64IFD-LABEL: fcvt_l_d:
644 ; RV64IFD: # %bb.0:
645 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
646 ; RV64IFD-NEXT: ret
647 ;
648 ; RV32IZFINXZDINX-LABEL: fcvt_l_d:
649 ; RV32IZFINXZDINX: # %bb.0:
650 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
651 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
652 ; RV32IZFINXZDINX-NEXT: call __fixdfdi
653 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
654 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
655 ; RV32IZFINXZDINX-NEXT: ret
656 ;
657 ; RV64IZFINXZDINX-LABEL: fcvt_l_d:
658 ; RV64IZFINXZDINX: # %bb.0:
659 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
660 ; RV64IZFINXZDINX-NEXT: ret
661 ;
662 ; RV32I-LABEL: fcvt_l_d:
663 ; RV32I: # %bb.0:
664 ; RV32I-NEXT: addi sp, sp, -16
665 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
666 ; RV32I-NEXT: call __fixdfdi
667 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
668 ; RV32I-NEXT: addi sp, sp, 16
669 ; RV32I-NEXT: ret
670 ;
671 ; RV64I-LABEL: fcvt_l_d:
672 ; RV64I: # %bb.0:
673 ; RV64I-NEXT: addi sp, sp, -16
674 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
675 ; RV64I-NEXT: call __fixdfdi
676 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
677 ; RV64I-NEXT: addi sp, sp, 16
678 ; RV64I-NEXT: ret
679 %1 = fptosi double %a to i64
680 ret i64 %1
681 }
683 define i64 @fcvt_l_d_sat(double %a) nounwind {
684 ; RV32IFD-LABEL: fcvt_l_d_sat:
685 ; RV32IFD: # %bb.0: # %start
686 ; RV32IFD-NEXT: addi sp, sp, -16
687 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
688 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
689 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
690 ; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
691 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
692 ; RV32IFD-NEXT: fmv.d fs0, fa0
693 ; RV32IFD-NEXT: fle.d s0, fa5, fa0
694 ; RV32IFD-NEXT: call __fixdfdi
695 ; RV32IFD-NEXT: lui a4, 524288
696 ; RV32IFD-NEXT: lui a2, 524288
697 ; RV32IFD-NEXT: beqz s0, .LBB12_2
698 ; RV32IFD-NEXT: # %bb.1: # %start
699 ; RV32IFD-NEXT: mv a2, a1
700 ; RV32IFD-NEXT: .LBB12_2: # %start
701 ; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1)
702 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1)
703 ; RV32IFD-NEXT: flt.d a3, fa5, fs0
704 ; RV32IFD-NEXT: beqz a3, .LBB12_4
705 ; RV32IFD-NEXT: # %bb.3:
706 ; RV32IFD-NEXT: addi a2, a4, -1
707 ; RV32IFD-NEXT: .LBB12_4: # %start
708 ; RV32IFD-NEXT: feq.d a1, fs0, fs0
709 ; RV32IFD-NEXT: neg a4, a1
710 ; RV32IFD-NEXT: and a1, a4, a2
711 ; RV32IFD-NEXT: neg a2, a3
712 ; RV32IFD-NEXT: neg a3, s0
713 ; RV32IFD-NEXT: and a0, a3, a0
714 ; RV32IFD-NEXT: or a0, a2, a0
715 ; RV32IFD-NEXT: and a0, a4, a0
716 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
717 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
718 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
719 ; RV32IFD-NEXT: addi sp, sp, 16
720 ; RV32IFD-NEXT: ret
721 ;
722 ; RV64IFD-LABEL: fcvt_l_d_sat:
723 ; RV64IFD: # %bb.0: # %start
724 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
725 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
726 ; RV64IFD-NEXT: seqz a1, a1
727 ; RV64IFD-NEXT: addi a1, a1, -1
728 ; RV64IFD-NEXT: and a0, a1, a0
729 ; RV64IFD-NEXT: ret
730 ;
731 ; RV32IZFINXZDINX-LABEL: fcvt_l_d_sat:
732 ; RV32IZFINXZDINX: # %bb.0: # %start
733 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
734 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
735 ; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
736 ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
737 ; RV32IZFINXZDINX-NEXT: mv s1, a1
738 ; RV32IZFINXZDINX-NEXT: mv s0, a0
739 ; RV32IZFINXZDINX-NEXT: call __fixdfdi
740 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
741 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
742 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
743 ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
744 ; RV32IZFINXZDINX-NEXT: lui a5, 524288
745 ; RV32IZFINXZDINX-NEXT: lui a3, 524288
746 ; RV32IZFINXZDINX-NEXT: beqz a2, .LBB12_2
747 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
748 ; RV32IZFINXZDINX-NEXT: mv a3, a1
749 ; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start
750 ; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI12_1)
751 ; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI12_1)(a1)
752 ; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI12_1+4)(a1)
753 ; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
754 ; RV32IZFINXZDINX-NEXT: beqz a4, .LBB12_4
755 ; RV32IZFINXZDINX-NEXT: # %bb.3:
756 ; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
757 ; RV32IZFINXZDINX-NEXT: .LBB12_4: # %start
758 ; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
759 ; RV32IZFINXZDINX-NEXT: neg a5, a1
760 ; RV32IZFINXZDINX-NEXT: and a1, a5, a3
761 ; RV32IZFINXZDINX-NEXT: neg a2, a2
762 ; RV32IZFINXZDINX-NEXT: and a0, a2, a0
763 ; RV32IZFINXZDINX-NEXT: neg a2, a4
764 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0
765 ; RV32IZFINXZDINX-NEXT: and a0, a5, a0
766 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
767 ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
768 ; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
769 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
770 ; RV32IZFINXZDINX-NEXT: ret
771 ;
772 ; RV64IZFINXZDINX-LABEL: fcvt_l_d_sat:
773 ; RV64IZFINXZDINX: # %bb.0: # %start
774 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a1, a0, rtz
775 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
776 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
777 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
778 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
779 ; RV64IZFINXZDINX-NEXT: ret
780 ;
781 ; RV32I-LABEL: fcvt_l_d_sat:
782 ; RV32I: # %bb.0: # %start
783 ; RV32I-NEXT: addi sp, sp, -32
784 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
785 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
786 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
787 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
788 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
789 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
790 ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
791 ; RV32I-NEXT: mv s0, a1
792 ; RV32I-NEXT: mv s1, a0
793 ; RV32I-NEXT: lui a3, 278016
794 ; RV32I-NEXT: addi a3, a3, -1
795 ; RV32I-NEXT: li a2, -1
796 ; RV32I-NEXT: call __gtdf2
797 ; RV32I-NEXT: mv s2, a0
798 ; RV32I-NEXT: lui a3, 802304
799 ; RV32I-NEXT: mv a0, s1
800 ; RV32I-NEXT: mv a1, s0
801 ; RV32I-NEXT: li a2, 0
802 ; RV32I-NEXT: call __gedf2
803 ; RV32I-NEXT: mv s3, a0
804 ; RV32I-NEXT: mv a0, s1
805 ; RV32I-NEXT: mv a1, s0
806 ; RV32I-NEXT: call __fixdfdi
807 ; RV32I-NEXT: mv s4, a0
808 ; RV32I-NEXT: mv s5, a1
809 ; RV32I-NEXT: lui a0, 524288
810 ; RV32I-NEXT: bgez s3, .LBB12_2
811 ; RV32I-NEXT: # %bb.1: # %start
812 ; RV32I-NEXT: lui s5, 524288
813 ; RV32I-NEXT: .LBB12_2: # %start
814 ; RV32I-NEXT: blez s2, .LBB12_4
815 ; RV32I-NEXT: # %bb.3: # %start
816 ; RV32I-NEXT: addi s5, a0, -1
817 ; RV32I-NEXT: .LBB12_4: # %start
818 ; RV32I-NEXT: mv a0, s1
819 ; RV32I-NEXT: mv a1, s0
820 ; RV32I-NEXT: mv a2, s1
821 ; RV32I-NEXT: mv a3, s0
822 ; RV32I-NEXT: call __unorddf2
823 ; RV32I-NEXT: snez a0, a0
824 ; RV32I-NEXT: addi a0, a0, -1
825 ; RV32I-NEXT: and a1, a0, s5
826 ; RV32I-NEXT: slti a2, s3, 0
827 ; RV32I-NEXT: addi a2, a2, -1
828 ; RV32I-NEXT: and a2, a2, s4
829 ; RV32I-NEXT: sgtz a3, s2
830 ; RV32I-NEXT: neg a3, a3
831 ; RV32I-NEXT: or a2, a3, a2
832 ; RV32I-NEXT: and a0, a0, a2
833 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
834 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
835 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
836 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
837 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
838 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
839 ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
840 ; RV32I-NEXT: addi sp, sp, 32
841 ; RV32I-NEXT: ret
842 ;
843 ; RV64I-LABEL: fcvt_l_d_sat:
844 ; RV64I: # %bb.0: # %start
845 ; RV64I-NEXT: addi sp, sp, -48
846 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
847 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
848 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
849 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
850 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
851 ; RV64I-NEXT: mv s0, a0
852 ; RV64I-NEXT: li a1, -481
853 ; RV64I-NEXT: slli a1, a1, 53
854 ; RV64I-NEXT: call __gedf2
855 ; RV64I-NEXT: mv s2, a0
856 ; RV64I-NEXT: mv a0, s0
857 ; RV64I-NEXT: call __fixdfdi
858 ; RV64I-NEXT: mv s1, a0
859 ; RV64I-NEXT: li s3, -1
860 ; RV64I-NEXT: bgez s2, .LBB12_2
861 ; RV64I-NEXT: # %bb.1: # %start
862 ; RV64I-NEXT: slli s1, s3, 63
863 ; RV64I-NEXT: .LBB12_2: # %start
864 ; RV64I-NEXT: li a0, 543
865 ; RV64I-NEXT: slli a0, a0, 53
866 ; RV64I-NEXT: addi a1, a0, -1
867 ; RV64I-NEXT: mv a0, s0
868 ; RV64I-NEXT: call __gtdf2
869 ; RV64I-NEXT: blez a0, .LBB12_4
870 ; RV64I-NEXT: # %bb.3: # %start
871 ; RV64I-NEXT: srli s1, s3, 1
872 ; RV64I-NEXT: .LBB12_4: # %start
873 ; RV64I-NEXT: mv a0, s0
874 ; RV64I-NEXT: mv a1, s0
875 ; RV64I-NEXT: call __unorddf2
876 ; RV64I-NEXT: snez a0, a0
877 ; RV64I-NEXT: addi a0, a0, -1
878 ; RV64I-NEXT: and a0, a0, s1
879 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
880 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
881 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
882 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
883 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
884 ; RV64I-NEXT: addi sp, sp, 48
885 ; RV64I-NEXT: ret
886 start:
887 %0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
888 ret i64 %0
889 }
890 declare i64 @llvm.fptosi.sat.i64.f64(double)
892 define i64 @fcvt_lu_d(double %a) nounwind {
893 ; RV32IFD-LABEL: fcvt_lu_d:
894 ; RV32IFD: # %bb.0:
895 ; RV32IFD-NEXT: addi sp, sp, -16
896 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
897 ; RV32IFD-NEXT: call __fixunsdfdi
898 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
899 ; RV32IFD-NEXT: addi sp, sp, 16
900 ; RV32IFD-NEXT: ret
901 ;
902 ; RV64IFD-LABEL: fcvt_lu_d:
903 ; RV64IFD: # %bb.0:
904 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
905 ; RV64IFD-NEXT: ret
906 ;
907 ; RV32IZFINXZDINX-LABEL: fcvt_lu_d:
908 ; RV32IZFINXZDINX: # %bb.0:
909 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
910 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
911 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
912 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
913 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
914 ; RV32IZFINXZDINX-NEXT: ret
915 ;
916 ; RV64IZFINXZDINX-LABEL: fcvt_lu_d:
917 ; RV64IZFINXZDINX: # %bb.0:
918 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
919 ; RV64IZFINXZDINX-NEXT: ret
920 ;
921 ; RV32I-LABEL: fcvt_lu_d:
922 ; RV32I: # %bb.0:
923 ; RV32I-NEXT: addi sp, sp, -16
924 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
925 ; RV32I-NEXT: call __fixunsdfdi
926 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
927 ; RV32I-NEXT: addi sp, sp, 16
928 ; RV32I-NEXT: ret
929 ;
930 ; RV64I-LABEL: fcvt_lu_d:
931 ; RV64I: # %bb.0:
932 ; RV64I-NEXT: addi sp, sp, -16
933 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
934 ; RV64I-NEXT: call __fixunsdfdi
935 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
936 ; RV64I-NEXT: addi sp, sp, 16
937 ; RV64I-NEXT: ret
938 %1 = fptoui double %a to i64
939 ret i64 %1
940 }
942 define i64 @fcvt_lu_d_sat(double %a) nounwind {
943 ; RV32IFD-LABEL: fcvt_lu_d_sat:
944 ; RV32IFD: # %bb.0: # %start
945 ; RV32IFD-NEXT: addi sp, sp, -16
946 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
947 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
948 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
949 ; RV32IFD-NEXT: fmv.d fs0, fa0
950 ; RV32IFD-NEXT: fcvt.d.w fa5, zero
951 ; RV32IFD-NEXT: fle.d a0, fa5, fa0
952 ; RV32IFD-NEXT: neg s0, a0
953 ; RV32IFD-NEXT: call __fixunsdfdi
954 ; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0)
955 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2)
956 ; RV32IFD-NEXT: and a0, s0, a0
957 ; RV32IFD-NEXT: flt.d a2, fa5, fs0
958 ; RV32IFD-NEXT: neg a2, a2
959 ; RV32IFD-NEXT: or a0, a2, a0
960 ; RV32IFD-NEXT: and a1, s0, a1
961 ; RV32IFD-NEXT: or a1, a2, a1
962 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
963 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
964 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
965 ; RV32IFD-NEXT: addi sp, sp, 16
966 ; RV32IFD-NEXT: ret
967 ;
968 ; RV64IFD-LABEL: fcvt_lu_d_sat:
969 ; RV64IFD: # %bb.0: # %start
970 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
971 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
972 ; RV64IFD-NEXT: seqz a1, a1
973 ; RV64IFD-NEXT: addi a1, a1, -1
974 ; RV64IFD-NEXT: and a0, a1, a0
975 ; RV64IFD-NEXT: ret
976 ;
977 ; RV32IZFINXZDINX-LABEL: fcvt_lu_d_sat:
978 ; RV32IZFINXZDINX: # %bb.0: # %start
979 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
980 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
981 ; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
982 ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
983 ; RV32IZFINXZDINX-NEXT: mv s1, a1
984 ; RV32IZFINXZDINX-NEXT: mv s0, a0
985 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
986 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
987 ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0)
988 ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4)
989 ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a4)
990 ; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
991 ; RV32IZFINXZDINX-NEXT: neg a2, a2
992 ; RV32IZFINXZDINX-NEXT: and a0, a2, a0
993 ; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0
994 ; RV32IZFINXZDINX-NEXT: neg a3, a3
995 ; RV32IZFINXZDINX-NEXT: or a0, a3, a0
996 ; RV32IZFINXZDINX-NEXT: and a1, a2, a1
997 ; RV32IZFINXZDINX-NEXT: or a1, a3, a1
998 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
999 ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1000 ; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1001 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1002 ; RV32IZFINXZDINX-NEXT: ret
1003 ;
1004 ; RV64IZFINXZDINX-LABEL: fcvt_lu_d_sat:
1005 ; RV64IZFINXZDINX: # %bb.0: # %start
1006 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a1, a0, rtz
1007 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
1008 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
1009 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
1010 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
1011 ; RV64IZFINXZDINX-NEXT: ret
1012 ;
1013 ; RV32I-LABEL: fcvt_lu_d_sat:
1014 ; RV32I: # %bb.0: # %start
1015 ; RV32I-NEXT: addi sp, sp, -32
1016 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1017 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1018 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1019 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1020 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1021 ; RV32I-NEXT: mv s0, a1
1022 ; RV32I-NEXT: mv s1, a0
1023 ; RV32I-NEXT: lui a3, 278272
1024 ; RV32I-NEXT: addi a3, a3, -1
1025 ; RV32I-NEXT: li a2, -1
1026 ; RV32I-NEXT: call __gtdf2
1027 ; RV32I-NEXT: sgtz a0, a0
1028 ; RV32I-NEXT: neg s2, a0
1029 ; RV32I-NEXT: mv a0, s1
1030 ; RV32I-NEXT: mv a1, s0
1031 ; RV32I-NEXT: li a2, 0
1032 ; RV32I-NEXT: li a3, 0
1033 ; RV32I-NEXT: call __gedf2
1034 ; RV32I-NEXT: slti a0, a0, 0
1035 ; RV32I-NEXT: addi s3, a0, -1
1036 ; RV32I-NEXT: mv a0, s1
1037 ; RV32I-NEXT: mv a1, s0
1038 ; RV32I-NEXT: call __fixunsdfdi
1039 ; RV32I-NEXT: and a0, s3, a0
1040 ; RV32I-NEXT: or a0, s2, a0
1041 ; RV32I-NEXT: and a1, s3, a1
1042 ; RV32I-NEXT: or a1, s2, a1
1043 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1044 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1045 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1046 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1047 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1048 ; RV32I-NEXT: addi sp, sp, 32
1049 ; RV32I-NEXT: ret
1050 ;
1051 ; RV64I-LABEL: fcvt_lu_d_sat:
1052 ; RV64I: # %bb.0: # %start
1053 ; RV64I-NEXT: addi sp, sp, -32
1054 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1055 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1056 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1057 ; RV64I-NEXT: mv s0, a0
1058 ; RV64I-NEXT: li a1, 0
1059 ; RV64I-NEXT: call __gedf2
1060 ; RV64I-NEXT: slti a0, a0, 0
1061 ; RV64I-NEXT: addi s1, a0, -1
1062 ; RV64I-NEXT: mv a0, s0
1063 ; RV64I-NEXT: call __fixunsdfdi
1064 ; RV64I-NEXT: and s1, s1, a0
1065 ; RV64I-NEXT: li a0, 1087
1066 ; RV64I-NEXT: slli a0, a0, 52
1067 ; RV64I-NEXT: addi a1, a0, -1
1068 ; RV64I-NEXT: mv a0, s0
1069 ; RV64I-NEXT: call __gtdf2
1070 ; RV64I-NEXT: sgtz a0, a0
1071 ; RV64I-NEXT: neg a0, a0
1072 ; RV64I-NEXT: or a0, a0, s1
1073 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1074 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1075 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1076 ; RV64I-NEXT: addi sp, sp, 32
1077 ; RV64I-NEXT: ret
1078 start:
1079 %0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
1080 ret i64 %0
1081 }
1082 declare i64 @llvm.fptoui.sat.i64.f64(double)
1084 define i64 @fmv_x_d(double %a, double %b) nounwind {
1085 ; RV32IFD-LABEL: fmv_x_d:
1086 ; RV32IFD: # %bb.0:
1087 ; RV32IFD-NEXT: addi sp, sp, -16
1088 ; RV32IFD-NEXT: fadd.d fa5, fa0, fa1
1089 ; RV32IFD-NEXT: fsd fa5, 8(sp)
1090 ; RV32IFD-NEXT: lw a0, 8(sp)
1091 ; RV32IFD-NEXT: lw a1, 12(sp)
1092 ; RV32IFD-NEXT: addi sp, sp, 16
1093 ; RV32IFD-NEXT: ret
1094 ;
1095 ; RV64IFD-LABEL: fmv_x_d:
1096 ; RV64IFD: # %bb.0:
1097 ; RV64IFD-NEXT: fadd.d fa5, fa0, fa1
1098 ; RV64IFD-NEXT: fmv.x.d a0, fa5
1099 ; RV64IFD-NEXT: ret
1100 ;
1101 ; RV32IZFINXZDINX-LABEL: fmv_x_d:
1102 ; RV32IZFINXZDINX: # %bb.0:
1103 ; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
1104 ; RV32IZFINXZDINX-NEXT: ret
1105 ;
1106 ; RV64IZFINXZDINX-LABEL: fmv_x_d:
1107 ; RV64IZFINXZDINX: # %bb.0:
1108 ; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1
1109 ; RV64IZFINXZDINX-NEXT: ret
1110 ;
1111 ; RV32I-LABEL: fmv_x_d:
1112 ; RV32I: # %bb.0:
1113 ; RV32I-NEXT: addi sp, sp, -16
1114 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1115 ; RV32I-NEXT: call __adddf3
1116 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1117 ; RV32I-NEXT: addi sp, sp, 16
1118 ; RV32I-NEXT: ret
1119 ;
1120 ; RV64I-LABEL: fmv_x_d:
1121 ; RV64I: # %bb.0:
1122 ; RV64I-NEXT: addi sp, sp, -16
1123 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1124 ; RV64I-NEXT: call __adddf3
1125 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1126 ; RV64I-NEXT: addi sp, sp, 16
1127 ; RV64I-NEXT: ret
1128 %1 = fadd double %a, %b
1129 %2 = bitcast double %1 to i64
1130 ret i64 %2
1131 }
1133 define double @fcvt_d_l(i64 %a) nounwind {
1134 ; RV32IFD-LABEL: fcvt_d_l:
1135 ; RV32IFD: # %bb.0:
1136 ; RV32IFD-NEXT: addi sp, sp, -16
1137 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1138 ; RV32IFD-NEXT: call __floatdidf
1139 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1140 ; RV32IFD-NEXT: addi sp, sp, 16
1141 ; RV32IFD-NEXT: ret
1142 ;
1143 ; RV64IFD-LABEL: fcvt_d_l:
1144 ; RV64IFD: # %bb.0:
1145 ; RV64IFD-NEXT: fcvt.d.l fa0, a0
1146 ; RV64IFD-NEXT: ret
1147 ;
1148 ; RV32IZFINXZDINX-LABEL: fcvt_d_l:
1149 ; RV32IZFINXZDINX: # %bb.0:
1150 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1151 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1152 ; RV32IZFINXZDINX-NEXT: call __floatdidf
1153 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1154 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1155 ; RV32IZFINXZDINX-NEXT: ret
1156 ;
1157 ; RV64IZFINXZDINX-LABEL: fcvt_d_l:
1158 ; RV64IZFINXZDINX: # %bb.0:
1159 ; RV64IZFINXZDINX-NEXT: fcvt.d.l a0, a0
1160 ; RV64IZFINXZDINX-NEXT: ret
1161 ;
1162 ; RV32I-LABEL: fcvt_d_l:
1163 ; RV32I: # %bb.0:
1164 ; RV32I-NEXT: addi sp, sp, -16
1165 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1166 ; RV32I-NEXT: call __floatdidf
1167 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1168 ; RV32I-NEXT: addi sp, sp, 16
1169 ; RV32I-NEXT: ret
1170 ;
1171 ; RV64I-LABEL: fcvt_d_l:
1172 ; RV64I: # %bb.0:
1173 ; RV64I-NEXT: addi sp, sp, -16
1174 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1175 ; RV64I-NEXT: call __floatdidf
1176 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1177 ; RV64I-NEXT: addi sp, sp, 16
1178 ; RV64I-NEXT: ret
1179 %1 = sitofp i64 %a to double
1180 ret double %1
1181 }
1183 define double @fcvt_d_lu(i64 %a) nounwind {
1184 ; RV32IFD-LABEL: fcvt_d_lu:
1185 ; RV32IFD: # %bb.0:
1186 ; RV32IFD-NEXT: addi sp, sp, -16
1187 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1188 ; RV32IFD-NEXT: call __floatundidf
1189 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1190 ; RV32IFD-NEXT: addi sp, sp, 16
1191 ; RV32IFD-NEXT: ret
1192 ;
1193 ; RV64IFD-LABEL: fcvt_d_lu:
1194 ; RV64IFD: # %bb.0:
1195 ; RV64IFD-NEXT: fcvt.d.lu fa0, a0
1196 ; RV64IFD-NEXT: ret
1197 ;
1198 ; RV32IZFINXZDINX-LABEL: fcvt_d_lu:
1199 ; RV32IZFINXZDINX: # %bb.0:
1200 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1201 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1202 ; RV32IZFINXZDINX-NEXT: call __floatundidf
1203 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1204 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1205 ; RV32IZFINXZDINX-NEXT: ret
1206 ;
1207 ; RV64IZFINXZDINX-LABEL: fcvt_d_lu:
1208 ; RV64IZFINXZDINX: # %bb.0:
1209 ; RV64IZFINXZDINX-NEXT: fcvt.d.lu a0, a0
1210 ; RV64IZFINXZDINX-NEXT: ret
1211 ;
1212 ; RV32I-LABEL: fcvt_d_lu:
1213 ; RV32I: # %bb.0:
1214 ; RV32I-NEXT: addi sp, sp, -16
1215 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1216 ; RV32I-NEXT: call __floatundidf
1217 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1218 ; RV32I-NEXT: addi sp, sp, 16
1219 ; RV32I-NEXT: ret
1220 ;
1221 ; RV64I-LABEL: fcvt_d_lu:
1222 ; RV64I: # %bb.0:
1223 ; RV64I-NEXT: addi sp, sp, -16
1224 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1225 ; RV64I-NEXT: call __floatundidf
1226 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1227 ; RV64I-NEXT: addi sp, sp, 16
1228 ; RV64I-NEXT: ret
1229 %1 = uitofp i64 %a to double
1230 ret double %1
1231 }
1233 define double @fmv_d_x(i64 %a, i64 %b) nounwind {
1234 ; Ensure fmv.w.x is generated even for a soft double calling convention
1235 ; RV32IFD-LABEL: fmv_d_x:
1236 ; RV32IFD: # %bb.0:
1237 ; RV32IFD-NEXT: addi sp, sp, -16
1238 ; RV32IFD-NEXT: sw a0, 8(sp)
1239 ; RV32IFD-NEXT: sw a1, 12(sp)
1240 ; RV32IFD-NEXT: fld fa5, 8(sp)
1241 ; RV32IFD-NEXT: sw a2, 8(sp)
1242 ; RV32IFD-NEXT: sw a3, 12(sp)
1243 ; RV32IFD-NEXT: fld fa4, 8(sp)
1244 ; RV32IFD-NEXT: fadd.d fa0, fa5, fa4
1245 ; RV32IFD-NEXT: addi sp, sp, 16
1246 ; RV32IFD-NEXT: ret
1247 ;
1248 ; RV64IFD-LABEL: fmv_d_x:
1249 ; RV64IFD: # %bb.0:
1250 ; RV64IFD-NEXT: fmv.d.x fa5, a0
1251 ; RV64IFD-NEXT: fmv.d.x fa4, a1
1252 ; RV64IFD-NEXT: fadd.d fa0, fa5, fa4
1253 ; RV64IFD-NEXT: ret
1254 ;
1255 ; RV32IZFINXZDINX-LABEL: fmv_d_x:
1256 ; RV32IZFINXZDINX: # %bb.0:
1257 ; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
1258 ; RV32IZFINXZDINX-NEXT: ret
1259 ;
1260 ; RV64IZFINXZDINX-LABEL: fmv_d_x:
1261 ; RV64IZFINXZDINX: # %bb.0:
1262 ; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1
1263 ; RV64IZFINXZDINX-NEXT: ret
1264 ;
1265 ; RV32I-LABEL: fmv_d_x:
1266 ; RV32I: # %bb.0:
1267 ; RV32I-NEXT: addi sp, sp, -16
1268 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1269 ; RV32I-NEXT: call __adddf3
1270 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1271 ; RV32I-NEXT: addi sp, sp, 16
1272 ; RV32I-NEXT: ret
1273 ;
1274 ; RV64I-LABEL: fmv_d_x:
1275 ; RV64I: # %bb.0:
1276 ; RV64I-NEXT: addi sp, sp, -16
1277 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1278 ; RV64I-NEXT: call __adddf3
1279 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1280 ; RV64I-NEXT: addi sp, sp, 16
1281 ; RV64I-NEXT: ret
1282 %1 = bitcast i64 %a to double
1283 %2 = bitcast i64 %b to double
1284 %3 = fadd double %1, %2
1285 ret double %3
1286 }
1288 define double @fcvt_d_w_i8(i8 signext %a) nounwind {
1289 ; CHECKIFD-LABEL: fcvt_d_w_i8:
1290 ; CHECKIFD: # %bb.0:
1291 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
1292 ; CHECKIFD-NEXT: ret
1293 ;
1294 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_i8:
1295 ; RV32IZFINXZDINX: # %bb.0:
1296 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1297 ; RV32IZFINXZDINX-NEXT: ret
1298 ;
1299 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_i8:
1300 ; RV64IZFINXZDINX: # %bb.0:
1301 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1302 ; RV64IZFINXZDINX-NEXT: ret
1303 ;
1304 ; RV32I-LABEL: fcvt_d_w_i8:
1305 ; RV32I: # %bb.0:
1306 ; RV32I-NEXT: addi sp, sp, -16
1307 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1308 ; RV32I-NEXT: call __floatsidf
1309 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1310 ; RV32I-NEXT: addi sp, sp, 16
1311 ; RV32I-NEXT: ret
1312 ;
1313 ; RV64I-LABEL: fcvt_d_w_i8:
1314 ; RV64I: # %bb.0:
1315 ; RV64I-NEXT: addi sp, sp, -16
1316 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1317 ; RV64I-NEXT: call __floatsidf
1318 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1319 ; RV64I-NEXT: addi sp, sp, 16
1320 ; RV64I-NEXT: ret
1321 %1 = sitofp i8 %a to double
1322 ret double %1
1323 }
1325 define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
1326 ; CHECKIFD-LABEL: fcvt_d_wu_i8:
1327 ; CHECKIFD: # %bb.0:
1328 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
1329 ; CHECKIFD-NEXT: ret
1330 ;
1331 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i8:
1332 ; RV32IZFINXZDINX: # %bb.0:
1333 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1334 ; RV32IZFINXZDINX-NEXT: ret
1335 ;
1336 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i8:
1337 ; RV64IZFINXZDINX: # %bb.0:
1338 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1339 ; RV64IZFINXZDINX-NEXT: ret
1340 ;
1341 ; RV32I-LABEL: fcvt_d_wu_i8:
1342 ; RV32I: # %bb.0:
1343 ; RV32I-NEXT: addi sp, sp, -16
1344 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1345 ; RV32I-NEXT: call __floatunsidf
1346 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1347 ; RV32I-NEXT: addi sp, sp, 16
1348 ; RV32I-NEXT: ret
1349 ;
1350 ; RV64I-LABEL: fcvt_d_wu_i8:
1351 ; RV64I: # %bb.0:
1352 ; RV64I-NEXT: addi sp, sp, -16
1353 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1354 ; RV64I-NEXT: call __floatunsidf
1355 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1356 ; RV64I-NEXT: addi sp, sp, 16
1357 ; RV64I-NEXT: ret
1358 %1 = uitofp i8 %a to double
1359 ret double %1
1360 }
1362 define double @fcvt_d_w_i16(i16 signext %a) nounwind {
1363 ; CHECKIFD-LABEL: fcvt_d_w_i16:
1364 ; CHECKIFD: # %bb.0:
1365 ; CHECKIFD-NEXT: fcvt.d.w fa0, a0
1366 ; CHECKIFD-NEXT: ret
1367 ;
1368 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_i16:
1369 ; RV32IZFINXZDINX: # %bb.0:
1370 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1371 ; RV32IZFINXZDINX-NEXT: ret
1372 ;
1373 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_i16:
1374 ; RV64IZFINXZDINX: # %bb.0:
1375 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1376 ; RV64IZFINXZDINX-NEXT: ret
1377 ;
1378 ; RV32I-LABEL: fcvt_d_w_i16:
1379 ; RV32I: # %bb.0:
1380 ; RV32I-NEXT: addi sp, sp, -16
1381 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1382 ; RV32I-NEXT: call __floatsidf
1383 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1384 ; RV32I-NEXT: addi sp, sp, 16
1385 ; RV32I-NEXT: ret
1386 ;
1387 ; RV64I-LABEL: fcvt_d_w_i16:
1388 ; RV64I: # %bb.0:
1389 ; RV64I-NEXT: addi sp, sp, -16
1390 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1391 ; RV64I-NEXT: call __floatsidf
1392 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1393 ; RV64I-NEXT: addi sp, sp, 16
1394 ; RV64I-NEXT: ret
1395 %1 = sitofp i16 %a to double
1396 ret double %1
1397 }
1399 define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
1400 ; CHECKIFD-LABEL: fcvt_d_wu_i16:
1401 ; CHECKIFD: # %bb.0:
1402 ; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
1403 ; CHECKIFD-NEXT: ret
1404 ;
1405 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_i16:
1406 ; RV32IZFINXZDINX: # %bb.0:
1407 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1408 ; RV32IZFINXZDINX-NEXT: ret
1409 ;
1410 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_i16:
1411 ; RV64IZFINXZDINX: # %bb.0:
1412 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a0, a0
1413 ; RV64IZFINXZDINX-NEXT: ret
1414 ;
1415 ; RV32I-LABEL: fcvt_d_wu_i16:
1416 ; RV32I: # %bb.0:
1417 ; RV32I-NEXT: addi sp, sp, -16
1418 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1419 ; RV32I-NEXT: call __floatunsidf
1420 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1421 ; RV32I-NEXT: addi sp, sp, 16
1422 ; RV32I-NEXT: ret
1423 ;
1424 ; RV64I-LABEL: fcvt_d_wu_i16:
1425 ; RV64I: # %bb.0:
1426 ; RV64I-NEXT: addi sp, sp, -16
1427 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1428 ; RV64I-NEXT: call __floatunsidf
1429 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1430 ; RV64I-NEXT: addi sp, sp, 16
1431 ; RV64I-NEXT: ret
1432 %1 = uitofp i16 %a to double
1433 ret double %1
1434 }
1436 ; Make sure we select W version of addi on RV64.
1437 define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
1438 ; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
1439 ; RV32IFD: # %bb.0:
1440 ; RV32IFD-NEXT: addi a0, a0, 1
1441 ; RV32IFD-NEXT: fcvt.d.w fa5, a0
1442 ; RV32IFD-NEXT: fsd fa5, 0(a1)
1443 ; RV32IFD-NEXT: ret
1444 ;
1445 ; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
1446 ; RV64IFD: # %bb.0:
1447 ; RV64IFD-NEXT: addiw a0, a0, 1
1448 ; RV64IFD-NEXT: fcvt.d.w fa5, a0
1449 ; RV64IFD-NEXT: fsd fa5, 0(a1)
1450 ; RV64IFD-NEXT: ret
1451 ;
1452 ; RV32IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
1453 ; RV32IZFINXZDINX: # %bb.0:
1454 ; RV32IZFINXZDINX-NEXT: addi a0, a0, 1
1455 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, a0
1456 ; RV32IZFINXZDINX-NEXT: sw a2, 0(a1)
1457 ; RV32IZFINXZDINX-NEXT: sw a3, 4(a1)
1458 ; RV32IZFINXZDINX-NEXT: ret
1459 ;
1460 ; RV64IZFINXZDINX-LABEL: fcvt_d_w_demanded_bits:
1461 ; RV64IZFINXZDINX: # %bb.0:
1462 ; RV64IZFINXZDINX-NEXT: addiw a2, a0, 1
1463 ; RV64IZFINXZDINX-NEXT: addi a0, a0, 1
1464 ; RV64IZFINXZDINX-NEXT: fcvt.d.w a0, a0
1465 ; RV64IZFINXZDINX-NEXT: sd a0, 0(a1)
1466 ; RV64IZFINXZDINX-NEXT: mv a0, a2
1467 ; RV64IZFINXZDINX-NEXT: ret
1468 ;
1469 ; RV32I-LABEL: fcvt_d_w_demanded_bits:
1470 ; RV32I: # %bb.0:
1471 ; RV32I-NEXT: addi sp, sp, -16
1472 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1473 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1474 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1475 ; RV32I-NEXT: mv s0, a1
1476 ; RV32I-NEXT: addi s1, a0, 1
1477 ; RV32I-NEXT: mv a0, s1
1478 ; RV32I-NEXT: call __floatsidf
1479 ; RV32I-NEXT: sw a1, 4(s0)
1480 ; RV32I-NEXT: sw a0, 0(s0)
1481 ; RV32I-NEXT: mv a0, s1
1482 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1483 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1484 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1485 ; RV32I-NEXT: addi sp, sp, 16
1486 ; RV32I-NEXT: ret
1487 ;
1488 ; RV64I-LABEL: fcvt_d_w_demanded_bits:
1489 ; RV64I: # %bb.0:
1490 ; RV64I-NEXT: addi sp, sp, -32
1491 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1492 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1493 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1494 ; RV64I-NEXT: mv s0, a1
1495 ; RV64I-NEXT: addiw s1, a0, 1
1496 ; RV64I-NEXT: mv a0, s1
1497 ; RV64I-NEXT: call __floatsidf
1498 ; RV64I-NEXT: sd a0, 0(s0)
1499 ; RV64I-NEXT: mv a0, s1
1500 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1501 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1502 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1503 ; RV64I-NEXT: addi sp, sp, 32
1504 ; RV64I-NEXT: ret
1505 %3 = add i32 %0, 1
1506 %4 = sitofp i32 %3 to double
1507 store double %4, ptr %1, align 8
1508 ret i32 %3
1509 }
1511 ; Make sure we select W version of addi on RV64.
1512 define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
1513 ; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
1514 ; RV32IFD: # %bb.0:
1515 ; RV32IFD-NEXT: addi a0, a0, 1
1516 ; RV32IFD-NEXT: fcvt.d.wu fa5, a0
1517 ; RV32IFD-NEXT: fsd fa5, 0(a1)
1518 ; RV32IFD-NEXT: ret
1519 ;
1520 ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
1521 ; RV64IFD: # %bb.0:
1522 ; RV64IFD-NEXT: addiw a0, a0, 1
1523 ; RV64IFD-NEXT: fcvt.d.wu fa5, a0
1524 ; RV64IFD-NEXT: fsd fa5, 0(a1)
1525 ; RV64IFD-NEXT: ret
1526 ;
1527 ; RV32IZFINXZDINX-LABEL: fcvt_d_wu_demanded_bits:
1528 ; RV32IZFINXZDINX: # %bb.0:
1529 ; RV32IZFINXZDINX-NEXT: addi a0, a0, 1
1530 ; RV32IZFINXZDINX-NEXT: fcvt.d.wu a2, a0
1531 ; RV32IZFINXZDINX-NEXT: sw a2, 0(a1)
1532 ; RV32IZFINXZDINX-NEXT: sw a3, 4(a1)
1533 ; RV32IZFINXZDINX-NEXT: ret
1534 ;
1535 ; RV64IZFINXZDINX-LABEL: fcvt_d_wu_demanded_bits:
1536 ; RV64IZFINXZDINX: # %bb.0:
1537 ; RV64IZFINXZDINX-NEXT: addiw a0, a0, 1
1538 ; RV64IZFINXZDINX-NEXT: fcvt.d.wu a2, a0
1539 ; RV64IZFINXZDINX-NEXT: sd a2, 0(a1)
1540 ; RV64IZFINXZDINX-NEXT: ret
1541 ;
1542 ; RV32I-LABEL: fcvt_d_wu_demanded_bits:
1543 ; RV32I: # %bb.0:
1544 ; RV32I-NEXT: addi sp, sp, -16
1545 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1546 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1547 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1548 ; RV32I-NEXT: mv s0, a1
1549 ; RV32I-NEXT: addi s1, a0, 1
1550 ; RV32I-NEXT: mv a0, s1
1551 ; RV32I-NEXT: call __floatunsidf
1552 ; RV32I-NEXT: sw a1, 4(s0)
1553 ; RV32I-NEXT: sw a0, 0(s0)
1554 ; RV32I-NEXT: mv a0, s1
1555 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1556 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1557 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1558 ; RV32I-NEXT: addi sp, sp, 16
1559 ; RV32I-NEXT: ret
1560 ;
1561 ; RV64I-LABEL: fcvt_d_wu_demanded_bits:
1562 ; RV64I: # %bb.0:
1563 ; RV64I-NEXT: addi sp, sp, -32
1564 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1565 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1566 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1567 ; RV64I-NEXT: mv s0, a1
1568 ; RV64I-NEXT: addiw s1, a0, 1
1569 ; RV64I-NEXT: mv a0, s1
1570 ; RV64I-NEXT: call __floatunsidf
1571 ; RV64I-NEXT: sd a0, 0(s0)
1572 ; RV64I-NEXT: mv a0, s1
1573 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1574 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1575 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1576 ; RV64I-NEXT: addi sp, sp, 32
1577 ; RV64I-NEXT: ret
1578 %3 = add i32 %0, 1
1579 %4 = uitofp i32 %3 to double
1580 store double %4, ptr %1, align 8
1581 ret i32 %3
1582 }
1584 define signext i16 @fcvt_w_s_i16(double %a) nounwind {
1585 ; RV32IFD-LABEL: fcvt_w_s_i16:
1586 ; RV32IFD: # %bb.0:
1587 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
1588 ; RV32IFD-NEXT: ret
1589 ;
1590 ; RV64IFD-LABEL: fcvt_w_s_i16:
1591 ; RV64IFD: # %bb.0:
1592 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
1593 ; RV64IFD-NEXT: ret
1594 ;
1595 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_i16:
1596 ; RV32IZFINXZDINX: # %bb.0:
1597 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
1598 ; RV32IZFINXZDINX-NEXT: ret
1599 ;
1600 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_i16:
1601 ; RV64IZFINXZDINX: # %bb.0:
1602 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
1603 ; RV64IZFINXZDINX-NEXT: ret
1604 ;
1605 ; RV32I-LABEL: fcvt_w_s_i16:
1606 ; RV32I: # %bb.0:
1607 ; RV32I-NEXT: addi sp, sp, -16
1608 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1609 ; RV32I-NEXT: call __fixdfsi
1610 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1611 ; RV32I-NEXT: addi sp, sp, 16
1612 ; RV32I-NEXT: ret
1613 ;
1614 ; RV64I-LABEL: fcvt_w_s_i16:
1615 ; RV64I: # %bb.0:
1616 ; RV64I-NEXT: addi sp, sp, -16
1617 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1618 ; RV64I-NEXT: call __fixdfdi
1619 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1620 ; RV64I-NEXT: addi sp, sp, 16
1621 ; RV64I-NEXT: ret
1622 %1 = fptosi double %a to i16
1623 ret i16 %1
1624 }
1626 define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
1627 ; RV32IFD-LABEL: fcvt_w_s_sat_i16:
1628 ; RV32IFD: # %bb.0: # %start
1629 ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0)
1630 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
1631 ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1)
1632 ; RV32IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
1633 ; RV32IFD-NEXT: feq.d a0, fa0, fa0
1634 ; RV32IFD-NEXT: neg a0, a0
1635 ; RV32IFD-NEXT: fmax.d fa5, fa0, fa5
1636 ; RV32IFD-NEXT: fmin.d fa5, fa5, fa4
1637 ; RV32IFD-NEXT: fcvt.w.d a1, fa5, rtz
1638 ; RV32IFD-NEXT: and a0, a0, a1
1639 ; RV32IFD-NEXT: ret
1640 ;
1641 ; RV64IFD-LABEL: fcvt_w_s_sat_i16:
1642 ; RV64IFD: # %bb.0: # %start
1643 ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0)
1644 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
1645 ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
1646 ; RV64IFD-NEXT: fld fa4, %lo(.LCPI26_1)(a0)
1647 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
1648 ; RV64IFD-NEXT: neg a0, a0
1649 ; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
1650 ; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
1651 ; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
1652 ; RV64IFD-NEXT: and a0, a0, a1
1653 ; RV64IFD-NEXT: ret
1654 ;
1655 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
1656 ; RV32IZFINXZDINX: # %bb.0: # %start
1657 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0)
1658 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI26_0+4)(a2)
1659 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_0)(a2)
1660 ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI26_1)
1661 ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI26_1+4)(a4)
1662 ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_1)(a4)
1663 ; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
1664 ; RV32IZFINXZDINX-NEXT: neg a6, a6
1665 ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
1666 ; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
1667 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
1668 ; RV32IZFINXZDINX-NEXT: and a0, a6, a0
1669 ; RV32IZFINXZDINX-NEXT: ret
1670 ;
1671 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i16:
1672 ; RV64IZFINXZDINX: # %bb.0: # %start
1673 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI26_0)
1674 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI26_0)(a1)
1675 ; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_1)
1676 ; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI26_1)(a2)
1677 ; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
1678 ; RV64IZFINXZDINX-NEXT: neg a3, a3
1679 ; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
1680 ; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
1681 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
1682 ; RV64IZFINXZDINX-NEXT: and a0, a3, a0
1683 ; RV64IZFINXZDINX-NEXT: ret
1684 ;
1685 ; RV32I-LABEL: fcvt_w_s_sat_i16:
1686 ; RV32I: # %bb.0: # %start
1687 ; RV32I-NEXT: addi sp, sp, -32
1688 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1689 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1690 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1691 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1692 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1693 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
1694 ; RV32I-NEXT: mv s0, a1
1695 ; RV32I-NEXT: mv s1, a0
1696 ; RV32I-NEXT: lui a0, 265728
1697 ; RV32I-NEXT: addi a3, a0, -64
1698 ; RV32I-NEXT: mv a0, s1
1699 ; RV32I-NEXT: li a2, 0
1700 ; RV32I-NEXT: call __gtdf2
1701 ; RV32I-NEXT: mv s2, a0
1702 ; RV32I-NEXT: lui a3, 790016
1703 ; RV32I-NEXT: mv a0, s1
1704 ; RV32I-NEXT: mv a1, s0
1705 ; RV32I-NEXT: li a2, 0
1706 ; RV32I-NEXT: call __gedf2
1707 ; RV32I-NEXT: mv s4, a0
1708 ; RV32I-NEXT: mv a0, s1
1709 ; RV32I-NEXT: mv a1, s0
1710 ; RV32I-NEXT: call __fixdfsi
1711 ; RV32I-NEXT: mv s3, a0
1712 ; RV32I-NEXT: bgez s4, .LBB26_2
1713 ; RV32I-NEXT: # %bb.1: # %start
1714 ; RV32I-NEXT: lui s3, 1048568
1715 ; RV32I-NEXT: .LBB26_2: # %start
1716 ; RV32I-NEXT: blez s2, .LBB26_4
1717 ; RV32I-NEXT: # %bb.3: # %start
1718 ; RV32I-NEXT: lui s3, 8
1719 ; RV32I-NEXT: addi s3, s3, -1
1720 ; RV32I-NEXT: .LBB26_4: # %start
1721 ; RV32I-NEXT: mv a0, s1
1722 ; RV32I-NEXT: mv a1, s0
1723 ; RV32I-NEXT: mv a2, s1
1724 ; RV32I-NEXT: mv a3, s0
1725 ; RV32I-NEXT: call __unorddf2
1726 ; RV32I-NEXT: snez a0, a0
1727 ; RV32I-NEXT: addi a0, a0, -1
1728 ; RV32I-NEXT: and a0, a0, s3
1729 ; RV32I-NEXT: slli a0, a0, 16
1730 ; RV32I-NEXT: srai a0, a0, 16
1731 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1732 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1733 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1734 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1735 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1736 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
1737 ; RV32I-NEXT: addi sp, sp, 32
1738 ; RV32I-NEXT: ret
1739 ;
1740 ; RV64I-LABEL: fcvt_w_s_sat_i16:
1741 ; RV64I: # %bb.0: # %start
1742 ; RV64I-NEXT: addi sp, sp, -32
1743 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1744 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1745 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1746 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1747 ; RV64I-NEXT: mv s0, a0
1748 ; RV64I-NEXT: li a1, -505
1749 ; RV64I-NEXT: slli a1, a1, 53
1750 ; RV64I-NEXT: call __gedf2
1751 ; RV64I-NEXT: mv s2, a0
1752 ; RV64I-NEXT: mv a0, s0
1753 ; RV64I-NEXT: call __fixdfdi
1754 ; RV64I-NEXT: mv s1, a0
1755 ; RV64I-NEXT: bgez s2, .LBB26_2
1756 ; RV64I-NEXT: # %bb.1: # %start
1757 ; RV64I-NEXT: lui s1, 1048568
1758 ; RV64I-NEXT: .LBB26_2: # %start
1759 ; RV64I-NEXT: lui a0, 4152
1760 ; RV64I-NEXT: addi a0, a0, -1
1761 ; RV64I-NEXT: slli a1, a0, 38
1762 ; RV64I-NEXT: mv a0, s0
1763 ; RV64I-NEXT: call __gtdf2
1764 ; RV64I-NEXT: blez a0, .LBB26_4
1765 ; RV64I-NEXT: # %bb.3: # %start
1766 ; RV64I-NEXT: lui s1, 8
1767 ; RV64I-NEXT: addi s1, s1, -1
1768 ; RV64I-NEXT: .LBB26_4: # %start
1769 ; RV64I-NEXT: mv a0, s0
1770 ; RV64I-NEXT: mv a1, s0
1771 ; RV64I-NEXT: call __unorddf2
1772 ; RV64I-NEXT: snez a0, a0
1773 ; RV64I-NEXT: addi a0, a0, -1
1774 ; RV64I-NEXT: and a0, a0, s1
1775 ; RV64I-NEXT: slli a0, a0, 48
1776 ; RV64I-NEXT: srai a0, a0, 48
1777 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1778 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1779 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1780 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1781 ; RV64I-NEXT: addi sp, sp, 32
1782 ; RV64I-NEXT: ret
1783 start:
1784 %0 = tail call i16 @llvm.fptosi.sat.i16.f64(double %a)
1785 ret i16 %0
1786 }
1787 declare i16 @llvm.fptosi.sat.i16.f64(double)
1789 define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
1790 ; RV32IFD-LABEL: fcvt_wu_s_i16:
1791 ; RV32IFD: # %bb.0:
1792 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
1793 ; RV32IFD-NEXT: ret
1794 ;
1795 ; RV64IFD-LABEL: fcvt_wu_s_i16:
1796 ; RV64IFD: # %bb.0:
1797 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
1798 ; RV64IFD-NEXT: ret
1799 ;
1800 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_i16:
1801 ; RV32IZFINXZDINX: # %bb.0:
1802 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
1803 ; RV32IZFINXZDINX-NEXT: ret
1804 ;
1805 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_i16:
1806 ; RV64IZFINXZDINX: # %bb.0:
1807 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
1808 ; RV64IZFINXZDINX-NEXT: ret
1809 ;
1810 ; RV32I-LABEL: fcvt_wu_s_i16:
1811 ; RV32I: # %bb.0:
1812 ; RV32I-NEXT: addi sp, sp, -16
1813 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1814 ; RV32I-NEXT: call __fixunsdfsi
1815 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1816 ; RV32I-NEXT: addi sp, sp, 16
1817 ; RV32I-NEXT: ret
1818 ;
1819 ; RV64I-LABEL: fcvt_wu_s_i16:
1820 ; RV64I: # %bb.0:
1821 ; RV64I-NEXT: addi sp, sp, -16
1822 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1823 ; RV64I-NEXT: call __fixunsdfdi
1824 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1825 ; RV64I-NEXT: addi sp, sp, 16
1826 ; RV64I-NEXT: ret
1827 %1 = fptoui double %a to i16
1828 ret i16 %1
1829 }
1831 define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
1832 ; RV32IFD-LABEL: fcvt_wu_s_sat_i16:
1833 ; RV32IFD: # %bb.0: # %start
1834 ; RV32IFD-NEXT: lui a0, %hi(.LCPI28_0)
1835 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI28_0)(a0)
1836 ; RV32IFD-NEXT: fcvt.d.w fa4, zero
1837 ; RV32IFD-NEXT: fmax.d fa4, fa0, fa4
1838 ; RV32IFD-NEXT: fmin.d fa5, fa4, fa5
1839 ; RV32IFD-NEXT: fcvt.wu.d a0, fa5, rtz
1840 ; RV32IFD-NEXT: ret
1841 ;
1842 ; RV64IFD-LABEL: fcvt_wu_s_sat_i16:
1843 ; RV64IFD: # %bb.0: # %start
1844 ; RV64IFD-NEXT: lui a0, %hi(.LCPI28_0)
1845 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI28_0)(a0)
1846 ; RV64IFD-NEXT: fmv.d.x fa4, zero
1847 ; RV64IFD-NEXT: fmax.d fa4, fa0, fa4
1848 ; RV64IFD-NEXT: fmin.d fa5, fa4, fa5
1849 ; RV64IFD-NEXT: fcvt.lu.d a0, fa5, rtz
1850 ; RV64IFD-NEXT: ret
1851 ;
1852 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
1853 ; RV32IZFINXZDINX: # %bb.0: # %start
1854 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI28_0)
1855 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI28_0+4)(a2)
1856 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI28_0)(a2)
1857 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a4, zero
1858 ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
1859 ; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
1860 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
1861 ; RV32IZFINXZDINX-NEXT: ret
1862 ;
1863 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16:
1864 ; RV64IZFINXZDINX: # %bb.0: # %start
1865 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI28_0)
1866 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI28_0)(a1)
1867 ; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, zero
1868 ; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
1869 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
1870 ; RV64IZFINXZDINX-NEXT: ret
1871 ;
1872 ; RV32I-LABEL: fcvt_wu_s_sat_i16:
1873 ; RV32I: # %bb.0: # %start
1874 ; RV32I-NEXT: addi sp, sp, -32
1875 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1876 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1877 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1878 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1879 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1880 ; RV32I-NEXT: mv s1, a1
1881 ; RV32I-NEXT: mv s2, a0
1882 ; RV32I-NEXT: lui a3, 265984
1883 ; RV32I-NEXT: addi a3, a3, -32
1884 ; RV32I-NEXT: li a2, 0
1885 ; RV32I-NEXT: call __gtdf2
1886 ; RV32I-NEXT: mv s3, a0
1887 ; RV32I-NEXT: mv a0, s2
1888 ; RV32I-NEXT: mv a1, s1
1889 ; RV32I-NEXT: li a2, 0
1890 ; RV32I-NEXT: li a3, 0
1891 ; RV32I-NEXT: call __gedf2
1892 ; RV32I-NEXT: mv s0, a0
1893 ; RV32I-NEXT: mv a0, s2
1894 ; RV32I-NEXT: mv a1, s1
1895 ; RV32I-NEXT: call __fixunsdfsi
1896 ; RV32I-NEXT: lui a1, 16
1897 ; RV32I-NEXT: addi a1, a1, -1
1898 ; RV32I-NEXT: blez s3, .LBB28_2
1899 ; RV32I-NEXT: # %bb.1: # %start
1900 ; RV32I-NEXT: mv a0, a1
1901 ; RV32I-NEXT: j .LBB28_3
1902 ; RV32I-NEXT: .LBB28_2:
1903 ; RV32I-NEXT: slti a2, s0, 0
1904 ; RV32I-NEXT: addi a2, a2, -1
1905 ; RV32I-NEXT: and a0, a2, a0
1906 ; RV32I-NEXT: .LBB28_3: # %start
1907 ; RV32I-NEXT: and a0, a0, a1
1908 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1909 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1910 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1911 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1912 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1913 ; RV32I-NEXT: addi sp, sp, 32
1914 ; RV32I-NEXT: ret
1915 ;
1916 ; RV64I-LABEL: fcvt_wu_s_sat_i16:
1917 ; RV64I: # %bb.0: # %start
1918 ; RV64I-NEXT: addi sp, sp, -32
1919 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1920 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1921 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1922 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1923 ; RV64I-NEXT: mv s2, a0
1924 ; RV64I-NEXT: li a1, 0
1925 ; RV64I-NEXT: call __gedf2
1926 ; RV64I-NEXT: mv s0, a0
1927 ; RV64I-NEXT: mv a0, s2
1928 ; RV64I-NEXT: call __fixunsdfdi
1929 ; RV64I-NEXT: mv s1, a0
1930 ; RV64I-NEXT: lui a0, 8312
1931 ; RV64I-NEXT: addi a0, a0, -1
1932 ; RV64I-NEXT: slli a1, a0, 37
1933 ; RV64I-NEXT: mv a0, s2
1934 ; RV64I-NEXT: call __gtdf2
1935 ; RV64I-NEXT: lui a1, 16
1936 ; RV64I-NEXT: addiw a1, a1, -1
1937 ; RV64I-NEXT: blez a0, .LBB28_2
1938 ; RV64I-NEXT: # %bb.1: # %start
1939 ; RV64I-NEXT: mv a0, a1
1940 ; RV64I-NEXT: j .LBB28_3
1941 ; RV64I-NEXT: .LBB28_2:
1942 ; RV64I-NEXT: slti a0, s0, 0
1943 ; RV64I-NEXT: addi a0, a0, -1
1944 ; RV64I-NEXT: and a0, a0, s1
1945 ; RV64I-NEXT: .LBB28_3: # %start
1946 ; RV64I-NEXT: and a0, a0, a1
1947 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1948 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1949 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1950 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1951 ; RV64I-NEXT: addi sp, sp, 32
1952 ; RV64I-NEXT: ret
1953 start:
1954 %0 = tail call i16 @llvm.fptoui.sat.i16.f64(double %a)
1955 ret i16 %0
1956 }
1957 declare i16 @llvm.fptoui.sat.i16.f64(double)
1959 define signext i8 @fcvt_w_s_i8(double %a) nounwind {
1960 ; RV32IFD-LABEL: fcvt_w_s_i8:
1961 ; RV32IFD: # %bb.0:
1962 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
1963 ; RV32IFD-NEXT: ret
1964 ;
1965 ; RV64IFD-LABEL: fcvt_w_s_i8:
1966 ; RV64IFD: # %bb.0:
1967 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
1968 ; RV64IFD-NEXT: ret
1969 ;
1970 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_i8:
1971 ; RV32IZFINXZDINX: # %bb.0:
1972 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
1973 ; RV32IZFINXZDINX-NEXT: ret
1974 ;
1975 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_i8:
1976 ; RV64IZFINXZDINX: # %bb.0:
1977 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
1978 ; RV64IZFINXZDINX-NEXT: ret
1979 ;
1980 ; RV32I-LABEL: fcvt_w_s_i8:
1981 ; RV32I: # %bb.0:
1982 ; RV32I-NEXT: addi sp, sp, -16
1983 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1984 ; RV32I-NEXT: call __fixdfsi
1985 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1986 ; RV32I-NEXT: addi sp, sp, 16
1987 ; RV32I-NEXT: ret
1988 ;
1989 ; RV64I-LABEL: fcvt_w_s_i8:
1990 ; RV64I: # %bb.0:
1991 ; RV64I-NEXT: addi sp, sp, -16
1992 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1993 ; RV64I-NEXT: call __fixdfdi
1994 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1995 ; RV64I-NEXT: addi sp, sp, 16
1996 ; RV64I-NEXT: ret
1997 %1 = fptosi double %a to i8
1998 ret i8 %1
1999 }
2001 define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
2002 ; RV32IFD-LABEL: fcvt_w_s_sat_i8:
2003 ; RV32IFD: # %bb.0: # %start
2004 ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0)
2005 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0)
2006 ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1)
2007 ; RV32IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
2008 ; RV32IFD-NEXT: feq.d a0, fa0, fa0
2009 ; RV32IFD-NEXT: neg a0, a0
2010 ; RV32IFD-NEXT: fmax.d fa5, fa0, fa5
2011 ; RV32IFD-NEXT: fmin.d fa5, fa5, fa4
2012 ; RV32IFD-NEXT: fcvt.w.d a1, fa5, rtz
2013 ; RV32IFD-NEXT: and a0, a0, a1
2014 ; RV32IFD-NEXT: ret
2015 ;
2016 ; RV64IFD-LABEL: fcvt_w_s_sat_i8:
2017 ; RV64IFD: # %bb.0: # %start
2018 ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0)
2019 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI30_0)(a0)
2020 ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
2021 ; RV64IFD-NEXT: fld fa4, %lo(.LCPI30_1)(a0)
2022 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
2023 ; RV64IFD-NEXT: neg a0, a0
2024 ; RV64IFD-NEXT: fmax.d fa5, fa0, fa5
2025 ; RV64IFD-NEXT: fmin.d fa5, fa5, fa4
2026 ; RV64IFD-NEXT: fcvt.l.d a1, fa5, rtz
2027 ; RV64IFD-NEXT: and a0, a0, a1
2028 ; RV64IFD-NEXT: ret
2029 ;
2030 ; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
2031 ; RV32IZFINXZDINX: # %bb.0: # %start
2032 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_0)
2033 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI30_0+4)(a2)
2034 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_0)(a2)
2035 ; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI30_1)
2036 ; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI30_1+4)(a4)
2037 ; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_1)(a4)
2038 ; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
2039 ; RV32IZFINXZDINX-NEXT: neg a6, a6
2040 ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
2041 ; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
2042 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz
2043 ; RV32IZFINXZDINX-NEXT: and a0, a6, a0
2044 ; RV32IZFINXZDINX-NEXT: ret
2045 ;
2046 ; RV64IZFINXZDINX-LABEL: fcvt_w_s_sat_i8:
2047 ; RV64IZFINXZDINX: # %bb.0: # %start
2048 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI30_0)
2049 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI30_0)(a1)
2050 ; RV64IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_1)
2051 ; RV64IZFINXZDINX-NEXT: ld a2, %lo(.LCPI30_1)(a2)
2052 ; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
2053 ; RV64IZFINXZDINX-NEXT: neg a3, a3
2054 ; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a1
2055 ; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
2056 ; RV64IZFINXZDINX-NEXT: fcvt.l.d a0, a0, rtz
2057 ; RV64IZFINXZDINX-NEXT: and a0, a3, a0
2058 ; RV64IZFINXZDINX-NEXT: ret
2059 ;
2060 ; RV32I-LABEL: fcvt_w_s_sat_i8:
2061 ; RV32I: # %bb.0: # %start
2062 ; RV32I-NEXT: addi sp, sp, -32
2063 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2064 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2065 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2066 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2067 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2068 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
2069 ; RV32I-NEXT: mv s0, a1
2070 ; RV32I-NEXT: mv s1, a0
2071 ; RV32I-NEXT: lui a3, 263676
2072 ; RV32I-NEXT: li a2, 0
2073 ; RV32I-NEXT: call __gtdf2
2074 ; RV32I-NEXT: mv s2, a0
2075 ; RV32I-NEXT: lui a3, 787968
2076 ; RV32I-NEXT: mv a0, s1
2077 ; RV32I-NEXT: mv a1, s0
2078 ; RV32I-NEXT: li a2, 0
2079 ; RV32I-NEXT: call __gedf2
2080 ; RV32I-NEXT: mv s4, a0
2081 ; RV32I-NEXT: mv a0, s1
2082 ; RV32I-NEXT: mv a1, s0
2083 ; RV32I-NEXT: call __fixdfsi
2084 ; RV32I-NEXT: mv s3, a0
2085 ; RV32I-NEXT: bgez s4, .LBB30_2
2086 ; RV32I-NEXT: # %bb.1: # %start
2087 ; RV32I-NEXT: li s3, -128
2088 ; RV32I-NEXT: .LBB30_2: # %start
2089 ; RV32I-NEXT: blez s2, .LBB30_4
2090 ; RV32I-NEXT: # %bb.3: # %start
2091 ; RV32I-NEXT: li s3, 127
2092 ; RV32I-NEXT: .LBB30_4: # %start
2093 ; RV32I-NEXT: mv a0, s1
2094 ; RV32I-NEXT: mv a1, s0
2095 ; RV32I-NEXT: mv a2, s1
2096 ; RV32I-NEXT: mv a3, s0
2097 ; RV32I-NEXT: call __unorddf2
2098 ; RV32I-NEXT: snez a0, a0
2099 ; RV32I-NEXT: addi a0, a0, -1
2100 ; RV32I-NEXT: and a0, a0, s3
2101 ; RV32I-NEXT: slli a0, a0, 24
2102 ; RV32I-NEXT: srai a0, a0, 24
2103 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2104 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2105 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2106 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2107 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2108 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
2109 ; RV32I-NEXT: addi sp, sp, 32
2110 ; RV32I-NEXT: ret
2111 ;
2112 ; RV64I-LABEL: fcvt_w_s_sat_i8:
2113 ; RV64I: # %bb.0: # %start
2114 ; RV64I-NEXT: addi sp, sp, -32
2115 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2116 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2117 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2118 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2119 ; RV64I-NEXT: mv s0, a0
2120 ; RV64I-NEXT: li a1, -509
2121 ; RV64I-NEXT: slli a1, a1, 53
2122 ; RV64I-NEXT: call __gedf2
2123 ; RV64I-NEXT: mv s2, a0
2124 ; RV64I-NEXT: mv a0, s0
2125 ; RV64I-NEXT: call __fixdfdi
2126 ; RV64I-NEXT: mv s1, a0
2127 ; RV64I-NEXT: bgez s2, .LBB30_2
2128 ; RV64I-NEXT: # %bb.1: # %start
2129 ; RV64I-NEXT: li s1, -128
2130 ; RV64I-NEXT: .LBB30_2: # %start
2131 ; RV64I-NEXT: lui a1, 65919
2132 ; RV64I-NEXT: slli a1, a1, 34
2133 ; RV64I-NEXT: mv a0, s0
2134 ; RV64I-NEXT: call __gtdf2
2135 ; RV64I-NEXT: blez a0, .LBB30_4
2136 ; RV64I-NEXT: # %bb.3: # %start
2137 ; RV64I-NEXT: li s1, 127
2138 ; RV64I-NEXT: .LBB30_4: # %start
2139 ; RV64I-NEXT: mv a0, s0
2140 ; RV64I-NEXT: mv a1, s0
2141 ; RV64I-NEXT: call __unorddf2
2142 ; RV64I-NEXT: snez a0, a0
2143 ; RV64I-NEXT: addi a0, a0, -1
2144 ; RV64I-NEXT: and a0, a0, s1
2145 ; RV64I-NEXT: slli a0, a0, 56
2146 ; RV64I-NEXT: srai a0, a0, 56
2147 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2148 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2149 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2150 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2151 ; RV64I-NEXT: addi sp, sp, 32
2152 ; RV64I-NEXT: ret
2153 start:
2154 %0 = tail call i8 @llvm.fptosi.sat.i8.f64(double %a)
2155 ret i8 %0
2156 }
2157 declare i8 @llvm.fptosi.sat.i8.f64(double)
2159 define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
2160 ;
2161 ;
2162 ; RV32IFD-LABEL: fcvt_wu_s_i8:
2163 ; RV32IFD: # %bb.0:
2164 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
2165 ; RV32IFD-NEXT: ret
2166 ;
2167 ; RV64IFD-LABEL: fcvt_wu_s_i8:
2168 ; RV64IFD: # %bb.0:
2169 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
2170 ; RV64IFD-NEXT: ret
2171 ;
2172 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_i8:
2173 ; RV32IZFINXZDINX: # %bb.0:
2174 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
2175 ; RV32IZFINXZDINX-NEXT: ret
2176 ;
2177 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_i8:
2178 ; RV64IZFINXZDINX: # %bb.0:
2179 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
2180 ; RV64IZFINXZDINX-NEXT: ret
2181 ;
2182 ; RV32I-LABEL: fcvt_wu_s_i8:
2183 ; RV32I: # %bb.0:
2184 ; RV32I-NEXT: addi sp, sp, -16
2185 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2186 ; RV32I-NEXT: call __fixunsdfsi
2187 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2188 ; RV32I-NEXT: addi sp, sp, 16
2189 ; RV32I-NEXT: ret
2190 ;
2191 ; RV64I-LABEL: fcvt_wu_s_i8:
2192 ; RV64I: # %bb.0:
2193 ; RV64I-NEXT: addi sp, sp, -16
2194 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2195 ; RV64I-NEXT: call __fixunsdfdi
2196 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2197 ; RV64I-NEXT: addi sp, sp, 16
2198 ; RV64I-NEXT: ret
2199 %1 = fptoui double %a to i8
2200 ret i8 %1
2201 }
2203 define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
2204 ;
2205 ;
2206 ; RV32IFD-LABEL: fcvt_wu_s_sat_i8:
2207 ; RV32IFD: # %bb.0: # %start
2208 ; RV32IFD-NEXT: lui a0, %hi(.LCPI32_0)
2209 ; RV32IFD-NEXT: fld fa5, %lo(.LCPI32_0)(a0)
2210 ; RV32IFD-NEXT: fcvt.d.w fa4, zero
2211 ; RV32IFD-NEXT: fmax.d fa4, fa0, fa4
2212 ; RV32IFD-NEXT: fmin.d fa5, fa4, fa5
2213 ; RV32IFD-NEXT: fcvt.wu.d a0, fa5, rtz
2214 ; RV32IFD-NEXT: ret
2215 ;
2216 ; RV64IFD-LABEL: fcvt_wu_s_sat_i8:
2217 ; RV64IFD: # %bb.0: # %start
2218 ; RV64IFD-NEXT: lui a0, %hi(.LCPI32_0)
2219 ; RV64IFD-NEXT: fld fa5, %lo(.LCPI32_0)(a0)
2220 ; RV64IFD-NEXT: fmv.d.x fa4, zero
2221 ; RV64IFD-NEXT: fmax.d fa4, fa0, fa4
2222 ; RV64IFD-NEXT: fmin.d fa5, fa4, fa5
2223 ; RV64IFD-NEXT: fcvt.lu.d a0, fa5, rtz
2224 ; RV64IFD-NEXT: ret
2225 ;
2226 ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
2227 ; RV32IZFINXZDINX: # %bb.0: # %start
2228 ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI32_0)
2229 ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI32_0+4)(a2)
2230 ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
2231 ; RV32IZFINXZDINX-NEXT: fcvt.d.w a4, zero
2232 ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
2233 ; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2
2234 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
2235 ; RV32IZFINXZDINX-NEXT: ret
2236 ;
2237 ; RV64IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8:
2238 ; RV64IZFINXZDINX: # %bb.0: # %start
2239 ; RV64IZFINXZDINX-NEXT: lui a1, %hi(.LCPI32_0)
2240 ; RV64IZFINXZDINX-NEXT: ld a1, %lo(.LCPI32_0)(a1)
2241 ; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, zero
2242 ; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a1
2243 ; RV64IZFINXZDINX-NEXT: fcvt.lu.d a0, a0, rtz
2244 ; RV64IZFINXZDINX-NEXT: ret
2245 ;
2246 ; RV32I-LABEL: fcvt_wu_s_sat_i8:
2247 ; RV32I: # %bb.0: # %start
2248 ; RV32I-NEXT: addi sp, sp, -32
2249 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2250 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2251 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2252 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2253 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2254 ; RV32I-NEXT: mv s1, a1
2255 ; RV32I-NEXT: mv s2, a0
2256 ; RV32I-NEXT: lui a3, 263934
2257 ; RV32I-NEXT: li a2, 0
2258 ; RV32I-NEXT: call __gtdf2
2259 ; RV32I-NEXT: mv s3, a0
2260 ; RV32I-NEXT: mv a0, s2
2261 ; RV32I-NEXT: mv a1, s1
2262 ; RV32I-NEXT: li a2, 0
2263 ; RV32I-NEXT: li a3, 0
2264 ; RV32I-NEXT: call __gedf2
2265 ; RV32I-NEXT: mv s0, a0
2266 ; RV32I-NEXT: mv a0, s2
2267 ; RV32I-NEXT: mv a1, s1
2268 ; RV32I-NEXT: call __fixunsdfsi
2269 ; RV32I-NEXT: blez s3, .LBB32_2
2270 ; RV32I-NEXT: # %bb.1: # %start
2271 ; RV32I-NEXT: li a0, 255
2272 ; RV32I-NEXT: j .LBB32_3
2273 ; RV32I-NEXT: .LBB32_2:
2274 ; RV32I-NEXT: slti a1, s0, 0
2275 ; RV32I-NEXT: addi a1, a1, -1
2276 ; RV32I-NEXT: and a0, a1, a0
2277 ; RV32I-NEXT: .LBB32_3: # %start
2278 ; RV32I-NEXT: andi a0, a0, 255
2279 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2280 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2281 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2282 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2283 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2284 ; RV32I-NEXT: addi sp, sp, 32
2285 ; RV32I-NEXT: ret
2286 ;
2287 ; RV64I-LABEL: fcvt_wu_s_sat_i8:
2288 ; RV64I: # %bb.0: # %start
2289 ; RV64I-NEXT: addi sp, sp, -32
2290 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2291 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2292 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2293 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2294 ; RV64I-NEXT: mv s2, a0
2295 ; RV64I-NEXT: li a1, 0
2296 ; RV64I-NEXT: call __gedf2
2297 ; RV64I-NEXT: mv s0, a0
2298 ; RV64I-NEXT: mv a0, s2
2299 ; RV64I-NEXT: call __fixunsdfdi
2300 ; RV64I-NEXT: mv s1, a0
2301 ; RV64I-NEXT: lui a1, 131967
2302 ; RV64I-NEXT: slli a1, a1, 33
2303 ; RV64I-NEXT: mv a0, s2
2304 ; RV64I-NEXT: call __gtdf2
2305 ; RV64I-NEXT: blez a0, .LBB32_2
2306 ; RV64I-NEXT: # %bb.1: # %start
2307 ; RV64I-NEXT: li a0, 255
2308 ; RV64I-NEXT: j .LBB32_3
2309 ; RV64I-NEXT: .LBB32_2:
2310 ; RV64I-NEXT: slti a0, s0, 0
2311 ; RV64I-NEXT: addi a0, a0, -1
2312 ; RV64I-NEXT: and a0, a0, s1
2313 ; RV64I-NEXT: .LBB32_3: # %start
2314 ; RV64I-NEXT: andi a0, a0, 255
2315 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2316 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2317 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2318 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2319 ; RV64I-NEXT: addi sp, sp, 32
2320 ; RV64I-NEXT: ret
2321 start:
2322 %0 = tail call i8 @llvm.fptoui.sat.i8.f64(double %a)
2323 ret i8 %0
2324 }
2325 declare i8 @llvm.fptoui.sat.i8.f64(double)
2327 define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind {
2328 ; RV32IFD-LABEL: fcvt_wu_d_sat_zext:
2329 ; RV32IFD: # %bb.0: # %start
2330 ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
2331 ; RV32IFD-NEXT: feq.d a1, fa0, fa0
2332 ; RV32IFD-NEXT: seqz a1, a1
2333 ; RV32IFD-NEXT: addi a1, a1, -1
2334 ; RV32IFD-NEXT: and a0, a1, a0
2335 ; RV32IFD-NEXT: ret
2336 ;
2337 ; RV64IFD-LABEL: fcvt_wu_d_sat_zext:
2338 ; RV64IFD: # %bb.0: # %start
2339 ; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
2340 ; RV64IFD-NEXT: feq.d a1, fa0, fa0
2341 ; RV64IFD-NEXT: seqz a1, a1
2342 ; RV64IFD-NEXT: addi a1, a1, -1
2343 ; RV64IFD-NEXT: and a0, a0, a1
2344 ; RV64IFD-NEXT: slli a0, a0, 32
2345 ; RV64IFD-NEXT: srli a0, a0, 32
2346 ; RV64IFD-NEXT: ret
2347 ;
2348 ; RV32IZFINXZDINX-LABEL: fcvt_wu_d_sat_zext:
2349 ; RV32IZFINXZDINX: # %bb.0: # %start
2350 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a2, a0, rtz
2351 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
2352 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
2353 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
2354 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
2355 ; RV32IZFINXZDINX-NEXT: ret
2356 ;
2357 ; RV64IZFINXZDINX-LABEL: fcvt_wu_d_sat_zext:
2358 ; RV64IZFINXZDINX: # %bb.0: # %start
2359 ; RV64IZFINXZDINX-NEXT: fcvt.wu.d a1, a0, rtz
2360 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
2361 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
2362 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
2363 ; RV64IZFINXZDINX-NEXT: and a0, a1, a0
2364 ; RV64IZFINXZDINX-NEXT: slli a0, a0, 32
2365 ; RV64IZFINXZDINX-NEXT: srli a0, a0, 32
2366 ; RV64IZFINXZDINX-NEXT: ret
2367 ;
2368 ; RV32I-LABEL: fcvt_wu_d_sat_zext:
2369 ; RV32I: # %bb.0: # %start
2370 ; RV32I-NEXT: addi sp, sp, -32
2371 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2372 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2373 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2374 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2375 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2376 ; RV32I-NEXT: mv s0, a1
2377 ; RV32I-NEXT: mv s1, a0
2378 ; RV32I-NEXT: lui a3, 270080
2379 ; RV32I-NEXT: addi a3, a3, -1
2380 ; RV32I-NEXT: lui a2, 1048064
2381 ; RV32I-NEXT: call __gtdf2
2382 ; RV32I-NEXT: sgtz a0, a0
2383 ; RV32I-NEXT: neg s2, a0
2384 ; RV32I-NEXT: mv a0, s1
2385 ; RV32I-NEXT: mv a1, s0
2386 ; RV32I-NEXT: li a2, 0
2387 ; RV32I-NEXT: li a3, 0
2388 ; RV32I-NEXT: call __gedf2
2389 ; RV32I-NEXT: slti a0, a0, 0
2390 ; RV32I-NEXT: addi s3, a0, -1
2391 ; RV32I-NEXT: mv a0, s1
2392 ; RV32I-NEXT: mv a1, s0
2393 ; RV32I-NEXT: call __fixunsdfsi
2394 ; RV32I-NEXT: and a0, s3, a0
2395 ; RV32I-NEXT: or a0, s2, a0
2396 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2397 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2398 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2399 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2400 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2401 ; RV32I-NEXT: addi sp, sp, 32
2402 ; RV32I-NEXT: ret
2403 ;
2404 ; RV64I-LABEL: fcvt_wu_d_sat_zext:
2405 ; RV64I: # %bb.0: # %start
2406 ; RV64I-NEXT: addi sp, sp, -32
2407 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2408 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2409 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2410 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2411 ; RV64I-NEXT: mv s2, a0
2412 ; RV64I-NEXT: li a1, 0
2413 ; RV64I-NEXT: call __gedf2
2414 ; RV64I-NEXT: mv s0, a0
2415 ; RV64I-NEXT: mv a0, s2
2416 ; RV64I-NEXT: call __fixunsdfdi
2417 ; RV64I-NEXT: mv s1, a0
2418 ; RV64I-NEXT: li a0, 1055
2419 ; RV64I-NEXT: slli a0, a0, 31
2420 ; RV64I-NEXT: addi a0, a0, -1
2421 ; RV64I-NEXT: slli a1, a0, 21
2422 ; RV64I-NEXT: mv a0, s2
2423 ; RV64I-NEXT: call __gtdf2
2424 ; RV64I-NEXT: blez a0, .LBB33_2
2425 ; RV64I-NEXT: # %bb.1: # %start
2426 ; RV64I-NEXT: li a0, -1
2427 ; RV64I-NEXT: srli a0, a0, 32
2428 ; RV64I-NEXT: j .LBB33_3
2429 ; RV64I-NEXT: .LBB33_2:
2430 ; RV64I-NEXT: slti a0, s0, 0
2431 ; RV64I-NEXT: addi a0, a0, -1
2432 ; RV64I-NEXT: and a0, a0, s1
2433 ; RV64I-NEXT: .LBB33_3: # %start
2434 ; RV64I-NEXT: slli a0, a0, 32
2435 ; RV64I-NEXT: srli a0, a0, 32
2436 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2437 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2438 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2439 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2440 ; RV64I-NEXT: addi sp, sp, 32
2441 ; RV64I-NEXT: ret
2442 start:
2443 %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
2444 ret i32 %0
2445 }
2447 define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
2448 ; CHECKIFD-LABEL: fcvt_w_d_sat_sext:
2449 ; CHECKIFD: # %bb.0: # %start
2450 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
2451 ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
2452 ; CHECKIFD-NEXT: seqz a1, a1
2453 ; CHECKIFD-NEXT: addi a1, a1, -1
2454 ; CHECKIFD-NEXT: and a0, a1, a0
2455 ; CHECKIFD-NEXT: ret
2456 ;
2457 ; RV32IZFINXZDINX-LABEL: fcvt_w_d_sat_sext:
2458 ; RV32IZFINXZDINX: # %bb.0: # %start
2459 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a2, a0, rtz
2460 ; RV32IZFINXZDINX-NEXT: feq.d a0, a0, a0
2461 ; RV32IZFINXZDINX-NEXT: seqz a0, a0
2462 ; RV32IZFINXZDINX-NEXT: addi a0, a0, -1
2463 ; RV32IZFINXZDINX-NEXT: and a0, a0, a2
2464 ; RV32IZFINXZDINX-NEXT: ret
2465 ;
2466 ; RV64IZFINXZDINX-LABEL: fcvt_w_d_sat_sext:
2467 ; RV64IZFINXZDINX: # %bb.0: # %start
2468 ; RV64IZFINXZDINX-NEXT: fcvt.w.d a1, a0, rtz
2469 ; RV64IZFINXZDINX-NEXT: feq.d a0, a0, a0
2470 ; RV64IZFINXZDINX-NEXT: seqz a0, a0
2471 ; RV64IZFINXZDINX-NEXT: addi a0, a0, -1
2472 ; RV64IZFINXZDINX-NEXT: and a0, a0, a1
2473 ; RV64IZFINXZDINX-NEXT: ret
2474 ;
2475 ; RV32I-LABEL: fcvt_w_d_sat_sext:
2476 ; RV32I: # %bb.0: # %start
2477 ; RV32I-NEXT: addi sp, sp, -32
2478 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2479 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2480 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2481 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2482 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2483 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
2484 ; RV32I-NEXT: mv s0, a1
2485 ; RV32I-NEXT: mv s1, a0
2486 ; RV32I-NEXT: lui a3, 269824
2487 ; RV32I-NEXT: addi a3, a3, -1
2488 ; RV32I-NEXT: lui a2, 1047552
2489 ; RV32I-NEXT: call __gtdf2
2490 ; RV32I-NEXT: mv s2, a0
2491 ; RV32I-NEXT: lui a3, 794112
2492 ; RV32I-NEXT: mv a0, s1
2493 ; RV32I-NEXT: mv a1, s0
2494 ; RV32I-NEXT: li a2, 0
2495 ; RV32I-NEXT: call __gedf2
2496 ; RV32I-NEXT: mv s4, a0
2497 ; RV32I-NEXT: mv a0, s1
2498 ; RV32I-NEXT: mv a1, s0
2499 ; RV32I-NEXT: call __fixdfsi
2500 ; RV32I-NEXT: mv s3, a0
2501 ; RV32I-NEXT: lui a0, 524288
2502 ; RV32I-NEXT: bgez s4, .LBB34_2
2503 ; RV32I-NEXT: # %bb.1: # %start
2504 ; RV32I-NEXT: lui s3, 524288
2505 ; RV32I-NEXT: .LBB34_2: # %start
2506 ; RV32I-NEXT: blez s2, .LBB34_4
2507 ; RV32I-NEXT: # %bb.3: # %start
2508 ; RV32I-NEXT: addi s3, a0, -1
2509 ; RV32I-NEXT: .LBB34_4: # %start
2510 ; RV32I-NEXT: mv a0, s1
2511 ; RV32I-NEXT: mv a1, s0
2512 ; RV32I-NEXT: mv a2, s1
2513 ; RV32I-NEXT: mv a3, s0
2514 ; RV32I-NEXT: call __unorddf2
2515 ; RV32I-NEXT: snez a0, a0
2516 ; RV32I-NEXT: addi a0, a0, -1
2517 ; RV32I-NEXT: and a0, a0, s3
2518 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2519 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2520 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2521 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2522 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2523 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
2524 ; RV32I-NEXT: addi sp, sp, 32
2525 ; RV32I-NEXT: ret
2526 ;
2527 ; RV64I-LABEL: fcvt_w_d_sat_sext:
2528 ; RV64I: # %bb.0: # %start
2529 ; RV64I-NEXT: addi sp, sp, -48
2530 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
2531 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
2532 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
2533 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
2534 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
2535 ; RV64I-NEXT: mv s0, a0
2536 ; RV64I-NEXT: li a1, -497
2537 ; RV64I-NEXT: slli a1, a1, 53
2538 ; RV64I-NEXT: call __gedf2
2539 ; RV64I-NEXT: mv s2, a0
2540 ; RV64I-NEXT: mv a0, s0
2541 ; RV64I-NEXT: call __fixdfdi
2542 ; RV64I-NEXT: mv s1, a0
2543 ; RV64I-NEXT: lui s3, 524288
2544 ; RV64I-NEXT: bgez s2, .LBB34_2
2545 ; RV64I-NEXT: # %bb.1: # %start
2546 ; RV64I-NEXT: lui s1, 524288
2547 ; RV64I-NEXT: .LBB34_2: # %start
2548 ; RV64I-NEXT: li a0, 527
2549 ; RV64I-NEXT: slli a0, a0, 31
2550 ; RV64I-NEXT: addi a0, a0, -1
2551 ; RV64I-NEXT: slli a1, a0, 22
2552 ; RV64I-NEXT: mv a0, s0
2553 ; RV64I-NEXT: call __gtdf2
2554 ; RV64I-NEXT: blez a0, .LBB34_4
2555 ; RV64I-NEXT: # %bb.3: # %start
2556 ; RV64I-NEXT: addi s1, s3, -1
2557 ; RV64I-NEXT: .LBB34_4: # %start
2558 ; RV64I-NEXT: mv a0, s0
2559 ; RV64I-NEXT: mv a1, s0
2560 ; RV64I-NEXT: call __unorddf2
2561 ; RV64I-NEXT: snez a0, a0
2562 ; RV64I-NEXT: addi a0, a0, -1
2563 ; RV64I-NEXT: and a0, a0, s1
2564 ; RV64I-NEXT: sext.w a0, a0
2565 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
2566 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
2567 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
2568 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
2569 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
2570 ; RV64I-NEXT: addi sp, sp, 48
2571 ; RV64I-NEXT: ret
2572 start:
2573 %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
2574 ret i32 %0
2575 }