| blob | 7eabd3f5f2273af5dcb5bdfa454b803d38d0ec94 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZFINX,RV32IZFINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZFINX,RV64IZFINX %s
10 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
11 ; RUN: | FileCheck -check-prefix=RV32I %s
12 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
13 ; RUN: | FileCheck -check-prefix=RV64I %s
15 define i32 @fcvt_w_s(float %a) nounwind {
16 ; CHECKIF-LABEL: fcvt_w_s:
17 ; CHECKIF: # %bb.0:
18 ; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
19 ; CHECKIF-NEXT: ret
20 ;
21 ; CHECKIZFINX-LABEL: fcvt_w_s:
22 ; CHECKIZFINX: # %bb.0:
23 ; CHECKIZFINX-NEXT: fcvt.w.s a0, a0, rtz
24 ; CHECKIZFINX-NEXT: ret
25 ;
26 ; RV32I-LABEL: fcvt_w_s:
27 ; RV32I: # %bb.0:
28 ; RV32I-NEXT: addi sp, sp, -16
29 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
30 ; RV32I-NEXT: call __fixsfsi
31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
32 ; RV32I-NEXT: addi sp, sp, 16
33 ; RV32I-NEXT: ret
34 ;
35 ; RV64I-LABEL: fcvt_w_s:
36 ; RV64I: # %bb.0:
37 ; RV64I-NEXT: addi sp, sp, -16
38 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
39 ; RV64I-NEXT: call __fixsfsi
40 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
41 ; RV64I-NEXT: addi sp, sp, 16
42 ; RV64I-NEXT: ret
43 %1 = fptosi float %a to i32
44 ret i32 %1
45 }
47 define i32 @fcvt_w_s_sat(float %a) nounwind {
48 ; CHECKIF-LABEL: fcvt_w_s_sat:
49 ; CHECKIF: # %bb.0: # %start
50 ; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
51 ; CHECKIF-NEXT: feq.s a1, fa0, fa0
52 ; CHECKIF-NEXT: seqz a1, a1
53 ; CHECKIF-NEXT: addi a1, a1, -1
54 ; CHECKIF-NEXT: and a0, a1, a0
55 ; CHECKIF-NEXT: ret
56 ;
57 ; CHECKIZFINX-LABEL: fcvt_w_s_sat:
58 ; CHECKIZFINX: # %bb.0: # %start
59 ; CHECKIZFINX-NEXT: fcvt.w.s a1, a0, rtz
60 ; CHECKIZFINX-NEXT: feq.s a0, a0, a0
61 ; CHECKIZFINX-NEXT: seqz a0, a0
62 ; CHECKIZFINX-NEXT: addi a0, a0, -1
63 ; CHECKIZFINX-NEXT: and a0, a0, a1
64 ; CHECKIZFINX-NEXT: ret
65 ;
66 ; RV32I-LABEL: fcvt_w_s_sat:
67 ; RV32I: # %bb.0: # %start
68 ; RV32I-NEXT: addi sp, sp, -32
69 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
70 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
71 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
72 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
73 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
74 ; RV32I-NEXT: mv s0, a0
75 ; RV32I-NEXT: lui a1, 847872
76 ; RV32I-NEXT: call __gesf2
77 ; RV32I-NEXT: mv s2, a0
78 ; RV32I-NEXT: mv a0, s0
79 ; RV32I-NEXT: call __fixsfsi
80 ; RV32I-NEXT: mv s1, a0
81 ; RV32I-NEXT: lui s3, 524288
82 ; RV32I-NEXT: bgez s2, .LBB1_2
83 ; RV32I-NEXT: # %bb.1: # %start
84 ; RV32I-NEXT: lui s1, 524288
85 ; RV32I-NEXT: .LBB1_2: # %start
86 ; RV32I-NEXT: lui a1, 323584
87 ; RV32I-NEXT: addi a1, a1, -1
88 ; RV32I-NEXT: mv a0, s0
89 ; RV32I-NEXT: call __gtsf2
90 ; RV32I-NEXT: blez a0, .LBB1_4
91 ; RV32I-NEXT: # %bb.3: # %start
92 ; RV32I-NEXT: addi s1, s3, -1
93 ; RV32I-NEXT: .LBB1_4: # %start
94 ; RV32I-NEXT: mv a0, s0
95 ; RV32I-NEXT: mv a1, s0
96 ; RV32I-NEXT: call __unordsf2
97 ; RV32I-NEXT: snez a0, a0
98 ; RV32I-NEXT: addi a0, a0, -1
99 ; RV32I-NEXT: and a0, a0, s1
100 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
101 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
102 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
103 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
104 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
105 ; RV32I-NEXT: addi sp, sp, 32
106 ; RV32I-NEXT: ret
107 ;
108 ; RV64I-LABEL: fcvt_w_s_sat:
109 ; RV64I: # %bb.0: # %start
110 ; RV64I-NEXT: addi sp, sp, -48
111 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
112 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
113 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
114 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
115 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
116 ; RV64I-NEXT: mv s0, a0
117 ; RV64I-NEXT: lui a1, 847872
118 ; RV64I-NEXT: call __gesf2
119 ; RV64I-NEXT: mv s2, a0
120 ; RV64I-NEXT: mv a0, s0
121 ; RV64I-NEXT: call __fixsfdi
122 ; RV64I-NEXT: mv s1, a0
123 ; RV64I-NEXT: lui s3, 524288
124 ; RV64I-NEXT: bgez s2, .LBB1_2
125 ; RV64I-NEXT: # %bb.1: # %start
126 ; RV64I-NEXT: lui s1, 524288
127 ; RV64I-NEXT: .LBB1_2: # %start
128 ; RV64I-NEXT: lui a1, 323584
129 ; RV64I-NEXT: addiw a1, a1, -1
130 ; RV64I-NEXT: mv a0, s0
131 ; RV64I-NEXT: call __gtsf2
132 ; RV64I-NEXT: blez a0, .LBB1_4
133 ; RV64I-NEXT: # %bb.3: # %start
134 ; RV64I-NEXT: addiw s1, s3, -1
135 ; RV64I-NEXT: .LBB1_4: # %start
136 ; RV64I-NEXT: mv a0, s0
137 ; RV64I-NEXT: mv a1, s0
138 ; RV64I-NEXT: call __unordsf2
139 ; RV64I-NEXT: snez a0, a0
140 ; RV64I-NEXT: addi a0, a0, -1
141 ; RV64I-NEXT: and a0, a0, s1
142 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
143 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
144 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
145 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
146 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
147 ; RV64I-NEXT: addi sp, sp, 48
148 ; RV64I-NEXT: ret
149 start:
150 %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
151 ret i32 %0
152 }
153 declare i32 @llvm.fptosi.sat.i32.f32(float)
155 define i32 @fcvt_wu_s(float %a) nounwind {
156 ; CHECKIF-LABEL: fcvt_wu_s:
157 ; CHECKIF: # %bb.0:
158 ; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
159 ; CHECKIF-NEXT: ret
160 ;
161 ; CHECKIZFINX-LABEL: fcvt_wu_s:
162 ; CHECKIZFINX: # %bb.0:
163 ; CHECKIZFINX-NEXT: fcvt.wu.s a0, a0, rtz
164 ; CHECKIZFINX-NEXT: ret
165 ;
166 ; RV32I-LABEL: fcvt_wu_s:
167 ; RV32I: # %bb.0:
168 ; RV32I-NEXT: addi sp, sp, -16
169 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
170 ; RV32I-NEXT: call __fixunssfsi
171 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
172 ; RV32I-NEXT: addi sp, sp, 16
173 ; RV32I-NEXT: ret
174 ;
175 ; RV64I-LABEL: fcvt_wu_s:
176 ; RV64I: # %bb.0:
177 ; RV64I-NEXT: addi sp, sp, -16
178 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
179 ; RV64I-NEXT: call __fixunssfsi
180 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
181 ; RV64I-NEXT: addi sp, sp, 16
182 ; RV64I-NEXT: ret
183 %1 = fptoui float %a to i32
184 ret i32 %1
185 }
187 ; Test where the fptoui has multiple uses, one of which causes a sext to be
188 ; inserted on RV64.
189 define i32 @fcvt_wu_s_multiple_use(float %x, ptr %y) nounwind {
190 ; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
191 ; CHECKIF: # %bb.0:
192 ; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
193 ; CHECKIF-NEXT: seqz a1, a0
194 ; CHECKIF-NEXT: add a0, a0, a1
195 ; CHECKIF-NEXT: ret
196 ;
197 ; CHECKIZFINX-LABEL: fcvt_wu_s_multiple_use:
198 ; CHECKIZFINX: # %bb.0:
199 ; CHECKIZFINX-NEXT: fcvt.wu.s a0, a0, rtz
200 ; CHECKIZFINX-NEXT: seqz a1, a0
201 ; CHECKIZFINX-NEXT: add a0, a0, a1
202 ; CHECKIZFINX-NEXT: ret
203 ;
204 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
205 ; RV32I: # %bb.0:
206 ; RV32I-NEXT: addi sp, sp, -16
207 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
208 ; RV32I-NEXT: call __fixunssfsi
209 ; RV32I-NEXT: seqz a1, a0
210 ; RV32I-NEXT: add a0, a0, a1
211 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
212 ; RV32I-NEXT: addi sp, sp, 16
213 ; RV32I-NEXT: ret
214 ;
215 ; RV64I-LABEL: fcvt_wu_s_multiple_use:
216 ; RV64I: # %bb.0:
217 ; RV64I-NEXT: addi sp, sp, -16
218 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
219 ; RV64I-NEXT: call __fixunssfsi
220 ; RV64I-NEXT: seqz a1, a0
221 ; RV64I-NEXT: add a0, a0, a1
222 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
223 ; RV64I-NEXT: addi sp, sp, 16
224 ; RV64I-NEXT: ret
225 %a = fptoui float %x to i32
226 %b = icmp eq i32 %a, 0
227 %c = select i1 %b, i32 1, i32 %a
228 ret i32 %c
229 }
231 define i32 @fcvt_wu_s_sat(float %a) nounwind {
232 ; RV32IF-LABEL: fcvt_wu_s_sat:
233 ; RV32IF: # %bb.0: # %start
234 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
235 ; RV32IF-NEXT: feq.s a1, fa0, fa0
236 ; RV32IF-NEXT: seqz a1, a1
237 ; RV32IF-NEXT: addi a1, a1, -1
238 ; RV32IF-NEXT: and a0, a1, a0
239 ; RV32IF-NEXT: ret
240 ;
241 ; RV64IF-LABEL: fcvt_wu_s_sat:
242 ; RV64IF: # %bb.0: # %start
243 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
244 ; RV64IF-NEXT: feq.s a1, fa0, fa0
245 ; RV64IF-NEXT: seqz a1, a1
246 ; RV64IF-NEXT: addi a1, a1, -1
247 ; RV64IF-NEXT: and a0, a0, a1
248 ; RV64IF-NEXT: slli a0, a0, 32
249 ; RV64IF-NEXT: srli a0, a0, 32
250 ; RV64IF-NEXT: ret
251 ;
252 ; RV32IZFINX-LABEL: fcvt_wu_s_sat:
253 ; RV32IZFINX: # %bb.0: # %start
254 ; RV32IZFINX-NEXT: fcvt.wu.s a1, a0, rtz
255 ; RV32IZFINX-NEXT: feq.s a0, a0, a0
256 ; RV32IZFINX-NEXT: seqz a0, a0
257 ; RV32IZFINX-NEXT: addi a0, a0, -1
258 ; RV32IZFINX-NEXT: and a0, a0, a1
259 ; RV32IZFINX-NEXT: ret
260 ;
261 ; RV64IZFINX-LABEL: fcvt_wu_s_sat:
262 ; RV64IZFINX: # %bb.0: # %start
263 ; RV64IZFINX-NEXT: fcvt.wu.s a1, a0, rtz
264 ; RV64IZFINX-NEXT: feq.s a0, a0, a0
265 ; RV64IZFINX-NEXT: seqz a0, a0
266 ; RV64IZFINX-NEXT: addi a0, a0, -1
267 ; RV64IZFINX-NEXT: and a0, a1, a0
268 ; RV64IZFINX-NEXT: slli a0, a0, 32
269 ; RV64IZFINX-NEXT: srli a0, a0, 32
270 ; RV64IZFINX-NEXT: ret
271 ;
272 ; RV32I-LABEL: fcvt_wu_s_sat:
273 ; RV32I: # %bb.0: # %start
274 ; RV32I-NEXT: addi sp, sp, -16
275 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
276 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
277 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
278 ; RV32I-NEXT: mv s0, a0
279 ; RV32I-NEXT: li a1, 0
280 ; RV32I-NEXT: call __gesf2
281 ; RV32I-NEXT: slti a0, a0, 0
282 ; RV32I-NEXT: addi s1, a0, -1
283 ; RV32I-NEXT: mv a0, s0
284 ; RV32I-NEXT: call __fixunssfsi
285 ; RV32I-NEXT: and s1, s1, a0
286 ; RV32I-NEXT: lui a1, 325632
287 ; RV32I-NEXT: addi a1, a1, -1
288 ; RV32I-NEXT: mv a0, s0
289 ; RV32I-NEXT: call __gtsf2
290 ; RV32I-NEXT: sgtz a0, a0
291 ; RV32I-NEXT: neg a0, a0
292 ; RV32I-NEXT: or a0, a0, s1
293 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
294 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
295 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
296 ; RV32I-NEXT: addi sp, sp, 16
297 ; RV32I-NEXT: ret
298 ;
299 ; RV64I-LABEL: fcvt_wu_s_sat:
300 ; RV64I: # %bb.0: # %start
301 ; RV64I-NEXT: addi sp, sp, -32
302 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
303 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
304 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
305 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
306 ; RV64I-NEXT: mv s2, a0
307 ; RV64I-NEXT: li a1, 0
308 ; RV64I-NEXT: call __gesf2
309 ; RV64I-NEXT: mv s0, a0
310 ; RV64I-NEXT: mv a0, s2
311 ; RV64I-NEXT: call __fixunssfdi
312 ; RV64I-NEXT: mv s1, a0
313 ; RV64I-NEXT: lui a1, 325632
314 ; RV64I-NEXT: addiw a1, a1, -1
315 ; RV64I-NEXT: mv a0, s2
316 ; RV64I-NEXT: call __gtsf2
317 ; RV64I-NEXT: blez a0, .LBB4_2
318 ; RV64I-NEXT: # %bb.1: # %start
319 ; RV64I-NEXT: li a0, -1
320 ; RV64I-NEXT: srli a0, a0, 32
321 ; RV64I-NEXT: j .LBB4_3
322 ; RV64I-NEXT: .LBB4_2:
323 ; RV64I-NEXT: slti a0, s0, 0
324 ; RV64I-NEXT: addi a0, a0, -1
325 ; RV64I-NEXT: and a0, a0, s1
326 ; RV64I-NEXT: .LBB4_3: # %start
327 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
328 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
329 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
330 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
331 ; RV64I-NEXT: addi sp, sp, 32
332 ; RV64I-NEXT: ret
333 start:
334 %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
335 ret i32 %0
336 }
337 declare i32 @llvm.fptoui.sat.i32.f32(float)
339 define i32 @fmv_x_w(float %a, float %b) nounwind {
340 ; CHECKIF-LABEL: fmv_x_w:
341 ; CHECKIF: # %bb.0:
342 ; CHECKIF-NEXT: fadd.s fa5, fa0, fa1
343 ; CHECKIF-NEXT: fmv.x.w a0, fa5
344 ; CHECKIF-NEXT: ret
345 ;
346 ; CHECKIZFINX-LABEL: fmv_x_w:
347 ; CHECKIZFINX: # %bb.0:
348 ; CHECKIZFINX-NEXT: fadd.s a0, a0, a1
349 ; CHECKIZFINX-NEXT: ret
350 ;
351 ; RV32I-LABEL: fmv_x_w:
352 ; RV32I: # %bb.0:
353 ; RV32I-NEXT: addi sp, sp, -16
354 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
355 ; RV32I-NEXT: call __addsf3
356 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
357 ; RV32I-NEXT: addi sp, sp, 16
358 ; RV32I-NEXT: ret
359 ;
360 ; RV64I-LABEL: fmv_x_w:
361 ; RV64I: # %bb.0:
362 ; RV64I-NEXT: addi sp, sp, -16
363 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
364 ; RV64I-NEXT: call __addsf3
365 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
366 ; RV64I-NEXT: addi sp, sp, 16
367 ; RV64I-NEXT: ret
368 ; Ensure fmv.x.w is generated even for a soft float calling convention
369 %1 = fadd float %a, %b
370 %2 = bitcast float %1 to i32
371 ret i32 %2
372 }
374 define float @fcvt_s_w(i32 %a) nounwind {
375 ; CHECKIF-LABEL: fcvt_s_w:
376 ; CHECKIF: # %bb.0:
377 ; CHECKIF-NEXT: fcvt.s.w fa0, a0
378 ; CHECKIF-NEXT: ret
379 ;
380 ; CHECKIZFINX-LABEL: fcvt_s_w:
381 ; CHECKIZFINX: # %bb.0:
382 ; CHECKIZFINX-NEXT: fcvt.s.w a0, a0
383 ; CHECKIZFINX-NEXT: ret
384 ;
385 ; RV32I-LABEL: fcvt_s_w:
386 ; RV32I: # %bb.0:
387 ; RV32I-NEXT: addi sp, sp, -16
388 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
389 ; RV32I-NEXT: call __floatsisf
390 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
391 ; RV32I-NEXT: addi sp, sp, 16
392 ; RV32I-NEXT: ret
393 ;
394 ; RV64I-LABEL: fcvt_s_w:
395 ; RV64I: # %bb.0:
396 ; RV64I-NEXT: addi sp, sp, -16
397 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
398 ; RV64I-NEXT: sext.w a0, a0
399 ; RV64I-NEXT: call __floatsisf
400 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
401 ; RV64I-NEXT: addi sp, sp, 16
402 ; RV64I-NEXT: ret
403 %1 = sitofp i32 %a to float
404 ret float %1
405 }
407 define float @fcvt_s_w_load(ptr %p) nounwind {
408 ; CHECKIF-LABEL: fcvt_s_w_load:
409 ; CHECKIF: # %bb.0:
410 ; CHECKIF-NEXT: lw a0, 0(a0)
411 ; CHECKIF-NEXT: fcvt.s.w fa0, a0
412 ; CHECKIF-NEXT: ret
413 ;
414 ; CHECKIZFINX-LABEL: fcvt_s_w_load:
415 ; CHECKIZFINX: # %bb.0:
416 ; CHECKIZFINX-NEXT: lw a0, 0(a0)
417 ; CHECKIZFINX-NEXT: fcvt.s.w a0, a0
418 ; CHECKIZFINX-NEXT: ret
419 ;
420 ; RV32I-LABEL: fcvt_s_w_load:
421 ; RV32I: # %bb.0:
422 ; RV32I-NEXT: addi sp, sp, -16
423 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
424 ; RV32I-NEXT: lw a0, 0(a0)
425 ; RV32I-NEXT: call __floatsisf
426 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
427 ; RV32I-NEXT: addi sp, sp, 16
428 ; RV32I-NEXT: ret
429 ;
430 ; RV64I-LABEL: fcvt_s_w_load:
431 ; RV64I: # %bb.0:
432 ; RV64I-NEXT: addi sp, sp, -16
433 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
434 ; RV64I-NEXT: lw a0, 0(a0)
435 ; RV64I-NEXT: call __floatsisf
436 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
437 ; RV64I-NEXT: addi sp, sp, 16
438 ; RV64I-NEXT: ret
439 %a = load i32, ptr %p
440 %1 = sitofp i32 %a to float
441 ret float %1
442 }
444 define float @fcvt_s_wu(i32 %a) nounwind {
445 ; CHECKIF-LABEL: fcvt_s_wu:
446 ; CHECKIF: # %bb.0:
447 ; CHECKIF-NEXT: fcvt.s.wu fa0, a0
448 ; CHECKIF-NEXT: ret
449 ;
450 ; CHECKIZFINX-LABEL: fcvt_s_wu:
451 ; CHECKIZFINX: # %bb.0:
452 ; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0
453 ; CHECKIZFINX-NEXT: ret
454 ;
455 ; RV32I-LABEL: fcvt_s_wu:
456 ; RV32I: # %bb.0:
457 ; RV32I-NEXT: addi sp, sp, -16
458 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
459 ; RV32I-NEXT: call __floatunsisf
460 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
461 ; RV32I-NEXT: addi sp, sp, 16
462 ; RV32I-NEXT: ret
463 ;
464 ; RV64I-LABEL: fcvt_s_wu:
465 ; RV64I: # %bb.0:
466 ; RV64I-NEXT: addi sp, sp, -16
467 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
468 ; RV64I-NEXT: sext.w a0, a0
469 ; RV64I-NEXT: call __floatunsisf
470 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
471 ; RV64I-NEXT: addi sp, sp, 16
472 ; RV64I-NEXT: ret
473 %1 = uitofp i32 %a to float
474 ret float %1
475 }
477 define float @fcvt_s_wu_load(ptr %p) nounwind {
478 ; RV32IF-LABEL: fcvt_s_wu_load:
479 ; RV32IF: # %bb.0:
480 ; RV32IF-NEXT: lw a0, 0(a0)
481 ; RV32IF-NEXT: fcvt.s.wu fa0, a0
482 ; RV32IF-NEXT: ret
483 ;
484 ; RV64IF-LABEL: fcvt_s_wu_load:
485 ; RV64IF: # %bb.0:
486 ; RV64IF-NEXT: lwu a0, 0(a0)
487 ; RV64IF-NEXT: fcvt.s.wu fa0, a0
488 ; RV64IF-NEXT: ret
489 ;
490 ; RV32IZFINX-LABEL: fcvt_s_wu_load:
491 ; RV32IZFINX: # %bb.0:
492 ; RV32IZFINX-NEXT: lw a0, 0(a0)
493 ; RV32IZFINX-NEXT: fcvt.s.wu a0, a0
494 ; RV32IZFINX-NEXT: ret
495 ;
496 ; RV64IZFINX-LABEL: fcvt_s_wu_load:
497 ; RV64IZFINX: # %bb.0:
498 ; RV64IZFINX-NEXT: lwu a0, 0(a0)
499 ; RV64IZFINX-NEXT: fcvt.s.wu a0, a0
500 ; RV64IZFINX-NEXT: ret
501 ;
502 ; RV32I-LABEL: fcvt_s_wu_load:
503 ; RV32I: # %bb.0:
504 ; RV32I-NEXT: addi sp, sp, -16
505 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
506 ; RV32I-NEXT: lw a0, 0(a0)
507 ; RV32I-NEXT: call __floatunsisf
508 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
509 ; RV32I-NEXT: addi sp, sp, 16
510 ; RV32I-NEXT: ret
511 ;
512 ; RV64I-LABEL: fcvt_s_wu_load:
513 ; RV64I: # %bb.0:
514 ; RV64I-NEXT: addi sp, sp, -16
515 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
516 ; RV64I-NEXT: lw a0, 0(a0)
517 ; RV64I-NEXT: call __floatunsisf
518 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
519 ; RV64I-NEXT: addi sp, sp, 16
520 ; RV64I-NEXT: ret
521 %a = load i32, ptr %p
522 %1 = uitofp i32 %a to float
523 ret float %1
524 }
526 define float @fmv_w_x(i32 %a, i32 %b) nounwind {
527 ; CHECKIF-LABEL: fmv_w_x:
528 ; CHECKIF: # %bb.0:
529 ; CHECKIF-NEXT: fmv.w.x fa5, a0
530 ; CHECKIF-NEXT: fmv.w.x fa4, a1
531 ; CHECKIF-NEXT: fadd.s fa0, fa5, fa4
532 ; CHECKIF-NEXT: ret
533 ;
534 ; CHECKIZFINX-LABEL: fmv_w_x:
535 ; CHECKIZFINX: # %bb.0:
536 ; CHECKIZFINX-NEXT: fadd.s a0, a0, a1
537 ; CHECKIZFINX-NEXT: ret
538 ;
539 ; RV32I-LABEL: fmv_w_x:
540 ; RV32I: # %bb.0:
541 ; RV32I-NEXT: addi sp, sp, -16
542 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
543 ; RV32I-NEXT: call __addsf3
544 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
545 ; RV32I-NEXT: addi sp, sp, 16
546 ; RV32I-NEXT: ret
547 ;
548 ; RV64I-LABEL: fmv_w_x:
549 ; RV64I: # %bb.0:
550 ; RV64I-NEXT: addi sp, sp, -16
551 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
552 ; RV64I-NEXT: call __addsf3
553 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
554 ; RV64I-NEXT: addi sp, sp, 16
555 ; RV64I-NEXT: ret
556 ; Ensure fmv.w.x is generated even for a soft float calling convention
557 %1 = bitcast i32 %a to float
558 %2 = bitcast i32 %b to float
559 %3 = fadd float %1, %2
560 ret float %3
561 }
563 define i64 @fcvt_l_s(float %a) nounwind {
564 ; RV32IF-LABEL: fcvt_l_s:
565 ; RV32IF: # %bb.0:
566 ; RV32IF-NEXT: addi sp, sp, -16
567 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
568 ; RV32IF-NEXT: call __fixsfdi
569 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
570 ; RV32IF-NEXT: addi sp, sp, 16
571 ; RV32IF-NEXT: ret
572 ;
573 ; RV64IF-LABEL: fcvt_l_s:
574 ; RV64IF: # %bb.0:
575 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
576 ; RV64IF-NEXT: ret
577 ;
578 ; RV32IZFINX-LABEL: fcvt_l_s:
579 ; RV32IZFINX: # %bb.0:
580 ; RV32IZFINX-NEXT: addi sp, sp, -16
581 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
582 ; RV32IZFINX-NEXT: call __fixsfdi
583 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
584 ; RV32IZFINX-NEXT: addi sp, sp, 16
585 ; RV32IZFINX-NEXT: ret
586 ;
587 ; RV64IZFINX-LABEL: fcvt_l_s:
588 ; RV64IZFINX: # %bb.0:
589 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
590 ; RV64IZFINX-NEXT: ret
591 ;
592 ; RV32I-LABEL: fcvt_l_s:
593 ; RV32I: # %bb.0:
594 ; RV32I-NEXT: addi sp, sp, -16
595 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
596 ; RV32I-NEXT: call __fixsfdi
597 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
598 ; RV32I-NEXT: addi sp, sp, 16
599 ; RV32I-NEXT: ret
600 ;
601 ; RV64I-LABEL: fcvt_l_s:
602 ; RV64I: # %bb.0:
603 ; RV64I-NEXT: addi sp, sp, -16
604 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
605 ; RV64I-NEXT: call __fixsfdi
606 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
607 ; RV64I-NEXT: addi sp, sp, 16
608 ; RV64I-NEXT: ret
609 %1 = fptosi float %a to i64
610 ret i64 %1
611 }
613 define i64 @fcvt_l_s_sat(float %a) nounwind {
614 ; RV32IF-LABEL: fcvt_l_s_sat:
615 ; RV32IF: # %bb.0: # %start
616 ; RV32IF-NEXT: addi sp, sp, -16
617 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
618 ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
619 ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
620 ; RV32IF-NEXT: fmv.s fs0, fa0
621 ; RV32IF-NEXT: lui a0, 913408
622 ; RV32IF-NEXT: fmv.w.x fa5, a0
623 ; RV32IF-NEXT: fle.s s0, fa5, fa0
624 ; RV32IF-NEXT: call __fixsfdi
625 ; RV32IF-NEXT: lui a4, 524288
626 ; RV32IF-NEXT: lui a2, 524288
627 ; RV32IF-NEXT: beqz s0, .LBB12_2
628 ; RV32IF-NEXT: # %bb.1: # %start
629 ; RV32IF-NEXT: mv a2, a1
630 ; RV32IF-NEXT: .LBB12_2: # %start
631 ; RV32IF-NEXT: lui a1, %hi(.LCPI12_0)
632 ; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a1)
633 ; RV32IF-NEXT: flt.s a3, fa5, fs0
634 ; RV32IF-NEXT: beqz a3, .LBB12_4
635 ; RV32IF-NEXT: # %bb.3:
636 ; RV32IF-NEXT: addi a2, a4, -1
637 ; RV32IF-NEXT: .LBB12_4: # %start
638 ; RV32IF-NEXT: feq.s a1, fs0, fs0
639 ; RV32IF-NEXT: neg a4, a1
640 ; RV32IF-NEXT: and a1, a4, a2
641 ; RV32IF-NEXT: neg a2, s0
642 ; RV32IF-NEXT: and a0, a2, a0
643 ; RV32IF-NEXT: neg a2, a3
644 ; RV32IF-NEXT: or a0, a2, a0
645 ; RV32IF-NEXT: and a0, a4, a0
646 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
647 ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
648 ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
649 ; RV32IF-NEXT: addi sp, sp, 16
650 ; RV32IF-NEXT: ret
651 ;
652 ; RV64IF-LABEL: fcvt_l_s_sat:
653 ; RV64IF: # %bb.0: # %start
654 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
655 ; RV64IF-NEXT: feq.s a1, fa0, fa0
656 ; RV64IF-NEXT: seqz a1, a1
657 ; RV64IF-NEXT: addi a1, a1, -1
658 ; RV64IF-NEXT: and a0, a1, a0
659 ; RV64IF-NEXT: ret
660 ;
661 ; RV32IZFINX-LABEL: fcvt_l_s_sat:
662 ; RV32IZFINX: # %bb.0: # %start
663 ; RV32IZFINX-NEXT: addi sp, sp, -16
664 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
665 ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
666 ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
667 ; RV32IZFINX-NEXT: mv s0, a0
668 ; RV32IZFINX-NEXT: lui a0, 913408
669 ; RV32IZFINX-NEXT: fle.s s1, a0, s0
670 ; RV32IZFINX-NEXT: mv a0, s0
671 ; RV32IZFINX-NEXT: call __fixsfdi
672 ; RV32IZFINX-NEXT: lui a4, 524288
673 ; RV32IZFINX-NEXT: lui a2, 524288
674 ; RV32IZFINX-NEXT: beqz s1, .LBB12_2
675 ; RV32IZFINX-NEXT: # %bb.1: # %start
676 ; RV32IZFINX-NEXT: mv a2, a1
677 ; RV32IZFINX-NEXT: .LBB12_2: # %start
678 ; RV32IZFINX-NEXT: lui a1, %hi(.LCPI12_0)
679 ; RV32IZFINX-NEXT: lw a1, %lo(.LCPI12_0)(a1)
680 ; RV32IZFINX-NEXT: flt.s a3, a1, s0
681 ; RV32IZFINX-NEXT: beqz a3, .LBB12_4
682 ; RV32IZFINX-NEXT: # %bb.3:
683 ; RV32IZFINX-NEXT: addi a2, a4, -1
684 ; RV32IZFINX-NEXT: .LBB12_4: # %start
685 ; RV32IZFINX-NEXT: feq.s a1, s0, s0
686 ; RV32IZFINX-NEXT: neg a4, a1
687 ; RV32IZFINX-NEXT: and a1, a4, a2
688 ; RV32IZFINX-NEXT: neg a2, s1
689 ; RV32IZFINX-NEXT: and a0, a2, a0
690 ; RV32IZFINX-NEXT: neg a2, a3
691 ; RV32IZFINX-NEXT: or a0, a2, a0
692 ; RV32IZFINX-NEXT: and a0, a4, a0
693 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
694 ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
695 ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
696 ; RV32IZFINX-NEXT: addi sp, sp, 16
697 ; RV32IZFINX-NEXT: ret
698 ;
699 ; RV64IZFINX-LABEL: fcvt_l_s_sat:
700 ; RV64IZFINX: # %bb.0: # %start
701 ; RV64IZFINX-NEXT: fcvt.l.s a1, a0, rtz
702 ; RV64IZFINX-NEXT: feq.s a0, a0, a0
703 ; RV64IZFINX-NEXT: seqz a0, a0
704 ; RV64IZFINX-NEXT: addi a0, a0, -1
705 ; RV64IZFINX-NEXT: and a0, a0, a1
706 ; RV64IZFINX-NEXT: ret
707 ;
708 ; RV32I-LABEL: fcvt_l_s_sat:
709 ; RV32I: # %bb.0: # %start
710 ; RV32I-NEXT: addi sp, sp, -32
711 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
712 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
713 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
714 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
715 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
716 ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
717 ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
718 ; RV32I-NEXT: mv s0, a0
719 ; RV32I-NEXT: lui a1, 913408
720 ; RV32I-NEXT: call __gesf2
721 ; RV32I-NEXT: mv s1, a0
722 ; RV32I-NEXT: mv a0, s0
723 ; RV32I-NEXT: call __fixsfdi
724 ; RV32I-NEXT: mv s2, a0
725 ; RV32I-NEXT: mv s3, a1
726 ; RV32I-NEXT: lui s5, 524288
727 ; RV32I-NEXT: bgez s1, .LBB12_2
728 ; RV32I-NEXT: # %bb.1: # %start
729 ; RV32I-NEXT: lui s3, 524288
730 ; RV32I-NEXT: .LBB12_2: # %start
731 ; RV32I-NEXT: lui a1, 389120
732 ; RV32I-NEXT: addi a1, a1, -1
733 ; RV32I-NEXT: mv a0, s0
734 ; RV32I-NEXT: call __gtsf2
735 ; RV32I-NEXT: mv s4, a0
736 ; RV32I-NEXT: blez a0, .LBB12_4
737 ; RV32I-NEXT: # %bb.3: # %start
738 ; RV32I-NEXT: addi s3, s5, -1
739 ; RV32I-NEXT: .LBB12_4: # %start
740 ; RV32I-NEXT: mv a0, s0
741 ; RV32I-NEXT: mv a1, s0
742 ; RV32I-NEXT: call __unordsf2
743 ; RV32I-NEXT: snez a0, a0
744 ; RV32I-NEXT: addi a0, a0, -1
745 ; RV32I-NEXT: and a1, a0, s3
746 ; RV32I-NEXT: slti a2, s1, 0
747 ; RV32I-NEXT: addi a2, a2, -1
748 ; RV32I-NEXT: and a2, a2, s2
749 ; RV32I-NEXT: sgtz a3, s4
750 ; RV32I-NEXT: neg a3, a3
751 ; RV32I-NEXT: or a2, a3, a2
752 ; RV32I-NEXT: and a0, a0, a2
753 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
754 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
755 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
756 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
757 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
758 ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
759 ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
760 ; RV32I-NEXT: addi sp, sp, 32
761 ; RV32I-NEXT: ret
762 ;
763 ; RV64I-LABEL: fcvt_l_s_sat:
764 ; RV64I: # %bb.0: # %start
765 ; RV64I-NEXT: addi sp, sp, -48
766 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
767 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
768 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
769 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
770 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
771 ; RV64I-NEXT: mv s0, a0
772 ; RV64I-NEXT: lui a1, 913408
773 ; RV64I-NEXT: call __gesf2
774 ; RV64I-NEXT: mv s2, a0
775 ; RV64I-NEXT: mv a0, s0
776 ; RV64I-NEXT: call __fixsfdi
777 ; RV64I-NEXT: mv s1, a0
778 ; RV64I-NEXT: li s3, -1
779 ; RV64I-NEXT: bgez s2, .LBB12_2
780 ; RV64I-NEXT: # %bb.1: # %start
781 ; RV64I-NEXT: slli s1, s3, 63
782 ; RV64I-NEXT: .LBB12_2: # %start
783 ; RV64I-NEXT: lui a1, 389120
784 ; RV64I-NEXT: addiw a1, a1, -1
785 ; RV64I-NEXT: mv a0, s0
786 ; RV64I-NEXT: call __gtsf2
787 ; RV64I-NEXT: blez a0, .LBB12_4
788 ; RV64I-NEXT: # %bb.3: # %start
789 ; RV64I-NEXT: srli s1, s3, 1
790 ; RV64I-NEXT: .LBB12_4: # %start
791 ; RV64I-NEXT: mv a0, s0
792 ; RV64I-NEXT: mv a1, s0
793 ; RV64I-NEXT: call __unordsf2
794 ; RV64I-NEXT: snez a0, a0
795 ; RV64I-NEXT: addi a0, a0, -1
796 ; RV64I-NEXT: and a0, a0, s1
797 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
798 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
799 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
800 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
801 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
802 ; RV64I-NEXT: addi sp, sp, 48
803 ; RV64I-NEXT: ret
804 start:
805 %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
806 ret i64 %0
807 }
808 declare i64 @llvm.fptosi.sat.i64.f32(float)
810 define i64 @fcvt_lu_s(float %a) nounwind {
811 ; RV32IF-LABEL: fcvt_lu_s:
812 ; RV32IF: # %bb.0:
813 ; RV32IF-NEXT: addi sp, sp, -16
814 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
815 ; RV32IF-NEXT: call __fixunssfdi
816 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
817 ; RV32IF-NEXT: addi sp, sp, 16
818 ; RV32IF-NEXT: ret
819 ;
820 ; RV64IF-LABEL: fcvt_lu_s:
821 ; RV64IF: # %bb.0:
822 ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
823 ; RV64IF-NEXT: ret
824 ;
825 ; RV32IZFINX-LABEL: fcvt_lu_s:
826 ; RV32IZFINX: # %bb.0:
827 ; RV32IZFINX-NEXT: addi sp, sp, -16
828 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
829 ; RV32IZFINX-NEXT: call __fixunssfdi
830 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
831 ; RV32IZFINX-NEXT: addi sp, sp, 16
832 ; RV32IZFINX-NEXT: ret
833 ;
834 ; RV64IZFINX-LABEL: fcvt_lu_s:
835 ; RV64IZFINX: # %bb.0:
836 ; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
837 ; RV64IZFINX-NEXT: ret
838 ;
839 ; RV32I-LABEL: fcvt_lu_s:
840 ; RV32I: # %bb.0:
841 ; RV32I-NEXT: addi sp, sp, -16
842 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
843 ; RV32I-NEXT: call __fixunssfdi
844 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
845 ; RV32I-NEXT: addi sp, sp, 16
846 ; RV32I-NEXT: ret
847 ;
848 ; RV64I-LABEL: fcvt_lu_s:
849 ; RV64I: # %bb.0:
850 ; RV64I-NEXT: addi sp, sp, -16
851 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
852 ; RV64I-NEXT: call __fixunssfdi
853 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
854 ; RV64I-NEXT: addi sp, sp, 16
855 ; RV64I-NEXT: ret
856 %1 = fptoui float %a to i64
857 ret i64 %1
858 }
860 define i64 @fcvt_lu_s_sat(float %a) nounwind {
861 ; RV32IF-LABEL: fcvt_lu_s_sat:
862 ; RV32IF: # %bb.0: # %start
863 ; RV32IF-NEXT: addi sp, sp, -16
864 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
865 ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
866 ; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
867 ; RV32IF-NEXT: fmv.s fs0, fa0
868 ; RV32IF-NEXT: fmv.w.x fa5, zero
869 ; RV32IF-NEXT: fle.s a0, fa5, fa0
870 ; RV32IF-NEXT: neg s0, a0
871 ; RV32IF-NEXT: call __fixunssfdi
872 ; RV32IF-NEXT: lui a2, %hi(.LCPI14_0)
873 ; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2)
874 ; RV32IF-NEXT: and a0, s0, a0
875 ; RV32IF-NEXT: flt.s a2, fa5, fs0
876 ; RV32IF-NEXT: neg a2, a2
877 ; RV32IF-NEXT: or a0, a2, a0
878 ; RV32IF-NEXT: and a1, s0, a1
879 ; RV32IF-NEXT: or a1, a2, a1
880 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
881 ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
882 ; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
883 ; RV32IF-NEXT: addi sp, sp, 16
884 ; RV32IF-NEXT: ret
885 ;
886 ; RV64IF-LABEL: fcvt_lu_s_sat:
887 ; RV64IF: # %bb.0: # %start
888 ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
889 ; RV64IF-NEXT: feq.s a1, fa0, fa0
890 ; RV64IF-NEXT: seqz a1, a1
891 ; RV64IF-NEXT: addi a1, a1, -1
892 ; RV64IF-NEXT: and a0, a1, a0
893 ; RV64IF-NEXT: ret
894 ;
895 ; RV32IZFINX-LABEL: fcvt_lu_s_sat:
896 ; RV32IZFINX: # %bb.0: # %start
897 ; RV32IZFINX-NEXT: addi sp, sp, -16
898 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
899 ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
900 ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
901 ; RV32IZFINX-NEXT: mv s0, a0
902 ; RV32IZFINX-NEXT: fle.s a0, zero, a0
903 ; RV32IZFINX-NEXT: neg s1, a0
904 ; RV32IZFINX-NEXT: mv a0, s0
905 ; RV32IZFINX-NEXT: call __fixunssfdi
906 ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0)
907 ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2)
908 ; RV32IZFINX-NEXT: and a0, s1, a0
909 ; RV32IZFINX-NEXT: flt.s a2, a2, s0
910 ; RV32IZFINX-NEXT: neg a2, a2
911 ; RV32IZFINX-NEXT: or a0, a2, a0
912 ; RV32IZFINX-NEXT: and a1, s1, a1
913 ; RV32IZFINX-NEXT: or a1, a2, a1
914 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
915 ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
916 ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
917 ; RV32IZFINX-NEXT: addi sp, sp, 16
918 ; RV32IZFINX-NEXT: ret
919 ;
920 ; RV64IZFINX-LABEL: fcvt_lu_s_sat:
921 ; RV64IZFINX: # %bb.0: # %start
922 ; RV64IZFINX-NEXT: fcvt.lu.s a1, a0, rtz
923 ; RV64IZFINX-NEXT: feq.s a0, a0, a0
924 ; RV64IZFINX-NEXT: seqz a0, a0
925 ; RV64IZFINX-NEXT: addi a0, a0, -1
926 ; RV64IZFINX-NEXT: and a0, a0, a1
927 ; RV64IZFINX-NEXT: ret
928 ;
929 ; RV32I-LABEL: fcvt_lu_s_sat:
930 ; RV32I: # %bb.0: # %start
931 ; RV32I-NEXT: addi sp, sp, -32
932 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
933 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
934 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
935 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
936 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
937 ; RV32I-NEXT: mv s0, a0
938 ; RV32I-NEXT: li a1, 0
939 ; RV32I-NEXT: call __gesf2
940 ; RV32I-NEXT: slti a0, a0, 0
941 ; RV32I-NEXT: addi s2, a0, -1
942 ; RV32I-NEXT: mv a0, s0
943 ; RV32I-NEXT: call __fixunssfdi
944 ; RV32I-NEXT: mv s1, a1
945 ; RV32I-NEXT: and s3, s2, a0
946 ; RV32I-NEXT: lui a1, 391168
947 ; RV32I-NEXT: addi a1, a1, -1
948 ; RV32I-NEXT: mv a0, s0
949 ; RV32I-NEXT: call __gtsf2
950 ; RV32I-NEXT: sgtz a0, a0
951 ; RV32I-NEXT: neg a1, a0
952 ; RV32I-NEXT: or a0, a1, s3
953 ; RV32I-NEXT: and a2, s2, s1
954 ; RV32I-NEXT: or a1, a1, a2
955 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
956 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
957 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
958 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
959 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
960 ; RV32I-NEXT: addi sp, sp, 32
961 ; RV32I-NEXT: ret
962 ;
963 ; RV64I-LABEL: fcvt_lu_s_sat:
964 ; RV64I: # %bb.0: # %start
965 ; RV64I-NEXT: addi sp, sp, -32
966 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
967 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
968 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
969 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
970 ; RV64I-NEXT: mv s0, a0
971 ; RV64I-NEXT: lui a1, 391168
972 ; RV64I-NEXT: addiw a1, a1, -1
973 ; RV64I-NEXT: call __gtsf2
974 ; RV64I-NEXT: sgtz a0, a0
975 ; RV64I-NEXT: neg s1, a0
976 ; RV64I-NEXT: mv a0, s0
977 ; RV64I-NEXT: li a1, 0
978 ; RV64I-NEXT: call __gesf2
979 ; RV64I-NEXT: slti a0, a0, 0
980 ; RV64I-NEXT: addi s2, a0, -1
981 ; RV64I-NEXT: mv a0, s0
982 ; RV64I-NEXT: call __fixunssfdi
983 ; RV64I-NEXT: and a0, s2, a0
984 ; RV64I-NEXT: or a0, s1, a0
985 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
986 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
987 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
988 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
989 ; RV64I-NEXT: addi sp, sp, 32
990 ; RV64I-NEXT: ret
991 start:
992 %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
993 ret i64 %0
994 }
995 declare i64 @llvm.fptoui.sat.i64.f32(float)
997 define float @fcvt_s_l(i64 %a) nounwind {
998 ; RV32IF-LABEL: fcvt_s_l:
999 ; RV32IF: # %bb.0:
1000 ; RV32IF-NEXT: addi sp, sp, -16
1001 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1002 ; RV32IF-NEXT: call __floatdisf
1003 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1004 ; RV32IF-NEXT: addi sp, sp, 16
1005 ; RV32IF-NEXT: ret
1006 ;
1007 ; RV64IF-LABEL: fcvt_s_l:
1008 ; RV64IF: # %bb.0:
1009 ; RV64IF-NEXT: fcvt.s.l fa0, a0
1010 ; RV64IF-NEXT: ret
1011 ;
1012 ; RV32IZFINX-LABEL: fcvt_s_l:
1013 ; RV32IZFINX: # %bb.0:
1014 ; RV32IZFINX-NEXT: addi sp, sp, -16
1015 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1016 ; RV32IZFINX-NEXT: call __floatdisf
1017 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1018 ; RV32IZFINX-NEXT: addi sp, sp, 16
1019 ; RV32IZFINX-NEXT: ret
1020 ;
1021 ; RV64IZFINX-LABEL: fcvt_s_l:
1022 ; RV64IZFINX: # %bb.0:
1023 ; RV64IZFINX-NEXT: fcvt.s.l a0, a0
1024 ; RV64IZFINX-NEXT: ret
1025 ;
1026 ; RV32I-LABEL: fcvt_s_l:
1027 ; RV32I: # %bb.0:
1028 ; RV32I-NEXT: addi sp, sp, -16
1029 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1030 ; RV32I-NEXT: call __floatdisf
1031 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1032 ; RV32I-NEXT: addi sp, sp, 16
1033 ; RV32I-NEXT: ret
1034 ;
1035 ; RV64I-LABEL: fcvt_s_l:
1036 ; RV64I: # %bb.0:
1037 ; RV64I-NEXT: addi sp, sp, -16
1038 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1039 ; RV64I-NEXT: call __floatdisf
1040 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1041 ; RV64I-NEXT: addi sp, sp, 16
1042 ; RV64I-NEXT: ret
1043 %1 = sitofp i64 %a to float
1044 ret float %1
1045 }
1047 define float @fcvt_s_lu(i64 %a) nounwind {
1048 ; RV32IF-LABEL: fcvt_s_lu:
1049 ; RV32IF: # %bb.0:
1050 ; RV32IF-NEXT: addi sp, sp, -16
1051 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1052 ; RV32IF-NEXT: call __floatundisf
1053 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1054 ; RV32IF-NEXT: addi sp, sp, 16
1055 ; RV32IF-NEXT: ret
1056 ;
1057 ; RV64IF-LABEL: fcvt_s_lu:
1058 ; RV64IF: # %bb.0:
1059 ; RV64IF-NEXT: fcvt.s.lu fa0, a0
1060 ; RV64IF-NEXT: ret
1061 ;
1062 ; RV32IZFINX-LABEL: fcvt_s_lu:
1063 ; RV32IZFINX: # %bb.0:
1064 ; RV32IZFINX-NEXT: addi sp, sp, -16
1065 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1066 ; RV32IZFINX-NEXT: call __floatundisf
1067 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1068 ; RV32IZFINX-NEXT: addi sp, sp, 16
1069 ; RV32IZFINX-NEXT: ret
1070 ;
1071 ; RV64IZFINX-LABEL: fcvt_s_lu:
1072 ; RV64IZFINX: # %bb.0:
1073 ; RV64IZFINX-NEXT: fcvt.s.lu a0, a0
1074 ; RV64IZFINX-NEXT: ret
1075 ;
1076 ; RV32I-LABEL: fcvt_s_lu:
1077 ; RV32I: # %bb.0:
1078 ; RV32I-NEXT: addi sp, sp, -16
1079 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1080 ; RV32I-NEXT: call __floatundisf
1081 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1082 ; RV32I-NEXT: addi sp, sp, 16
1083 ; RV32I-NEXT: ret
1084 ;
1085 ; RV64I-LABEL: fcvt_s_lu:
1086 ; RV64I: # %bb.0:
1087 ; RV64I-NEXT: addi sp, sp, -16
1088 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1089 ; RV64I-NEXT: call __floatundisf
1090 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1091 ; RV64I-NEXT: addi sp, sp, 16
1092 ; RV64I-NEXT: ret
1093 %1 = uitofp i64 %a to float
1094 ret float %1
1095 }
1097 define float @fcvt_s_w_i8(i8 signext %a) nounwind {
1098 ; CHECKIF-LABEL: fcvt_s_w_i8:
1099 ; CHECKIF: # %bb.0:
1100 ; CHECKIF-NEXT: fcvt.s.w fa0, a0
1101 ; CHECKIF-NEXT: ret
1102 ;
1103 ; CHECKIZFINX-LABEL: fcvt_s_w_i8:
1104 ; CHECKIZFINX: # %bb.0:
1105 ; CHECKIZFINX-NEXT: fcvt.s.w a0, a0
1106 ; CHECKIZFINX-NEXT: ret
1107 ;
1108 ; RV32I-LABEL: fcvt_s_w_i8:
1109 ; RV32I: # %bb.0:
1110 ; RV32I-NEXT: addi sp, sp, -16
1111 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1112 ; RV32I-NEXT: call __floatsisf
1113 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1114 ; RV32I-NEXT: addi sp, sp, 16
1115 ; RV32I-NEXT: ret
1116 ;
1117 ; RV64I-LABEL: fcvt_s_w_i8:
1118 ; RV64I: # %bb.0:
1119 ; RV64I-NEXT: addi sp, sp, -16
1120 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1121 ; RV64I-NEXT: call __floatsisf
1122 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1123 ; RV64I-NEXT: addi sp, sp, 16
1124 ; RV64I-NEXT: ret
1125 %1 = sitofp i8 %a to float
1126 ret float %1
1127 }
1129 define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
1130 ; CHECKIF-LABEL: fcvt_s_wu_i8:
1131 ; CHECKIF: # %bb.0:
1132 ; CHECKIF-NEXT: fcvt.s.wu fa0, a0
1133 ; CHECKIF-NEXT: ret
1134 ;
1135 ; CHECKIZFINX-LABEL: fcvt_s_wu_i8:
1136 ; CHECKIZFINX: # %bb.0:
1137 ; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0
1138 ; CHECKIZFINX-NEXT: ret
1139 ;
1140 ; RV32I-LABEL: fcvt_s_wu_i8:
1141 ; RV32I: # %bb.0:
1142 ; RV32I-NEXT: addi sp, sp, -16
1143 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1144 ; RV32I-NEXT: call __floatunsisf
1145 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1146 ; RV32I-NEXT: addi sp, sp, 16
1147 ; RV32I-NEXT: ret
1148 ;
1149 ; RV64I-LABEL: fcvt_s_wu_i8:
1150 ; RV64I: # %bb.0:
1151 ; RV64I-NEXT: addi sp, sp, -16
1152 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1153 ; RV64I-NEXT: call __floatunsisf
1154 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1155 ; RV64I-NEXT: addi sp, sp, 16
1156 ; RV64I-NEXT: ret
1157 %1 = uitofp i8 %a to float
1158 ret float %1
1159 }
1161 define float @fcvt_s_w_i16(i16 signext %a) nounwind {
1162 ; CHECKIF-LABEL: fcvt_s_w_i16:
1163 ; CHECKIF: # %bb.0:
1164 ; CHECKIF-NEXT: fcvt.s.w fa0, a0
1165 ; CHECKIF-NEXT: ret
1166 ;
1167 ; CHECKIZFINX-LABEL: fcvt_s_w_i16:
1168 ; CHECKIZFINX: # %bb.0:
1169 ; CHECKIZFINX-NEXT: fcvt.s.w a0, a0
1170 ; CHECKIZFINX-NEXT: ret
1171 ;
1172 ; RV32I-LABEL: fcvt_s_w_i16:
1173 ; RV32I: # %bb.0:
1174 ; RV32I-NEXT: addi sp, sp, -16
1175 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1176 ; RV32I-NEXT: call __floatsisf
1177 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1178 ; RV32I-NEXT: addi sp, sp, 16
1179 ; RV32I-NEXT: ret
1180 ;
1181 ; RV64I-LABEL: fcvt_s_w_i16:
1182 ; RV64I: # %bb.0:
1183 ; RV64I-NEXT: addi sp, sp, -16
1184 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1185 ; RV64I-NEXT: call __floatsisf
1186 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1187 ; RV64I-NEXT: addi sp, sp, 16
1188 ; RV64I-NEXT: ret
1189 %1 = sitofp i16 %a to float
1190 ret float %1
1191 }
1193 define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
1194 ; CHECKIF-LABEL: fcvt_s_wu_i16:
1195 ; CHECKIF: # %bb.0:
1196 ; CHECKIF-NEXT: fcvt.s.wu fa0, a0
1197 ; CHECKIF-NEXT: ret
1198 ;
1199 ; CHECKIZFINX-LABEL: fcvt_s_wu_i16:
1200 ; CHECKIZFINX: # %bb.0:
1201 ; CHECKIZFINX-NEXT: fcvt.s.wu a0, a0
1202 ; CHECKIZFINX-NEXT: ret
1203 ;
1204 ; RV32I-LABEL: fcvt_s_wu_i16:
1205 ; RV32I: # %bb.0:
1206 ; RV32I-NEXT: addi sp, sp, -16
1207 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1208 ; RV32I-NEXT: call __floatunsisf
1209 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1210 ; RV32I-NEXT: addi sp, sp, 16
1211 ; RV32I-NEXT: ret
1212 ;
1213 ; RV64I-LABEL: fcvt_s_wu_i16:
1214 ; RV64I: # %bb.0:
1215 ; RV64I-NEXT: addi sp, sp, -16
1216 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1217 ; RV64I-NEXT: call __floatunsisf
1218 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1219 ; RV64I-NEXT: addi sp, sp, 16
1220 ; RV64I-NEXT: ret
1221 %1 = uitofp i16 %a to float
1222 ret float %1
1223 }
1225 ; Make sure we select W version of addi on RV64.
1226 define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
1227 ; RV32IF-LABEL: fcvt_s_w_demanded_bits:
1228 ; RV32IF: # %bb.0:
1229 ; RV32IF-NEXT: addi a0, a0, 1
1230 ; RV32IF-NEXT: fcvt.s.w fa5, a0
1231 ; RV32IF-NEXT: fsw fa5, 0(a1)
1232 ; RV32IF-NEXT: ret
1233 ;
1234 ; RV64IF-LABEL: fcvt_s_w_demanded_bits:
1235 ; RV64IF: # %bb.0:
1236 ; RV64IF-NEXT: addiw a0, a0, 1
1237 ; RV64IF-NEXT: fcvt.s.w fa5, a0
1238 ; RV64IF-NEXT: fsw fa5, 0(a1)
1239 ; RV64IF-NEXT: ret
1240 ;
1241 ; RV32IZFINX-LABEL: fcvt_s_w_demanded_bits:
1242 ; RV32IZFINX: # %bb.0:
1243 ; RV32IZFINX-NEXT: addi a0, a0, 1
1244 ; RV32IZFINX-NEXT: fcvt.s.w a2, a0
1245 ; RV32IZFINX-NEXT: sw a2, 0(a1)
1246 ; RV32IZFINX-NEXT: ret
1247 ;
1248 ; RV64IZFINX-LABEL: fcvt_s_w_demanded_bits:
1249 ; RV64IZFINX: # %bb.0:
1250 ; RV64IZFINX-NEXT: addiw a2, a0, 1
1251 ; RV64IZFINX-NEXT: addi a0, a0, 1
1252 ; RV64IZFINX-NEXT: fcvt.s.w a0, a0
1253 ; RV64IZFINX-NEXT: sw a0, 0(a1)
1254 ; RV64IZFINX-NEXT: mv a0, a2
1255 ; RV64IZFINX-NEXT: ret
1256 ;
1257 ; RV32I-LABEL: fcvt_s_w_demanded_bits:
1258 ; RV32I: # %bb.0:
1259 ; RV32I-NEXT: addi sp, sp, -16
1260 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1261 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1262 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1263 ; RV32I-NEXT: mv s0, a1
1264 ; RV32I-NEXT: addi s1, a0, 1
1265 ; RV32I-NEXT: mv a0, s1
1266 ; RV32I-NEXT: call __floatsisf
1267 ; RV32I-NEXT: sw a0, 0(s0)
1268 ; RV32I-NEXT: mv a0, s1
1269 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1270 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1271 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1272 ; RV32I-NEXT: addi sp, sp, 16
1273 ; RV32I-NEXT: ret
1274 ;
1275 ; RV64I-LABEL: fcvt_s_w_demanded_bits:
1276 ; RV64I: # %bb.0:
1277 ; RV64I-NEXT: addi sp, sp, -32
1278 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1279 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1280 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1281 ; RV64I-NEXT: mv s0, a1
1282 ; RV64I-NEXT: addiw s1, a0, 1
1283 ; RV64I-NEXT: mv a0, s1
1284 ; RV64I-NEXT: call __floatsisf
1285 ; RV64I-NEXT: sw a0, 0(s0)
1286 ; RV64I-NEXT: mv a0, s1
1287 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1288 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1289 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1290 ; RV64I-NEXT: addi sp, sp, 32
1291 ; RV64I-NEXT: ret
1292 %3 = add i32 %0, 1
1293 %4 = sitofp i32 %3 to float
1294 store float %4, ptr %1, align 4
1295 ret i32 %3
1296 }
1298 ; Make sure we select W version of addi on RV64.
1299 define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
1300 ; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
1301 ; RV32IF: # %bb.0:
1302 ; RV32IF-NEXT: addi a0, a0, 1
1303 ; RV32IF-NEXT: fcvt.s.wu fa5, a0
1304 ; RV32IF-NEXT: fsw fa5, 0(a1)
1305 ; RV32IF-NEXT: ret
1306 ;
1307 ; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
1308 ; RV64IF: # %bb.0:
1309 ; RV64IF-NEXT: addiw a0, a0, 1
1310 ; RV64IF-NEXT: fcvt.s.wu fa5, a0
1311 ; RV64IF-NEXT: fsw fa5, 0(a1)
1312 ; RV64IF-NEXT: ret
1313 ;
1314 ; RV32IZFINX-LABEL: fcvt_s_wu_demanded_bits:
1315 ; RV32IZFINX: # %bb.0:
1316 ; RV32IZFINX-NEXT: addi a0, a0, 1
1317 ; RV32IZFINX-NEXT: fcvt.s.wu a2, a0
1318 ; RV32IZFINX-NEXT: sw a2, 0(a1)
1319 ; RV32IZFINX-NEXT: ret
1320 ;
1321 ; RV64IZFINX-LABEL: fcvt_s_wu_demanded_bits:
1322 ; RV64IZFINX: # %bb.0:
1323 ; RV64IZFINX-NEXT: addiw a0, a0, 1
1324 ; RV64IZFINX-NEXT: fcvt.s.wu a2, a0
1325 ; RV64IZFINX-NEXT: sw a2, 0(a1)
1326 ; RV64IZFINX-NEXT: ret
1327 ;
1328 ; RV32I-LABEL: fcvt_s_wu_demanded_bits:
1329 ; RV32I: # %bb.0:
1330 ; RV32I-NEXT: addi sp, sp, -16
1331 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1332 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1333 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1334 ; RV32I-NEXT: mv s0, a1
1335 ; RV32I-NEXT: addi s1, a0, 1
1336 ; RV32I-NEXT: mv a0, s1
1337 ; RV32I-NEXT: call __floatunsisf
1338 ; RV32I-NEXT: sw a0, 0(s0)
1339 ; RV32I-NEXT: mv a0, s1
1340 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1341 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1342 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1343 ; RV32I-NEXT: addi sp, sp, 16
1344 ; RV32I-NEXT: ret
1345 ;
1346 ; RV64I-LABEL: fcvt_s_wu_demanded_bits:
1347 ; RV64I: # %bb.0:
1348 ; RV64I-NEXT: addi sp, sp, -32
1349 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1350 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1351 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1352 ; RV64I-NEXT: mv s0, a1
1353 ; RV64I-NEXT: addiw s1, a0, 1
1354 ; RV64I-NEXT: mv a0, s1
1355 ; RV64I-NEXT: call __floatunsisf
1356 ; RV64I-NEXT: sw a0, 0(s0)
1357 ; RV64I-NEXT: mv a0, s1
1358 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1359 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1360 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1361 ; RV64I-NEXT: addi sp, sp, 32
1362 ; RV64I-NEXT: ret
1363 %3 = add i32 %0, 1
1364 %4 = uitofp i32 %3 to float
1365 store float %4, ptr %1, align 4
1366 ret i32 %3
1367 }
1369 define signext i16 @fcvt_w_s_i16(float %a) nounwind {
1370 ; RV32IF-LABEL: fcvt_w_s_i16:
1371 ; RV32IF: # %bb.0:
1372 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
1373 ; RV32IF-NEXT: ret
1374 ;
1375 ; RV64IF-LABEL: fcvt_w_s_i16:
1376 ; RV64IF: # %bb.0:
1377 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
1378 ; RV64IF-NEXT: ret
1379 ;
1380 ; RV32IZFINX-LABEL: fcvt_w_s_i16:
1381 ; RV32IZFINX: # %bb.0:
1382 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz
1383 ; RV32IZFINX-NEXT: ret
1384 ;
1385 ; RV64IZFINX-LABEL: fcvt_w_s_i16:
1386 ; RV64IZFINX: # %bb.0:
1387 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
1388 ; RV64IZFINX-NEXT: ret
1389 ;
1390 ; RV32I-LABEL: fcvt_w_s_i16:
1391 ; RV32I: # %bb.0:
1392 ; RV32I-NEXT: addi sp, sp, -16
1393 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1394 ; RV32I-NEXT: call __fixsfsi
1395 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1396 ; RV32I-NEXT: addi sp, sp, 16
1397 ; RV32I-NEXT: ret
1398 ;
1399 ; RV64I-LABEL: fcvt_w_s_i16:
1400 ; RV64I: # %bb.0:
1401 ; RV64I-NEXT: addi sp, sp, -16
1402 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1403 ; RV64I-NEXT: call __fixsfdi
1404 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1405 ; RV64I-NEXT: addi sp, sp, 16
1406 ; RV64I-NEXT: ret
1407 %1 = fptosi float %a to i16
1408 ret i16 %1
1409 }
1411 define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
1412 ; RV32IF-LABEL: fcvt_w_s_sat_i16:
1413 ; RV32IF: # %bb.0: # %start
1414 ; RV32IF-NEXT: feq.s a0, fa0, fa0
1415 ; RV32IF-NEXT: neg a0, a0
1416 ; RV32IF-NEXT: lui a1, %hi(.LCPI24_0)
1417 ; RV32IF-NEXT: flw fa5, %lo(.LCPI24_0)(a1)
1418 ; RV32IF-NEXT: lui a1, 815104
1419 ; RV32IF-NEXT: fmv.w.x fa4, a1
1420 ; RV32IF-NEXT: fmax.s fa4, fa0, fa4
1421 ; RV32IF-NEXT: fmin.s fa5, fa4, fa5
1422 ; RV32IF-NEXT: fcvt.w.s a1, fa5, rtz
1423 ; RV32IF-NEXT: and a0, a0, a1
1424 ; RV32IF-NEXT: ret
1425 ;
1426 ; RV64IF-LABEL: fcvt_w_s_sat_i16:
1427 ; RV64IF: # %bb.0: # %start
1428 ; RV64IF-NEXT: feq.s a0, fa0, fa0
1429 ; RV64IF-NEXT: neg a0, a0
1430 ; RV64IF-NEXT: lui a1, %hi(.LCPI24_0)
1431 ; RV64IF-NEXT: flw fa5, %lo(.LCPI24_0)(a1)
1432 ; RV64IF-NEXT: lui a1, 815104
1433 ; RV64IF-NEXT: fmv.w.x fa4, a1
1434 ; RV64IF-NEXT: fmax.s fa4, fa0, fa4
1435 ; RV64IF-NEXT: fmin.s fa5, fa4, fa5
1436 ; RV64IF-NEXT: fcvt.l.s a1, fa5, rtz
1437 ; RV64IF-NEXT: and a0, a0, a1
1438 ; RV64IF-NEXT: ret
1439 ;
1440 ; RV32IZFINX-LABEL: fcvt_w_s_sat_i16:
1441 ; RV32IZFINX: # %bb.0: # %start
1442 ; RV32IZFINX-NEXT: feq.s a1, a0, a0
1443 ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
1444 ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
1445 ; RV32IZFINX-NEXT: neg a1, a1
1446 ; RV32IZFINX-NEXT: lui a3, 815104
1447 ; RV32IZFINX-NEXT: fmax.s a0, a0, a3
1448 ; RV32IZFINX-NEXT: fmin.s a0, a0, a2
1449 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz
1450 ; RV32IZFINX-NEXT: and a0, a1, a0
1451 ; RV32IZFINX-NEXT: ret
1452 ;
1453 ; RV64IZFINX-LABEL: fcvt_w_s_sat_i16:
1454 ; RV64IZFINX: # %bb.0: # %start
1455 ; RV64IZFINX-NEXT: feq.s a1, a0, a0
1456 ; RV64IZFINX-NEXT: lui a2, %hi(.LCPI24_0)
1457 ; RV64IZFINX-NEXT: lw a2, %lo(.LCPI24_0)(a2)
1458 ; RV64IZFINX-NEXT: neg a1, a1
1459 ; RV64IZFINX-NEXT: lui a3, 815104
1460 ; RV64IZFINX-NEXT: fmax.s a0, a0, a3
1461 ; RV64IZFINX-NEXT: fmin.s a0, a0, a2
1462 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
1463 ; RV64IZFINX-NEXT: and a0, a1, a0
1464 ; RV64IZFINX-NEXT: ret
1465 ;
1466 ; RV32I-LABEL: fcvt_w_s_sat_i16:
1467 ; RV32I: # %bb.0: # %start
1468 ; RV32I-NEXT: addi sp, sp, -16
1469 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1470 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1471 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1472 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1473 ; RV32I-NEXT: mv s0, a0
1474 ; RV32I-NEXT: lui a1, 815104
1475 ; RV32I-NEXT: call __gesf2
1476 ; RV32I-NEXT: mv s2, a0
1477 ; RV32I-NEXT: mv a0, s0
1478 ; RV32I-NEXT: call __fixsfsi
1479 ; RV32I-NEXT: mv s1, a0
1480 ; RV32I-NEXT: bgez s2, .LBB24_2
1481 ; RV32I-NEXT: # %bb.1: # %start
1482 ; RV32I-NEXT: lui s1, 1048568
1483 ; RV32I-NEXT: .LBB24_2: # %start
1484 ; RV32I-NEXT: lui a0, 290816
1485 ; RV32I-NEXT: addi a1, a0, -512
1486 ; RV32I-NEXT: mv a0, s0
1487 ; RV32I-NEXT: call __gtsf2
1488 ; RV32I-NEXT: blez a0, .LBB24_4
1489 ; RV32I-NEXT: # %bb.3: # %start
1490 ; RV32I-NEXT: lui s1, 8
1491 ; RV32I-NEXT: addi s1, s1, -1
1492 ; RV32I-NEXT: .LBB24_4: # %start
1493 ; RV32I-NEXT: mv a0, s0
1494 ; RV32I-NEXT: mv a1, s0
1495 ; RV32I-NEXT: call __unordsf2
1496 ; RV32I-NEXT: snez a0, a0
1497 ; RV32I-NEXT: addi a0, a0, -1
1498 ; RV32I-NEXT: and a0, a0, s1
1499 ; RV32I-NEXT: slli a0, a0, 16
1500 ; RV32I-NEXT: srai a0, a0, 16
1501 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1502 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1503 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1504 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1505 ; RV32I-NEXT: addi sp, sp, 16
1506 ; RV32I-NEXT: ret
1507 ;
1508 ; RV64I-LABEL: fcvt_w_s_sat_i16:
1509 ; RV64I: # %bb.0: # %start
1510 ; RV64I-NEXT: addi sp, sp, -32
1511 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1512 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1513 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1514 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1515 ; RV64I-NEXT: mv s0, a0
1516 ; RV64I-NEXT: lui a1, 815104
1517 ; RV64I-NEXT: call __gesf2
1518 ; RV64I-NEXT: mv s2, a0
1519 ; RV64I-NEXT: mv a0, s0
1520 ; RV64I-NEXT: call __fixsfdi
1521 ; RV64I-NEXT: mv s1, a0
1522 ; RV64I-NEXT: bgez s2, .LBB24_2
1523 ; RV64I-NEXT: # %bb.1: # %start
1524 ; RV64I-NEXT: lui s1, 1048568
1525 ; RV64I-NEXT: .LBB24_2: # %start
1526 ; RV64I-NEXT: lui a0, 290816
1527 ; RV64I-NEXT: addiw a1, a0, -512
1528 ; RV64I-NEXT: mv a0, s0
1529 ; RV64I-NEXT: call __gtsf2
1530 ; RV64I-NEXT: blez a0, .LBB24_4
1531 ; RV64I-NEXT: # %bb.3: # %start
1532 ; RV64I-NEXT: lui s1, 8
1533 ; RV64I-NEXT: addi s1, s1, -1
1534 ; RV64I-NEXT: .LBB24_4: # %start
1535 ; RV64I-NEXT: mv a0, s0
1536 ; RV64I-NEXT: mv a1, s0
1537 ; RV64I-NEXT: call __unordsf2
1538 ; RV64I-NEXT: snez a0, a0
1539 ; RV64I-NEXT: addi a0, a0, -1
1540 ; RV64I-NEXT: and a0, a0, s1
1541 ; RV64I-NEXT: slli a0, a0, 48
1542 ; RV64I-NEXT: srai a0, a0, 48
1543 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1544 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1545 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1546 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1547 ; RV64I-NEXT: addi sp, sp, 32
1548 ; RV64I-NEXT: ret
1549 start:
1550 %0 = tail call i16 @llvm.fptosi.sat.i16.f32(float %a)
1551 ret i16 %0
1552 }
1553 declare i16 @llvm.fptosi.sat.i16.f32(float)
1555 define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
1556 ; RV32IF-LABEL: fcvt_wu_s_i16:
1557 ; RV32IF: # %bb.0:
1558 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
1559 ; RV32IF-NEXT: ret
1560 ;
1561 ; RV64IF-LABEL: fcvt_wu_s_i16:
1562 ; RV64IF: # %bb.0:
1563 ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
1564 ; RV64IF-NEXT: ret
1565 ;
1566 ; RV32IZFINX-LABEL: fcvt_wu_s_i16:
1567 ; RV32IZFINX: # %bb.0:
1568 ; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz
1569 ; RV32IZFINX-NEXT: ret
1570 ;
1571 ; RV64IZFINX-LABEL: fcvt_wu_s_i16:
1572 ; RV64IZFINX: # %bb.0:
1573 ; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
1574 ; RV64IZFINX-NEXT: ret
1575 ;
1576 ; RV32I-LABEL: fcvt_wu_s_i16:
1577 ; RV32I: # %bb.0:
1578 ; RV32I-NEXT: addi sp, sp, -16
1579 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1580 ; RV32I-NEXT: call __fixunssfsi
1581 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1582 ; RV32I-NEXT: addi sp, sp, 16
1583 ; RV32I-NEXT: ret
1584 ;
1585 ; RV64I-LABEL: fcvt_wu_s_i16:
1586 ; RV64I: # %bb.0:
1587 ; RV64I-NEXT: addi sp, sp, -16
1588 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1589 ; RV64I-NEXT: call __fixunssfdi
1590 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1591 ; RV64I-NEXT: addi sp, sp, 16
1592 ; RV64I-NEXT: ret
1593 %1 = fptoui float %a to i16
1594 ret i16 %1
1595 }
1597 define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
1598 ; RV32IF-LABEL: fcvt_wu_s_sat_i16:
1599 ; RV32IF: # %bb.0: # %start
1600 ; RV32IF-NEXT: lui a0, %hi(.LCPI26_0)
1601 ; RV32IF-NEXT: flw fa5, %lo(.LCPI26_0)(a0)
1602 ; RV32IF-NEXT: fmv.w.x fa4, zero
1603 ; RV32IF-NEXT: fmax.s fa4, fa0, fa4
1604 ; RV32IF-NEXT: fmin.s fa5, fa4, fa5
1605 ; RV32IF-NEXT: fcvt.wu.s a0, fa5, rtz
1606 ; RV32IF-NEXT: ret
1607 ;
1608 ; RV64IF-LABEL: fcvt_wu_s_sat_i16:
1609 ; RV64IF: # %bb.0: # %start
1610 ; RV64IF-NEXT: lui a0, %hi(.LCPI26_0)
1611 ; RV64IF-NEXT: flw fa5, %lo(.LCPI26_0)(a0)
1612 ; RV64IF-NEXT: fmv.w.x fa4, zero
1613 ; RV64IF-NEXT: fmax.s fa4, fa0, fa4
1614 ; RV64IF-NEXT: fmin.s fa5, fa4, fa5
1615 ; RV64IF-NEXT: fcvt.lu.s a0, fa5, rtz
1616 ; RV64IF-NEXT: ret
1617 ;
1618 ; RV32IZFINX-LABEL: fcvt_wu_s_sat_i16:
1619 ; RV32IZFINX: # %bb.0: # %start
1620 ; RV32IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
1621 ; RV32IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
1622 ; RV32IZFINX-NEXT: fmax.s a0, a0, zero
1623 ; RV32IZFINX-NEXT: fmin.s a0, a0, a1
1624 ; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz
1625 ; RV32IZFINX-NEXT: ret
1626 ;
1627 ; RV64IZFINX-LABEL: fcvt_wu_s_sat_i16:
1628 ; RV64IZFINX: # %bb.0: # %start
1629 ; RV64IZFINX-NEXT: lui a1, %hi(.LCPI26_0)
1630 ; RV64IZFINX-NEXT: lw a1, %lo(.LCPI26_0)(a1)
1631 ; RV64IZFINX-NEXT: fmax.s a0, a0, zero
1632 ; RV64IZFINX-NEXT: fmin.s a0, a0, a1
1633 ; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
1634 ; RV64IZFINX-NEXT: ret
1635 ;
1636 ; RV32I-LABEL: fcvt_wu_s_sat_i16:
1637 ; RV32I: # %bb.0: # %start
1638 ; RV32I-NEXT: addi sp, sp, -16
1639 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1640 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1641 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1642 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1643 ; RV32I-NEXT: mv s2, a0
1644 ; RV32I-NEXT: li a1, 0
1645 ; RV32I-NEXT: call __gesf2
1646 ; RV32I-NEXT: mv s0, a0
1647 ; RV32I-NEXT: mv a0, s2
1648 ; RV32I-NEXT: call __fixunssfsi
1649 ; RV32I-NEXT: mv s1, a0
1650 ; RV32I-NEXT: lui a0, 292864
1651 ; RV32I-NEXT: addi a1, a0, -256
1652 ; RV32I-NEXT: mv a0, s2
1653 ; RV32I-NEXT: call __gtsf2
1654 ; RV32I-NEXT: lui a1, 16
1655 ; RV32I-NEXT: addi a1, a1, -1
1656 ; RV32I-NEXT: blez a0, .LBB26_2
1657 ; RV32I-NEXT: # %bb.1: # %start
1658 ; RV32I-NEXT: mv a0, a1
1659 ; RV32I-NEXT: j .LBB26_3
1660 ; RV32I-NEXT: .LBB26_2:
1661 ; RV32I-NEXT: slti a0, s0, 0
1662 ; RV32I-NEXT: addi a0, a0, -1
1663 ; RV32I-NEXT: and a0, a0, s1
1664 ; RV32I-NEXT: .LBB26_3: # %start
1665 ; RV32I-NEXT: and a0, a0, a1
1666 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1667 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1668 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1669 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1670 ; RV32I-NEXT: addi sp, sp, 16
1671 ; RV32I-NEXT: ret
1672 ;
1673 ; RV64I-LABEL: fcvt_wu_s_sat_i16:
1674 ; RV64I: # %bb.0: # %start
1675 ; RV64I-NEXT: addi sp, sp, -32
1676 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1677 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1678 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1679 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1680 ; RV64I-NEXT: mv s2, a0
1681 ; RV64I-NEXT: li a1, 0
1682 ; RV64I-NEXT: call __gesf2
1683 ; RV64I-NEXT: mv s0, a0
1684 ; RV64I-NEXT: mv a0, s2
1685 ; RV64I-NEXT: call __fixunssfdi
1686 ; RV64I-NEXT: mv s1, a0
1687 ; RV64I-NEXT: lui a0, 292864
1688 ; RV64I-NEXT: addiw a1, a0, -256
1689 ; RV64I-NEXT: mv a0, s2
1690 ; RV64I-NEXT: call __gtsf2
1691 ; RV64I-NEXT: lui a1, 16
1692 ; RV64I-NEXT: addiw a1, a1, -1
1693 ; RV64I-NEXT: blez a0, .LBB26_2
1694 ; RV64I-NEXT: # %bb.1: # %start
1695 ; RV64I-NEXT: mv a0, a1
1696 ; RV64I-NEXT: j .LBB26_3
1697 ; RV64I-NEXT: .LBB26_2:
1698 ; RV64I-NEXT: slti a0, s0, 0
1699 ; RV64I-NEXT: addi a0, a0, -1
1700 ; RV64I-NEXT: and a0, a0, s1
1701 ; RV64I-NEXT: .LBB26_3: # %start
1702 ; RV64I-NEXT: and a0, a0, a1
1703 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1704 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1705 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1706 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1707 ; RV64I-NEXT: addi sp, sp, 32
1708 ; RV64I-NEXT: ret
1709 start:
1710 %0 = tail call i16 @llvm.fptoui.sat.i16.f32(float %a)
1711 ret i16 %0
1712 }
1713 declare i16 @llvm.fptoui.sat.i16.f32(float)
1715 define signext i8 @fcvt_w_s_i8(float %a) nounwind {
1716 ; RV32IF-LABEL: fcvt_w_s_i8:
1717 ; RV32IF: # %bb.0:
1718 ; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
1719 ; RV32IF-NEXT: ret
1720 ;
1721 ; RV64IF-LABEL: fcvt_w_s_i8:
1722 ; RV64IF: # %bb.0:
1723 ; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
1724 ; RV64IF-NEXT: ret
1725 ;
1726 ; RV32IZFINX-LABEL: fcvt_w_s_i8:
1727 ; RV32IZFINX: # %bb.0:
1728 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz
1729 ; RV32IZFINX-NEXT: ret
1730 ;
1731 ; RV64IZFINX-LABEL: fcvt_w_s_i8:
1732 ; RV64IZFINX: # %bb.0:
1733 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
1734 ; RV64IZFINX-NEXT: ret
1735 ;
1736 ; RV32I-LABEL: fcvt_w_s_i8:
1737 ; RV32I: # %bb.0:
1738 ; RV32I-NEXT: addi sp, sp, -16
1739 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1740 ; RV32I-NEXT: call __fixsfsi
1741 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1742 ; RV32I-NEXT: addi sp, sp, 16
1743 ; RV32I-NEXT: ret
1744 ;
1745 ; RV64I-LABEL: fcvt_w_s_i8:
1746 ; RV64I: # %bb.0:
1747 ; RV64I-NEXT: addi sp, sp, -16
1748 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1749 ; RV64I-NEXT: call __fixsfdi
1750 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1751 ; RV64I-NEXT: addi sp, sp, 16
1752 ; RV64I-NEXT: ret
1753 %1 = fptosi float %a to i8
1754 ret i8 %1
1755 }
1757 define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
1758 ; RV32IF-LABEL: fcvt_w_s_sat_i8:
1759 ; RV32IF: # %bb.0: # %start
1760 ; RV32IF-NEXT: feq.s a0, fa0, fa0
1761 ; RV32IF-NEXT: neg a0, a0
1762 ; RV32IF-NEXT: lui a1, 798720
1763 ; RV32IF-NEXT: fmv.w.x fa5, a1
1764 ; RV32IF-NEXT: fmax.s fa5, fa0, fa5
1765 ; RV32IF-NEXT: lui a1, 274400
1766 ; RV32IF-NEXT: fmv.w.x fa4, a1
1767 ; RV32IF-NEXT: fmin.s fa5, fa5, fa4
1768 ; RV32IF-NEXT: fcvt.w.s a1, fa5, rtz
1769 ; RV32IF-NEXT: and a0, a0, a1
1770 ; RV32IF-NEXT: ret
1771 ;
1772 ; RV64IF-LABEL: fcvt_w_s_sat_i8:
1773 ; RV64IF: # %bb.0: # %start
1774 ; RV64IF-NEXT: feq.s a0, fa0, fa0
1775 ; RV64IF-NEXT: neg a0, a0
1776 ; RV64IF-NEXT: lui a1, 798720
1777 ; RV64IF-NEXT: fmv.w.x fa5, a1
1778 ; RV64IF-NEXT: fmax.s fa5, fa0, fa5
1779 ; RV64IF-NEXT: lui a1, 274400
1780 ; RV64IF-NEXT: fmv.w.x fa4, a1
1781 ; RV64IF-NEXT: fmin.s fa5, fa5, fa4
1782 ; RV64IF-NEXT: fcvt.l.s a1, fa5, rtz
1783 ; RV64IF-NEXT: and a0, a0, a1
1784 ; RV64IF-NEXT: ret
1785 ;
1786 ; RV32IZFINX-LABEL: fcvt_w_s_sat_i8:
1787 ; RV32IZFINX: # %bb.0: # %start
1788 ; RV32IZFINX-NEXT: feq.s a1, a0, a0
1789 ; RV32IZFINX-NEXT: neg a1, a1
1790 ; RV32IZFINX-NEXT: lui a2, 798720
1791 ; RV32IZFINX-NEXT: fmax.s a0, a0, a2
1792 ; RV32IZFINX-NEXT: lui a2, 274400
1793 ; RV32IZFINX-NEXT: fmin.s a0, a0, a2
1794 ; RV32IZFINX-NEXT: fcvt.w.s a0, a0, rtz
1795 ; RV32IZFINX-NEXT: and a0, a1, a0
1796 ; RV32IZFINX-NEXT: ret
1797 ;
1798 ; RV64IZFINX-LABEL: fcvt_w_s_sat_i8:
1799 ; RV64IZFINX: # %bb.0: # %start
1800 ; RV64IZFINX-NEXT: feq.s a1, a0, a0
1801 ; RV64IZFINX-NEXT: neg a1, a1
1802 ; RV64IZFINX-NEXT: lui a2, 798720
1803 ; RV64IZFINX-NEXT: fmax.s a0, a0, a2
1804 ; RV64IZFINX-NEXT: lui a2, 274400
1805 ; RV64IZFINX-NEXT: fmin.s a0, a0, a2
1806 ; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rtz
1807 ; RV64IZFINX-NEXT: and a0, a1, a0
1808 ; RV64IZFINX-NEXT: ret
1809 ;
1810 ; RV32I-LABEL: fcvt_w_s_sat_i8:
1811 ; RV32I: # %bb.0: # %start
1812 ; RV32I-NEXT: addi sp, sp, -16
1813 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1814 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1815 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1816 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1817 ; RV32I-NEXT: mv s0, a0
1818 ; RV32I-NEXT: lui a1, 798720
1819 ; RV32I-NEXT: call __gesf2
1820 ; RV32I-NEXT: mv s2, a0
1821 ; RV32I-NEXT: mv a0, s0
1822 ; RV32I-NEXT: call __fixsfsi
1823 ; RV32I-NEXT: mv s1, a0
1824 ; RV32I-NEXT: bgez s2, .LBB28_2
1825 ; RV32I-NEXT: # %bb.1: # %start
1826 ; RV32I-NEXT: li s1, -128
1827 ; RV32I-NEXT: .LBB28_2: # %start
1828 ; RV32I-NEXT: lui a1, 274400
1829 ; RV32I-NEXT: mv a0, s0
1830 ; RV32I-NEXT: call __gtsf2
1831 ; RV32I-NEXT: blez a0, .LBB28_4
1832 ; RV32I-NEXT: # %bb.3: # %start
1833 ; RV32I-NEXT: li s1, 127
1834 ; RV32I-NEXT: .LBB28_4: # %start
1835 ; RV32I-NEXT: mv a0, s0
1836 ; RV32I-NEXT: mv a1, s0
1837 ; RV32I-NEXT: call __unordsf2
1838 ; RV32I-NEXT: snez a0, a0
1839 ; RV32I-NEXT: addi a0, a0, -1
1840 ; RV32I-NEXT: and a0, a0, s1
1841 ; RV32I-NEXT: slli a0, a0, 24
1842 ; RV32I-NEXT: srai a0, a0, 24
1843 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1844 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1845 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1846 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1847 ; RV32I-NEXT: addi sp, sp, 16
1848 ; RV32I-NEXT: ret
1849 ;
1850 ; RV64I-LABEL: fcvt_w_s_sat_i8:
1851 ; RV64I: # %bb.0: # %start
1852 ; RV64I-NEXT: addi sp, sp, -32
1853 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1854 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1855 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1856 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1857 ; RV64I-NEXT: mv s0, a0
1858 ; RV64I-NEXT: lui a1, 798720
1859 ; RV64I-NEXT: call __gesf2
1860 ; RV64I-NEXT: mv s2, a0
1861 ; RV64I-NEXT: mv a0, s0
1862 ; RV64I-NEXT: call __fixsfdi
1863 ; RV64I-NEXT: mv s1, a0
1864 ; RV64I-NEXT: bgez s2, .LBB28_2
1865 ; RV64I-NEXT: # %bb.1: # %start
1866 ; RV64I-NEXT: li s1, -128
1867 ; RV64I-NEXT: .LBB28_2: # %start
1868 ; RV64I-NEXT: lui a1, 274400
1869 ; RV64I-NEXT: mv a0, s0
1870 ; RV64I-NEXT: call __gtsf2
1871 ; RV64I-NEXT: blez a0, .LBB28_4
1872 ; RV64I-NEXT: # %bb.3: # %start
1873 ; RV64I-NEXT: li s1, 127
1874 ; RV64I-NEXT: .LBB28_4: # %start
1875 ; RV64I-NEXT: mv a0, s0
1876 ; RV64I-NEXT: mv a1, s0
1877 ; RV64I-NEXT: call __unordsf2
1878 ; RV64I-NEXT: snez a0, a0
1879 ; RV64I-NEXT: addi a0, a0, -1
1880 ; RV64I-NEXT: and a0, a0, s1
1881 ; RV64I-NEXT: slli a0, a0, 56
1882 ; RV64I-NEXT: srai a0, a0, 56
1883 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1884 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1885 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1886 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1887 ; RV64I-NEXT: addi sp, sp, 32
1888 ; RV64I-NEXT: ret
1889 start:
1890 %0 = tail call i8 @llvm.fptosi.sat.i8.f32(float %a)
1891 ret i8 %0
1892 }
1893 declare i8 @llvm.fptosi.sat.i8.f32(float)
1895 define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
1896 ; RV32IF-LABEL: fcvt_wu_s_i8:
1897 ; RV32IF: # %bb.0:
1898 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
1899 ; RV32IF-NEXT: ret
1900 ;
1901 ; RV64IF-LABEL: fcvt_wu_s_i8:
1902 ; RV64IF: # %bb.0:
1903 ; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
1904 ; RV64IF-NEXT: ret
1905 ;
1906 ; RV32IZFINX-LABEL: fcvt_wu_s_i8:
1907 ; RV32IZFINX: # %bb.0:
1908 ; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz
1909 ; RV32IZFINX-NEXT: ret
1910 ;
1911 ; RV64IZFINX-LABEL: fcvt_wu_s_i8:
1912 ; RV64IZFINX: # %bb.0:
1913 ; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
1914 ; RV64IZFINX-NEXT: ret
1915 ;
1916 ; RV32I-LABEL: fcvt_wu_s_i8:
1917 ; RV32I: # %bb.0:
1918 ; RV32I-NEXT: addi sp, sp, -16
1919 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1920 ; RV32I-NEXT: call __fixunssfsi
1921 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1922 ; RV32I-NEXT: addi sp, sp, 16
1923 ; RV32I-NEXT: ret
1924 ;
1925 ; RV64I-LABEL: fcvt_wu_s_i8:
1926 ; RV64I: # %bb.0:
1927 ; RV64I-NEXT: addi sp, sp, -16
1928 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1929 ; RV64I-NEXT: call __fixunssfdi
1930 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1931 ; RV64I-NEXT: addi sp, sp, 16
1932 ; RV64I-NEXT: ret
1933 %1 = fptoui float %a to i8
1934 ret i8 %1
1935 }
1937 define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind {
1938 ; RV32IF-LABEL: fcvt_wu_s_sat_i8:
1939 ; RV32IF: # %bb.0: # %start
1940 ; RV32IF-NEXT: fmv.w.x fa5, zero
1941 ; RV32IF-NEXT: fmax.s fa5, fa0, fa5
1942 ; RV32IF-NEXT: lui a0, 276464
1943 ; RV32IF-NEXT: fmv.w.x fa4, a0
1944 ; RV32IF-NEXT: fmin.s fa5, fa5, fa4
1945 ; RV32IF-NEXT: fcvt.wu.s a0, fa5, rtz
1946 ; RV32IF-NEXT: ret
1947 ;
1948 ; RV64IF-LABEL: fcvt_wu_s_sat_i8:
1949 ; RV64IF: # %bb.0: # %start
1950 ; RV64IF-NEXT: fmv.w.x fa5, zero
1951 ; RV64IF-NEXT: fmax.s fa5, fa0, fa5
1952 ; RV64IF-NEXT: lui a0, 276464
1953 ; RV64IF-NEXT: fmv.w.x fa4, a0
1954 ; RV64IF-NEXT: fmin.s fa5, fa5, fa4
1955 ; RV64IF-NEXT: fcvt.lu.s a0, fa5, rtz
1956 ; RV64IF-NEXT: ret
1957 ;
1958 ; RV32IZFINX-LABEL: fcvt_wu_s_sat_i8:
1959 ; RV32IZFINX: # %bb.0: # %start
1960 ; RV32IZFINX-NEXT: fmax.s a0, a0, zero
1961 ; RV32IZFINX-NEXT: lui a1, 276464
1962 ; RV32IZFINX-NEXT: fmin.s a0, a0, a1
1963 ; RV32IZFINX-NEXT: fcvt.wu.s a0, a0, rtz
1964 ; RV32IZFINX-NEXT: ret
1965 ;
1966 ; RV64IZFINX-LABEL: fcvt_wu_s_sat_i8:
1967 ; RV64IZFINX: # %bb.0: # %start
1968 ; RV64IZFINX-NEXT: fmax.s a0, a0, zero
1969 ; RV64IZFINX-NEXT: lui a1, 276464
1970 ; RV64IZFINX-NEXT: fmin.s a0, a0, a1
1971 ; RV64IZFINX-NEXT: fcvt.lu.s a0, a0, rtz
1972 ; RV64IZFINX-NEXT: ret
1973 ;
1974 ; RV32I-LABEL: fcvt_wu_s_sat_i8:
1975 ; RV32I: # %bb.0: # %start
1976 ; RV32I-NEXT: addi sp, sp, -16
1977 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1978 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1979 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1980 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1981 ; RV32I-NEXT: mv s2, a0
1982 ; RV32I-NEXT: li a1, 0
1983 ; RV32I-NEXT: call __gesf2
1984 ; RV32I-NEXT: mv s0, a0
1985 ; RV32I-NEXT: mv a0, s2
1986 ; RV32I-NEXT: call __fixunssfsi
1987 ; RV32I-NEXT: mv s1, a0
1988 ; RV32I-NEXT: lui a1, 276464
1989 ; RV32I-NEXT: mv a0, s2
1990 ; RV32I-NEXT: call __gtsf2
1991 ; RV32I-NEXT: blez a0, .LBB30_2
1992 ; RV32I-NEXT: # %bb.1: # %start
1993 ; RV32I-NEXT: li a0, 255
1994 ; RV32I-NEXT: j .LBB30_3
1995 ; RV32I-NEXT: .LBB30_2:
1996 ; RV32I-NEXT: slti a0, s0, 0
1997 ; RV32I-NEXT: addi a0, a0, -1
1998 ; RV32I-NEXT: and a0, a0, s1
1999 ; RV32I-NEXT: .LBB30_3: # %start
2000 ; RV32I-NEXT: andi a0, a0, 255
2001 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2002 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2003 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2004 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
2005 ; RV32I-NEXT: addi sp, sp, 16
2006 ; RV32I-NEXT: ret
2007 ;
2008 ; RV64I-LABEL: fcvt_wu_s_sat_i8:
2009 ; RV64I: # %bb.0: # %start
2010 ; RV64I-NEXT: addi sp, sp, -32
2011 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2012 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2013 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2014 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2015 ; RV64I-NEXT: mv s2, a0
2016 ; RV64I-NEXT: li a1, 0
2017 ; RV64I-NEXT: call __gesf2
2018 ; RV64I-NEXT: mv s0, a0
2019 ; RV64I-NEXT: mv a0, s2
2020 ; RV64I-NEXT: call __fixunssfdi
2021 ; RV64I-NEXT: mv s1, a0
2022 ; RV64I-NEXT: lui a1, 276464
2023 ; RV64I-NEXT: mv a0, s2
2024 ; RV64I-NEXT: call __gtsf2
2025 ; RV64I-NEXT: blez a0, .LBB30_2
2026 ; RV64I-NEXT: # %bb.1: # %start
2027 ; RV64I-NEXT: li a0, 255
2028 ; RV64I-NEXT: j .LBB30_3
2029 ; RV64I-NEXT: .LBB30_2:
2030 ; RV64I-NEXT: slti a0, s0, 0
2031 ; RV64I-NEXT: addi a0, a0, -1
2032 ; RV64I-NEXT: and a0, a0, s1
2033 ; RV64I-NEXT: .LBB30_3: # %start
2034 ; RV64I-NEXT: andi a0, a0, 255
2035 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2036 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2037 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2038 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2039 ; RV64I-NEXT: addi sp, sp, 32
2040 ; RV64I-NEXT: ret
2041 start:
2042 %0 = tail call i8 @llvm.fptoui.sat.i8.f32(float %a)
2043 ret i8 %0
2044 }
2045 declare i8 @llvm.fptoui.sat.i8.f32(float)
2047 define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind {
2048 ; RV32IF-LABEL: fcvt_wu_s_sat_zext:
2049 ; RV32IF: # %bb.0: # %start
2050 ; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
2051 ; RV32IF-NEXT: feq.s a1, fa0, fa0
2052 ; RV32IF-NEXT: seqz a1, a1
2053 ; RV32IF-NEXT: addi a1, a1, -1
2054 ; RV32IF-NEXT: and a0, a1, a0
2055 ; RV32IF-NEXT: ret
2056 ;
2057 ; RV64IF-LABEL: fcvt_wu_s_sat_zext:
2058 ; RV64IF: # %bb.0: # %start
2059 ; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
2060 ; RV64IF-NEXT: feq.s a1, fa0, fa0
2061 ; RV64IF-NEXT: seqz a1, a1
2062 ; RV64IF-NEXT: addi a1, a1, -1
2063 ; RV64IF-NEXT: and a0, a0, a1
2064 ; RV64IF-NEXT: slli a0, a0, 32
2065 ; RV64IF-NEXT: srli a0, a0, 32
2066 ; RV64IF-NEXT: ret
2067 ;
2068 ; RV32IZFINX-LABEL: fcvt_wu_s_sat_zext:
2069 ; RV32IZFINX: # %bb.0: # %start
2070 ; RV32IZFINX-NEXT: fcvt.wu.s a1, a0, rtz
2071 ; RV32IZFINX-NEXT: feq.s a0, a0, a0
2072 ; RV32IZFINX-NEXT: seqz a0, a0
2073 ; RV32IZFINX-NEXT: addi a0, a0, -1
2074 ; RV32IZFINX-NEXT: and a0, a0, a1
2075 ; RV32IZFINX-NEXT: ret
2076 ;
2077 ; RV64IZFINX-LABEL: fcvt_wu_s_sat_zext:
2078 ; RV64IZFINX: # %bb.0: # %start
2079 ; RV64IZFINX-NEXT: fcvt.wu.s a1, a0, rtz
2080 ; RV64IZFINX-NEXT: feq.s a0, a0, a0
2081 ; RV64IZFINX-NEXT: seqz a0, a0
2082 ; RV64IZFINX-NEXT: addi a0, a0, -1
2083 ; RV64IZFINX-NEXT: and a0, a1, a0
2084 ; RV64IZFINX-NEXT: slli a0, a0, 32
2085 ; RV64IZFINX-NEXT: srli a0, a0, 32
2086 ; RV64IZFINX-NEXT: ret
2087 ;
2088 ; RV32I-LABEL: fcvt_wu_s_sat_zext:
2089 ; RV32I: # %bb.0: # %start
2090 ; RV32I-NEXT: addi sp, sp, -16
2091 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2092 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2093 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
2094 ; RV32I-NEXT: mv s0, a0
2095 ; RV32I-NEXT: li a1, 0
2096 ; RV32I-NEXT: call __gesf2
2097 ; RV32I-NEXT: slti a0, a0, 0
2098 ; RV32I-NEXT: addi s1, a0, -1
2099 ; RV32I-NEXT: mv a0, s0
2100 ; RV32I-NEXT: call __fixunssfsi
2101 ; RV32I-NEXT: and s1, s1, a0
2102 ; RV32I-NEXT: lui a1, 325632
2103 ; RV32I-NEXT: addi a1, a1, -1
2104 ; RV32I-NEXT: mv a0, s0
2105 ; RV32I-NEXT: call __gtsf2
2106 ; RV32I-NEXT: sgtz a0, a0
2107 ; RV32I-NEXT: neg a0, a0
2108 ; RV32I-NEXT: or a0, a0, s1
2109 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2110 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2111 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2112 ; RV32I-NEXT: addi sp, sp, 16
2113 ; RV32I-NEXT: ret
2114 ;
2115 ; RV64I-LABEL: fcvt_wu_s_sat_zext:
2116 ; RV64I: # %bb.0: # %start
2117 ; RV64I-NEXT: addi sp, sp, -32
2118 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
2119 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
2120 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
2121 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
2122 ; RV64I-NEXT: mv s2, a0
2123 ; RV64I-NEXT: li a1, 0
2124 ; RV64I-NEXT: call __gesf2
2125 ; RV64I-NEXT: mv s0, a0
2126 ; RV64I-NEXT: mv a0, s2
2127 ; RV64I-NEXT: call __fixunssfdi
2128 ; RV64I-NEXT: mv s1, a0
2129 ; RV64I-NEXT: lui a1, 325632
2130 ; RV64I-NEXT: addiw a1, a1, -1
2131 ; RV64I-NEXT: mv a0, s2
2132 ; RV64I-NEXT: call __gtsf2
2133 ; RV64I-NEXT: blez a0, .LBB31_2
2134 ; RV64I-NEXT: # %bb.1: # %start
2135 ; RV64I-NEXT: li a0, -1
2136 ; RV64I-NEXT: srli a0, a0, 32
2137 ; RV64I-NEXT: j .LBB31_3
2138 ; RV64I-NEXT: .LBB31_2:
2139 ; RV64I-NEXT: slti a0, s0, 0
2140 ; RV64I-NEXT: addi a0, a0, -1
2141 ; RV64I-NEXT: and a0, a0, s1
2142 ; RV64I-NEXT: .LBB31_3: # %start
2143 ; RV64I-NEXT: slli a0, a0, 32
2144 ; RV64I-NEXT: srli a0, a0, 32
2145 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
2146 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
2147 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
2148 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
2149 ; RV64I-NEXT: addi sp, sp, 32
2150 ; RV64I-NEXT: ret
2151 start:
2152 %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
2153 ret i32 %0
2154 }
2156 define signext i32 @fcvt_w_s_sat_sext(float %a) nounwind {
2157 ; CHECKIF-LABEL: fcvt_w_s_sat_sext:
2158 ; CHECKIF: # %bb.0: # %start
2159 ; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
2160 ; CHECKIF-NEXT: feq.s a1, fa0, fa0
2161 ; CHECKIF-NEXT: seqz a1, a1
2162 ; CHECKIF-NEXT: addi a1, a1, -1
2163 ; CHECKIF-NEXT: and a0, a1, a0
2164 ; CHECKIF-NEXT: ret
2165 ;
2166 ; CHECKIZFINX-LABEL: fcvt_w_s_sat_sext:
2167 ; CHECKIZFINX: # %bb.0: # %start
2168 ; CHECKIZFINX-NEXT: fcvt.w.s a1, a0, rtz
2169 ; CHECKIZFINX-NEXT: feq.s a0, a0, a0
2170 ; CHECKIZFINX-NEXT: seqz a0, a0
2171 ; CHECKIZFINX-NEXT: addi a0, a0, -1
2172 ; CHECKIZFINX-NEXT: and a0, a0, a1
2173 ; CHECKIZFINX-NEXT: ret
2174 ;
2175 ; RV32I-LABEL: fcvt_w_s_sat_sext:
2176 ; RV32I: # %bb.0: # %start
2177 ; RV32I-NEXT: addi sp, sp, -32
2178 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
2179 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
2180 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
2181 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
2182 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
2183 ; RV32I-NEXT: mv s0, a0
2184 ; RV32I-NEXT: lui a1, 847872
2185 ; RV32I-NEXT: call __gesf2
2186 ; RV32I-NEXT: mv s2, a0
2187 ; RV32I-NEXT: mv a0, s0
2188 ; RV32I-NEXT: call __fixsfsi
2189 ; RV32I-NEXT: mv s1, a0
2190 ; RV32I-NEXT: lui s3, 524288
2191 ; RV32I-NEXT: bgez s2, .LBB32_2
2192 ; RV32I-NEXT: # %bb.1: # %start
2193 ; RV32I-NEXT: lui s1, 524288
2194 ; RV32I-NEXT: .LBB32_2: # %start
2195 ; RV32I-NEXT: lui a1, 323584
2196 ; RV32I-NEXT: addi a1, a1, -1
2197 ; RV32I-NEXT: mv a0, s0
2198 ; RV32I-NEXT: call __gtsf2
2199 ; RV32I-NEXT: blez a0, .LBB32_4
2200 ; RV32I-NEXT: # %bb.3: # %start
2201 ; RV32I-NEXT: addi s1, s3, -1
2202 ; RV32I-NEXT: .LBB32_4: # %start
2203 ; RV32I-NEXT: mv a0, s0
2204 ; RV32I-NEXT: mv a1, s0
2205 ; RV32I-NEXT: call __unordsf2
2206 ; RV32I-NEXT: snez a0, a0
2207 ; RV32I-NEXT: addi a0, a0, -1
2208 ; RV32I-NEXT: and a0, a0, s1
2209 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
2210 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
2211 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
2212 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
2213 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
2214 ; RV32I-NEXT: addi sp, sp, 32
2215 ; RV32I-NEXT: ret
2216 ;
2217 ; RV64I-LABEL: fcvt_w_s_sat_sext:
2218 ; RV64I: # %bb.0: # %start
2219 ; RV64I-NEXT: addi sp, sp, -48
2220 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
2221 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
2222 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
2223 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
2224 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
2225 ; RV64I-NEXT: mv s0, a0
2226 ; RV64I-NEXT: lui a1, 847872
2227 ; RV64I-NEXT: call __gesf2
2228 ; RV64I-NEXT: mv s2, a0
2229 ; RV64I-NEXT: mv a0, s0
2230 ; RV64I-NEXT: call __fixsfdi
2231 ; RV64I-NEXT: mv s1, a0
2232 ; RV64I-NEXT: lui s3, 524288
2233 ; RV64I-NEXT: bgez s2, .LBB32_2
2234 ; RV64I-NEXT: # %bb.1: # %start
2235 ; RV64I-NEXT: lui s1, 524288
2236 ; RV64I-NEXT: .LBB32_2: # %start
2237 ; RV64I-NEXT: lui a1, 323584
2238 ; RV64I-NEXT: addiw a1, a1, -1
2239 ; RV64I-NEXT: mv a0, s0
2240 ; RV64I-NEXT: call __gtsf2
2241 ; RV64I-NEXT: blez a0, .LBB32_4
2242 ; RV64I-NEXT: # %bb.3: # %start
2243 ; RV64I-NEXT: addi s1, s3, -1
2244 ; RV64I-NEXT: .LBB32_4: # %start
2245 ; RV64I-NEXT: mv a0, s0
2246 ; RV64I-NEXT: mv a1, s0
2247 ; RV64I-NEXT: call __unordsf2
2248 ; RV64I-NEXT: snez a0, a0
2249 ; RV64I-NEXT: addi a0, a0, -1
2250 ; RV64I-NEXT: and a0, a0, s1
2251 ; RV64I-NEXT: sext.w a0, a0
2252 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
2253 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
2254 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
2255 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
2256 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
2257 ; RV64I-NEXT: addi sp, sp, 48
2258 ; RV64I-NEXT: ret
2259 start:
2260 %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
2261 ret i32 %0
2262 }