| blob | 04a8a66f44598f46795c068c7302f652fcd450ce |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
10 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
11 ; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
12 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
13 ; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
14 ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
15 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
16 ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
17 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
19 define signext i32 @test_floor_si32(half %x) {
20 ; CHECKIZFH-LABEL: test_floor_si32:
21 ; CHECKIZFH: # %bb.0:
22 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
23 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
24 ; CHECKIZFH-NEXT: seqz a1, a1
25 ; CHECKIZFH-NEXT: addi a1, a1, -1
26 ; CHECKIZFH-NEXT: and a0, a1, a0
27 ; CHECKIZFH-NEXT: ret
28 ;
29 ; CHECKIZHINX-LABEL: test_floor_si32:
30 ; CHECKIZHINX: # %bb.0:
31 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI0_0)
32 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI0_0)(a1)
33 ; CHECKIZHINX-NEXT: fabs.h a2, a0
34 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
35 ; CHECKIZHINX-NEXT: beqz a1, .LBB0_2
36 ; CHECKIZHINX-NEXT: # %bb.1:
37 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
38 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
39 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
40 ; CHECKIZHINX-NEXT: .LBB0_2:
41 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
42 ; CHECKIZHINX-NEXT: feq.h a0, a0, a0
43 ; CHECKIZHINX-NEXT: seqz a0, a0
44 ; CHECKIZHINX-NEXT: addi a0, a0, -1
45 ; CHECKIZHINX-NEXT: and a0, a0, a1
46 ; CHECKIZHINX-NEXT: ret
47 ;
48 ; CHECKIZFHMIN-LABEL: test_floor_si32:
49 ; CHECKIZFHMIN: # %bb.0:
50 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
51 ; CHECKIZFHMIN-NEXT: lui a0, 307200
52 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
53 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
54 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
55 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB0_2
56 ; CHECKIZFHMIN-NEXT: # %bb.1:
57 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
58 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
59 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
60 ; CHECKIZFHMIN-NEXT: .LBB0_2:
61 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
62 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
63 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
64 ; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
65 ; CHECKIZFHMIN-NEXT: seqz a1, a1
66 ; CHECKIZFHMIN-NEXT: addi a1, a1, -1
67 ; CHECKIZFHMIN-NEXT: and a0, a1, a0
68 ; CHECKIZFHMIN-NEXT: ret
69 ;
70 ; CHECKIZHINXMIN-LABEL: test_floor_si32:
71 ; CHECKIZHINXMIN: # %bb.0:
72 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
73 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
74 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
75 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
76 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB0_2
77 ; CHECKIZHINXMIN-NEXT: # %bb.1:
78 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
79 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
80 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
81 ; CHECKIZHINXMIN-NEXT: .LBB0_2:
82 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
83 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
84 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
85 ; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0
86 ; CHECKIZHINXMIN-NEXT: seqz a0, a0
87 ; CHECKIZHINXMIN-NEXT: addi a0, a0, -1
88 ; CHECKIZHINXMIN-NEXT: and a0, a0, a1
89 ; CHECKIZHINXMIN-NEXT: ret
90 %a = call half @llvm.floor.f16(half %x)
91 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
92 ret i32 %b
93 }
95 define i64 @test_floor_si64(half %x) nounwind {
96 ; RV32IZFH-LABEL: test_floor_si64:
97 ; RV32IZFH: # %bb.0:
98 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
99 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI1_0)(a0)
100 ; RV32IZFH-NEXT: fabs.h fa4, fa0
101 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
102 ; RV32IZFH-NEXT: beqz a0, .LBB1_2
103 ; RV32IZFH-NEXT: # %bb.1:
104 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
105 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
106 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
107 ; RV32IZFH-NEXT: .LBB1_2:
108 ; RV32IZFH-NEXT: addi sp, sp, -16
109 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
110 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
111 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
112 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
113 ; RV32IZFH-NEXT: lui a0, 913408
114 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
115 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
116 ; RV32IZFH-NEXT: fmv.s fa0, fs0
117 ; RV32IZFH-NEXT: call __fixsfdi
118 ; RV32IZFH-NEXT: lui a4, 524288
119 ; RV32IZFH-NEXT: lui a2, 524288
120 ; RV32IZFH-NEXT: beqz s0, .LBB1_4
121 ; RV32IZFH-NEXT: # %bb.3:
122 ; RV32IZFH-NEXT: mv a2, a1
123 ; RV32IZFH-NEXT: .LBB1_4:
124 ; RV32IZFH-NEXT: lui a1, %hi(.LCPI1_1)
125 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a1)
126 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
127 ; RV32IZFH-NEXT: beqz a3, .LBB1_6
128 ; RV32IZFH-NEXT: # %bb.5:
129 ; RV32IZFH-NEXT: addi a2, a4, -1
130 ; RV32IZFH-NEXT: .LBB1_6:
131 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
132 ; RV32IZFH-NEXT: neg a4, a1
133 ; RV32IZFH-NEXT: and a1, a4, a2
134 ; RV32IZFH-NEXT: neg a2, s0
135 ; RV32IZFH-NEXT: and a0, a2, a0
136 ; RV32IZFH-NEXT: neg a2, a3
137 ; RV32IZFH-NEXT: or a0, a2, a0
138 ; RV32IZFH-NEXT: and a0, a4, a0
139 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
140 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
141 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
142 ; RV32IZFH-NEXT: addi sp, sp, 16
143 ; RV32IZFH-NEXT: ret
144 ;
145 ; RV64IZFH-LABEL: test_floor_si64:
146 ; RV64IZFH: # %bb.0:
147 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
148 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
149 ; RV64IZFH-NEXT: seqz a1, a1
150 ; RV64IZFH-NEXT: addi a1, a1, -1
151 ; RV64IZFH-NEXT: and a0, a1, a0
152 ; RV64IZFH-NEXT: ret
153 ;
154 ; RV32IZHINX-LABEL: test_floor_si64:
155 ; RV32IZHINX: # %bb.0:
156 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
157 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
158 ; RV32IZHINX-NEXT: fabs.h a2, a0
159 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
160 ; RV32IZHINX-NEXT: beqz a1, .LBB1_2
161 ; RV32IZHINX-NEXT: # %bb.1:
162 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
163 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
164 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
165 ; RV32IZHINX-NEXT: .LBB1_2:
166 ; RV32IZHINX-NEXT: addi sp, sp, -16
167 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
168 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
169 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
170 ; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
171 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
172 ; RV32IZHINX-NEXT: lui a0, 913408
173 ; RV32IZHINX-NEXT: fle.s s1, a0, s0
174 ; RV32IZHINX-NEXT: neg s2, s1
175 ; RV32IZHINX-NEXT: mv a0, s0
176 ; RV32IZHINX-NEXT: call __fixsfdi
177 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_1)
178 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_1)(a2)
179 ; RV32IZHINX-NEXT: and a0, s2, a0
180 ; RV32IZHINX-NEXT: flt.s a4, a2, s0
181 ; RV32IZHINX-NEXT: neg a2, a4
182 ; RV32IZHINX-NEXT: or a0, a2, a0
183 ; RV32IZHINX-NEXT: feq.s a2, s0, s0
184 ; RV32IZHINX-NEXT: neg a2, a2
185 ; RV32IZHINX-NEXT: lui a5, 524288
186 ; RV32IZHINX-NEXT: lui a3, 524288
187 ; RV32IZHINX-NEXT: beqz s1, .LBB1_4
188 ; RV32IZHINX-NEXT: # %bb.3:
189 ; RV32IZHINX-NEXT: mv a3, a1
190 ; RV32IZHINX-NEXT: .LBB1_4:
191 ; RV32IZHINX-NEXT: and a0, a2, a0
192 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
193 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
194 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
195 ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
196 ; RV32IZHINX-NEXT: addi sp, sp, 16
197 ; RV32IZHINX-NEXT: beqz a4, .LBB1_6
198 ; RV32IZHINX-NEXT: # %bb.5:
199 ; RV32IZHINX-NEXT: addi a3, a5, -1
200 ; RV32IZHINX-NEXT: .LBB1_6:
201 ; RV32IZHINX-NEXT: and a1, a2, a3
202 ; RV32IZHINX-NEXT: ret
203 ;
204 ; RV64IZHINX-LABEL: test_floor_si64:
205 ; RV64IZHINX: # %bb.0:
206 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
207 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
208 ; RV64IZHINX-NEXT: fabs.h a2, a0
209 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
210 ; RV64IZHINX-NEXT: beqz a1, .LBB1_2
211 ; RV64IZHINX-NEXT: # %bb.1:
212 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
213 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
214 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
215 ; RV64IZHINX-NEXT: .LBB1_2:
216 ; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz
217 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
218 ; RV64IZHINX-NEXT: seqz a0, a0
219 ; RV64IZHINX-NEXT: addi a0, a0, -1
220 ; RV64IZHINX-NEXT: and a0, a0, a1
221 ; RV64IZHINX-NEXT: ret
222 ;
223 ; RV32IZFHMIN-LABEL: test_floor_si64:
224 ; RV32IZFHMIN: # %bb.0:
225 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
226 ; RV32IZFHMIN-NEXT: lui a0, 307200
227 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
228 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
229 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
230 ; RV32IZFHMIN-NEXT: beqz a0, .LBB1_2
231 ; RV32IZFHMIN-NEXT: # %bb.1:
232 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
233 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
234 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
235 ; RV32IZFHMIN-NEXT: .LBB1_2:
236 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
237 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
238 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
239 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
240 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
241 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
242 ; RV32IZFHMIN-NEXT: lui a0, 913408
243 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
244 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
245 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
246 ; RV32IZFHMIN-NEXT: call __fixsfdi
247 ; RV32IZFHMIN-NEXT: lui a4, 524288
248 ; RV32IZFHMIN-NEXT: lui a2, 524288
249 ; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4
250 ; RV32IZFHMIN-NEXT: # %bb.3:
251 ; RV32IZFHMIN-NEXT: mv a2, a1
252 ; RV32IZFHMIN-NEXT: .LBB1_4:
253 ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI1_0)
254 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a1)
255 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
256 ; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6
257 ; RV32IZFHMIN-NEXT: # %bb.5:
258 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
259 ; RV32IZFHMIN-NEXT: .LBB1_6:
260 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
261 ; RV32IZFHMIN-NEXT: neg a4, a1
262 ; RV32IZFHMIN-NEXT: and a1, a4, a2
263 ; RV32IZFHMIN-NEXT: neg a2, s0
264 ; RV32IZFHMIN-NEXT: and a0, a2, a0
265 ; RV32IZFHMIN-NEXT: neg a2, a3
266 ; RV32IZFHMIN-NEXT: or a0, a2, a0
267 ; RV32IZFHMIN-NEXT: and a0, a4, a0
268 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
269 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
270 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
271 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
272 ; RV32IZFHMIN-NEXT: ret
273 ;
274 ; RV64IZFHMIN-LABEL: test_floor_si64:
275 ; RV64IZFHMIN: # %bb.0:
276 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
277 ; RV64IZFHMIN-NEXT: lui a0, 307200
278 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
279 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
280 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
281 ; RV64IZFHMIN-NEXT: beqz a0, .LBB1_2
282 ; RV64IZFHMIN-NEXT: # %bb.1:
283 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
284 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
285 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
286 ; RV64IZFHMIN-NEXT: .LBB1_2:
287 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
288 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
289 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
290 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
291 ; RV64IZFHMIN-NEXT: seqz a1, a1
292 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
293 ; RV64IZFHMIN-NEXT: and a0, a1, a0
294 ; RV64IZFHMIN-NEXT: ret
295 ;
296 ; RV32IZHINXMIN-LABEL: test_floor_si64:
297 ; RV32IZHINXMIN: # %bb.0:
298 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
299 ; RV32IZHINXMIN-NEXT: lui a1, 307200
300 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
301 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
302 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB1_2
303 ; RV32IZHINXMIN-NEXT: # %bb.1:
304 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
305 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
306 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
307 ; RV32IZHINXMIN-NEXT: .LBB1_2:
308 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
309 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
310 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
311 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
312 ; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
313 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
314 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
315 ; RV32IZHINXMIN-NEXT: lui a0, 913408
316 ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0
317 ; RV32IZHINXMIN-NEXT: neg s2, s1
318 ; RV32IZHINXMIN-NEXT: mv a0, s0
319 ; RV32IZHINXMIN-NEXT: call __fixsfdi
320 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
321 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
322 ; RV32IZHINXMIN-NEXT: and a0, s2, a0
323 ; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
324 ; RV32IZHINXMIN-NEXT: neg a2, a4
325 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
326 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0
327 ; RV32IZHINXMIN-NEXT: neg a2, a2
328 ; RV32IZHINXMIN-NEXT: lui a5, 524288
329 ; RV32IZHINXMIN-NEXT: lui a3, 524288
330 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB1_4
331 ; RV32IZHINXMIN-NEXT: # %bb.3:
332 ; RV32IZHINXMIN-NEXT: mv a3, a1
333 ; RV32IZHINXMIN-NEXT: .LBB1_4:
334 ; RV32IZHINXMIN-NEXT: and a0, a2, a0
335 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
336 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
337 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
338 ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
339 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
340 ; RV32IZHINXMIN-NEXT: beqz a4, .LBB1_6
341 ; RV32IZHINXMIN-NEXT: # %bb.5:
342 ; RV32IZHINXMIN-NEXT: addi a3, a5, -1
343 ; RV32IZHINXMIN-NEXT: .LBB1_6:
344 ; RV32IZHINXMIN-NEXT: and a1, a2, a3
345 ; RV32IZHINXMIN-NEXT: ret
346 ;
347 ; RV64IZHINXMIN-LABEL: test_floor_si64:
348 ; RV64IZHINXMIN: # %bb.0:
349 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
350 ; RV64IZHINXMIN-NEXT: lui a1, 307200
351 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
352 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
353 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB1_2
354 ; RV64IZHINXMIN-NEXT: # %bb.1:
355 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
356 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
357 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
358 ; RV64IZHINXMIN-NEXT: .LBB1_2:
359 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
360 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
361 ; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz
362 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
363 ; RV64IZHINXMIN-NEXT: seqz a0, a0
364 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
365 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
366 ; RV64IZHINXMIN-NEXT: ret
367 %a = call half @llvm.floor.f16(half %x)
368 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
369 ret i64 %b
370 }
372 define signext i32 @test_floor_ui32(half %x) {
373 ; CHECKIZFH-LABEL: test_floor_ui32:
374 ; CHECKIZFH: # %bb.0:
375 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rdn
376 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
377 ; CHECKIZFH-NEXT: seqz a1, a1
378 ; CHECKIZFH-NEXT: addi a1, a1, -1
379 ; CHECKIZFH-NEXT: and a0, a1, a0
380 ; CHECKIZFH-NEXT: ret
381 ;
382 ; RV32IZHINX-LABEL: test_floor_ui32:
383 ; RV32IZHINX: # %bb.0:
384 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI2_0)
385 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI2_0)(a1)
386 ; RV32IZHINX-NEXT: fabs.h a2, a0
387 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
388 ; RV32IZHINX-NEXT: beqz a1, .LBB2_2
389 ; RV32IZHINX-NEXT: # %bb.1:
390 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
391 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
392 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
393 ; RV32IZHINX-NEXT: .LBB2_2:
394 ; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
395 ; RV32IZHINX-NEXT: feq.h a0, a0, a0
396 ; RV32IZHINX-NEXT: seqz a0, a0
397 ; RV32IZHINX-NEXT: addi a0, a0, -1
398 ; RV32IZHINX-NEXT: and a0, a0, a1
399 ; RV32IZHINX-NEXT: ret
400 ;
401 ; RV64IZHINX-LABEL: test_floor_ui32:
402 ; RV64IZHINX: # %bb.0:
403 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI2_0)
404 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI2_0)(a1)
405 ; RV64IZHINX-NEXT: fabs.h a2, a0
406 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
407 ; RV64IZHINX-NEXT: beqz a1, .LBB2_2
408 ; RV64IZHINX-NEXT: # %bb.1:
409 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
410 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
411 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
412 ; RV64IZHINX-NEXT: .LBB2_2:
413 ; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
414 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
415 ; RV64IZHINX-NEXT: seqz a0, a0
416 ; RV64IZHINX-NEXT: addiw a0, a0, -1
417 ; RV64IZHINX-NEXT: and a0, a1, a0
418 ; RV64IZHINX-NEXT: ret
419 ;
420 ; RV32IZFHMIN-LABEL: test_floor_ui32:
421 ; RV32IZFHMIN: # %bb.0:
422 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
423 ; RV32IZFHMIN-NEXT: lui a0, 307200
424 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
425 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
426 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
427 ; RV32IZFHMIN-NEXT: beqz a0, .LBB2_2
428 ; RV32IZFHMIN-NEXT: # %bb.1:
429 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
430 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
431 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
432 ; RV32IZFHMIN-NEXT: .LBB2_2:
433 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
434 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
435 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
436 ; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5
437 ; RV32IZFHMIN-NEXT: seqz a1, a1
438 ; RV32IZFHMIN-NEXT: addi a1, a1, -1
439 ; RV32IZFHMIN-NEXT: and a0, a1, a0
440 ; RV32IZFHMIN-NEXT: ret
441 ;
442 ; RV64IZFHMIN-LABEL: test_floor_ui32:
443 ; RV64IZFHMIN: # %bb.0:
444 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
445 ; RV64IZFHMIN-NEXT: lui a0, 307200
446 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
447 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
448 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
449 ; RV64IZFHMIN-NEXT: beqz a0, .LBB2_2
450 ; RV64IZFHMIN-NEXT: # %bb.1:
451 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
452 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
453 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
454 ; RV64IZFHMIN-NEXT: .LBB2_2:
455 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
456 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
457 ; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
458 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
459 ; RV64IZFHMIN-NEXT: seqz a1, a1
460 ; RV64IZFHMIN-NEXT: addiw a1, a1, -1
461 ; RV64IZFHMIN-NEXT: and a0, a0, a1
462 ; RV64IZFHMIN-NEXT: ret
463 ;
464 ; RV32IZHINXMIN-LABEL: test_floor_ui32:
465 ; RV32IZHINXMIN: # %bb.0:
466 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
467 ; RV32IZHINXMIN-NEXT: lui a1, 307200
468 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
469 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
470 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB2_2
471 ; RV32IZHINXMIN-NEXT: # %bb.1:
472 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
473 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
474 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
475 ; RV32IZHINXMIN-NEXT: .LBB2_2:
476 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
477 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
478 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
479 ; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0
480 ; RV32IZHINXMIN-NEXT: seqz a0, a0
481 ; RV32IZHINXMIN-NEXT: addi a0, a0, -1
482 ; RV32IZHINXMIN-NEXT: and a0, a0, a1
483 ; RV32IZHINXMIN-NEXT: ret
484 ;
485 ; RV64IZHINXMIN-LABEL: test_floor_ui32:
486 ; RV64IZHINXMIN: # %bb.0:
487 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
488 ; RV64IZHINXMIN-NEXT: lui a1, 307200
489 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
490 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
491 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB2_2
492 ; RV64IZHINXMIN-NEXT: # %bb.1:
493 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
494 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
495 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
496 ; RV64IZHINXMIN-NEXT: .LBB2_2:
497 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
498 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
499 ; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
500 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
501 ; RV64IZHINXMIN-NEXT: seqz a0, a0
502 ; RV64IZHINXMIN-NEXT: addiw a0, a0, -1
503 ; RV64IZHINXMIN-NEXT: and a0, a1, a0
504 ; RV64IZHINXMIN-NEXT: ret
505 %a = call half @llvm.floor.f16(half %x)
506 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
507 ret i32 %b
508 }
510 define i64 @test_floor_ui64(half %x) nounwind {
511 ; RV32IZFH-LABEL: test_floor_ui64:
512 ; RV32IZFH: # %bb.0:
513 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
514 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
515 ; RV32IZFH-NEXT: fabs.h fa4, fa0
516 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
517 ; RV32IZFH-NEXT: beqz a0, .LBB3_2
518 ; RV32IZFH-NEXT: # %bb.1:
519 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
520 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
521 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
522 ; RV32IZFH-NEXT: .LBB3_2:
523 ; RV32IZFH-NEXT: addi sp, sp, -16
524 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
525 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
526 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
527 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
528 ; RV32IZFH-NEXT: fmv.w.x fa5, zero
529 ; RV32IZFH-NEXT: fle.s a0, fa5, fs0
530 ; RV32IZFH-NEXT: neg s0, a0
531 ; RV32IZFH-NEXT: fmv.s fa0, fs0
532 ; RV32IZFH-NEXT: call __fixunssfdi
533 ; RV32IZFH-NEXT: lui a2, %hi(.LCPI3_1)
534 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI3_1)(a2)
535 ; RV32IZFH-NEXT: and a0, s0, a0
536 ; RV32IZFH-NEXT: flt.s a2, fa5, fs0
537 ; RV32IZFH-NEXT: neg a2, a2
538 ; RV32IZFH-NEXT: or a0, a2, a0
539 ; RV32IZFH-NEXT: and a1, s0, a1
540 ; RV32IZFH-NEXT: or a1, a2, a1
541 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
542 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
543 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
544 ; RV32IZFH-NEXT: addi sp, sp, 16
545 ; RV32IZFH-NEXT: ret
546 ;
547 ; RV64IZFH-LABEL: test_floor_ui64:
548 ; RV64IZFH: # %bb.0:
549 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
550 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
551 ; RV64IZFH-NEXT: seqz a1, a1
552 ; RV64IZFH-NEXT: addi a1, a1, -1
553 ; RV64IZFH-NEXT: and a0, a1, a0
554 ; RV64IZFH-NEXT: ret
555 ;
556 ; RV32IZHINX-LABEL: test_floor_ui64:
557 ; RV32IZHINX: # %bb.0:
558 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
559 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
560 ; RV32IZHINX-NEXT: fabs.h a2, a0
561 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
562 ; RV32IZHINX-NEXT: beqz a1, .LBB3_2
563 ; RV32IZHINX-NEXT: # %bb.1:
564 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
565 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
566 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
567 ; RV32IZHINX-NEXT: .LBB3_2:
568 ; RV32IZHINX-NEXT: addi sp, sp, -16
569 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
570 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
571 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
572 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
573 ; RV32IZHINX-NEXT: fle.s a0, zero, s0
574 ; RV32IZHINX-NEXT: neg s1, a0
575 ; RV32IZHINX-NEXT: mv a0, s0
576 ; RV32IZHINX-NEXT: call __fixunssfdi
577 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI3_1)
578 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI3_1)(a2)
579 ; RV32IZHINX-NEXT: and a0, s1, a0
580 ; RV32IZHINX-NEXT: flt.s a2, a2, s0
581 ; RV32IZHINX-NEXT: neg a2, a2
582 ; RV32IZHINX-NEXT: or a0, a2, a0
583 ; RV32IZHINX-NEXT: and a1, s1, a1
584 ; RV32IZHINX-NEXT: or a1, a2, a1
585 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
586 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
587 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
588 ; RV32IZHINX-NEXT: addi sp, sp, 16
589 ; RV32IZHINX-NEXT: ret
590 ;
591 ; RV64IZHINX-LABEL: test_floor_ui64:
592 ; RV64IZHINX: # %bb.0:
593 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
594 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
595 ; RV64IZHINX-NEXT: fabs.h a2, a0
596 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
597 ; RV64IZHINX-NEXT: beqz a1, .LBB3_2
598 ; RV64IZHINX-NEXT: # %bb.1:
599 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
600 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
601 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
602 ; RV64IZHINX-NEXT: .LBB3_2:
603 ; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz
604 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
605 ; RV64IZHINX-NEXT: seqz a0, a0
606 ; RV64IZHINX-NEXT: addi a0, a0, -1
607 ; RV64IZHINX-NEXT: and a0, a0, a1
608 ; RV64IZHINX-NEXT: ret
609 ;
610 ; RV32IZFHMIN-LABEL: test_floor_ui64:
611 ; RV32IZFHMIN: # %bb.0:
612 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
613 ; RV32IZFHMIN-NEXT: lui a0, 307200
614 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
615 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
616 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
617 ; RV32IZFHMIN-NEXT: beqz a0, .LBB3_2
618 ; RV32IZFHMIN-NEXT: # %bb.1:
619 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
620 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
621 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
622 ; RV32IZFHMIN-NEXT: .LBB3_2:
623 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
624 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
625 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
626 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
627 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
628 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
629 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
630 ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
631 ; RV32IZFHMIN-NEXT: neg s0, a0
632 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
633 ; RV32IZFHMIN-NEXT: call __fixunssfdi
634 ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI3_0)
635 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a2)
636 ; RV32IZFHMIN-NEXT: and a0, s0, a0
637 ; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0
638 ; RV32IZFHMIN-NEXT: neg a2, a2
639 ; RV32IZFHMIN-NEXT: or a0, a2, a0
640 ; RV32IZFHMIN-NEXT: and a1, s0, a1
641 ; RV32IZFHMIN-NEXT: or a1, a2, a1
642 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
643 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
644 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
645 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
646 ; RV32IZFHMIN-NEXT: ret
647 ;
648 ; RV64IZFHMIN-LABEL: test_floor_ui64:
649 ; RV64IZFHMIN: # %bb.0:
650 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
651 ; RV64IZFHMIN-NEXT: lui a0, 307200
652 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
653 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
654 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
655 ; RV64IZFHMIN-NEXT: beqz a0, .LBB3_2
656 ; RV64IZFHMIN-NEXT: # %bb.1:
657 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
658 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
659 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
660 ; RV64IZFHMIN-NEXT: .LBB3_2:
661 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
662 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
663 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
664 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
665 ; RV64IZFHMIN-NEXT: seqz a1, a1
666 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
667 ; RV64IZFHMIN-NEXT: and a0, a1, a0
668 ; RV64IZFHMIN-NEXT: ret
669 ;
670 ; RV32IZHINXMIN-LABEL: test_floor_ui64:
671 ; RV32IZHINXMIN: # %bb.0:
672 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
673 ; RV32IZHINXMIN-NEXT: lui a1, 307200
674 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
675 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
676 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB3_2
677 ; RV32IZHINXMIN-NEXT: # %bb.1:
678 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
679 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
680 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
681 ; RV32IZHINXMIN-NEXT: .LBB3_2:
682 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
683 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
684 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
685 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
686 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
687 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
688 ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0
689 ; RV32IZHINXMIN-NEXT: neg s1, a0
690 ; RV32IZHINXMIN-NEXT: mv a0, s0
691 ; RV32IZHINXMIN-NEXT: call __fixunssfdi
692 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI3_0)
693 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI3_0)(a2)
694 ; RV32IZHINXMIN-NEXT: and a0, s1, a0
695 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
696 ; RV32IZHINXMIN-NEXT: neg a2, a2
697 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
698 ; RV32IZHINXMIN-NEXT: and a1, s1, a1
699 ; RV32IZHINXMIN-NEXT: or a1, a2, a1
700 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
701 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
702 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
703 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
704 ; RV32IZHINXMIN-NEXT: ret
705 ;
706 ; RV64IZHINXMIN-LABEL: test_floor_ui64:
707 ; RV64IZHINXMIN: # %bb.0:
708 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
709 ; RV64IZHINXMIN-NEXT: lui a1, 307200
710 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
711 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
712 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB3_2
713 ; RV64IZHINXMIN-NEXT: # %bb.1:
714 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
715 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
716 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
717 ; RV64IZHINXMIN-NEXT: .LBB3_2:
718 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
719 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
720 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz
721 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
722 ; RV64IZHINXMIN-NEXT: seqz a0, a0
723 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
724 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
725 ; RV64IZHINXMIN-NEXT: ret
726 %a = call half @llvm.floor.f16(half %x)
727 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
728 ret i64 %b
729 }
731 define signext i32 @test_ceil_si32(half %x) {
732 ; CHECKIZFH-LABEL: test_ceil_si32:
733 ; CHECKIZFH: # %bb.0:
734 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
735 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
736 ; CHECKIZFH-NEXT: seqz a1, a1
737 ; CHECKIZFH-NEXT: addi a1, a1, -1
738 ; CHECKIZFH-NEXT: and a0, a1, a0
739 ; CHECKIZFH-NEXT: ret
740 ;
741 ; CHECKIZHINX-LABEL: test_ceil_si32:
742 ; CHECKIZHINX: # %bb.0:
743 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI4_0)
744 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI4_0)(a1)
745 ; CHECKIZHINX-NEXT: fabs.h a2, a0
746 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
747 ; CHECKIZHINX-NEXT: beqz a1, .LBB4_2
748 ; CHECKIZHINX-NEXT: # %bb.1:
749 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
750 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
751 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
752 ; CHECKIZHINX-NEXT: .LBB4_2:
753 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
754 ; CHECKIZHINX-NEXT: feq.h a0, a0, a0
755 ; CHECKIZHINX-NEXT: seqz a0, a0
756 ; CHECKIZHINX-NEXT: addi a0, a0, -1
757 ; CHECKIZHINX-NEXT: and a0, a0, a1
758 ; CHECKIZHINX-NEXT: ret
759 ;
760 ; CHECKIZFHMIN-LABEL: test_ceil_si32:
761 ; CHECKIZFHMIN: # %bb.0:
762 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
763 ; CHECKIZFHMIN-NEXT: lui a0, 307200
764 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
765 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
766 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
767 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB4_2
768 ; CHECKIZFHMIN-NEXT: # %bb.1:
769 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
770 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
771 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
772 ; CHECKIZFHMIN-NEXT: .LBB4_2:
773 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
774 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
775 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
776 ; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
777 ; CHECKIZFHMIN-NEXT: seqz a1, a1
778 ; CHECKIZFHMIN-NEXT: addi a1, a1, -1
779 ; CHECKIZFHMIN-NEXT: and a0, a1, a0
780 ; CHECKIZFHMIN-NEXT: ret
781 ;
782 ; CHECKIZHINXMIN-LABEL: test_ceil_si32:
783 ; CHECKIZHINXMIN: # %bb.0:
784 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
785 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
786 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
787 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
788 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB4_2
789 ; CHECKIZHINXMIN-NEXT: # %bb.1:
790 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
791 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
792 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
793 ; CHECKIZHINXMIN-NEXT: .LBB4_2:
794 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
795 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
796 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
797 ; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0
798 ; CHECKIZHINXMIN-NEXT: seqz a0, a0
799 ; CHECKIZHINXMIN-NEXT: addi a0, a0, -1
800 ; CHECKIZHINXMIN-NEXT: and a0, a0, a1
801 ; CHECKIZHINXMIN-NEXT: ret
802 %a = call half @llvm.ceil.f16(half %x)
803 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
804 ret i32 %b
805 }
807 define i64 @test_ceil_si64(half %x) nounwind {
808 ; RV32IZFH-LABEL: test_ceil_si64:
809 ; RV32IZFH: # %bb.0:
810 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI5_0)
811 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
812 ; RV32IZFH-NEXT: fabs.h fa4, fa0
813 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
814 ; RV32IZFH-NEXT: beqz a0, .LBB5_2
815 ; RV32IZFH-NEXT: # %bb.1:
816 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
817 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
818 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
819 ; RV32IZFH-NEXT: .LBB5_2:
820 ; RV32IZFH-NEXT: addi sp, sp, -16
821 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
822 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
823 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
824 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
825 ; RV32IZFH-NEXT: lui a0, 913408
826 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
827 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
828 ; RV32IZFH-NEXT: fmv.s fa0, fs0
829 ; RV32IZFH-NEXT: call __fixsfdi
830 ; RV32IZFH-NEXT: lui a4, 524288
831 ; RV32IZFH-NEXT: lui a2, 524288
832 ; RV32IZFH-NEXT: beqz s0, .LBB5_4
833 ; RV32IZFH-NEXT: # %bb.3:
834 ; RV32IZFH-NEXT: mv a2, a1
835 ; RV32IZFH-NEXT: .LBB5_4:
836 ; RV32IZFH-NEXT: lui a1, %hi(.LCPI5_1)
837 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a1)
838 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
839 ; RV32IZFH-NEXT: beqz a3, .LBB5_6
840 ; RV32IZFH-NEXT: # %bb.5:
841 ; RV32IZFH-NEXT: addi a2, a4, -1
842 ; RV32IZFH-NEXT: .LBB5_6:
843 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
844 ; RV32IZFH-NEXT: neg a4, a1
845 ; RV32IZFH-NEXT: and a1, a4, a2
846 ; RV32IZFH-NEXT: neg a2, s0
847 ; RV32IZFH-NEXT: and a0, a2, a0
848 ; RV32IZFH-NEXT: neg a2, a3
849 ; RV32IZFH-NEXT: or a0, a2, a0
850 ; RV32IZFH-NEXT: and a0, a4, a0
851 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
852 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
853 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
854 ; RV32IZFH-NEXT: addi sp, sp, 16
855 ; RV32IZFH-NEXT: ret
856 ;
857 ; RV64IZFH-LABEL: test_ceil_si64:
858 ; RV64IZFH: # %bb.0:
859 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
860 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
861 ; RV64IZFH-NEXT: seqz a1, a1
862 ; RV64IZFH-NEXT: addi a1, a1, -1
863 ; RV64IZFH-NEXT: and a0, a1, a0
864 ; RV64IZFH-NEXT: ret
865 ;
866 ; RV32IZHINX-LABEL: test_ceil_si64:
867 ; RV32IZHINX: # %bb.0:
868 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
869 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
870 ; RV32IZHINX-NEXT: fabs.h a2, a0
871 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
872 ; RV32IZHINX-NEXT: beqz a1, .LBB5_2
873 ; RV32IZHINX-NEXT: # %bb.1:
874 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
875 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
876 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
877 ; RV32IZHINX-NEXT: .LBB5_2:
878 ; RV32IZHINX-NEXT: addi sp, sp, -16
879 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
880 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
881 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
882 ; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
883 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
884 ; RV32IZHINX-NEXT: lui a0, 913408
885 ; RV32IZHINX-NEXT: fle.s s1, a0, s0
886 ; RV32IZHINX-NEXT: neg s2, s1
887 ; RV32IZHINX-NEXT: mv a0, s0
888 ; RV32IZHINX-NEXT: call __fixsfdi
889 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI5_1)
890 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI5_1)(a2)
891 ; RV32IZHINX-NEXT: and a0, s2, a0
892 ; RV32IZHINX-NEXT: flt.s a4, a2, s0
893 ; RV32IZHINX-NEXT: neg a2, a4
894 ; RV32IZHINX-NEXT: or a0, a2, a0
895 ; RV32IZHINX-NEXT: feq.s a2, s0, s0
896 ; RV32IZHINX-NEXT: neg a2, a2
897 ; RV32IZHINX-NEXT: lui a5, 524288
898 ; RV32IZHINX-NEXT: lui a3, 524288
899 ; RV32IZHINX-NEXT: beqz s1, .LBB5_4
900 ; RV32IZHINX-NEXT: # %bb.3:
901 ; RV32IZHINX-NEXT: mv a3, a1
902 ; RV32IZHINX-NEXT: .LBB5_4:
903 ; RV32IZHINX-NEXT: and a0, a2, a0
904 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
905 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
906 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
907 ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
908 ; RV32IZHINX-NEXT: addi sp, sp, 16
909 ; RV32IZHINX-NEXT: beqz a4, .LBB5_6
910 ; RV32IZHINX-NEXT: # %bb.5:
911 ; RV32IZHINX-NEXT: addi a3, a5, -1
912 ; RV32IZHINX-NEXT: .LBB5_6:
913 ; RV32IZHINX-NEXT: and a1, a2, a3
914 ; RV32IZHINX-NEXT: ret
915 ;
916 ; RV64IZHINX-LABEL: test_ceil_si64:
917 ; RV64IZHINX: # %bb.0:
918 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
919 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
920 ; RV64IZHINX-NEXT: fabs.h a2, a0
921 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
922 ; RV64IZHINX-NEXT: beqz a1, .LBB5_2
923 ; RV64IZHINX-NEXT: # %bb.1:
924 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
925 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
926 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
927 ; RV64IZHINX-NEXT: .LBB5_2:
928 ; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz
929 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
930 ; RV64IZHINX-NEXT: seqz a0, a0
931 ; RV64IZHINX-NEXT: addi a0, a0, -1
932 ; RV64IZHINX-NEXT: and a0, a0, a1
933 ; RV64IZHINX-NEXT: ret
934 ;
935 ; RV32IZFHMIN-LABEL: test_ceil_si64:
936 ; RV32IZFHMIN: # %bb.0:
937 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
938 ; RV32IZFHMIN-NEXT: lui a0, 307200
939 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
940 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
941 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
942 ; RV32IZFHMIN-NEXT: beqz a0, .LBB5_2
943 ; RV32IZFHMIN-NEXT: # %bb.1:
944 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
945 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
946 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
947 ; RV32IZFHMIN-NEXT: .LBB5_2:
948 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
949 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
950 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
951 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
952 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
953 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
954 ; RV32IZFHMIN-NEXT: lui a0, 913408
955 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
956 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
957 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
958 ; RV32IZFHMIN-NEXT: call __fixsfdi
959 ; RV32IZFHMIN-NEXT: lui a4, 524288
960 ; RV32IZFHMIN-NEXT: lui a2, 524288
961 ; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4
962 ; RV32IZFHMIN-NEXT: # %bb.3:
963 ; RV32IZFHMIN-NEXT: mv a2, a1
964 ; RV32IZFHMIN-NEXT: .LBB5_4:
965 ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI5_0)
966 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a1)
967 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
968 ; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6
969 ; RV32IZFHMIN-NEXT: # %bb.5:
970 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
971 ; RV32IZFHMIN-NEXT: .LBB5_6:
972 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
973 ; RV32IZFHMIN-NEXT: neg a4, a1
974 ; RV32IZFHMIN-NEXT: and a1, a4, a2
975 ; RV32IZFHMIN-NEXT: neg a2, s0
976 ; RV32IZFHMIN-NEXT: and a0, a2, a0
977 ; RV32IZFHMIN-NEXT: neg a2, a3
978 ; RV32IZFHMIN-NEXT: or a0, a2, a0
979 ; RV32IZFHMIN-NEXT: and a0, a4, a0
980 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
981 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
982 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
983 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
984 ; RV32IZFHMIN-NEXT: ret
985 ;
986 ; RV64IZFHMIN-LABEL: test_ceil_si64:
987 ; RV64IZFHMIN: # %bb.0:
988 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
989 ; RV64IZFHMIN-NEXT: lui a0, 307200
990 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
991 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
992 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
993 ; RV64IZFHMIN-NEXT: beqz a0, .LBB5_2
994 ; RV64IZFHMIN-NEXT: # %bb.1:
995 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
996 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
997 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
998 ; RV64IZFHMIN-NEXT: .LBB5_2:
999 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1000 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1001 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1002 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
1003 ; RV64IZFHMIN-NEXT: seqz a1, a1
1004 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
1005 ; RV64IZFHMIN-NEXT: and a0, a1, a0
1006 ; RV64IZFHMIN-NEXT: ret
1007 ;
1008 ; RV32IZHINXMIN-LABEL: test_ceil_si64:
1009 ; RV32IZHINXMIN: # %bb.0:
1010 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1011 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1012 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1013 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1014 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB5_2
1015 ; RV32IZHINXMIN-NEXT: # %bb.1:
1016 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1017 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1018 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1019 ; RV32IZHINXMIN-NEXT: .LBB5_2:
1020 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1021 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1022 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1023 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1024 ; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1025 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1026 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
1027 ; RV32IZHINXMIN-NEXT: lui a0, 913408
1028 ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0
1029 ; RV32IZHINXMIN-NEXT: neg s2, s1
1030 ; RV32IZHINXMIN-NEXT: mv a0, s0
1031 ; RV32IZHINXMIN-NEXT: call __fixsfdi
1032 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI5_0)
1033 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI5_0)(a2)
1034 ; RV32IZHINXMIN-NEXT: and a0, s2, a0
1035 ; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
1036 ; RV32IZHINXMIN-NEXT: neg a2, a4
1037 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
1038 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0
1039 ; RV32IZHINXMIN-NEXT: neg a2, a2
1040 ; RV32IZHINXMIN-NEXT: lui a5, 524288
1041 ; RV32IZHINXMIN-NEXT: lui a3, 524288
1042 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB5_4
1043 ; RV32IZHINXMIN-NEXT: # %bb.3:
1044 ; RV32IZHINXMIN-NEXT: mv a3, a1
1045 ; RV32IZHINXMIN-NEXT: .LBB5_4:
1046 ; RV32IZHINXMIN-NEXT: and a0, a2, a0
1047 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1048 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1049 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1050 ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1051 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1052 ; RV32IZHINXMIN-NEXT: beqz a4, .LBB5_6
1053 ; RV32IZHINXMIN-NEXT: # %bb.5:
1054 ; RV32IZHINXMIN-NEXT: addi a3, a5, -1
1055 ; RV32IZHINXMIN-NEXT: .LBB5_6:
1056 ; RV32IZHINXMIN-NEXT: and a1, a2, a3
1057 ; RV32IZHINXMIN-NEXT: ret
1058 ;
1059 ; RV64IZHINXMIN-LABEL: test_ceil_si64:
1060 ; RV64IZHINXMIN: # %bb.0:
1061 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1062 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1063 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1064 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1065 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB5_2
1066 ; RV64IZHINXMIN-NEXT: # %bb.1:
1067 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1068 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1069 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1070 ; RV64IZHINXMIN-NEXT: .LBB5_2:
1071 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1072 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1073 ; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz
1074 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
1075 ; RV64IZHINXMIN-NEXT: seqz a0, a0
1076 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
1077 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
1078 ; RV64IZHINXMIN-NEXT: ret
1079 %a = call half @llvm.ceil.f16(half %x)
1080 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
1081 ret i64 %b
1082 }
1084 define signext i32 @test_ceil_ui32(half %x) {
1085 ; CHECKIZFH-LABEL: test_ceil_ui32:
1086 ; CHECKIZFH: # %bb.0:
1087 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rup
1088 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
1089 ; CHECKIZFH-NEXT: seqz a1, a1
1090 ; CHECKIZFH-NEXT: addi a1, a1, -1
1091 ; CHECKIZFH-NEXT: and a0, a1, a0
1092 ; CHECKIZFH-NEXT: ret
1093 ;
1094 ; RV32IZHINX-LABEL: test_ceil_ui32:
1095 ; RV32IZHINX: # %bb.0:
1096 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI6_0)
1097 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI6_0)(a1)
1098 ; RV32IZHINX-NEXT: fabs.h a2, a0
1099 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1100 ; RV32IZHINX-NEXT: beqz a1, .LBB6_2
1101 ; RV32IZHINX-NEXT: # %bb.1:
1102 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1103 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1104 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1105 ; RV32IZHINX-NEXT: .LBB6_2:
1106 ; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
1107 ; RV32IZHINX-NEXT: feq.h a0, a0, a0
1108 ; RV32IZHINX-NEXT: seqz a0, a0
1109 ; RV32IZHINX-NEXT: addi a0, a0, -1
1110 ; RV32IZHINX-NEXT: and a0, a0, a1
1111 ; RV32IZHINX-NEXT: ret
1112 ;
1113 ; RV64IZHINX-LABEL: test_ceil_ui32:
1114 ; RV64IZHINX: # %bb.0:
1115 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI6_0)
1116 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI6_0)(a1)
1117 ; RV64IZHINX-NEXT: fabs.h a2, a0
1118 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1119 ; RV64IZHINX-NEXT: beqz a1, .LBB6_2
1120 ; RV64IZHINX-NEXT: # %bb.1:
1121 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1122 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1123 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1124 ; RV64IZHINX-NEXT: .LBB6_2:
1125 ; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
1126 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
1127 ; RV64IZHINX-NEXT: seqz a0, a0
1128 ; RV64IZHINX-NEXT: addiw a0, a0, -1
1129 ; RV64IZHINX-NEXT: and a0, a1, a0
1130 ; RV64IZHINX-NEXT: ret
1131 ;
1132 ; RV32IZFHMIN-LABEL: test_ceil_ui32:
1133 ; RV32IZFHMIN: # %bb.0:
1134 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1135 ; RV32IZFHMIN-NEXT: lui a0, 307200
1136 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1137 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1138 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1139 ; RV32IZFHMIN-NEXT: beqz a0, .LBB6_2
1140 ; RV32IZFHMIN-NEXT: # %bb.1:
1141 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1142 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1143 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1144 ; RV32IZFHMIN-NEXT: .LBB6_2:
1145 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1146 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1147 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1148 ; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5
1149 ; RV32IZFHMIN-NEXT: seqz a1, a1
1150 ; RV32IZFHMIN-NEXT: addi a1, a1, -1
1151 ; RV32IZFHMIN-NEXT: and a0, a1, a0
1152 ; RV32IZFHMIN-NEXT: ret
1153 ;
1154 ; RV64IZFHMIN-LABEL: test_ceil_ui32:
1155 ; RV64IZFHMIN: # %bb.0:
1156 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1157 ; RV64IZFHMIN-NEXT: lui a0, 307200
1158 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1159 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1160 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1161 ; RV64IZFHMIN-NEXT: beqz a0, .LBB6_2
1162 ; RV64IZFHMIN-NEXT: # %bb.1:
1163 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1164 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1165 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1166 ; RV64IZFHMIN-NEXT: .LBB6_2:
1167 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1168 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1169 ; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1170 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
1171 ; RV64IZFHMIN-NEXT: seqz a1, a1
1172 ; RV64IZFHMIN-NEXT: addiw a1, a1, -1
1173 ; RV64IZFHMIN-NEXT: and a0, a0, a1
1174 ; RV64IZFHMIN-NEXT: ret
1175 ;
1176 ; RV32IZHINXMIN-LABEL: test_ceil_ui32:
1177 ; RV32IZHINXMIN: # %bb.0:
1178 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1179 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1180 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1181 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1182 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB6_2
1183 ; RV32IZHINXMIN-NEXT: # %bb.1:
1184 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1185 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1186 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1187 ; RV32IZHINXMIN-NEXT: .LBB6_2:
1188 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1189 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1190 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
1191 ; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0
1192 ; RV32IZHINXMIN-NEXT: seqz a0, a0
1193 ; RV32IZHINXMIN-NEXT: addi a0, a0, -1
1194 ; RV32IZHINXMIN-NEXT: and a0, a0, a1
1195 ; RV32IZHINXMIN-NEXT: ret
1196 ;
1197 ; RV64IZHINXMIN-LABEL: test_ceil_ui32:
1198 ; RV64IZHINXMIN: # %bb.0:
1199 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1200 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1201 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1202 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1203 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB6_2
1204 ; RV64IZHINXMIN-NEXT: # %bb.1:
1205 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1206 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1207 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1208 ; RV64IZHINXMIN-NEXT: .LBB6_2:
1209 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1210 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1211 ; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
1212 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
1213 ; RV64IZHINXMIN-NEXT: seqz a0, a0
1214 ; RV64IZHINXMIN-NEXT: addiw a0, a0, -1
1215 ; RV64IZHINXMIN-NEXT: and a0, a1, a0
1216 ; RV64IZHINXMIN-NEXT: ret
1217 %a = call half @llvm.ceil.f16(half %x)
1218 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
1219 ret i32 %b
1220 }
1222 define i64 @test_ceil_ui64(half %x) nounwind {
1223 ; RV32IZFH-LABEL: test_ceil_ui64:
1224 ; RV32IZFH: # %bb.0:
1225 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0)
1226 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0)
1227 ; RV32IZFH-NEXT: fabs.h fa4, fa0
1228 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
1229 ; RV32IZFH-NEXT: beqz a0, .LBB7_2
1230 ; RV32IZFH-NEXT: # %bb.1:
1231 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
1232 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
1233 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
1234 ; RV32IZFH-NEXT: .LBB7_2:
1235 ; RV32IZFH-NEXT: addi sp, sp, -16
1236 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1237 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1238 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
1239 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
1240 ; RV32IZFH-NEXT: fmv.w.x fa5, zero
1241 ; RV32IZFH-NEXT: fle.s a0, fa5, fs0
1242 ; RV32IZFH-NEXT: neg s0, a0
1243 ; RV32IZFH-NEXT: fmv.s fa0, fs0
1244 ; RV32IZFH-NEXT: call __fixunssfdi
1245 ; RV32IZFH-NEXT: lui a2, %hi(.LCPI7_1)
1246 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI7_1)(a2)
1247 ; RV32IZFH-NEXT: and a0, s0, a0
1248 ; RV32IZFH-NEXT: flt.s a2, fa5, fs0
1249 ; RV32IZFH-NEXT: neg a2, a2
1250 ; RV32IZFH-NEXT: or a0, a2, a0
1251 ; RV32IZFH-NEXT: and a1, s0, a1
1252 ; RV32IZFH-NEXT: or a1, a2, a1
1253 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1254 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1255 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
1256 ; RV32IZFH-NEXT: addi sp, sp, 16
1257 ; RV32IZFH-NEXT: ret
1258 ;
1259 ; RV64IZFH-LABEL: test_ceil_ui64:
1260 ; RV64IZFH: # %bb.0:
1261 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
1262 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
1263 ; RV64IZFH-NEXT: seqz a1, a1
1264 ; RV64IZFH-NEXT: addi a1, a1, -1
1265 ; RV64IZFH-NEXT: and a0, a1, a0
1266 ; RV64IZFH-NEXT: ret
1267 ;
1268 ; RV32IZHINX-LABEL: test_ceil_ui64:
1269 ; RV32IZHINX: # %bb.0:
1270 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
1271 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
1272 ; RV32IZHINX-NEXT: fabs.h a2, a0
1273 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1274 ; RV32IZHINX-NEXT: beqz a1, .LBB7_2
1275 ; RV32IZHINX-NEXT: # %bb.1:
1276 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1277 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1278 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1279 ; RV32IZHINX-NEXT: .LBB7_2:
1280 ; RV32IZHINX-NEXT: addi sp, sp, -16
1281 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1282 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1283 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1284 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
1285 ; RV32IZHINX-NEXT: fle.s a0, zero, s0
1286 ; RV32IZHINX-NEXT: neg s1, a0
1287 ; RV32IZHINX-NEXT: mv a0, s0
1288 ; RV32IZHINX-NEXT: call __fixunssfdi
1289 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI7_1)
1290 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI7_1)(a2)
1291 ; RV32IZHINX-NEXT: and a0, s1, a0
1292 ; RV32IZHINX-NEXT: flt.s a2, a2, s0
1293 ; RV32IZHINX-NEXT: neg a2, a2
1294 ; RV32IZHINX-NEXT: or a0, a2, a0
1295 ; RV32IZHINX-NEXT: and a1, s1, a1
1296 ; RV32IZHINX-NEXT: or a1, a2, a1
1297 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1298 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1299 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1300 ; RV32IZHINX-NEXT: addi sp, sp, 16
1301 ; RV32IZHINX-NEXT: ret
1302 ;
1303 ; RV64IZHINX-LABEL: test_ceil_ui64:
1304 ; RV64IZHINX: # %bb.0:
1305 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
1306 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
1307 ; RV64IZHINX-NEXT: fabs.h a2, a0
1308 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1309 ; RV64IZHINX-NEXT: beqz a1, .LBB7_2
1310 ; RV64IZHINX-NEXT: # %bb.1:
1311 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1312 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1313 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1314 ; RV64IZHINX-NEXT: .LBB7_2:
1315 ; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz
1316 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
1317 ; RV64IZHINX-NEXT: seqz a0, a0
1318 ; RV64IZHINX-NEXT: addi a0, a0, -1
1319 ; RV64IZHINX-NEXT: and a0, a0, a1
1320 ; RV64IZHINX-NEXT: ret
1321 ;
1322 ; RV32IZFHMIN-LABEL: test_ceil_ui64:
1323 ; RV32IZFHMIN: # %bb.0:
1324 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1325 ; RV32IZFHMIN-NEXT: lui a0, 307200
1326 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1327 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1328 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1329 ; RV32IZFHMIN-NEXT: beqz a0, .LBB7_2
1330 ; RV32IZFHMIN-NEXT: # %bb.1:
1331 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1332 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1333 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1334 ; RV32IZFHMIN-NEXT: .LBB7_2:
1335 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1336 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1337 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1338 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
1339 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1340 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
1341 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
1342 ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
1343 ; RV32IZFHMIN-NEXT: neg s0, a0
1344 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
1345 ; RV32IZFHMIN-NEXT: call __fixunssfdi
1346 ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI7_0)
1347 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI7_0)(a2)
1348 ; RV32IZFHMIN-NEXT: and a0, s0, a0
1349 ; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0
1350 ; RV32IZFHMIN-NEXT: neg a2, a2
1351 ; RV32IZFHMIN-NEXT: or a0, a2, a0
1352 ; RV32IZFHMIN-NEXT: and a1, s0, a1
1353 ; RV32IZFHMIN-NEXT: or a1, a2, a1
1354 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1355 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1356 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
1357 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1358 ; RV32IZFHMIN-NEXT: ret
1359 ;
1360 ; RV64IZFHMIN-LABEL: test_ceil_ui64:
1361 ; RV64IZFHMIN: # %bb.0:
1362 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1363 ; RV64IZFHMIN-NEXT: lui a0, 307200
1364 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1365 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1366 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1367 ; RV64IZFHMIN-NEXT: beqz a0, .LBB7_2
1368 ; RV64IZFHMIN-NEXT: # %bb.1:
1369 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1370 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1371 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1372 ; RV64IZFHMIN-NEXT: .LBB7_2:
1373 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1374 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1375 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1376 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
1377 ; RV64IZFHMIN-NEXT: seqz a1, a1
1378 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
1379 ; RV64IZFHMIN-NEXT: and a0, a1, a0
1380 ; RV64IZFHMIN-NEXT: ret
1381 ;
1382 ; RV32IZHINXMIN-LABEL: test_ceil_ui64:
1383 ; RV32IZHINXMIN: # %bb.0:
1384 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1385 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1386 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1387 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1388 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB7_2
1389 ; RV32IZHINXMIN-NEXT: # %bb.1:
1390 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1391 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1392 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1393 ; RV32IZHINXMIN-NEXT: .LBB7_2:
1394 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1395 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1396 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1397 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1398 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1399 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
1400 ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0
1401 ; RV32IZHINXMIN-NEXT: neg s1, a0
1402 ; RV32IZHINXMIN-NEXT: mv a0, s0
1403 ; RV32IZHINXMIN-NEXT: call __fixunssfdi
1404 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI7_0)
1405 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI7_0)(a2)
1406 ; RV32IZHINXMIN-NEXT: and a0, s1, a0
1407 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
1408 ; RV32IZHINXMIN-NEXT: neg a2, a2
1409 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
1410 ; RV32IZHINXMIN-NEXT: and a1, s1, a1
1411 ; RV32IZHINXMIN-NEXT: or a1, a2, a1
1412 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1413 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1414 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1415 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1416 ; RV32IZHINXMIN-NEXT: ret
1417 ;
1418 ; RV64IZHINXMIN-LABEL: test_ceil_ui64:
1419 ; RV64IZHINXMIN: # %bb.0:
1420 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1421 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1422 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1423 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1424 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB7_2
1425 ; RV64IZHINXMIN-NEXT: # %bb.1:
1426 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1427 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1428 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1429 ; RV64IZHINXMIN-NEXT: .LBB7_2:
1430 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1431 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1432 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz
1433 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
1434 ; RV64IZHINXMIN-NEXT: seqz a0, a0
1435 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
1436 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
1437 ; RV64IZHINXMIN-NEXT: ret
1438 %a = call half @llvm.ceil.f16(half %x)
1439 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
1440 ret i64 %b
1441 }
1443 define signext i32 @test_trunc_si32(half %x) {
1444 ; CHECKIZFH-LABEL: test_trunc_si32:
1445 ; CHECKIZFH: # %bb.0:
1446 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
1447 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
1448 ; CHECKIZFH-NEXT: seqz a1, a1
1449 ; CHECKIZFH-NEXT: addi a1, a1, -1
1450 ; CHECKIZFH-NEXT: and a0, a1, a0
1451 ; CHECKIZFH-NEXT: ret
1452 ;
1453 ; CHECKIZHINX-LABEL: test_trunc_si32:
1454 ; CHECKIZHINX: # %bb.0:
1455 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI8_0)
1456 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI8_0)(a1)
1457 ; CHECKIZHINX-NEXT: fabs.h a2, a0
1458 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
1459 ; CHECKIZHINX-NEXT: beqz a1, .LBB8_2
1460 ; CHECKIZHINX-NEXT: # %bb.1:
1461 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
1462 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
1463 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
1464 ; CHECKIZHINX-NEXT: .LBB8_2:
1465 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
1466 ; CHECKIZHINX-NEXT: feq.h a0, a0, a0
1467 ; CHECKIZHINX-NEXT: seqz a0, a0
1468 ; CHECKIZHINX-NEXT: addi a0, a0, -1
1469 ; CHECKIZHINX-NEXT: and a0, a0, a1
1470 ; CHECKIZHINX-NEXT: ret
1471 ;
1472 ; CHECKIZFHMIN-LABEL: test_trunc_si32:
1473 ; CHECKIZFHMIN: # %bb.0:
1474 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
1475 ; CHECKIZFHMIN-NEXT: lui a0, 307200
1476 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
1477 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
1478 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
1479 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB8_2
1480 ; CHECKIZFHMIN-NEXT: # %bb.1:
1481 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1482 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1483 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1484 ; CHECKIZFHMIN-NEXT: .LBB8_2:
1485 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
1486 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
1487 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1488 ; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
1489 ; CHECKIZFHMIN-NEXT: seqz a1, a1
1490 ; CHECKIZFHMIN-NEXT: addi a1, a1, -1
1491 ; CHECKIZFHMIN-NEXT: and a0, a1, a0
1492 ; CHECKIZFHMIN-NEXT: ret
1493 ;
1494 ; CHECKIZHINXMIN-LABEL: test_trunc_si32:
1495 ; CHECKIZHINXMIN: # %bb.0:
1496 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1497 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
1498 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
1499 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
1500 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB8_2
1501 ; CHECKIZHINXMIN-NEXT: # %bb.1:
1502 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1503 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1504 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1505 ; CHECKIZHINXMIN-NEXT: .LBB8_2:
1506 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1507 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1508 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1509 ; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0
1510 ; CHECKIZHINXMIN-NEXT: seqz a0, a0
1511 ; CHECKIZHINXMIN-NEXT: addi a0, a0, -1
1512 ; CHECKIZHINXMIN-NEXT: and a0, a0, a1
1513 ; CHECKIZHINXMIN-NEXT: ret
1514 %a = call half @llvm.trunc.f16(half %x)
1515 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
1516 ret i32 %b
1517 }
1519 define i64 @test_trunc_si64(half %x) nounwind {
1520 ; RV32IZFH-LABEL: test_trunc_si64:
1521 ; RV32IZFH: # %bb.0:
1522 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI9_0)
1523 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI9_0)(a0)
1524 ; RV32IZFH-NEXT: fabs.h fa4, fa0
1525 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
1526 ; RV32IZFH-NEXT: beqz a0, .LBB9_2
1527 ; RV32IZFH-NEXT: # %bb.1:
1528 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
1529 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
1530 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
1531 ; RV32IZFH-NEXT: .LBB9_2:
1532 ; RV32IZFH-NEXT: addi sp, sp, -16
1533 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1534 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1535 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
1536 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
1537 ; RV32IZFH-NEXT: lui a0, 913408
1538 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
1539 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
1540 ; RV32IZFH-NEXT: fmv.s fa0, fs0
1541 ; RV32IZFH-NEXT: call __fixsfdi
1542 ; RV32IZFH-NEXT: lui a4, 524288
1543 ; RV32IZFH-NEXT: lui a2, 524288
1544 ; RV32IZFH-NEXT: beqz s0, .LBB9_4
1545 ; RV32IZFH-NEXT: # %bb.3:
1546 ; RV32IZFH-NEXT: mv a2, a1
1547 ; RV32IZFH-NEXT: .LBB9_4:
1548 ; RV32IZFH-NEXT: lui a1, %hi(.LCPI9_1)
1549 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a1)
1550 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
1551 ; RV32IZFH-NEXT: beqz a3, .LBB9_6
1552 ; RV32IZFH-NEXT: # %bb.5:
1553 ; RV32IZFH-NEXT: addi a2, a4, -1
1554 ; RV32IZFH-NEXT: .LBB9_6:
1555 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
1556 ; RV32IZFH-NEXT: neg a4, a1
1557 ; RV32IZFH-NEXT: and a1, a4, a2
1558 ; RV32IZFH-NEXT: neg a2, s0
1559 ; RV32IZFH-NEXT: and a0, a2, a0
1560 ; RV32IZFH-NEXT: neg a2, a3
1561 ; RV32IZFH-NEXT: or a0, a2, a0
1562 ; RV32IZFH-NEXT: and a0, a4, a0
1563 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1564 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1565 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
1566 ; RV32IZFH-NEXT: addi sp, sp, 16
1567 ; RV32IZFH-NEXT: ret
1568 ;
1569 ; RV64IZFH-LABEL: test_trunc_si64:
1570 ; RV64IZFH: # %bb.0:
1571 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
1572 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
1573 ; RV64IZFH-NEXT: seqz a1, a1
1574 ; RV64IZFH-NEXT: addi a1, a1, -1
1575 ; RV64IZFH-NEXT: and a0, a1, a0
1576 ; RV64IZFH-NEXT: ret
1577 ;
1578 ; RV32IZHINX-LABEL: test_trunc_si64:
1579 ; RV32IZHINX: # %bb.0:
1580 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
1581 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
1582 ; RV32IZHINX-NEXT: fabs.h a2, a0
1583 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1584 ; RV32IZHINX-NEXT: beqz a1, .LBB9_2
1585 ; RV32IZHINX-NEXT: # %bb.1:
1586 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1587 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1588 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1589 ; RV32IZHINX-NEXT: .LBB9_2:
1590 ; RV32IZHINX-NEXT: addi sp, sp, -16
1591 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1592 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1593 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1594 ; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1595 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
1596 ; RV32IZHINX-NEXT: lui a0, 913408
1597 ; RV32IZHINX-NEXT: fle.s s1, a0, s0
1598 ; RV32IZHINX-NEXT: neg s2, s1
1599 ; RV32IZHINX-NEXT: mv a0, s0
1600 ; RV32IZHINX-NEXT: call __fixsfdi
1601 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI9_1)
1602 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI9_1)(a2)
1603 ; RV32IZHINX-NEXT: and a0, s2, a0
1604 ; RV32IZHINX-NEXT: flt.s a4, a2, s0
1605 ; RV32IZHINX-NEXT: neg a2, a4
1606 ; RV32IZHINX-NEXT: or a0, a2, a0
1607 ; RV32IZHINX-NEXT: feq.s a2, s0, s0
1608 ; RV32IZHINX-NEXT: neg a2, a2
1609 ; RV32IZHINX-NEXT: lui a5, 524288
1610 ; RV32IZHINX-NEXT: lui a3, 524288
1611 ; RV32IZHINX-NEXT: beqz s1, .LBB9_4
1612 ; RV32IZHINX-NEXT: # %bb.3:
1613 ; RV32IZHINX-NEXT: mv a3, a1
1614 ; RV32IZHINX-NEXT: .LBB9_4:
1615 ; RV32IZHINX-NEXT: and a0, a2, a0
1616 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1617 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1618 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1619 ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1620 ; RV32IZHINX-NEXT: addi sp, sp, 16
1621 ; RV32IZHINX-NEXT: beqz a4, .LBB9_6
1622 ; RV32IZHINX-NEXT: # %bb.5:
1623 ; RV32IZHINX-NEXT: addi a3, a5, -1
1624 ; RV32IZHINX-NEXT: .LBB9_6:
1625 ; RV32IZHINX-NEXT: and a1, a2, a3
1626 ; RV32IZHINX-NEXT: ret
1627 ;
1628 ; RV64IZHINX-LABEL: test_trunc_si64:
1629 ; RV64IZHINX: # %bb.0:
1630 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
1631 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
1632 ; RV64IZHINX-NEXT: fabs.h a2, a0
1633 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1634 ; RV64IZHINX-NEXT: beqz a1, .LBB9_2
1635 ; RV64IZHINX-NEXT: # %bb.1:
1636 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1637 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1638 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1639 ; RV64IZHINX-NEXT: .LBB9_2:
1640 ; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz
1641 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
1642 ; RV64IZHINX-NEXT: seqz a0, a0
1643 ; RV64IZHINX-NEXT: addi a0, a0, -1
1644 ; RV64IZHINX-NEXT: and a0, a0, a1
1645 ; RV64IZHINX-NEXT: ret
1646 ;
1647 ; RV32IZFHMIN-LABEL: test_trunc_si64:
1648 ; RV32IZFHMIN: # %bb.0:
1649 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1650 ; RV32IZFHMIN-NEXT: lui a0, 307200
1651 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1652 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1653 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1654 ; RV32IZFHMIN-NEXT: beqz a0, .LBB9_2
1655 ; RV32IZFHMIN-NEXT: # %bb.1:
1656 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1657 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1658 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1659 ; RV32IZFHMIN-NEXT: .LBB9_2:
1660 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1661 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1662 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1663 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
1664 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1665 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
1666 ; RV32IZFHMIN-NEXT: lui a0, 913408
1667 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
1668 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
1669 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
1670 ; RV32IZFHMIN-NEXT: call __fixsfdi
1671 ; RV32IZFHMIN-NEXT: lui a4, 524288
1672 ; RV32IZFHMIN-NEXT: lui a2, 524288
1673 ; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4
1674 ; RV32IZFHMIN-NEXT: # %bb.3:
1675 ; RV32IZFHMIN-NEXT: mv a2, a1
1676 ; RV32IZFHMIN-NEXT: .LBB9_4:
1677 ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI9_0)
1678 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a1)
1679 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
1680 ; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6
1681 ; RV32IZFHMIN-NEXT: # %bb.5:
1682 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
1683 ; RV32IZFHMIN-NEXT: .LBB9_6:
1684 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
1685 ; RV32IZFHMIN-NEXT: neg a4, a1
1686 ; RV32IZFHMIN-NEXT: and a1, a4, a2
1687 ; RV32IZFHMIN-NEXT: neg a2, s0
1688 ; RV32IZFHMIN-NEXT: and a0, a2, a0
1689 ; RV32IZFHMIN-NEXT: neg a2, a3
1690 ; RV32IZFHMIN-NEXT: or a0, a2, a0
1691 ; RV32IZFHMIN-NEXT: and a0, a4, a0
1692 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1693 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1694 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
1695 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1696 ; RV32IZFHMIN-NEXT: ret
1697 ;
1698 ; RV64IZFHMIN-LABEL: test_trunc_si64:
1699 ; RV64IZFHMIN: # %bb.0:
1700 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1701 ; RV64IZFHMIN-NEXT: lui a0, 307200
1702 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1703 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1704 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1705 ; RV64IZFHMIN-NEXT: beqz a0, .LBB9_2
1706 ; RV64IZFHMIN-NEXT: # %bb.1:
1707 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1708 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1709 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1710 ; RV64IZFHMIN-NEXT: .LBB9_2:
1711 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1712 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1713 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1714 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
1715 ; RV64IZFHMIN-NEXT: seqz a1, a1
1716 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
1717 ; RV64IZFHMIN-NEXT: and a0, a1, a0
1718 ; RV64IZFHMIN-NEXT: ret
1719 ;
1720 ; RV32IZHINXMIN-LABEL: test_trunc_si64:
1721 ; RV32IZHINXMIN: # %bb.0:
1722 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1723 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1724 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1725 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1726 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB9_2
1727 ; RV32IZHINXMIN-NEXT: # %bb.1:
1728 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1729 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1730 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1731 ; RV32IZHINXMIN-NEXT: .LBB9_2:
1732 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1733 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1734 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1735 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1736 ; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1737 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1738 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
1739 ; RV32IZHINXMIN-NEXT: lui a0, 913408
1740 ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0
1741 ; RV32IZHINXMIN-NEXT: neg s2, s1
1742 ; RV32IZHINXMIN-NEXT: mv a0, s0
1743 ; RV32IZHINXMIN-NEXT: call __fixsfdi
1744 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI9_0)
1745 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI9_0)(a2)
1746 ; RV32IZHINXMIN-NEXT: and a0, s2, a0
1747 ; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
1748 ; RV32IZHINXMIN-NEXT: neg a2, a4
1749 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
1750 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0
1751 ; RV32IZHINXMIN-NEXT: neg a2, a2
1752 ; RV32IZHINXMIN-NEXT: lui a5, 524288
1753 ; RV32IZHINXMIN-NEXT: lui a3, 524288
1754 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB9_4
1755 ; RV32IZHINXMIN-NEXT: # %bb.3:
1756 ; RV32IZHINXMIN-NEXT: mv a3, a1
1757 ; RV32IZHINXMIN-NEXT: .LBB9_4:
1758 ; RV32IZHINXMIN-NEXT: and a0, a2, a0
1759 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1760 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1761 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1762 ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1763 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1764 ; RV32IZHINXMIN-NEXT: beqz a4, .LBB9_6
1765 ; RV32IZHINXMIN-NEXT: # %bb.5:
1766 ; RV32IZHINXMIN-NEXT: addi a3, a5, -1
1767 ; RV32IZHINXMIN-NEXT: .LBB9_6:
1768 ; RV32IZHINXMIN-NEXT: and a1, a2, a3
1769 ; RV32IZHINXMIN-NEXT: ret
1770 ;
1771 ; RV64IZHINXMIN-LABEL: test_trunc_si64:
1772 ; RV64IZHINXMIN: # %bb.0:
1773 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1774 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1775 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1776 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1777 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB9_2
1778 ; RV64IZHINXMIN-NEXT: # %bb.1:
1779 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1780 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1781 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1782 ; RV64IZHINXMIN-NEXT: .LBB9_2:
1783 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1784 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1785 ; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz
1786 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
1787 ; RV64IZHINXMIN-NEXT: seqz a0, a0
1788 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
1789 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
1790 ; RV64IZHINXMIN-NEXT: ret
1791 %a = call half @llvm.trunc.f16(half %x)
1792 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
1793 ret i64 %b
1794 }
1796 define signext i32 @test_trunc_ui32(half %x) {
1797 ; CHECKIZFH-LABEL: test_trunc_ui32:
1798 ; CHECKIZFH: # %bb.0:
1799 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
1800 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
1801 ; CHECKIZFH-NEXT: seqz a1, a1
1802 ; CHECKIZFH-NEXT: addi a1, a1, -1
1803 ; CHECKIZFH-NEXT: and a0, a1, a0
1804 ; CHECKIZFH-NEXT: ret
1805 ;
1806 ; RV32IZHINX-LABEL: test_trunc_ui32:
1807 ; RV32IZHINX: # %bb.0:
1808 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI10_0)
1809 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI10_0)(a1)
1810 ; RV32IZHINX-NEXT: fabs.h a2, a0
1811 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1812 ; RV32IZHINX-NEXT: beqz a1, .LBB10_2
1813 ; RV32IZHINX-NEXT: # %bb.1:
1814 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1815 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1816 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1817 ; RV32IZHINX-NEXT: .LBB10_2:
1818 ; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
1819 ; RV32IZHINX-NEXT: feq.h a0, a0, a0
1820 ; RV32IZHINX-NEXT: seqz a0, a0
1821 ; RV32IZHINX-NEXT: addi a0, a0, -1
1822 ; RV32IZHINX-NEXT: and a0, a0, a1
1823 ; RV32IZHINX-NEXT: ret
1824 ;
1825 ; RV64IZHINX-LABEL: test_trunc_ui32:
1826 ; RV64IZHINX: # %bb.0:
1827 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI10_0)
1828 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI10_0)(a1)
1829 ; RV64IZHINX-NEXT: fabs.h a2, a0
1830 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1831 ; RV64IZHINX-NEXT: beqz a1, .LBB10_2
1832 ; RV64IZHINX-NEXT: # %bb.1:
1833 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1834 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1835 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1836 ; RV64IZHINX-NEXT: .LBB10_2:
1837 ; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
1838 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
1839 ; RV64IZHINX-NEXT: seqz a0, a0
1840 ; RV64IZHINX-NEXT: addiw a0, a0, -1
1841 ; RV64IZHINX-NEXT: and a0, a1, a0
1842 ; RV64IZHINX-NEXT: ret
1843 ;
1844 ; RV32IZFHMIN-LABEL: test_trunc_ui32:
1845 ; RV32IZFHMIN: # %bb.0:
1846 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1847 ; RV32IZFHMIN-NEXT: lui a0, 307200
1848 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1849 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1850 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1851 ; RV32IZFHMIN-NEXT: beqz a0, .LBB10_2
1852 ; RV32IZFHMIN-NEXT: # %bb.1:
1853 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1854 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1855 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1856 ; RV32IZFHMIN-NEXT: .LBB10_2:
1857 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1858 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1859 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1860 ; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5
1861 ; RV32IZFHMIN-NEXT: seqz a1, a1
1862 ; RV32IZFHMIN-NEXT: addi a1, a1, -1
1863 ; RV32IZFHMIN-NEXT: and a0, a1, a0
1864 ; RV32IZFHMIN-NEXT: ret
1865 ;
1866 ; RV64IZFHMIN-LABEL: test_trunc_ui32:
1867 ; RV64IZFHMIN: # %bb.0:
1868 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1869 ; RV64IZFHMIN-NEXT: lui a0, 307200
1870 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1871 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1872 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1873 ; RV64IZFHMIN-NEXT: beqz a0, .LBB10_2
1874 ; RV64IZFHMIN-NEXT: # %bb.1:
1875 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1876 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1877 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1878 ; RV64IZFHMIN-NEXT: .LBB10_2:
1879 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1880 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1881 ; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1882 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
1883 ; RV64IZFHMIN-NEXT: seqz a1, a1
1884 ; RV64IZFHMIN-NEXT: addiw a1, a1, -1
1885 ; RV64IZFHMIN-NEXT: and a0, a0, a1
1886 ; RV64IZFHMIN-NEXT: ret
1887 ;
1888 ; RV32IZHINXMIN-LABEL: test_trunc_ui32:
1889 ; RV32IZHINXMIN: # %bb.0:
1890 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1891 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1892 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1893 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1894 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB10_2
1895 ; RV32IZHINXMIN-NEXT: # %bb.1:
1896 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1897 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1898 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1899 ; RV32IZHINXMIN-NEXT: .LBB10_2:
1900 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1901 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1902 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
1903 ; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0
1904 ; RV32IZHINXMIN-NEXT: seqz a0, a0
1905 ; RV32IZHINXMIN-NEXT: addi a0, a0, -1
1906 ; RV32IZHINXMIN-NEXT: and a0, a0, a1
1907 ; RV32IZHINXMIN-NEXT: ret
1908 ;
1909 ; RV64IZHINXMIN-LABEL: test_trunc_ui32:
1910 ; RV64IZHINXMIN: # %bb.0:
1911 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1912 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1913 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1914 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1915 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB10_2
1916 ; RV64IZHINXMIN-NEXT: # %bb.1:
1917 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1918 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1919 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1920 ; RV64IZHINXMIN-NEXT: .LBB10_2:
1921 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1922 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1923 ; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
1924 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
1925 ; RV64IZHINXMIN-NEXT: seqz a0, a0
1926 ; RV64IZHINXMIN-NEXT: addiw a0, a0, -1
1927 ; RV64IZHINXMIN-NEXT: and a0, a1, a0
1928 ; RV64IZHINXMIN-NEXT: ret
1929 %a = call half @llvm.trunc.f16(half %x)
1930 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
1931 ret i32 %b
1932 }
1934 define i64 @test_trunc_ui64(half %x) nounwind {
1935 ; RV32IZFH-LABEL: test_trunc_ui64:
1936 ; RV32IZFH: # %bb.0:
1937 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0)
1938 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
1939 ; RV32IZFH-NEXT: fabs.h fa4, fa0
1940 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
1941 ; RV32IZFH-NEXT: beqz a0, .LBB11_2
1942 ; RV32IZFH-NEXT: # %bb.1:
1943 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
1944 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
1945 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
1946 ; RV32IZFH-NEXT: .LBB11_2:
1947 ; RV32IZFH-NEXT: addi sp, sp, -16
1948 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1949 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1950 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
1951 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
1952 ; RV32IZFH-NEXT: fmv.w.x fa5, zero
1953 ; RV32IZFH-NEXT: fle.s a0, fa5, fs0
1954 ; RV32IZFH-NEXT: neg s0, a0
1955 ; RV32IZFH-NEXT: fmv.s fa0, fs0
1956 ; RV32IZFH-NEXT: call __fixunssfdi
1957 ; RV32IZFH-NEXT: lui a2, %hi(.LCPI11_1)
1958 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI11_1)(a2)
1959 ; RV32IZFH-NEXT: and a0, s0, a0
1960 ; RV32IZFH-NEXT: flt.s a2, fa5, fs0
1961 ; RV32IZFH-NEXT: neg a2, a2
1962 ; RV32IZFH-NEXT: or a0, a2, a0
1963 ; RV32IZFH-NEXT: and a1, s0, a1
1964 ; RV32IZFH-NEXT: or a1, a2, a1
1965 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1966 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1967 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
1968 ; RV32IZFH-NEXT: addi sp, sp, 16
1969 ; RV32IZFH-NEXT: ret
1970 ;
1971 ; RV64IZFH-LABEL: test_trunc_ui64:
1972 ; RV64IZFH: # %bb.0:
1973 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
1974 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
1975 ; RV64IZFH-NEXT: seqz a1, a1
1976 ; RV64IZFH-NEXT: addi a1, a1, -1
1977 ; RV64IZFH-NEXT: and a0, a1, a0
1978 ; RV64IZFH-NEXT: ret
1979 ;
1980 ; RV32IZHINX-LABEL: test_trunc_ui64:
1981 ; RV32IZHINX: # %bb.0:
1982 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
1983 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
1984 ; RV32IZHINX-NEXT: fabs.h a2, a0
1985 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1986 ; RV32IZHINX-NEXT: beqz a1, .LBB11_2
1987 ; RV32IZHINX-NEXT: # %bb.1:
1988 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1989 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1990 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1991 ; RV32IZHINX-NEXT: .LBB11_2:
1992 ; RV32IZHINX-NEXT: addi sp, sp, -16
1993 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1994 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1995 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1996 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
1997 ; RV32IZHINX-NEXT: fle.s a0, zero, s0
1998 ; RV32IZHINX-NEXT: neg s1, a0
1999 ; RV32IZHINX-NEXT: mv a0, s0
2000 ; RV32IZHINX-NEXT: call __fixunssfdi
2001 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI11_1)
2002 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI11_1)(a2)
2003 ; RV32IZHINX-NEXT: and a0, s1, a0
2004 ; RV32IZHINX-NEXT: flt.s a2, a2, s0
2005 ; RV32IZHINX-NEXT: neg a2, a2
2006 ; RV32IZHINX-NEXT: or a0, a2, a0
2007 ; RV32IZHINX-NEXT: and a1, s1, a1
2008 ; RV32IZHINX-NEXT: or a1, a2, a1
2009 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2010 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2011 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2012 ; RV32IZHINX-NEXT: addi sp, sp, 16
2013 ; RV32IZHINX-NEXT: ret
2014 ;
2015 ; RV64IZHINX-LABEL: test_trunc_ui64:
2016 ; RV64IZHINX: # %bb.0:
2017 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
2018 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
2019 ; RV64IZHINX-NEXT: fabs.h a2, a0
2020 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2021 ; RV64IZHINX-NEXT: beqz a1, .LBB11_2
2022 ; RV64IZHINX-NEXT: # %bb.1:
2023 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2024 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2025 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2026 ; RV64IZHINX-NEXT: .LBB11_2:
2027 ; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz
2028 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
2029 ; RV64IZHINX-NEXT: seqz a0, a0
2030 ; RV64IZHINX-NEXT: addi a0, a0, -1
2031 ; RV64IZHINX-NEXT: and a0, a0, a1
2032 ; RV64IZHINX-NEXT: ret
2033 ;
2034 ; RV32IZFHMIN-LABEL: test_trunc_ui64:
2035 ; RV32IZFHMIN: # %bb.0:
2036 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2037 ; RV32IZFHMIN-NEXT: lui a0, 307200
2038 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2039 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2040 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2041 ; RV32IZFHMIN-NEXT: beqz a0, .LBB11_2
2042 ; RV32IZFHMIN-NEXT: # %bb.1:
2043 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2044 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2045 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2046 ; RV32IZFHMIN-NEXT: .LBB11_2:
2047 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2048 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2049 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2050 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
2051 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2052 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
2053 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
2054 ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
2055 ; RV32IZFHMIN-NEXT: neg s0, a0
2056 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
2057 ; RV32IZFHMIN-NEXT: call __fixunssfdi
2058 ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI11_0)
2059 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI11_0)(a2)
2060 ; RV32IZFHMIN-NEXT: and a0, s0, a0
2061 ; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0
2062 ; RV32IZFHMIN-NEXT: neg a2, a2
2063 ; RV32IZFHMIN-NEXT: or a0, a2, a0
2064 ; RV32IZFHMIN-NEXT: and a1, s0, a1
2065 ; RV32IZFHMIN-NEXT: or a1, a2, a1
2066 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2067 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2068 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
2069 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2070 ; RV32IZFHMIN-NEXT: ret
2071 ;
2072 ; RV64IZFHMIN-LABEL: test_trunc_ui64:
2073 ; RV64IZFHMIN: # %bb.0:
2074 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2075 ; RV64IZFHMIN-NEXT: lui a0, 307200
2076 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2077 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2078 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2079 ; RV64IZFHMIN-NEXT: beqz a0, .LBB11_2
2080 ; RV64IZFHMIN-NEXT: # %bb.1:
2081 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2082 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2083 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2084 ; RV64IZFHMIN-NEXT: .LBB11_2:
2085 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2086 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2087 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2088 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
2089 ; RV64IZFHMIN-NEXT: seqz a1, a1
2090 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
2091 ; RV64IZFHMIN-NEXT: and a0, a1, a0
2092 ; RV64IZFHMIN-NEXT: ret
2093 ;
2094 ; RV32IZHINXMIN-LABEL: test_trunc_ui64:
2095 ; RV32IZHINXMIN: # %bb.0:
2096 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2097 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2098 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2099 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2100 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB11_2
2101 ; RV32IZHINXMIN-NEXT: # %bb.1:
2102 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2103 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2104 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2105 ; RV32IZHINXMIN-NEXT: .LBB11_2:
2106 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2107 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2108 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2109 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
2110 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2111 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
2112 ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0
2113 ; RV32IZHINXMIN-NEXT: neg s1, a0
2114 ; RV32IZHINXMIN-NEXT: mv a0, s0
2115 ; RV32IZHINXMIN-NEXT: call __fixunssfdi
2116 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI11_0)
2117 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI11_0)(a2)
2118 ; RV32IZHINXMIN-NEXT: and a0, s1, a0
2119 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
2120 ; RV32IZHINXMIN-NEXT: neg a2, a2
2121 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
2122 ; RV32IZHINXMIN-NEXT: and a1, s1, a1
2123 ; RV32IZHINXMIN-NEXT: or a1, a2, a1
2124 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2125 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2126 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2127 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2128 ; RV32IZHINXMIN-NEXT: ret
2129 ;
2130 ; RV64IZHINXMIN-LABEL: test_trunc_ui64:
2131 ; RV64IZHINXMIN: # %bb.0:
2132 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2133 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2134 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2135 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2136 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB11_2
2137 ; RV64IZHINXMIN-NEXT: # %bb.1:
2138 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2139 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2140 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2141 ; RV64IZHINXMIN-NEXT: .LBB11_2:
2142 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2143 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2144 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz
2145 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
2146 ; RV64IZHINXMIN-NEXT: seqz a0, a0
2147 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
2148 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
2149 ; RV64IZHINXMIN-NEXT: ret
2150 %a = call half @llvm.trunc.f16(half %x)
2151 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
2152 ret i64 %b
2153 }
2155 define signext i32 @test_round_si32(half %x) {
2156 ; CHECKIZFH-LABEL: test_round_si32:
2157 ; CHECKIZFH: # %bb.0:
2158 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
2159 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
2160 ; CHECKIZFH-NEXT: seqz a1, a1
2161 ; CHECKIZFH-NEXT: addi a1, a1, -1
2162 ; CHECKIZFH-NEXT: and a0, a1, a0
2163 ; CHECKIZFH-NEXT: ret
2164 ;
2165 ; CHECKIZHINX-LABEL: test_round_si32:
2166 ; CHECKIZHINX: # %bb.0:
2167 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI12_0)
2168 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI12_0)(a1)
2169 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2170 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2171 ; CHECKIZHINX-NEXT: beqz a1, .LBB12_2
2172 ; CHECKIZHINX-NEXT: # %bb.1:
2173 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
2174 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
2175 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2176 ; CHECKIZHINX-NEXT: .LBB12_2:
2177 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2178 ; CHECKIZHINX-NEXT: feq.h a0, a0, a0
2179 ; CHECKIZHINX-NEXT: seqz a0, a0
2180 ; CHECKIZHINX-NEXT: addi a0, a0, -1
2181 ; CHECKIZHINX-NEXT: and a0, a0, a1
2182 ; CHECKIZHINX-NEXT: ret
2183 ;
2184 ; CHECKIZFHMIN-LABEL: test_round_si32:
2185 ; CHECKIZFHMIN: # %bb.0:
2186 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2187 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2188 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2189 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2190 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2191 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB12_2
2192 ; CHECKIZFHMIN-NEXT: # %bb.1:
2193 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2194 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2195 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2196 ; CHECKIZFHMIN-NEXT: .LBB12_2:
2197 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2198 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2199 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2200 ; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
2201 ; CHECKIZFHMIN-NEXT: seqz a1, a1
2202 ; CHECKIZFHMIN-NEXT: addi a1, a1, -1
2203 ; CHECKIZFHMIN-NEXT: and a0, a1, a0
2204 ; CHECKIZFHMIN-NEXT: ret
2205 ;
2206 ; CHECKIZHINXMIN-LABEL: test_round_si32:
2207 ; CHECKIZHINXMIN: # %bb.0:
2208 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2209 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2210 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2211 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2212 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB12_2
2213 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2214 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2215 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2216 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2217 ; CHECKIZHINXMIN-NEXT: .LBB12_2:
2218 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2219 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2220 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2221 ; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0
2222 ; CHECKIZHINXMIN-NEXT: seqz a0, a0
2223 ; CHECKIZHINXMIN-NEXT: addi a0, a0, -1
2224 ; CHECKIZHINXMIN-NEXT: and a0, a0, a1
2225 ; CHECKIZHINXMIN-NEXT: ret
2226 %a = call half @llvm.round.f16(half %x)
2227 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
2228 ret i32 %b
2229 }
2231 define i64 @test_round_si64(half %x) nounwind {
2232 ; RV32IZFH-LABEL: test_round_si64:
2233 ; RV32IZFH: # %bb.0:
2234 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI13_0)
2235 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI13_0)(a0)
2236 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2237 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2238 ; RV32IZFH-NEXT: beqz a0, .LBB13_2
2239 ; RV32IZFH-NEXT: # %bb.1:
2240 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2241 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
2242 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2243 ; RV32IZFH-NEXT: .LBB13_2:
2244 ; RV32IZFH-NEXT: addi sp, sp, -16
2245 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2246 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2247 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
2248 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
2249 ; RV32IZFH-NEXT: lui a0, 913408
2250 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
2251 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
2252 ; RV32IZFH-NEXT: fmv.s fa0, fs0
2253 ; RV32IZFH-NEXT: call __fixsfdi
2254 ; RV32IZFH-NEXT: lui a4, 524288
2255 ; RV32IZFH-NEXT: lui a2, 524288
2256 ; RV32IZFH-NEXT: beqz s0, .LBB13_4
2257 ; RV32IZFH-NEXT: # %bb.3:
2258 ; RV32IZFH-NEXT: mv a2, a1
2259 ; RV32IZFH-NEXT: .LBB13_4:
2260 ; RV32IZFH-NEXT: lui a1, %hi(.LCPI13_1)
2261 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a1)
2262 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
2263 ; RV32IZFH-NEXT: beqz a3, .LBB13_6
2264 ; RV32IZFH-NEXT: # %bb.5:
2265 ; RV32IZFH-NEXT: addi a2, a4, -1
2266 ; RV32IZFH-NEXT: .LBB13_6:
2267 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
2268 ; RV32IZFH-NEXT: neg a4, a1
2269 ; RV32IZFH-NEXT: and a1, a4, a2
2270 ; RV32IZFH-NEXT: neg a2, s0
2271 ; RV32IZFH-NEXT: and a0, a2, a0
2272 ; RV32IZFH-NEXT: neg a2, a3
2273 ; RV32IZFH-NEXT: or a0, a2, a0
2274 ; RV32IZFH-NEXT: and a0, a4, a0
2275 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2276 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2277 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
2278 ; RV32IZFH-NEXT: addi sp, sp, 16
2279 ; RV32IZFH-NEXT: ret
2280 ;
2281 ; RV64IZFH-LABEL: test_round_si64:
2282 ; RV64IZFH: # %bb.0:
2283 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
2284 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
2285 ; RV64IZFH-NEXT: seqz a1, a1
2286 ; RV64IZFH-NEXT: addi a1, a1, -1
2287 ; RV64IZFH-NEXT: and a0, a1, a0
2288 ; RV64IZFH-NEXT: ret
2289 ;
2290 ; RV32IZHINX-LABEL: test_round_si64:
2291 ; RV32IZHINX: # %bb.0:
2292 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
2293 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
2294 ; RV32IZHINX-NEXT: fabs.h a2, a0
2295 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2296 ; RV32IZHINX-NEXT: beqz a1, .LBB13_2
2297 ; RV32IZHINX-NEXT: # %bb.1:
2298 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2299 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2300 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2301 ; RV32IZHINX-NEXT: .LBB13_2:
2302 ; RV32IZHINX-NEXT: addi sp, sp, -16
2303 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2304 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2305 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
2306 ; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
2307 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
2308 ; RV32IZHINX-NEXT: lui a0, 913408
2309 ; RV32IZHINX-NEXT: fle.s s1, a0, s0
2310 ; RV32IZHINX-NEXT: neg s2, s1
2311 ; RV32IZHINX-NEXT: mv a0, s0
2312 ; RV32IZHINX-NEXT: call __fixsfdi
2313 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI13_1)
2314 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI13_1)(a2)
2315 ; RV32IZHINX-NEXT: and a0, s2, a0
2316 ; RV32IZHINX-NEXT: flt.s a4, a2, s0
2317 ; RV32IZHINX-NEXT: neg a2, a4
2318 ; RV32IZHINX-NEXT: or a0, a2, a0
2319 ; RV32IZHINX-NEXT: feq.s a2, s0, s0
2320 ; RV32IZHINX-NEXT: neg a2, a2
2321 ; RV32IZHINX-NEXT: lui a5, 524288
2322 ; RV32IZHINX-NEXT: lui a3, 524288
2323 ; RV32IZHINX-NEXT: beqz s1, .LBB13_4
2324 ; RV32IZHINX-NEXT: # %bb.3:
2325 ; RV32IZHINX-NEXT: mv a3, a1
2326 ; RV32IZHINX-NEXT: .LBB13_4:
2327 ; RV32IZHINX-NEXT: and a0, a2, a0
2328 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2329 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2330 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2331 ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
2332 ; RV32IZHINX-NEXT: addi sp, sp, 16
2333 ; RV32IZHINX-NEXT: beqz a4, .LBB13_6
2334 ; RV32IZHINX-NEXT: # %bb.5:
2335 ; RV32IZHINX-NEXT: addi a3, a5, -1
2336 ; RV32IZHINX-NEXT: .LBB13_6:
2337 ; RV32IZHINX-NEXT: and a1, a2, a3
2338 ; RV32IZHINX-NEXT: ret
2339 ;
2340 ; RV64IZHINX-LABEL: test_round_si64:
2341 ; RV64IZHINX: # %bb.0:
2342 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
2343 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
2344 ; RV64IZHINX-NEXT: fabs.h a2, a0
2345 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2346 ; RV64IZHINX-NEXT: beqz a1, .LBB13_2
2347 ; RV64IZHINX-NEXT: # %bb.1:
2348 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2349 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2350 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2351 ; RV64IZHINX-NEXT: .LBB13_2:
2352 ; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz
2353 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
2354 ; RV64IZHINX-NEXT: seqz a0, a0
2355 ; RV64IZHINX-NEXT: addi a0, a0, -1
2356 ; RV64IZHINX-NEXT: and a0, a0, a1
2357 ; RV64IZHINX-NEXT: ret
2358 ;
2359 ; RV32IZFHMIN-LABEL: test_round_si64:
2360 ; RV32IZFHMIN: # %bb.0:
2361 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2362 ; RV32IZFHMIN-NEXT: lui a0, 307200
2363 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2364 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2365 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2366 ; RV32IZFHMIN-NEXT: beqz a0, .LBB13_2
2367 ; RV32IZFHMIN-NEXT: # %bb.1:
2368 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2369 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2370 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2371 ; RV32IZFHMIN-NEXT: .LBB13_2:
2372 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2373 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2374 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2375 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
2376 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2377 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
2378 ; RV32IZFHMIN-NEXT: lui a0, 913408
2379 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
2380 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
2381 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
2382 ; RV32IZFHMIN-NEXT: call __fixsfdi
2383 ; RV32IZFHMIN-NEXT: lui a4, 524288
2384 ; RV32IZFHMIN-NEXT: lui a2, 524288
2385 ; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4
2386 ; RV32IZFHMIN-NEXT: # %bb.3:
2387 ; RV32IZFHMIN-NEXT: mv a2, a1
2388 ; RV32IZFHMIN-NEXT: .LBB13_4:
2389 ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI13_0)
2390 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a1)
2391 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
2392 ; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6
2393 ; RV32IZFHMIN-NEXT: # %bb.5:
2394 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
2395 ; RV32IZFHMIN-NEXT: .LBB13_6:
2396 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
2397 ; RV32IZFHMIN-NEXT: neg a4, a1
2398 ; RV32IZFHMIN-NEXT: and a1, a4, a2
2399 ; RV32IZFHMIN-NEXT: neg a2, s0
2400 ; RV32IZFHMIN-NEXT: and a0, a2, a0
2401 ; RV32IZFHMIN-NEXT: neg a2, a3
2402 ; RV32IZFHMIN-NEXT: or a0, a2, a0
2403 ; RV32IZFHMIN-NEXT: and a0, a4, a0
2404 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2405 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2406 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
2407 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2408 ; RV32IZFHMIN-NEXT: ret
2409 ;
2410 ; RV64IZFHMIN-LABEL: test_round_si64:
2411 ; RV64IZFHMIN: # %bb.0:
2412 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2413 ; RV64IZFHMIN-NEXT: lui a0, 307200
2414 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2415 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2416 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2417 ; RV64IZFHMIN-NEXT: beqz a0, .LBB13_2
2418 ; RV64IZFHMIN-NEXT: # %bb.1:
2419 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2420 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2421 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2422 ; RV64IZFHMIN-NEXT: .LBB13_2:
2423 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2424 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2425 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
2426 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
2427 ; RV64IZFHMIN-NEXT: seqz a1, a1
2428 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
2429 ; RV64IZFHMIN-NEXT: and a0, a1, a0
2430 ; RV64IZFHMIN-NEXT: ret
2431 ;
2432 ; RV32IZHINXMIN-LABEL: test_round_si64:
2433 ; RV32IZHINXMIN: # %bb.0:
2434 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2435 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2436 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2437 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2438 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB13_2
2439 ; RV32IZHINXMIN-NEXT: # %bb.1:
2440 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2441 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2442 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2443 ; RV32IZHINXMIN-NEXT: .LBB13_2:
2444 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2445 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2446 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2447 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
2448 ; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
2449 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2450 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
2451 ; RV32IZHINXMIN-NEXT: lui a0, 913408
2452 ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0
2453 ; RV32IZHINXMIN-NEXT: neg s2, s1
2454 ; RV32IZHINXMIN-NEXT: mv a0, s0
2455 ; RV32IZHINXMIN-NEXT: call __fixsfdi
2456 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI13_0)
2457 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI13_0)(a2)
2458 ; RV32IZHINXMIN-NEXT: and a0, s2, a0
2459 ; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
2460 ; RV32IZHINXMIN-NEXT: neg a2, a4
2461 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
2462 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0
2463 ; RV32IZHINXMIN-NEXT: neg a2, a2
2464 ; RV32IZHINXMIN-NEXT: lui a5, 524288
2465 ; RV32IZHINXMIN-NEXT: lui a3, 524288
2466 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB13_4
2467 ; RV32IZHINXMIN-NEXT: # %bb.3:
2468 ; RV32IZHINXMIN-NEXT: mv a3, a1
2469 ; RV32IZHINXMIN-NEXT: .LBB13_4:
2470 ; RV32IZHINXMIN-NEXT: and a0, a2, a0
2471 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2472 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2473 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2474 ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
2475 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2476 ; RV32IZHINXMIN-NEXT: beqz a4, .LBB13_6
2477 ; RV32IZHINXMIN-NEXT: # %bb.5:
2478 ; RV32IZHINXMIN-NEXT: addi a3, a5, -1
2479 ; RV32IZHINXMIN-NEXT: .LBB13_6:
2480 ; RV32IZHINXMIN-NEXT: and a1, a2, a3
2481 ; RV32IZHINXMIN-NEXT: ret
2482 ;
2483 ; RV64IZHINXMIN-LABEL: test_round_si64:
2484 ; RV64IZHINXMIN: # %bb.0:
2485 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2486 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2487 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2488 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2489 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB13_2
2490 ; RV64IZHINXMIN-NEXT: # %bb.1:
2491 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2492 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2493 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2494 ; RV64IZHINXMIN-NEXT: .LBB13_2:
2495 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2496 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2497 ; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz
2498 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
2499 ; RV64IZHINXMIN-NEXT: seqz a0, a0
2500 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
2501 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
2502 ; RV64IZHINXMIN-NEXT: ret
2503 %a = call half @llvm.round.f16(half %x)
2504 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
2505 ret i64 %b
2506 }
2508 define signext i32 @test_round_ui32(half %x) {
2509 ; CHECKIZFH-LABEL: test_round_ui32:
2510 ; CHECKIZFH: # %bb.0:
2511 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rmm
2512 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
2513 ; CHECKIZFH-NEXT: seqz a1, a1
2514 ; CHECKIZFH-NEXT: addi a1, a1, -1
2515 ; CHECKIZFH-NEXT: and a0, a1, a0
2516 ; CHECKIZFH-NEXT: ret
2517 ;
2518 ; RV32IZHINX-LABEL: test_round_ui32:
2519 ; RV32IZHINX: # %bb.0:
2520 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI14_0)
2521 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI14_0)(a1)
2522 ; RV32IZHINX-NEXT: fabs.h a2, a0
2523 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2524 ; RV32IZHINX-NEXT: beqz a1, .LBB14_2
2525 ; RV32IZHINX-NEXT: # %bb.1:
2526 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2527 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2528 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2529 ; RV32IZHINX-NEXT: .LBB14_2:
2530 ; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
2531 ; RV32IZHINX-NEXT: feq.h a0, a0, a0
2532 ; RV32IZHINX-NEXT: seqz a0, a0
2533 ; RV32IZHINX-NEXT: addi a0, a0, -1
2534 ; RV32IZHINX-NEXT: and a0, a0, a1
2535 ; RV32IZHINX-NEXT: ret
2536 ;
2537 ; RV64IZHINX-LABEL: test_round_ui32:
2538 ; RV64IZHINX: # %bb.0:
2539 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI14_0)
2540 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI14_0)(a1)
2541 ; RV64IZHINX-NEXT: fabs.h a2, a0
2542 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2543 ; RV64IZHINX-NEXT: beqz a1, .LBB14_2
2544 ; RV64IZHINX-NEXT: # %bb.1:
2545 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2546 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2547 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2548 ; RV64IZHINX-NEXT: .LBB14_2:
2549 ; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
2550 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
2551 ; RV64IZHINX-NEXT: seqz a0, a0
2552 ; RV64IZHINX-NEXT: addiw a0, a0, -1
2553 ; RV64IZHINX-NEXT: and a0, a1, a0
2554 ; RV64IZHINX-NEXT: ret
2555 ;
2556 ; RV32IZFHMIN-LABEL: test_round_ui32:
2557 ; RV32IZFHMIN: # %bb.0:
2558 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2559 ; RV32IZFHMIN-NEXT: lui a0, 307200
2560 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2561 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2562 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2563 ; RV32IZFHMIN-NEXT: beqz a0, .LBB14_2
2564 ; RV32IZFHMIN-NEXT: # %bb.1:
2565 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2566 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2567 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2568 ; RV32IZFHMIN-NEXT: .LBB14_2:
2569 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2570 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2571 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2572 ; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5
2573 ; RV32IZFHMIN-NEXT: seqz a1, a1
2574 ; RV32IZFHMIN-NEXT: addi a1, a1, -1
2575 ; RV32IZFHMIN-NEXT: and a0, a1, a0
2576 ; RV32IZFHMIN-NEXT: ret
2577 ;
2578 ; RV64IZFHMIN-LABEL: test_round_ui32:
2579 ; RV64IZFHMIN: # %bb.0:
2580 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2581 ; RV64IZFHMIN-NEXT: lui a0, 307200
2582 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2583 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2584 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2585 ; RV64IZFHMIN-NEXT: beqz a0, .LBB14_2
2586 ; RV64IZFHMIN-NEXT: # %bb.1:
2587 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2588 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2589 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2590 ; RV64IZFHMIN-NEXT: .LBB14_2:
2591 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2592 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2593 ; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2594 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
2595 ; RV64IZFHMIN-NEXT: seqz a1, a1
2596 ; RV64IZFHMIN-NEXT: addiw a1, a1, -1
2597 ; RV64IZFHMIN-NEXT: and a0, a0, a1
2598 ; RV64IZFHMIN-NEXT: ret
2599 ;
2600 ; RV32IZHINXMIN-LABEL: test_round_ui32:
2601 ; RV32IZHINXMIN: # %bb.0:
2602 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2603 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2604 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2605 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2606 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB14_2
2607 ; RV32IZHINXMIN-NEXT: # %bb.1:
2608 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2609 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2610 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2611 ; RV32IZHINXMIN-NEXT: .LBB14_2:
2612 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2613 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2614 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
2615 ; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0
2616 ; RV32IZHINXMIN-NEXT: seqz a0, a0
2617 ; RV32IZHINXMIN-NEXT: addi a0, a0, -1
2618 ; RV32IZHINXMIN-NEXT: and a0, a0, a1
2619 ; RV32IZHINXMIN-NEXT: ret
2620 ;
2621 ; RV64IZHINXMIN-LABEL: test_round_ui32:
2622 ; RV64IZHINXMIN: # %bb.0:
2623 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2624 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2625 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2626 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2627 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB14_2
2628 ; RV64IZHINXMIN-NEXT: # %bb.1:
2629 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2630 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2631 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2632 ; RV64IZHINXMIN-NEXT: .LBB14_2:
2633 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2634 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2635 ; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
2636 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
2637 ; RV64IZHINXMIN-NEXT: seqz a0, a0
2638 ; RV64IZHINXMIN-NEXT: addiw a0, a0, -1
2639 ; RV64IZHINXMIN-NEXT: and a0, a1, a0
2640 ; RV64IZHINXMIN-NEXT: ret
2641 %a = call half @llvm.round.f16(half %x)
2642 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
2643 ret i32 %b
2644 }
2646 define i64 @test_round_ui64(half %x) nounwind {
2647 ; RV32IZFH-LABEL: test_round_ui64:
2648 ; RV32IZFH: # %bb.0:
2649 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0)
2650 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI15_0)(a0)
2651 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2652 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2653 ; RV32IZFH-NEXT: beqz a0, .LBB15_2
2654 ; RV32IZFH-NEXT: # %bb.1:
2655 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2656 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
2657 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2658 ; RV32IZFH-NEXT: .LBB15_2:
2659 ; RV32IZFH-NEXT: addi sp, sp, -16
2660 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2661 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2662 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
2663 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
2664 ; RV32IZFH-NEXT: fmv.w.x fa5, zero
2665 ; RV32IZFH-NEXT: fle.s a0, fa5, fs0
2666 ; RV32IZFH-NEXT: neg s0, a0
2667 ; RV32IZFH-NEXT: fmv.s fa0, fs0
2668 ; RV32IZFH-NEXT: call __fixunssfdi
2669 ; RV32IZFH-NEXT: lui a2, %hi(.LCPI15_1)
2670 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI15_1)(a2)
2671 ; RV32IZFH-NEXT: and a0, s0, a0
2672 ; RV32IZFH-NEXT: flt.s a2, fa5, fs0
2673 ; RV32IZFH-NEXT: neg a2, a2
2674 ; RV32IZFH-NEXT: or a0, a2, a0
2675 ; RV32IZFH-NEXT: and a1, s0, a1
2676 ; RV32IZFH-NEXT: or a1, a2, a1
2677 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2678 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2679 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
2680 ; RV32IZFH-NEXT: addi sp, sp, 16
2681 ; RV32IZFH-NEXT: ret
2682 ;
2683 ; RV64IZFH-LABEL: test_round_ui64:
2684 ; RV64IZFH: # %bb.0:
2685 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
2686 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
2687 ; RV64IZFH-NEXT: seqz a1, a1
2688 ; RV64IZFH-NEXT: addi a1, a1, -1
2689 ; RV64IZFH-NEXT: and a0, a1, a0
2690 ; RV64IZFH-NEXT: ret
2691 ;
2692 ; RV32IZHINX-LABEL: test_round_ui64:
2693 ; RV32IZHINX: # %bb.0:
2694 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
2695 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
2696 ; RV32IZHINX-NEXT: fabs.h a2, a0
2697 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2698 ; RV32IZHINX-NEXT: beqz a1, .LBB15_2
2699 ; RV32IZHINX-NEXT: # %bb.1:
2700 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2701 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2702 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2703 ; RV32IZHINX-NEXT: .LBB15_2:
2704 ; RV32IZHINX-NEXT: addi sp, sp, -16
2705 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2706 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2707 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
2708 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
2709 ; RV32IZHINX-NEXT: fle.s a0, zero, s0
2710 ; RV32IZHINX-NEXT: neg s1, a0
2711 ; RV32IZHINX-NEXT: mv a0, s0
2712 ; RV32IZHINX-NEXT: call __fixunssfdi
2713 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI15_1)
2714 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI15_1)(a2)
2715 ; RV32IZHINX-NEXT: and a0, s1, a0
2716 ; RV32IZHINX-NEXT: flt.s a2, a2, s0
2717 ; RV32IZHINX-NEXT: neg a2, a2
2718 ; RV32IZHINX-NEXT: or a0, a2, a0
2719 ; RV32IZHINX-NEXT: and a1, s1, a1
2720 ; RV32IZHINX-NEXT: or a1, a2, a1
2721 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2722 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2723 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2724 ; RV32IZHINX-NEXT: addi sp, sp, 16
2725 ; RV32IZHINX-NEXT: ret
2726 ;
2727 ; RV64IZHINX-LABEL: test_round_ui64:
2728 ; RV64IZHINX: # %bb.0:
2729 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
2730 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
2731 ; RV64IZHINX-NEXT: fabs.h a2, a0
2732 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2733 ; RV64IZHINX-NEXT: beqz a1, .LBB15_2
2734 ; RV64IZHINX-NEXT: # %bb.1:
2735 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2736 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2737 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2738 ; RV64IZHINX-NEXT: .LBB15_2:
2739 ; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz
2740 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
2741 ; RV64IZHINX-NEXT: seqz a0, a0
2742 ; RV64IZHINX-NEXT: addi a0, a0, -1
2743 ; RV64IZHINX-NEXT: and a0, a0, a1
2744 ; RV64IZHINX-NEXT: ret
2745 ;
2746 ; RV32IZFHMIN-LABEL: test_round_ui64:
2747 ; RV32IZFHMIN: # %bb.0:
2748 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2749 ; RV32IZFHMIN-NEXT: lui a0, 307200
2750 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2751 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2752 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2753 ; RV32IZFHMIN-NEXT: beqz a0, .LBB15_2
2754 ; RV32IZFHMIN-NEXT: # %bb.1:
2755 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2756 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2757 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2758 ; RV32IZFHMIN-NEXT: .LBB15_2:
2759 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2760 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2761 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2762 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
2763 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2764 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
2765 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
2766 ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
2767 ; RV32IZFHMIN-NEXT: neg s0, a0
2768 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
2769 ; RV32IZFHMIN-NEXT: call __fixunssfdi
2770 ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI15_0)
2771 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI15_0)(a2)
2772 ; RV32IZFHMIN-NEXT: and a0, s0, a0
2773 ; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0
2774 ; RV32IZFHMIN-NEXT: neg a2, a2
2775 ; RV32IZFHMIN-NEXT: or a0, a2, a0
2776 ; RV32IZFHMIN-NEXT: and a1, s0, a1
2777 ; RV32IZFHMIN-NEXT: or a1, a2, a1
2778 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2779 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2780 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
2781 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2782 ; RV32IZFHMIN-NEXT: ret
2783 ;
2784 ; RV64IZFHMIN-LABEL: test_round_ui64:
2785 ; RV64IZFHMIN: # %bb.0:
2786 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2787 ; RV64IZFHMIN-NEXT: lui a0, 307200
2788 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2789 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2790 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2791 ; RV64IZFHMIN-NEXT: beqz a0, .LBB15_2
2792 ; RV64IZFHMIN-NEXT: # %bb.1:
2793 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2794 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2795 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2796 ; RV64IZFHMIN-NEXT: .LBB15_2:
2797 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2798 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2799 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2800 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
2801 ; RV64IZFHMIN-NEXT: seqz a1, a1
2802 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
2803 ; RV64IZFHMIN-NEXT: and a0, a1, a0
2804 ; RV64IZFHMIN-NEXT: ret
2805 ;
2806 ; RV32IZHINXMIN-LABEL: test_round_ui64:
2807 ; RV32IZHINXMIN: # %bb.0:
2808 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2809 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2810 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2811 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2812 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB15_2
2813 ; RV32IZHINXMIN-NEXT: # %bb.1:
2814 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2815 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2816 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2817 ; RV32IZHINXMIN-NEXT: .LBB15_2:
2818 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2819 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2820 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2821 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
2822 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2823 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
2824 ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0
2825 ; RV32IZHINXMIN-NEXT: neg s1, a0
2826 ; RV32IZHINXMIN-NEXT: mv a0, s0
2827 ; RV32IZHINXMIN-NEXT: call __fixunssfdi
2828 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI15_0)
2829 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI15_0)(a2)
2830 ; RV32IZHINXMIN-NEXT: and a0, s1, a0
2831 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
2832 ; RV32IZHINXMIN-NEXT: neg a2, a2
2833 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
2834 ; RV32IZHINXMIN-NEXT: and a1, s1, a1
2835 ; RV32IZHINXMIN-NEXT: or a1, a2, a1
2836 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2837 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2838 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
2839 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2840 ; RV32IZHINXMIN-NEXT: ret
2841 ;
2842 ; RV64IZHINXMIN-LABEL: test_round_ui64:
2843 ; RV64IZHINXMIN: # %bb.0:
2844 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2845 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2846 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2847 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2848 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB15_2
2849 ; RV64IZHINXMIN-NEXT: # %bb.1:
2850 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2851 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2852 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2853 ; RV64IZHINXMIN-NEXT: .LBB15_2:
2854 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2855 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2856 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz
2857 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
2858 ; RV64IZHINXMIN-NEXT: seqz a0, a0
2859 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
2860 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
2861 ; RV64IZHINXMIN-NEXT: ret
2862 %a = call half @llvm.round.f16(half %x)
2863 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
2864 ret i64 %b
2865 }
2867 define signext i32 @test_roundeven_si32(half %x) {
2868 ; CHECKIZFH-LABEL: test_roundeven_si32:
2869 ; CHECKIZFH: # %bb.0:
2870 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
2871 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
2872 ; CHECKIZFH-NEXT: seqz a1, a1
2873 ; CHECKIZFH-NEXT: addi a1, a1, -1
2874 ; CHECKIZFH-NEXT: and a0, a1, a0
2875 ; CHECKIZFH-NEXT: ret
2876 ;
2877 ; CHECKIZHINX-LABEL: test_roundeven_si32:
2878 ; CHECKIZHINX: # %bb.0:
2879 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI16_0)
2880 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI16_0)(a1)
2881 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2882 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2883 ; CHECKIZHINX-NEXT: beqz a1, .LBB16_2
2884 ; CHECKIZHINX-NEXT: # %bb.1:
2885 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
2886 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
2887 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2888 ; CHECKIZHINX-NEXT: .LBB16_2:
2889 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2890 ; CHECKIZHINX-NEXT: feq.h a0, a0, a0
2891 ; CHECKIZHINX-NEXT: seqz a0, a0
2892 ; CHECKIZHINX-NEXT: addi a0, a0, -1
2893 ; CHECKIZHINX-NEXT: and a0, a0, a1
2894 ; CHECKIZHINX-NEXT: ret
2895 ;
2896 ; CHECKIZFHMIN-LABEL: test_roundeven_si32:
2897 ; CHECKIZFHMIN: # %bb.0:
2898 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2899 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2900 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2901 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2902 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2903 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB16_2
2904 ; CHECKIZFHMIN-NEXT: # %bb.1:
2905 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
2906 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
2907 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2908 ; CHECKIZFHMIN-NEXT: .LBB16_2:
2909 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2910 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2911 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2912 ; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
2913 ; CHECKIZFHMIN-NEXT: seqz a1, a1
2914 ; CHECKIZFHMIN-NEXT: addi a1, a1, -1
2915 ; CHECKIZFHMIN-NEXT: and a0, a1, a0
2916 ; CHECKIZFHMIN-NEXT: ret
2917 ;
2918 ; CHECKIZHINXMIN-LABEL: test_roundeven_si32:
2919 ; CHECKIZHINXMIN: # %bb.0:
2920 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2921 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2922 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2923 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2924 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB16_2
2925 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2926 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
2927 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
2928 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2929 ; CHECKIZHINXMIN-NEXT: .LBB16_2:
2930 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2931 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2932 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2933 ; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0
2934 ; CHECKIZHINXMIN-NEXT: seqz a0, a0
2935 ; CHECKIZHINXMIN-NEXT: addi a0, a0, -1
2936 ; CHECKIZHINXMIN-NEXT: and a0, a0, a1
2937 ; CHECKIZHINXMIN-NEXT: ret
2938 %a = call half @llvm.roundeven.f16(half %x)
2939 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
2940 ret i32 %b
2941 }
2943 define i64 @test_roundeven_si64(half %x) nounwind {
2944 ; RV32IZFH-LABEL: test_roundeven_si64:
2945 ; RV32IZFH: # %bb.0:
2946 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI17_0)
2947 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI17_0)(a0)
2948 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2949 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2950 ; RV32IZFH-NEXT: beqz a0, .LBB17_2
2951 ; RV32IZFH-NEXT: # %bb.1:
2952 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
2953 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
2954 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2955 ; RV32IZFH-NEXT: .LBB17_2:
2956 ; RV32IZFH-NEXT: addi sp, sp, -16
2957 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2958 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
2959 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
2960 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
2961 ; RV32IZFH-NEXT: lui a0, 913408
2962 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
2963 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
2964 ; RV32IZFH-NEXT: fmv.s fa0, fs0
2965 ; RV32IZFH-NEXT: call __fixsfdi
2966 ; RV32IZFH-NEXT: lui a4, 524288
2967 ; RV32IZFH-NEXT: lui a2, 524288
2968 ; RV32IZFH-NEXT: beqz s0, .LBB17_4
2969 ; RV32IZFH-NEXT: # %bb.3:
2970 ; RV32IZFH-NEXT: mv a2, a1
2971 ; RV32IZFH-NEXT: .LBB17_4:
2972 ; RV32IZFH-NEXT: lui a1, %hi(.LCPI17_1)
2973 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a1)
2974 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
2975 ; RV32IZFH-NEXT: beqz a3, .LBB17_6
2976 ; RV32IZFH-NEXT: # %bb.5:
2977 ; RV32IZFH-NEXT: addi a2, a4, -1
2978 ; RV32IZFH-NEXT: .LBB17_6:
2979 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
2980 ; RV32IZFH-NEXT: neg a4, a1
2981 ; RV32IZFH-NEXT: and a1, a4, a2
2982 ; RV32IZFH-NEXT: neg a2, s0
2983 ; RV32IZFH-NEXT: and a0, a2, a0
2984 ; RV32IZFH-NEXT: neg a2, a3
2985 ; RV32IZFH-NEXT: or a0, a2, a0
2986 ; RV32IZFH-NEXT: and a0, a4, a0
2987 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2988 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
2989 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
2990 ; RV32IZFH-NEXT: addi sp, sp, 16
2991 ; RV32IZFH-NEXT: ret
2992 ;
2993 ; RV64IZFH-LABEL: test_roundeven_si64:
2994 ; RV64IZFH: # %bb.0:
2995 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
2996 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
2997 ; RV64IZFH-NEXT: seqz a1, a1
2998 ; RV64IZFH-NEXT: addi a1, a1, -1
2999 ; RV64IZFH-NEXT: and a0, a1, a0
3000 ; RV64IZFH-NEXT: ret
3001 ;
3002 ; RV32IZHINX-LABEL: test_roundeven_si64:
3003 ; RV32IZHINX: # %bb.0:
3004 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
3005 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
3006 ; RV32IZHINX-NEXT: fabs.h a2, a0
3007 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3008 ; RV32IZHINX-NEXT: beqz a1, .LBB17_2
3009 ; RV32IZHINX-NEXT: # %bb.1:
3010 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3011 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3012 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3013 ; RV32IZHINX-NEXT: .LBB17_2:
3014 ; RV32IZHINX-NEXT: addi sp, sp, -16
3015 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3016 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3017 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3018 ; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
3019 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
3020 ; RV32IZHINX-NEXT: lui a0, 913408
3021 ; RV32IZHINX-NEXT: fle.s s1, a0, s0
3022 ; RV32IZHINX-NEXT: neg s2, s1
3023 ; RV32IZHINX-NEXT: mv a0, s0
3024 ; RV32IZHINX-NEXT: call __fixsfdi
3025 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI17_1)
3026 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI17_1)(a2)
3027 ; RV32IZHINX-NEXT: and a0, s2, a0
3028 ; RV32IZHINX-NEXT: flt.s a4, a2, s0
3029 ; RV32IZHINX-NEXT: neg a2, a4
3030 ; RV32IZHINX-NEXT: or a0, a2, a0
3031 ; RV32IZHINX-NEXT: feq.s a2, s0, s0
3032 ; RV32IZHINX-NEXT: neg a2, a2
3033 ; RV32IZHINX-NEXT: lui a5, 524288
3034 ; RV32IZHINX-NEXT: lui a3, 524288
3035 ; RV32IZHINX-NEXT: beqz s1, .LBB17_4
3036 ; RV32IZHINX-NEXT: # %bb.3:
3037 ; RV32IZHINX-NEXT: mv a3, a1
3038 ; RV32IZHINX-NEXT: .LBB17_4:
3039 ; RV32IZHINX-NEXT: and a0, a2, a0
3040 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3041 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3042 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
3043 ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
3044 ; RV32IZHINX-NEXT: addi sp, sp, 16
3045 ; RV32IZHINX-NEXT: beqz a4, .LBB17_6
3046 ; RV32IZHINX-NEXT: # %bb.5:
3047 ; RV32IZHINX-NEXT: addi a3, a5, -1
3048 ; RV32IZHINX-NEXT: .LBB17_6:
3049 ; RV32IZHINX-NEXT: and a1, a2, a3
3050 ; RV32IZHINX-NEXT: ret
3051 ;
3052 ; RV64IZHINX-LABEL: test_roundeven_si64:
3053 ; RV64IZHINX: # %bb.0:
3054 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
3055 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
3056 ; RV64IZHINX-NEXT: fabs.h a2, a0
3057 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3058 ; RV64IZHINX-NEXT: beqz a1, .LBB17_2
3059 ; RV64IZHINX-NEXT: # %bb.1:
3060 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3061 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3062 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3063 ; RV64IZHINX-NEXT: .LBB17_2:
3064 ; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz
3065 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
3066 ; RV64IZHINX-NEXT: seqz a0, a0
3067 ; RV64IZHINX-NEXT: addi a0, a0, -1
3068 ; RV64IZHINX-NEXT: and a0, a0, a1
3069 ; RV64IZHINX-NEXT: ret
3070 ;
3071 ; RV32IZFHMIN-LABEL: test_roundeven_si64:
3072 ; RV32IZFHMIN: # %bb.0:
3073 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3074 ; RV32IZFHMIN-NEXT: lui a0, 307200
3075 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3076 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3077 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3078 ; RV32IZFHMIN-NEXT: beqz a0, .LBB17_2
3079 ; RV32IZFHMIN-NEXT: # %bb.1:
3080 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3081 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3082 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3083 ; RV32IZFHMIN-NEXT: .LBB17_2:
3084 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3085 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3086 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3087 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
3088 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3089 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
3090 ; RV32IZFHMIN-NEXT: lui a0, 913408
3091 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
3092 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
3093 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
3094 ; RV32IZFHMIN-NEXT: call __fixsfdi
3095 ; RV32IZFHMIN-NEXT: lui a4, 524288
3096 ; RV32IZFHMIN-NEXT: lui a2, 524288
3097 ; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4
3098 ; RV32IZFHMIN-NEXT: # %bb.3:
3099 ; RV32IZFHMIN-NEXT: mv a2, a1
3100 ; RV32IZFHMIN-NEXT: .LBB17_4:
3101 ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI17_0)
3102 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a1)
3103 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
3104 ; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6
3105 ; RV32IZFHMIN-NEXT: # %bb.5:
3106 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
3107 ; RV32IZFHMIN-NEXT: .LBB17_6:
3108 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
3109 ; RV32IZFHMIN-NEXT: neg a4, a1
3110 ; RV32IZFHMIN-NEXT: and a1, a4, a2
3111 ; RV32IZFHMIN-NEXT: neg a2, s0
3112 ; RV32IZFHMIN-NEXT: and a0, a2, a0
3113 ; RV32IZFHMIN-NEXT: neg a2, a3
3114 ; RV32IZFHMIN-NEXT: or a0, a2, a0
3115 ; RV32IZFHMIN-NEXT: and a0, a4, a0
3116 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3117 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3118 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
3119 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3120 ; RV32IZFHMIN-NEXT: ret
3121 ;
3122 ; RV64IZFHMIN-LABEL: test_roundeven_si64:
3123 ; RV64IZFHMIN: # %bb.0:
3124 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3125 ; RV64IZFHMIN-NEXT: lui a0, 307200
3126 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3127 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3128 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3129 ; RV64IZFHMIN-NEXT: beqz a0, .LBB17_2
3130 ; RV64IZFHMIN-NEXT: # %bb.1:
3131 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3132 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3133 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3134 ; RV64IZFHMIN-NEXT: .LBB17_2:
3135 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3136 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3137 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3138 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
3139 ; RV64IZFHMIN-NEXT: seqz a1, a1
3140 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
3141 ; RV64IZFHMIN-NEXT: and a0, a1, a0
3142 ; RV64IZFHMIN-NEXT: ret
3143 ;
3144 ; RV32IZHINXMIN-LABEL: test_roundeven_si64:
3145 ; RV32IZHINXMIN: # %bb.0:
3146 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3147 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3148 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3149 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3150 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB17_2
3151 ; RV32IZHINXMIN-NEXT: # %bb.1:
3152 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3153 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3154 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3155 ; RV32IZHINXMIN-NEXT: .LBB17_2:
3156 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3157 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3158 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3159 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3160 ; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
3161 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3162 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
3163 ; RV32IZHINXMIN-NEXT: lui a0, 913408
3164 ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0
3165 ; RV32IZHINXMIN-NEXT: neg s2, s1
3166 ; RV32IZHINXMIN-NEXT: mv a0, s0
3167 ; RV32IZHINXMIN-NEXT: call __fixsfdi
3168 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI17_0)
3169 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI17_0)(a2)
3170 ; RV32IZHINXMIN-NEXT: and a0, s2, a0
3171 ; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
3172 ; RV32IZHINXMIN-NEXT: neg a2, a4
3173 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
3174 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0
3175 ; RV32IZHINXMIN-NEXT: neg a2, a2
3176 ; RV32IZHINXMIN-NEXT: lui a5, 524288
3177 ; RV32IZHINXMIN-NEXT: lui a3, 524288
3178 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB17_4
3179 ; RV32IZHINXMIN-NEXT: # %bb.3:
3180 ; RV32IZHINXMIN-NEXT: mv a3, a1
3181 ; RV32IZHINXMIN-NEXT: .LBB17_4:
3182 ; RV32IZHINXMIN-NEXT: and a0, a2, a0
3183 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3184 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3185 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
3186 ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
3187 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3188 ; RV32IZHINXMIN-NEXT: beqz a4, .LBB17_6
3189 ; RV32IZHINXMIN-NEXT: # %bb.5:
3190 ; RV32IZHINXMIN-NEXT: addi a3, a5, -1
3191 ; RV32IZHINXMIN-NEXT: .LBB17_6:
3192 ; RV32IZHINXMIN-NEXT: and a1, a2, a3
3193 ; RV32IZHINXMIN-NEXT: ret
3194 ;
3195 ; RV64IZHINXMIN-LABEL: test_roundeven_si64:
3196 ; RV64IZHINXMIN: # %bb.0:
3197 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3198 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3199 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3200 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3201 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB17_2
3202 ; RV64IZHINXMIN-NEXT: # %bb.1:
3203 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3204 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3205 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3206 ; RV64IZHINXMIN-NEXT: .LBB17_2:
3207 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3208 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3209 ; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz
3210 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
3211 ; RV64IZHINXMIN-NEXT: seqz a0, a0
3212 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
3213 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
3214 ; RV64IZHINXMIN-NEXT: ret
3215 %a = call half @llvm.roundeven.f16(half %x)
3216 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
3217 ret i64 %b
3218 }
3220 define signext i32 @test_roundeven_ui32(half %x) {
3221 ; CHECKIZFH-LABEL: test_roundeven_ui32:
3222 ; CHECKIZFH: # %bb.0:
3223 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rne
3224 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
3225 ; CHECKIZFH-NEXT: seqz a1, a1
3226 ; CHECKIZFH-NEXT: addi a1, a1, -1
3227 ; CHECKIZFH-NEXT: and a0, a1, a0
3228 ; CHECKIZFH-NEXT: ret
3229 ;
3230 ; RV32IZHINX-LABEL: test_roundeven_ui32:
3231 ; RV32IZHINX: # %bb.0:
3232 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI18_0)
3233 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
3234 ; RV32IZHINX-NEXT: fabs.h a2, a0
3235 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3236 ; RV32IZHINX-NEXT: beqz a1, .LBB18_2
3237 ; RV32IZHINX-NEXT: # %bb.1:
3238 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3239 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3240 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3241 ; RV32IZHINX-NEXT: .LBB18_2:
3242 ; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
3243 ; RV32IZHINX-NEXT: feq.h a0, a0, a0
3244 ; RV32IZHINX-NEXT: seqz a0, a0
3245 ; RV32IZHINX-NEXT: addi a0, a0, -1
3246 ; RV32IZHINX-NEXT: and a0, a0, a1
3247 ; RV32IZHINX-NEXT: ret
3248 ;
3249 ; RV64IZHINX-LABEL: test_roundeven_ui32:
3250 ; RV64IZHINX: # %bb.0:
3251 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI18_0)
3252 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
3253 ; RV64IZHINX-NEXT: fabs.h a2, a0
3254 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3255 ; RV64IZHINX-NEXT: beqz a1, .LBB18_2
3256 ; RV64IZHINX-NEXT: # %bb.1:
3257 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3258 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3259 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3260 ; RV64IZHINX-NEXT: .LBB18_2:
3261 ; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
3262 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
3263 ; RV64IZHINX-NEXT: seqz a0, a0
3264 ; RV64IZHINX-NEXT: addiw a0, a0, -1
3265 ; RV64IZHINX-NEXT: and a0, a1, a0
3266 ; RV64IZHINX-NEXT: ret
3267 ;
3268 ; RV32IZFHMIN-LABEL: test_roundeven_ui32:
3269 ; RV32IZFHMIN: # %bb.0:
3270 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3271 ; RV32IZFHMIN-NEXT: lui a0, 307200
3272 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3273 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3274 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3275 ; RV32IZFHMIN-NEXT: beqz a0, .LBB18_2
3276 ; RV32IZFHMIN-NEXT: # %bb.1:
3277 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3278 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3279 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3280 ; RV32IZFHMIN-NEXT: .LBB18_2:
3281 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3282 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3283 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
3284 ; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5
3285 ; RV32IZFHMIN-NEXT: seqz a1, a1
3286 ; RV32IZFHMIN-NEXT: addi a1, a1, -1
3287 ; RV32IZFHMIN-NEXT: and a0, a1, a0
3288 ; RV32IZFHMIN-NEXT: ret
3289 ;
3290 ; RV64IZFHMIN-LABEL: test_roundeven_ui32:
3291 ; RV64IZFHMIN: # %bb.0:
3292 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3293 ; RV64IZFHMIN-NEXT: lui a0, 307200
3294 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3295 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3296 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3297 ; RV64IZFHMIN-NEXT: beqz a0, .LBB18_2
3298 ; RV64IZFHMIN-NEXT: # %bb.1:
3299 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3300 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3301 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3302 ; RV64IZFHMIN-NEXT: .LBB18_2:
3303 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3304 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3305 ; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
3306 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
3307 ; RV64IZFHMIN-NEXT: seqz a1, a1
3308 ; RV64IZFHMIN-NEXT: addiw a1, a1, -1
3309 ; RV64IZFHMIN-NEXT: and a0, a0, a1
3310 ; RV64IZFHMIN-NEXT: ret
3311 ;
3312 ; RV32IZHINXMIN-LABEL: test_roundeven_ui32:
3313 ; RV32IZHINXMIN: # %bb.0:
3314 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3315 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3316 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3317 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3318 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB18_2
3319 ; RV32IZHINXMIN-NEXT: # %bb.1:
3320 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3321 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3322 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3323 ; RV32IZHINXMIN-NEXT: .LBB18_2:
3324 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3325 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3326 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
3327 ; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0
3328 ; RV32IZHINXMIN-NEXT: seqz a0, a0
3329 ; RV32IZHINXMIN-NEXT: addi a0, a0, -1
3330 ; RV32IZHINXMIN-NEXT: and a0, a0, a1
3331 ; RV32IZHINXMIN-NEXT: ret
3332 ;
3333 ; RV64IZHINXMIN-LABEL: test_roundeven_ui32:
3334 ; RV64IZHINXMIN: # %bb.0:
3335 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3336 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3337 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3338 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3339 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB18_2
3340 ; RV64IZHINXMIN-NEXT: # %bb.1:
3341 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3342 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3343 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3344 ; RV64IZHINXMIN-NEXT: .LBB18_2:
3345 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3346 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3347 ; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
3348 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
3349 ; RV64IZHINXMIN-NEXT: seqz a0, a0
3350 ; RV64IZHINXMIN-NEXT: addiw a0, a0, -1
3351 ; RV64IZHINXMIN-NEXT: and a0, a1, a0
3352 ; RV64IZHINXMIN-NEXT: ret
3353 %a = call half @llvm.roundeven.f16(half %x)
3354 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
3355 ret i32 %b
3356 }
3358 define i64 @test_roundeven_ui64(half %x) nounwind {
3359 ; RV32IZFH-LABEL: test_roundeven_ui64:
3360 ; RV32IZFH: # %bb.0:
3361 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0)
3362 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0)
3363 ; RV32IZFH-NEXT: fabs.h fa4, fa0
3364 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
3365 ; RV32IZFH-NEXT: beqz a0, .LBB19_2
3366 ; RV32IZFH-NEXT: # %bb.1:
3367 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
3368 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
3369 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
3370 ; RV32IZFH-NEXT: .LBB19_2:
3371 ; RV32IZFH-NEXT: addi sp, sp, -16
3372 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3373 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3374 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
3375 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
3376 ; RV32IZFH-NEXT: fmv.w.x fa5, zero
3377 ; RV32IZFH-NEXT: fle.s a0, fa5, fs0
3378 ; RV32IZFH-NEXT: neg s0, a0
3379 ; RV32IZFH-NEXT: fmv.s fa0, fs0
3380 ; RV32IZFH-NEXT: call __fixunssfdi
3381 ; RV32IZFH-NEXT: lui a2, %hi(.LCPI19_1)
3382 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI19_1)(a2)
3383 ; RV32IZFH-NEXT: and a0, s0, a0
3384 ; RV32IZFH-NEXT: flt.s a2, fa5, fs0
3385 ; RV32IZFH-NEXT: neg a2, a2
3386 ; RV32IZFH-NEXT: or a0, a2, a0
3387 ; RV32IZFH-NEXT: and a1, s0, a1
3388 ; RV32IZFH-NEXT: or a1, a2, a1
3389 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3390 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3391 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
3392 ; RV32IZFH-NEXT: addi sp, sp, 16
3393 ; RV32IZFH-NEXT: ret
3394 ;
3395 ; RV64IZFH-LABEL: test_roundeven_ui64:
3396 ; RV64IZFH: # %bb.0:
3397 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
3398 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
3399 ; RV64IZFH-NEXT: seqz a1, a1
3400 ; RV64IZFH-NEXT: addi a1, a1, -1
3401 ; RV64IZFH-NEXT: and a0, a1, a0
3402 ; RV64IZFH-NEXT: ret
3403 ;
3404 ; RV32IZHINX-LABEL: test_roundeven_ui64:
3405 ; RV32IZHINX: # %bb.0:
3406 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
3407 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
3408 ; RV32IZHINX-NEXT: fabs.h a2, a0
3409 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3410 ; RV32IZHINX-NEXT: beqz a1, .LBB19_2
3411 ; RV32IZHINX-NEXT: # %bb.1:
3412 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3413 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3414 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3415 ; RV32IZHINX-NEXT: .LBB19_2:
3416 ; RV32IZHINX-NEXT: addi sp, sp, -16
3417 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3418 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3419 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3420 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
3421 ; RV32IZHINX-NEXT: fle.s a0, zero, s0
3422 ; RV32IZHINX-NEXT: neg s1, a0
3423 ; RV32IZHINX-NEXT: mv a0, s0
3424 ; RV32IZHINX-NEXT: call __fixunssfdi
3425 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI19_1)
3426 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI19_1)(a2)
3427 ; RV32IZHINX-NEXT: and a0, s1, a0
3428 ; RV32IZHINX-NEXT: flt.s a2, a2, s0
3429 ; RV32IZHINX-NEXT: neg a2, a2
3430 ; RV32IZHINX-NEXT: or a0, a2, a0
3431 ; RV32IZHINX-NEXT: and a1, s1, a1
3432 ; RV32IZHINX-NEXT: or a1, a2, a1
3433 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3434 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3435 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
3436 ; RV32IZHINX-NEXT: addi sp, sp, 16
3437 ; RV32IZHINX-NEXT: ret
3438 ;
3439 ; RV64IZHINX-LABEL: test_roundeven_ui64:
3440 ; RV64IZHINX: # %bb.0:
3441 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
3442 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
3443 ; RV64IZHINX-NEXT: fabs.h a2, a0
3444 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3445 ; RV64IZHINX-NEXT: beqz a1, .LBB19_2
3446 ; RV64IZHINX-NEXT: # %bb.1:
3447 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3448 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3449 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3450 ; RV64IZHINX-NEXT: .LBB19_2:
3451 ; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz
3452 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
3453 ; RV64IZHINX-NEXT: seqz a0, a0
3454 ; RV64IZHINX-NEXT: addi a0, a0, -1
3455 ; RV64IZHINX-NEXT: and a0, a0, a1
3456 ; RV64IZHINX-NEXT: ret
3457 ;
3458 ; RV32IZFHMIN-LABEL: test_roundeven_ui64:
3459 ; RV32IZFHMIN: # %bb.0:
3460 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3461 ; RV32IZFHMIN-NEXT: lui a0, 307200
3462 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3463 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3464 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3465 ; RV32IZFHMIN-NEXT: beqz a0, .LBB19_2
3466 ; RV32IZFHMIN-NEXT: # %bb.1:
3467 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3468 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3469 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3470 ; RV32IZFHMIN-NEXT: .LBB19_2:
3471 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3472 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3473 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3474 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
3475 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3476 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
3477 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
3478 ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
3479 ; RV32IZFHMIN-NEXT: neg s0, a0
3480 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
3481 ; RV32IZFHMIN-NEXT: call __fixunssfdi
3482 ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI19_0)
3483 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI19_0)(a2)
3484 ; RV32IZFHMIN-NEXT: and a0, s0, a0
3485 ; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0
3486 ; RV32IZFHMIN-NEXT: neg a2, a2
3487 ; RV32IZFHMIN-NEXT: or a0, a2, a0
3488 ; RV32IZFHMIN-NEXT: and a1, s0, a1
3489 ; RV32IZFHMIN-NEXT: or a1, a2, a1
3490 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3491 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3492 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
3493 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3494 ; RV32IZFHMIN-NEXT: ret
3495 ;
3496 ; RV64IZFHMIN-LABEL: test_roundeven_ui64:
3497 ; RV64IZFHMIN: # %bb.0:
3498 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3499 ; RV64IZFHMIN-NEXT: lui a0, 307200
3500 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3501 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3502 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3503 ; RV64IZFHMIN-NEXT: beqz a0, .LBB19_2
3504 ; RV64IZFHMIN-NEXT: # %bb.1:
3505 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3506 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3507 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3508 ; RV64IZFHMIN-NEXT: .LBB19_2:
3509 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3510 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3511 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
3512 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
3513 ; RV64IZFHMIN-NEXT: seqz a1, a1
3514 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
3515 ; RV64IZFHMIN-NEXT: and a0, a1, a0
3516 ; RV64IZFHMIN-NEXT: ret
3517 ;
3518 ; RV32IZHINXMIN-LABEL: test_roundeven_ui64:
3519 ; RV32IZHINXMIN: # %bb.0:
3520 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3521 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3522 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3523 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3524 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB19_2
3525 ; RV32IZHINXMIN-NEXT: # %bb.1:
3526 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3527 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3528 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3529 ; RV32IZHINXMIN-NEXT: .LBB19_2:
3530 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3531 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3532 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3533 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3534 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3535 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
3536 ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0
3537 ; RV32IZHINXMIN-NEXT: neg s1, a0
3538 ; RV32IZHINXMIN-NEXT: mv a0, s0
3539 ; RV32IZHINXMIN-NEXT: call __fixunssfdi
3540 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI19_0)
3541 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI19_0)(a2)
3542 ; RV32IZHINXMIN-NEXT: and a0, s1, a0
3543 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
3544 ; RV32IZHINXMIN-NEXT: neg a2, a2
3545 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
3546 ; RV32IZHINXMIN-NEXT: and a1, s1, a1
3547 ; RV32IZHINXMIN-NEXT: or a1, a2, a1
3548 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3549 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3550 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
3551 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3552 ; RV32IZHINXMIN-NEXT: ret
3553 ;
3554 ; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
3555 ; RV64IZHINXMIN: # %bb.0:
3556 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3557 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3558 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3559 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3560 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB19_2
3561 ; RV64IZHINXMIN-NEXT: # %bb.1:
3562 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3563 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3564 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3565 ; RV64IZHINXMIN-NEXT: .LBB19_2:
3566 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3567 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3568 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz
3569 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
3570 ; RV64IZHINXMIN-NEXT: seqz a0, a0
3571 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
3572 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
3573 ; RV64IZHINXMIN-NEXT: ret
3574 %a = call half @llvm.roundeven.f16(half %x)
3575 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
3576 ret i64 %b
3577 }
3579 define signext i32 @test_rint_si32(half %x) {
3580 ; CHECKIZFH-LABEL: test_rint_si32:
3581 ; CHECKIZFH: # %bb.0:
3582 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0
3583 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
3584 ; CHECKIZFH-NEXT: seqz a1, a1
3585 ; CHECKIZFH-NEXT: addi a1, a1, -1
3586 ; CHECKIZFH-NEXT: and a0, a1, a0
3587 ; CHECKIZFH-NEXT: ret
3588 ;
3589 ; CHECKIZHINX-LABEL: test_rint_si32:
3590 ; CHECKIZHINX: # %bb.0:
3591 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI20_0)
3592 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
3593 ; CHECKIZHINX-NEXT: fabs.h a2, a0
3594 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
3595 ; CHECKIZHINX-NEXT: beqz a1, .LBB20_2
3596 ; CHECKIZHINX-NEXT: # %bb.1:
3597 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0
3598 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1
3599 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
3600 ; CHECKIZHINX-NEXT: .LBB20_2:
3601 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
3602 ; CHECKIZHINX-NEXT: feq.h a0, a0, a0
3603 ; CHECKIZHINX-NEXT: seqz a0, a0
3604 ; CHECKIZHINX-NEXT: addi a0, a0, -1
3605 ; CHECKIZHINX-NEXT: and a0, a0, a1
3606 ; CHECKIZHINX-NEXT: ret
3607 ;
3608 ; CHECKIZFHMIN-LABEL: test_rint_si32:
3609 ; CHECKIZFHMIN: # %bb.0:
3610 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
3611 ; CHECKIZFHMIN-NEXT: lui a0, 307200
3612 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
3613 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
3614 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
3615 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB20_2
3616 ; CHECKIZFHMIN-NEXT: # %bb.1:
3617 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5
3618 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0
3619 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3620 ; CHECKIZFHMIN-NEXT: .LBB20_2:
3621 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
3622 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
3623 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3624 ; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
3625 ; CHECKIZFHMIN-NEXT: seqz a1, a1
3626 ; CHECKIZFHMIN-NEXT: addi a1, a1, -1
3627 ; CHECKIZFHMIN-NEXT: and a0, a1, a0
3628 ; CHECKIZFHMIN-NEXT: ret
3629 ;
3630 ; CHECKIZHINXMIN-LABEL: test_rint_si32:
3631 ; CHECKIZHINXMIN: # %bb.0:
3632 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3633 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
3634 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
3635 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
3636 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB20_2
3637 ; CHECKIZHINXMIN-NEXT: # %bb.1:
3638 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0
3639 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1
3640 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3641 ; CHECKIZHINXMIN-NEXT: .LBB20_2:
3642 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
3643 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3644 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
3645 ; CHECKIZHINXMIN-NEXT: feq.s a0, a0, a0
3646 ; CHECKIZHINXMIN-NEXT: seqz a0, a0
3647 ; CHECKIZHINXMIN-NEXT: addi a0, a0, -1
3648 ; CHECKIZHINXMIN-NEXT: and a0, a0, a1
3649 ; CHECKIZHINXMIN-NEXT: ret
3650 %a = call half @llvm.rint.f16(half %x)
3651 %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
3652 ret i32 %b
3653 }
3655 define i64 @test_rint_si64(half %x) nounwind {
3656 ; RV32IZFH-LABEL: test_rint_si64:
3657 ; RV32IZFH: # %bb.0:
3658 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI21_0)
3659 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI21_0)(a0)
3660 ; RV32IZFH-NEXT: fabs.h fa4, fa0
3661 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
3662 ; RV32IZFH-NEXT: beqz a0, .LBB21_2
3663 ; RV32IZFH-NEXT: # %bb.1:
3664 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0
3665 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0
3666 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
3667 ; RV32IZFH-NEXT: .LBB21_2:
3668 ; RV32IZFH-NEXT: addi sp, sp, -16
3669 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3670 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3671 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
3672 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
3673 ; RV32IZFH-NEXT: lui a0, 913408
3674 ; RV32IZFH-NEXT: fmv.w.x fa5, a0
3675 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0
3676 ; RV32IZFH-NEXT: fmv.s fa0, fs0
3677 ; RV32IZFH-NEXT: call __fixsfdi
3678 ; RV32IZFH-NEXT: lui a4, 524288
3679 ; RV32IZFH-NEXT: lui a2, 524288
3680 ; RV32IZFH-NEXT: beqz s0, .LBB21_4
3681 ; RV32IZFH-NEXT: # %bb.3:
3682 ; RV32IZFH-NEXT: mv a2, a1
3683 ; RV32IZFH-NEXT: .LBB21_4:
3684 ; RV32IZFH-NEXT: lui a1, %hi(.LCPI21_1)
3685 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a1)
3686 ; RV32IZFH-NEXT: flt.s a3, fa5, fs0
3687 ; RV32IZFH-NEXT: beqz a3, .LBB21_6
3688 ; RV32IZFH-NEXT: # %bb.5:
3689 ; RV32IZFH-NEXT: addi a2, a4, -1
3690 ; RV32IZFH-NEXT: .LBB21_6:
3691 ; RV32IZFH-NEXT: feq.s a1, fs0, fs0
3692 ; RV32IZFH-NEXT: neg a4, a1
3693 ; RV32IZFH-NEXT: and a1, a4, a2
3694 ; RV32IZFH-NEXT: neg a2, s0
3695 ; RV32IZFH-NEXT: and a0, a2, a0
3696 ; RV32IZFH-NEXT: neg a2, a3
3697 ; RV32IZFH-NEXT: or a0, a2, a0
3698 ; RV32IZFH-NEXT: and a0, a4, a0
3699 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3700 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3701 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
3702 ; RV32IZFH-NEXT: addi sp, sp, 16
3703 ; RV32IZFH-NEXT: ret
3704 ;
3705 ; RV64IZFH-LABEL: test_rint_si64:
3706 ; RV64IZFH: # %bb.0:
3707 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0
3708 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
3709 ; RV64IZFH-NEXT: seqz a1, a1
3710 ; RV64IZFH-NEXT: addi a1, a1, -1
3711 ; RV64IZFH-NEXT: and a0, a1, a0
3712 ; RV64IZFH-NEXT: ret
3713 ;
3714 ; RV32IZHINX-LABEL: test_rint_si64:
3715 ; RV32IZHINX: # %bb.0:
3716 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
3717 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
3718 ; RV32IZHINX-NEXT: fabs.h a2, a0
3719 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3720 ; RV32IZHINX-NEXT: beqz a1, .LBB21_2
3721 ; RV32IZHINX-NEXT: # %bb.1:
3722 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0
3723 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1
3724 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3725 ; RV32IZHINX-NEXT: .LBB21_2:
3726 ; RV32IZHINX-NEXT: addi sp, sp, -16
3727 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3728 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3729 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3730 ; RV32IZHINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
3731 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
3732 ; RV32IZHINX-NEXT: lui a0, 913408
3733 ; RV32IZHINX-NEXT: fle.s s1, a0, s0
3734 ; RV32IZHINX-NEXT: neg s2, s1
3735 ; RV32IZHINX-NEXT: mv a0, s0
3736 ; RV32IZHINX-NEXT: call __fixsfdi
3737 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI21_1)
3738 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI21_1)(a2)
3739 ; RV32IZHINX-NEXT: and a0, s2, a0
3740 ; RV32IZHINX-NEXT: flt.s a4, a2, s0
3741 ; RV32IZHINX-NEXT: neg a2, a4
3742 ; RV32IZHINX-NEXT: or a0, a2, a0
3743 ; RV32IZHINX-NEXT: feq.s a2, s0, s0
3744 ; RV32IZHINX-NEXT: neg a2, a2
3745 ; RV32IZHINX-NEXT: lui a5, 524288
3746 ; RV32IZHINX-NEXT: lui a3, 524288
3747 ; RV32IZHINX-NEXT: beqz s1, .LBB21_4
3748 ; RV32IZHINX-NEXT: # %bb.3:
3749 ; RV32IZHINX-NEXT: mv a3, a1
3750 ; RV32IZHINX-NEXT: .LBB21_4:
3751 ; RV32IZHINX-NEXT: and a0, a2, a0
3752 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3753 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3754 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
3755 ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
3756 ; RV32IZHINX-NEXT: addi sp, sp, 16
3757 ; RV32IZHINX-NEXT: beqz a4, .LBB21_6
3758 ; RV32IZHINX-NEXT: # %bb.5:
3759 ; RV32IZHINX-NEXT: addi a3, a5, -1
3760 ; RV32IZHINX-NEXT: .LBB21_6:
3761 ; RV32IZHINX-NEXT: and a1, a2, a3
3762 ; RV32IZHINX-NEXT: ret
3763 ;
3764 ; RV64IZHINX-LABEL: test_rint_si64:
3765 ; RV64IZHINX: # %bb.0:
3766 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
3767 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
3768 ; RV64IZHINX-NEXT: fabs.h a2, a0
3769 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3770 ; RV64IZHINX-NEXT: beqz a1, .LBB21_2
3771 ; RV64IZHINX-NEXT: # %bb.1:
3772 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0
3773 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1
3774 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3775 ; RV64IZHINX-NEXT: .LBB21_2:
3776 ; RV64IZHINX-NEXT: fcvt.l.h a1, a0, rtz
3777 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
3778 ; RV64IZHINX-NEXT: seqz a0, a0
3779 ; RV64IZHINX-NEXT: addi a0, a0, -1
3780 ; RV64IZHINX-NEXT: and a0, a0, a1
3781 ; RV64IZHINX-NEXT: ret
3782 ;
3783 ; RV32IZFHMIN-LABEL: test_rint_si64:
3784 ; RV32IZFHMIN: # %bb.0:
3785 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3786 ; RV32IZFHMIN-NEXT: lui a0, 307200
3787 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3788 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3789 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3790 ; RV32IZFHMIN-NEXT: beqz a0, .LBB21_2
3791 ; RV32IZFHMIN-NEXT: # %bb.1:
3792 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5
3793 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0
3794 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3795 ; RV32IZFHMIN-NEXT: .LBB21_2:
3796 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3797 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3798 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3799 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
3800 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3801 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
3802 ; RV32IZFHMIN-NEXT: lui a0, 913408
3803 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0
3804 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0
3805 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
3806 ; RV32IZFHMIN-NEXT: call __fixsfdi
3807 ; RV32IZFHMIN-NEXT: lui a4, 524288
3808 ; RV32IZFHMIN-NEXT: lui a2, 524288
3809 ; RV32IZFHMIN-NEXT: beqz s0, .LBB21_4
3810 ; RV32IZFHMIN-NEXT: # %bb.3:
3811 ; RV32IZFHMIN-NEXT: mv a2, a1
3812 ; RV32IZFHMIN-NEXT: .LBB21_4:
3813 ; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI21_0)
3814 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a1)
3815 ; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0
3816 ; RV32IZFHMIN-NEXT: beqz a3, .LBB21_6
3817 ; RV32IZFHMIN-NEXT: # %bb.5:
3818 ; RV32IZFHMIN-NEXT: addi a2, a4, -1
3819 ; RV32IZFHMIN-NEXT: .LBB21_6:
3820 ; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0
3821 ; RV32IZFHMIN-NEXT: neg a4, a1
3822 ; RV32IZFHMIN-NEXT: and a1, a4, a2
3823 ; RV32IZFHMIN-NEXT: neg a2, s0
3824 ; RV32IZFHMIN-NEXT: and a0, a2, a0
3825 ; RV32IZFHMIN-NEXT: neg a2, a3
3826 ; RV32IZFHMIN-NEXT: or a0, a2, a0
3827 ; RV32IZFHMIN-NEXT: and a0, a4, a0
3828 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3829 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3830 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
3831 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3832 ; RV32IZFHMIN-NEXT: ret
3833 ;
3834 ; RV64IZFHMIN-LABEL: test_rint_si64:
3835 ; RV64IZFHMIN: # %bb.0:
3836 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3837 ; RV64IZFHMIN-NEXT: lui a0, 307200
3838 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3839 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3840 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3841 ; RV64IZFHMIN-NEXT: beqz a0, .LBB21_2
3842 ; RV64IZFHMIN-NEXT: # %bb.1:
3843 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5
3844 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0
3845 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3846 ; RV64IZFHMIN-NEXT: .LBB21_2:
3847 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3848 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3849 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3850 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
3851 ; RV64IZFHMIN-NEXT: seqz a1, a1
3852 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
3853 ; RV64IZFHMIN-NEXT: and a0, a1, a0
3854 ; RV64IZFHMIN-NEXT: ret
3855 ;
3856 ; RV32IZHINXMIN-LABEL: test_rint_si64:
3857 ; RV32IZHINXMIN: # %bb.0:
3858 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3859 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3860 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3861 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3862 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB21_2
3863 ; RV32IZHINXMIN-NEXT: # %bb.1:
3864 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0
3865 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1
3866 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3867 ; RV32IZHINXMIN-NEXT: .LBB21_2:
3868 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3869 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3870 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3871 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
3872 ; RV32IZHINXMIN-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
3873 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3874 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
3875 ; RV32IZHINXMIN-NEXT: lui a0, 913408
3876 ; RV32IZHINXMIN-NEXT: fle.s s1, a0, s0
3877 ; RV32IZHINXMIN-NEXT: neg s2, s1
3878 ; RV32IZHINXMIN-NEXT: mv a0, s0
3879 ; RV32IZHINXMIN-NEXT: call __fixsfdi
3880 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI21_0)
3881 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI21_0)(a2)
3882 ; RV32IZHINXMIN-NEXT: and a0, s2, a0
3883 ; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0
3884 ; RV32IZHINXMIN-NEXT: neg a2, a4
3885 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
3886 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0
3887 ; RV32IZHINXMIN-NEXT: neg a2, a2
3888 ; RV32IZHINXMIN-NEXT: lui a5, 524288
3889 ; RV32IZHINXMIN-NEXT: lui a3, 524288
3890 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB21_4
3891 ; RV32IZHINXMIN-NEXT: # %bb.3:
3892 ; RV32IZHINXMIN-NEXT: mv a3, a1
3893 ; RV32IZHINXMIN-NEXT: .LBB21_4:
3894 ; RV32IZHINXMIN-NEXT: and a0, a2, a0
3895 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3896 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3897 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
3898 ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
3899 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3900 ; RV32IZHINXMIN-NEXT: beqz a4, .LBB21_6
3901 ; RV32IZHINXMIN-NEXT: # %bb.5:
3902 ; RV32IZHINXMIN-NEXT: addi a3, a5, -1
3903 ; RV32IZHINXMIN-NEXT: .LBB21_6:
3904 ; RV32IZHINXMIN-NEXT: and a1, a2, a3
3905 ; RV32IZHINXMIN-NEXT: ret
3906 ;
3907 ; RV64IZHINXMIN-LABEL: test_rint_si64:
3908 ; RV64IZHINXMIN: # %bb.0:
3909 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3910 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3911 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3912 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3913 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB21_2
3914 ; RV64IZHINXMIN-NEXT: # %bb.1:
3915 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0
3916 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1
3917 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3918 ; RV64IZHINXMIN-NEXT: .LBB21_2:
3919 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3920 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3921 ; RV64IZHINXMIN-NEXT: fcvt.l.s a1, a0, rtz
3922 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
3923 ; RV64IZHINXMIN-NEXT: seqz a0, a0
3924 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
3925 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
3926 ; RV64IZHINXMIN-NEXT: ret
3927 %a = call half @llvm.rint.f16(half %x)
3928 %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
3929 ret i64 %b
3930 }
3932 define signext i32 @test_rint_ui32(half %x) {
3933 ; CHECKIZFH-LABEL: test_rint_ui32:
3934 ; CHECKIZFH: # %bb.0:
3935 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0
3936 ; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
3937 ; CHECKIZFH-NEXT: seqz a1, a1
3938 ; CHECKIZFH-NEXT: addi a1, a1, -1
3939 ; CHECKIZFH-NEXT: and a0, a1, a0
3940 ; CHECKIZFH-NEXT: ret
3941 ;
3942 ; RV32IZHINX-LABEL: test_rint_ui32:
3943 ; RV32IZHINX: # %bb.0:
3944 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI22_0)
3945 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
3946 ; RV32IZHINX-NEXT: fabs.h a2, a0
3947 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3948 ; RV32IZHINX-NEXT: beqz a1, .LBB22_2
3949 ; RV32IZHINX-NEXT: # %bb.1:
3950 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0
3951 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1
3952 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3953 ; RV32IZHINX-NEXT: .LBB22_2:
3954 ; RV32IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
3955 ; RV32IZHINX-NEXT: feq.h a0, a0, a0
3956 ; RV32IZHINX-NEXT: seqz a0, a0
3957 ; RV32IZHINX-NEXT: addi a0, a0, -1
3958 ; RV32IZHINX-NEXT: and a0, a0, a1
3959 ; RV32IZHINX-NEXT: ret
3960 ;
3961 ; RV64IZHINX-LABEL: test_rint_ui32:
3962 ; RV64IZHINX: # %bb.0:
3963 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI22_0)
3964 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
3965 ; RV64IZHINX-NEXT: fabs.h a2, a0
3966 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3967 ; RV64IZHINX-NEXT: beqz a1, .LBB22_2
3968 ; RV64IZHINX-NEXT: # %bb.1:
3969 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0
3970 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1
3971 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3972 ; RV64IZHINX-NEXT: .LBB22_2:
3973 ; RV64IZHINX-NEXT: fcvt.wu.h a1, a0, rtz
3974 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
3975 ; RV64IZHINX-NEXT: seqz a0, a0
3976 ; RV64IZHINX-NEXT: addiw a0, a0, -1
3977 ; RV64IZHINX-NEXT: and a0, a1, a0
3978 ; RV64IZHINX-NEXT: ret
3979 ;
3980 ; RV32IZFHMIN-LABEL: test_rint_ui32:
3981 ; RV32IZFHMIN: # %bb.0:
3982 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3983 ; RV32IZFHMIN-NEXT: lui a0, 307200
3984 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3985 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3986 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3987 ; RV32IZFHMIN-NEXT: beqz a0, .LBB22_2
3988 ; RV32IZFHMIN-NEXT: # %bb.1:
3989 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5
3990 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0
3991 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3992 ; RV32IZFHMIN-NEXT: .LBB22_2:
3993 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3994 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3995 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
3996 ; RV32IZFHMIN-NEXT: feq.s a1, fa5, fa5
3997 ; RV32IZFHMIN-NEXT: seqz a1, a1
3998 ; RV32IZFHMIN-NEXT: addi a1, a1, -1
3999 ; RV32IZFHMIN-NEXT: and a0, a1, a0
4000 ; RV32IZFHMIN-NEXT: ret
4001 ;
4002 ; RV64IZFHMIN-LABEL: test_rint_ui32:
4003 ; RV64IZFHMIN: # %bb.0:
4004 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4005 ; RV64IZFHMIN-NEXT: lui a0, 307200
4006 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4007 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4008 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4009 ; RV64IZFHMIN-NEXT: beqz a0, .LBB22_2
4010 ; RV64IZFHMIN-NEXT: # %bb.1:
4011 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5
4012 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0
4013 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4014 ; RV64IZFHMIN-NEXT: .LBB22_2:
4015 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4016 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4017 ; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
4018 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
4019 ; RV64IZFHMIN-NEXT: seqz a1, a1
4020 ; RV64IZFHMIN-NEXT: addiw a1, a1, -1
4021 ; RV64IZFHMIN-NEXT: and a0, a0, a1
4022 ; RV64IZFHMIN-NEXT: ret
4023 ;
4024 ; RV32IZHINXMIN-LABEL: test_rint_ui32:
4025 ; RV32IZHINXMIN: # %bb.0:
4026 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4027 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4028 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4029 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4030 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB22_2
4031 ; RV32IZHINXMIN-NEXT: # %bb.1:
4032 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0
4033 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1
4034 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4035 ; RV32IZHINXMIN-NEXT: .LBB22_2:
4036 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4037 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4038 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
4039 ; RV32IZHINXMIN-NEXT: feq.s a0, a0, a0
4040 ; RV32IZHINXMIN-NEXT: seqz a0, a0
4041 ; RV32IZHINXMIN-NEXT: addi a0, a0, -1
4042 ; RV32IZHINXMIN-NEXT: and a0, a0, a1
4043 ; RV32IZHINXMIN-NEXT: ret
4044 ;
4045 ; RV64IZHINXMIN-LABEL: test_rint_ui32:
4046 ; RV64IZHINXMIN: # %bb.0:
4047 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4048 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4049 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4050 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4051 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB22_2
4052 ; RV64IZHINXMIN-NEXT: # %bb.1:
4053 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0
4054 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1
4055 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4056 ; RV64IZHINXMIN-NEXT: .LBB22_2:
4057 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4058 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4059 ; RV64IZHINXMIN-NEXT: fcvt.wu.s a1, a0, rtz
4060 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
4061 ; RV64IZHINXMIN-NEXT: seqz a0, a0
4062 ; RV64IZHINXMIN-NEXT: addiw a0, a0, -1
4063 ; RV64IZHINXMIN-NEXT: and a0, a1, a0
4064 ; RV64IZHINXMIN-NEXT: ret
4065 %a = call half @llvm.rint.f16(half %x)
4066 %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
4067 ret i32 %b
4068 }
4070 define i64 @test_rint_ui64(half %x) nounwind {
4071 ; RV32IZFH-LABEL: test_rint_ui64:
4072 ; RV32IZFH: # %bb.0:
4073 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI23_0)
4074 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
4075 ; RV32IZFH-NEXT: fabs.h fa4, fa0
4076 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
4077 ; RV32IZFH-NEXT: beqz a0, .LBB23_2
4078 ; RV32IZFH-NEXT: # %bb.1:
4079 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0
4080 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0
4081 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
4082 ; RV32IZFH-NEXT: .LBB23_2:
4083 ; RV32IZFH-NEXT: addi sp, sp, -16
4084 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4085 ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
4086 ; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
4087 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
4088 ; RV32IZFH-NEXT: fmv.w.x fa5, zero
4089 ; RV32IZFH-NEXT: fle.s a0, fa5, fs0
4090 ; RV32IZFH-NEXT: neg s0, a0
4091 ; RV32IZFH-NEXT: fmv.s fa0, fs0
4092 ; RV32IZFH-NEXT: call __fixunssfdi
4093 ; RV32IZFH-NEXT: lui a2, %hi(.LCPI23_1)
4094 ; RV32IZFH-NEXT: flw fa5, %lo(.LCPI23_1)(a2)
4095 ; RV32IZFH-NEXT: and a0, s0, a0
4096 ; RV32IZFH-NEXT: flt.s a2, fa5, fs0
4097 ; RV32IZFH-NEXT: neg a2, a2
4098 ; RV32IZFH-NEXT: or a0, a2, a0
4099 ; RV32IZFH-NEXT: and a1, s0, a1
4100 ; RV32IZFH-NEXT: or a1, a2, a1
4101 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4102 ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
4103 ; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
4104 ; RV32IZFH-NEXT: addi sp, sp, 16
4105 ; RV32IZFH-NEXT: ret
4106 ;
4107 ; RV64IZFH-LABEL: test_rint_ui64:
4108 ; RV64IZFH: # %bb.0:
4109 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0
4110 ; RV64IZFH-NEXT: feq.h a1, fa0, fa0
4111 ; RV64IZFH-NEXT: seqz a1, a1
4112 ; RV64IZFH-NEXT: addi a1, a1, -1
4113 ; RV64IZFH-NEXT: and a0, a1, a0
4114 ; RV64IZFH-NEXT: ret
4115 ;
4116 ; RV32IZHINX-LABEL: test_rint_ui64:
4117 ; RV32IZHINX: # %bb.0:
4118 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
4119 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
4120 ; RV32IZHINX-NEXT: fabs.h a2, a0
4121 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
4122 ; RV32IZHINX-NEXT: beqz a1, .LBB23_2
4123 ; RV32IZHINX-NEXT: # %bb.1:
4124 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0
4125 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1
4126 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
4127 ; RV32IZHINX-NEXT: .LBB23_2:
4128 ; RV32IZHINX-NEXT: addi sp, sp, -16
4129 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4130 ; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
4131 ; RV32IZHINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
4132 ; RV32IZHINX-NEXT: fcvt.s.h s0, a0
4133 ; RV32IZHINX-NEXT: fle.s a0, zero, s0
4134 ; RV32IZHINX-NEXT: neg s1, a0
4135 ; RV32IZHINX-NEXT: mv a0, s0
4136 ; RV32IZHINX-NEXT: call __fixunssfdi
4137 ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI23_1)
4138 ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI23_1)(a2)
4139 ; RV32IZHINX-NEXT: and a0, s1, a0
4140 ; RV32IZHINX-NEXT: flt.s a2, a2, s0
4141 ; RV32IZHINX-NEXT: neg a2, a2
4142 ; RV32IZHINX-NEXT: or a0, a2, a0
4143 ; RV32IZHINX-NEXT: and a1, s1, a1
4144 ; RV32IZHINX-NEXT: or a1, a2, a1
4145 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4146 ; RV32IZHINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
4147 ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
4148 ; RV32IZHINX-NEXT: addi sp, sp, 16
4149 ; RV32IZHINX-NEXT: ret
4150 ;
4151 ; RV64IZHINX-LABEL: test_rint_ui64:
4152 ; RV64IZHINX: # %bb.0:
4153 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
4154 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
4155 ; RV64IZHINX-NEXT: fabs.h a2, a0
4156 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
4157 ; RV64IZHINX-NEXT: beqz a1, .LBB23_2
4158 ; RV64IZHINX-NEXT: # %bb.1:
4159 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0
4160 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1
4161 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
4162 ; RV64IZHINX-NEXT: .LBB23_2:
4163 ; RV64IZHINX-NEXT: fcvt.lu.h a1, a0, rtz
4164 ; RV64IZHINX-NEXT: feq.h a0, a0, a0
4165 ; RV64IZHINX-NEXT: seqz a0, a0
4166 ; RV64IZHINX-NEXT: addi a0, a0, -1
4167 ; RV64IZHINX-NEXT: and a0, a0, a1
4168 ; RV64IZHINX-NEXT: ret
4169 ;
4170 ; RV32IZFHMIN-LABEL: test_rint_ui64:
4171 ; RV32IZFHMIN: # %bb.0:
4172 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4173 ; RV32IZFHMIN-NEXT: lui a0, 307200
4174 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
4175 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
4176 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
4177 ; RV32IZFHMIN-NEXT: beqz a0, .LBB23_2
4178 ; RV32IZFHMIN-NEXT: # %bb.1:
4179 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5
4180 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0
4181 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4182 ; RV32IZFHMIN-NEXT: .LBB23_2:
4183 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
4184 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4185 ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
4186 ; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
4187 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4188 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5
4189 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, zero
4190 ; RV32IZFHMIN-NEXT: fle.s a0, fa5, fs0
4191 ; RV32IZFHMIN-NEXT: neg s0, a0
4192 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0
4193 ; RV32IZFHMIN-NEXT: call __fixunssfdi
4194 ; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI23_0)
4195 ; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI23_0)(a2)
4196 ; RV32IZFHMIN-NEXT: and a0, s0, a0
4197 ; RV32IZFHMIN-NEXT: flt.s a2, fa5, fs0
4198 ; RV32IZFHMIN-NEXT: neg a2, a2
4199 ; RV32IZFHMIN-NEXT: or a0, a2, a0
4200 ; RV32IZFHMIN-NEXT: and a1, s0, a1
4201 ; RV32IZFHMIN-NEXT: or a1, a2, a1
4202 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4203 ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
4204 ; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
4205 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
4206 ; RV32IZFHMIN-NEXT: ret
4207 ;
4208 ; RV64IZFHMIN-LABEL: test_rint_ui64:
4209 ; RV64IZFHMIN: # %bb.0:
4210 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4211 ; RV64IZFHMIN-NEXT: lui a0, 307200
4212 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4213 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4214 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4215 ; RV64IZFHMIN-NEXT: beqz a0, .LBB23_2
4216 ; RV64IZFHMIN-NEXT: # %bb.1:
4217 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5
4218 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0
4219 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4220 ; RV64IZFHMIN-NEXT: .LBB23_2:
4221 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4222 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4223 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
4224 ; RV64IZFHMIN-NEXT: feq.s a1, fa5, fa5
4225 ; RV64IZFHMIN-NEXT: seqz a1, a1
4226 ; RV64IZFHMIN-NEXT: addi a1, a1, -1
4227 ; RV64IZFHMIN-NEXT: and a0, a1, a0
4228 ; RV64IZFHMIN-NEXT: ret
4229 ;
4230 ; RV32IZHINXMIN-LABEL: test_rint_ui64:
4231 ; RV32IZHINXMIN: # %bb.0:
4232 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4233 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4234 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4235 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4236 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB23_2
4237 ; RV32IZHINXMIN-NEXT: # %bb.1:
4238 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0
4239 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1
4240 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4241 ; RV32IZHINXMIN-NEXT: .LBB23_2:
4242 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
4243 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4244 ; RV32IZHINXMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
4245 ; RV32IZHINXMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
4246 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4247 ; RV32IZHINXMIN-NEXT: fcvt.s.h s0, a0
4248 ; RV32IZHINXMIN-NEXT: fle.s a0, zero, s0
4249 ; RV32IZHINXMIN-NEXT: neg s1, a0
4250 ; RV32IZHINXMIN-NEXT: mv a0, s0
4251 ; RV32IZHINXMIN-NEXT: call __fixunssfdi
4252 ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0)
4253 ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI23_0)(a2)
4254 ; RV32IZHINXMIN-NEXT: and a0, s1, a0
4255 ; RV32IZHINXMIN-NEXT: flt.s a2, a2, s0
4256 ; RV32IZHINXMIN-NEXT: neg a2, a2
4257 ; RV32IZHINXMIN-NEXT: or a0, a2, a0
4258 ; RV32IZHINXMIN-NEXT: and a1, s1, a1
4259 ; RV32IZHINXMIN-NEXT: or a1, a2, a1
4260 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4261 ; RV32IZHINXMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
4262 ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
4263 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
4264 ; RV32IZHINXMIN-NEXT: ret
4265 ;
4266 ; RV64IZHINXMIN-LABEL: test_rint_ui64:
4267 ; RV64IZHINXMIN: # %bb.0:
4268 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4269 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4270 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4271 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4272 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB23_2
4273 ; RV64IZHINXMIN-NEXT: # %bb.1:
4274 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0
4275 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1
4276 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4277 ; RV64IZHINXMIN-NEXT: .LBB23_2:
4278 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4279 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4280 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a1, a0, rtz
4281 ; RV64IZHINXMIN-NEXT: feq.s a0, a0, a0
4282 ; RV64IZHINXMIN-NEXT: seqz a0, a0
4283 ; RV64IZHINXMIN-NEXT: addi a0, a0, -1
4284 ; RV64IZHINXMIN-NEXT: and a0, a0, a1
4285 ; RV64IZHINXMIN-NEXT: ret
4286 %a = call half @llvm.rint.f16(half %x)
4287 %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
4288 ret i64 %b
4289 }
4291 declare half @llvm.floor.f16(half)
4292 declare half @llvm.ceil.f16(half)
4293 declare half @llvm.trunc.f16(half)
4294 declare half @llvm.round.f16(half)
4295 declare half @llvm.roundeven.f16(half)
4296 declare half @llvm.rint.f16(half)
4297 declare i32 @llvm.fptosi.sat.i32.f16(half)
4298 declare i64 @llvm.fptosi.sat.i64.f16(half)
4299 declare i32 @llvm.fptoui.sat.i32.f16(half)
4300 declare i64 @llvm.fptoui.sat.i64.f16(half)