| blob | 173164db5b7807e81daaf68044cd3614fbc30e52 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \
7 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \
9 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
10 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
11 ; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
12 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
13 ; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
14 ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
15 ; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
16 ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
17 ; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
19 define signext i8 @test_floor_si8(half %x) {
20 ; RV32IZFH-LABEL: test_floor_si8:
21 ; RV32IZFH: # %bb.0:
22 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
23 ; RV32IZFH-NEXT: ret
24 ;
25 ; RV64IZFH-LABEL: test_floor_si8:
26 ; RV64IZFH: # %bb.0:
27 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
28 ; RV64IZFH-NEXT: ret
29 ;
30 ; RV32IZHINX-LABEL: test_floor_si8:
31 ; RV32IZHINX: # %bb.0:
32 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI0_0)
33 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI0_0)(a1)
34 ; RV32IZHINX-NEXT: fabs.h a2, a0
35 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
36 ; RV32IZHINX-NEXT: beqz a1, .LBB0_2
37 ; RV32IZHINX-NEXT: # %bb.1:
38 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
39 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
40 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
41 ; RV32IZHINX-NEXT: .LBB0_2:
42 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
43 ; RV32IZHINX-NEXT: ret
44 ;
45 ; RV64IZHINX-LABEL: test_floor_si8:
46 ; RV64IZHINX: # %bb.0:
47 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI0_0)
48 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI0_0)(a1)
49 ; RV64IZHINX-NEXT: fabs.h a2, a0
50 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
51 ; RV64IZHINX-NEXT: beqz a1, .LBB0_2
52 ; RV64IZHINX-NEXT: # %bb.1:
53 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
54 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
55 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
56 ; RV64IZHINX-NEXT: .LBB0_2:
57 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
58 ; RV64IZHINX-NEXT: ret
59 ;
60 ; RV32IZFHMIN-LABEL: test_floor_si8:
61 ; RV32IZFHMIN: # %bb.0:
62 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
63 ; RV32IZFHMIN-NEXT: lui a0, 307200
64 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
65 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
66 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
67 ; RV32IZFHMIN-NEXT: beqz a0, .LBB0_2
68 ; RV32IZFHMIN-NEXT: # %bb.1:
69 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
70 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
71 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
72 ; RV32IZFHMIN-NEXT: .LBB0_2:
73 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
74 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
75 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
76 ; RV32IZFHMIN-NEXT: ret
77 ;
78 ; RV64IZFHMIN-LABEL: test_floor_si8:
79 ; RV64IZFHMIN: # %bb.0:
80 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
81 ; RV64IZFHMIN-NEXT: lui a0, 307200
82 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
83 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
84 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
85 ; RV64IZFHMIN-NEXT: beqz a0, .LBB0_2
86 ; RV64IZFHMIN-NEXT: # %bb.1:
87 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
88 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
89 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
90 ; RV64IZFHMIN-NEXT: .LBB0_2:
91 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
92 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
93 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
94 ; RV64IZFHMIN-NEXT: ret
95 ;
96 ; RV32IZHINXMIN-LABEL: test_floor_si8:
97 ; RV32IZHINXMIN: # %bb.0:
98 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
99 ; RV32IZHINXMIN-NEXT: lui a1, 307200
100 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
101 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
102 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB0_2
103 ; RV32IZHINXMIN-NEXT: # %bb.1:
104 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
105 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
106 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
107 ; RV32IZHINXMIN-NEXT: .LBB0_2:
108 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
109 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
110 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
111 ; RV32IZHINXMIN-NEXT: ret
112 ;
113 ; RV64IZHINXMIN-LABEL: test_floor_si8:
114 ; RV64IZHINXMIN: # %bb.0:
115 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
116 ; RV64IZHINXMIN-NEXT: lui a1, 307200
117 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
118 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
119 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB0_2
120 ; RV64IZHINXMIN-NEXT: # %bb.1:
121 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
122 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
123 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
124 ; RV64IZHINXMIN-NEXT: .LBB0_2:
125 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
126 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
127 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
128 ; RV64IZHINXMIN-NEXT: ret
129 %a = call half @llvm.floor.f16(half %x)
130 %b = fptosi half %a to i8
131 ret i8 %b
132 }
134 define signext i16 @test_floor_si16(half %x) {
135 ; RV32IZFH-LABEL: test_floor_si16:
136 ; RV32IZFH: # %bb.0:
137 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
138 ; RV32IZFH-NEXT: ret
139 ;
140 ; RV64IZFH-LABEL: test_floor_si16:
141 ; RV64IZFH: # %bb.0:
142 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
143 ; RV64IZFH-NEXT: ret
144 ;
145 ; RV32IZHINX-LABEL: test_floor_si16:
146 ; RV32IZHINX: # %bb.0:
147 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
148 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
149 ; RV32IZHINX-NEXT: fabs.h a2, a0
150 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
151 ; RV32IZHINX-NEXT: beqz a1, .LBB1_2
152 ; RV32IZHINX-NEXT: # %bb.1:
153 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
154 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
155 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
156 ; RV32IZHINX-NEXT: .LBB1_2:
157 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
158 ; RV32IZHINX-NEXT: ret
159 ;
160 ; RV64IZHINX-LABEL: test_floor_si16:
161 ; RV64IZHINX: # %bb.0:
162 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI1_0)
163 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI1_0)(a1)
164 ; RV64IZHINX-NEXT: fabs.h a2, a0
165 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
166 ; RV64IZHINX-NEXT: beqz a1, .LBB1_2
167 ; RV64IZHINX-NEXT: # %bb.1:
168 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
169 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
170 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
171 ; RV64IZHINX-NEXT: .LBB1_2:
172 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
173 ; RV64IZHINX-NEXT: ret
174 ;
175 ; RV32IZFHMIN-LABEL: test_floor_si16:
176 ; RV32IZFHMIN: # %bb.0:
177 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
178 ; RV32IZFHMIN-NEXT: lui a0, 307200
179 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
180 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
181 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
182 ; RV32IZFHMIN-NEXT: beqz a0, .LBB1_2
183 ; RV32IZFHMIN-NEXT: # %bb.1:
184 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
185 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
186 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
187 ; RV32IZFHMIN-NEXT: .LBB1_2:
188 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
189 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
190 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
191 ; RV32IZFHMIN-NEXT: ret
192 ;
193 ; RV64IZFHMIN-LABEL: test_floor_si16:
194 ; RV64IZFHMIN: # %bb.0:
195 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
196 ; RV64IZFHMIN-NEXT: lui a0, 307200
197 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
198 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
199 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
200 ; RV64IZFHMIN-NEXT: beqz a0, .LBB1_2
201 ; RV64IZFHMIN-NEXT: # %bb.1:
202 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
203 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
204 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
205 ; RV64IZFHMIN-NEXT: .LBB1_2:
206 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
207 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
208 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
209 ; RV64IZFHMIN-NEXT: ret
210 ;
211 ; RV32IZHINXMIN-LABEL: test_floor_si16:
212 ; RV32IZHINXMIN: # %bb.0:
213 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
214 ; RV32IZHINXMIN-NEXT: lui a1, 307200
215 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
216 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
217 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB1_2
218 ; RV32IZHINXMIN-NEXT: # %bb.1:
219 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
220 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
221 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
222 ; RV32IZHINXMIN-NEXT: .LBB1_2:
223 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
224 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
225 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
226 ; RV32IZHINXMIN-NEXT: ret
227 ;
228 ; RV64IZHINXMIN-LABEL: test_floor_si16:
229 ; RV64IZHINXMIN: # %bb.0:
230 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
231 ; RV64IZHINXMIN-NEXT: lui a1, 307200
232 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
233 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
234 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB1_2
235 ; RV64IZHINXMIN-NEXT: # %bb.1:
236 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
237 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
238 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
239 ; RV64IZHINXMIN-NEXT: .LBB1_2:
240 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
241 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
242 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
243 ; RV64IZHINXMIN-NEXT: ret
244 %a = call half @llvm.floor.f16(half %x)
245 %b = fptosi half %a to i16
246 ret i16 %b
247 }
249 define signext i32 @test_floor_si32(half %x) {
250 ; CHECKIZFH-LABEL: test_floor_si32:
251 ; CHECKIZFH: # %bb.0:
252 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
253 ; CHECKIZFH-NEXT: ret
254 ;
255 ; CHECKIZHINX-LABEL: test_floor_si32:
256 ; CHECKIZHINX: # %bb.0:
257 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI2_0)
258 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI2_0)(a1)
259 ; CHECKIZHINX-NEXT: fabs.h a2, a0
260 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
261 ; CHECKIZHINX-NEXT: beqz a1, .LBB2_2
262 ; CHECKIZHINX-NEXT: # %bb.1:
263 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
264 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
265 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
266 ; CHECKIZHINX-NEXT: .LBB2_2:
267 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
268 ; CHECKIZHINX-NEXT: ret
269 ;
270 ; CHECKIZFHMIN-LABEL: test_floor_si32:
271 ; CHECKIZFHMIN: # %bb.0:
272 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
273 ; CHECKIZFHMIN-NEXT: lui a0, 307200
274 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
275 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
276 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
277 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB2_2
278 ; CHECKIZFHMIN-NEXT: # %bb.1:
279 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
280 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
281 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
282 ; CHECKIZFHMIN-NEXT: .LBB2_2:
283 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
284 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
285 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
286 ; CHECKIZFHMIN-NEXT: ret
287 ;
288 ; CHECKIZHINXMIN-LABEL: test_floor_si32:
289 ; CHECKIZHINXMIN: # %bb.0:
290 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
291 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
292 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
293 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
294 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB2_2
295 ; CHECKIZHINXMIN-NEXT: # %bb.1:
296 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
297 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
298 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
299 ; CHECKIZHINXMIN-NEXT: .LBB2_2:
300 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
301 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
302 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
303 ; CHECKIZHINXMIN-NEXT: ret
304 %a = call half @llvm.floor.f16(half %x)
305 %b = fptosi half %a to i32
306 ret i32 %b
307 }
309 define i64 @test_floor_si64(half %x) {
310 ; RV32IZFH-LABEL: test_floor_si64:
311 ; RV32IZFH: # %bb.0:
312 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI3_0)
313 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI3_0)(a0)
314 ; RV32IZFH-NEXT: fabs.h fa4, fa0
315 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
316 ; RV32IZFH-NEXT: beqz a0, .LBB3_2
317 ; RV32IZFH-NEXT: # %bb.1:
318 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
319 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
320 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
321 ; RV32IZFH-NEXT: .LBB3_2:
322 ; RV32IZFH-NEXT: addi sp, sp, -16
323 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
324 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
325 ; RV32IZFH-NEXT: .cfi_offset ra, -4
326 ; RV32IZFH-NEXT: call __fixhfdi
327 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
328 ; RV32IZFH-NEXT: addi sp, sp, 16
329 ; RV32IZFH-NEXT: ret
330 ;
331 ; RV64IZFH-LABEL: test_floor_si64:
332 ; RV64IZFH: # %bb.0:
333 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
334 ; RV64IZFH-NEXT: ret
335 ;
336 ; RV32IZHINX-LABEL: test_floor_si64:
337 ; RV32IZHINX: # %bb.0:
338 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
339 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
340 ; RV32IZHINX-NEXT: fabs.h a2, a0
341 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
342 ; RV32IZHINX-NEXT: beqz a1, .LBB3_2
343 ; RV32IZHINX-NEXT: # %bb.1:
344 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
345 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
346 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
347 ; RV32IZHINX-NEXT: .LBB3_2:
348 ; RV32IZHINX-NEXT: addi sp, sp, -16
349 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
350 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
351 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
352 ; RV32IZHINX-NEXT: call __fixhfdi
353 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
354 ; RV32IZHINX-NEXT: addi sp, sp, 16
355 ; RV32IZHINX-NEXT: ret
356 ;
357 ; RV64IZHINX-LABEL: test_floor_si64:
358 ; RV64IZHINX: # %bb.0:
359 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI3_0)
360 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI3_0)(a1)
361 ; RV64IZHINX-NEXT: fabs.h a2, a0
362 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
363 ; RV64IZHINX-NEXT: beqz a1, .LBB3_2
364 ; RV64IZHINX-NEXT: # %bb.1:
365 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
366 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
367 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
368 ; RV64IZHINX-NEXT: .LBB3_2:
369 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
370 ; RV64IZHINX-NEXT: ret
371 ;
372 ; RV32IZFHMIN-LABEL: test_floor_si64:
373 ; RV32IZFHMIN: # %bb.0:
374 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
375 ; RV32IZFHMIN-NEXT: lui a0, 307200
376 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
377 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
378 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
379 ; RV32IZFHMIN-NEXT: beqz a0, .LBB3_2
380 ; RV32IZFHMIN-NEXT: # %bb.1:
381 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
382 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
383 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
384 ; RV32IZFHMIN-NEXT: .LBB3_2:
385 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
386 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
387 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
388 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
389 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
390 ; RV32IZFHMIN-NEXT: call __fixhfdi
391 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
392 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
393 ; RV32IZFHMIN-NEXT: ret
394 ;
395 ; RV64IZFHMIN-LABEL: test_floor_si64:
396 ; RV64IZFHMIN: # %bb.0:
397 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
398 ; RV64IZFHMIN-NEXT: lui a0, 307200
399 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
400 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
401 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
402 ; RV64IZFHMIN-NEXT: beqz a0, .LBB3_2
403 ; RV64IZFHMIN-NEXT: # %bb.1:
404 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
405 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
406 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
407 ; RV64IZFHMIN-NEXT: .LBB3_2:
408 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
409 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
410 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
411 ; RV64IZFHMIN-NEXT: ret
412 ;
413 ; RV32IZHINXMIN-LABEL: test_floor_si64:
414 ; RV32IZHINXMIN: # %bb.0:
415 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
416 ; RV32IZHINXMIN-NEXT: lui a1, 307200
417 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
418 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
419 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB3_2
420 ; RV32IZHINXMIN-NEXT: # %bb.1:
421 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
422 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
423 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
424 ; RV32IZHINXMIN-NEXT: .LBB3_2:
425 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
426 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
427 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
428 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
429 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
430 ; RV32IZHINXMIN-NEXT: call __fixhfdi
431 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
432 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
433 ; RV32IZHINXMIN-NEXT: ret
434 ;
435 ; RV64IZHINXMIN-LABEL: test_floor_si64:
436 ; RV64IZHINXMIN: # %bb.0:
437 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
438 ; RV64IZHINXMIN-NEXT: lui a1, 307200
439 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
440 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
441 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB3_2
442 ; RV64IZHINXMIN-NEXT: # %bb.1:
443 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
444 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
445 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
446 ; RV64IZHINXMIN-NEXT: .LBB3_2:
447 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
448 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
449 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
450 ; RV64IZHINXMIN-NEXT: ret
451 %a = call half @llvm.floor.f16(half %x)
452 %b = fptosi half %a to i64
453 ret i64 %b
454 }
456 define zeroext i8 @test_floor_ui8(half %x) {
457 ; RV32IZFH-LABEL: test_floor_ui8:
458 ; RV32IZFH: # %bb.0:
459 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
460 ; RV32IZFH-NEXT: ret
461 ;
462 ; RV64IZFH-LABEL: test_floor_ui8:
463 ; RV64IZFH: # %bb.0:
464 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
465 ; RV64IZFH-NEXT: ret
466 ;
467 ; RV32IZHINX-LABEL: test_floor_ui8:
468 ; RV32IZHINX: # %bb.0:
469 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI4_0)
470 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI4_0)(a1)
471 ; RV32IZHINX-NEXT: fabs.h a2, a0
472 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
473 ; RV32IZHINX-NEXT: beqz a1, .LBB4_2
474 ; RV32IZHINX-NEXT: # %bb.1:
475 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
476 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
477 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
478 ; RV32IZHINX-NEXT: .LBB4_2:
479 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
480 ; RV32IZHINX-NEXT: ret
481 ;
482 ; RV64IZHINX-LABEL: test_floor_ui8:
483 ; RV64IZHINX: # %bb.0:
484 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI4_0)
485 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI4_0)(a1)
486 ; RV64IZHINX-NEXT: fabs.h a2, a0
487 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
488 ; RV64IZHINX-NEXT: beqz a1, .LBB4_2
489 ; RV64IZHINX-NEXT: # %bb.1:
490 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
491 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
492 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
493 ; RV64IZHINX-NEXT: .LBB4_2:
494 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
495 ; RV64IZHINX-NEXT: ret
496 ;
497 ; RV32IZFHMIN-LABEL: test_floor_ui8:
498 ; RV32IZFHMIN: # %bb.0:
499 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
500 ; RV32IZFHMIN-NEXT: lui a0, 307200
501 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
502 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
503 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
504 ; RV32IZFHMIN-NEXT: beqz a0, .LBB4_2
505 ; RV32IZFHMIN-NEXT: # %bb.1:
506 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
507 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
508 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
509 ; RV32IZFHMIN-NEXT: .LBB4_2:
510 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
511 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
512 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
513 ; RV32IZFHMIN-NEXT: ret
514 ;
515 ; RV64IZFHMIN-LABEL: test_floor_ui8:
516 ; RV64IZFHMIN: # %bb.0:
517 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
518 ; RV64IZFHMIN-NEXT: lui a0, 307200
519 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
520 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
521 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
522 ; RV64IZFHMIN-NEXT: beqz a0, .LBB4_2
523 ; RV64IZFHMIN-NEXT: # %bb.1:
524 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
525 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
526 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
527 ; RV64IZFHMIN-NEXT: .LBB4_2:
528 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
529 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
530 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
531 ; RV64IZFHMIN-NEXT: ret
532 ;
533 ; RV32IZHINXMIN-LABEL: test_floor_ui8:
534 ; RV32IZHINXMIN: # %bb.0:
535 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
536 ; RV32IZHINXMIN-NEXT: lui a1, 307200
537 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
538 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
539 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB4_2
540 ; RV32IZHINXMIN-NEXT: # %bb.1:
541 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
542 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
543 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
544 ; RV32IZHINXMIN-NEXT: .LBB4_2:
545 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
546 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
547 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
548 ; RV32IZHINXMIN-NEXT: ret
549 ;
550 ; RV64IZHINXMIN-LABEL: test_floor_ui8:
551 ; RV64IZHINXMIN: # %bb.0:
552 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
553 ; RV64IZHINXMIN-NEXT: lui a1, 307200
554 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
555 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
556 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB4_2
557 ; RV64IZHINXMIN-NEXT: # %bb.1:
558 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
559 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
560 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
561 ; RV64IZHINXMIN-NEXT: .LBB4_2:
562 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
563 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
564 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
565 ; RV64IZHINXMIN-NEXT: ret
566 %a = call half @llvm.floor.f16(half %x)
567 %b = fptoui half %a to i8
568 ret i8 %b
569 }
571 define zeroext i16 @test_floor_ui16(half %x) {
572 ; RV32IZFH-LABEL: test_floor_ui16:
573 ; RV32IZFH: # %bb.0:
574 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
575 ; RV32IZFH-NEXT: ret
576 ;
577 ; RV64IZFH-LABEL: test_floor_ui16:
578 ; RV64IZFH: # %bb.0:
579 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
580 ; RV64IZFH-NEXT: ret
581 ;
582 ; RV32IZHINX-LABEL: test_floor_ui16:
583 ; RV32IZHINX: # %bb.0:
584 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
585 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
586 ; RV32IZHINX-NEXT: fabs.h a2, a0
587 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
588 ; RV32IZHINX-NEXT: beqz a1, .LBB5_2
589 ; RV32IZHINX-NEXT: # %bb.1:
590 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
591 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
592 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
593 ; RV32IZHINX-NEXT: .LBB5_2:
594 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
595 ; RV32IZHINX-NEXT: ret
596 ;
597 ; RV64IZHINX-LABEL: test_floor_ui16:
598 ; RV64IZHINX: # %bb.0:
599 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI5_0)
600 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI5_0)(a1)
601 ; RV64IZHINX-NEXT: fabs.h a2, a0
602 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
603 ; RV64IZHINX-NEXT: beqz a1, .LBB5_2
604 ; RV64IZHINX-NEXT: # %bb.1:
605 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
606 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
607 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
608 ; RV64IZHINX-NEXT: .LBB5_2:
609 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
610 ; RV64IZHINX-NEXT: ret
611 ;
612 ; RV32IZFHMIN-LABEL: test_floor_ui16:
613 ; RV32IZFHMIN: # %bb.0:
614 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
615 ; RV32IZFHMIN-NEXT: lui a0, 307200
616 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
617 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
618 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
619 ; RV32IZFHMIN-NEXT: beqz a0, .LBB5_2
620 ; RV32IZFHMIN-NEXT: # %bb.1:
621 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
622 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
623 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
624 ; RV32IZFHMIN-NEXT: .LBB5_2:
625 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
626 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
627 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
628 ; RV32IZFHMIN-NEXT: ret
629 ;
630 ; RV64IZFHMIN-LABEL: test_floor_ui16:
631 ; RV64IZFHMIN: # %bb.0:
632 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
633 ; RV64IZFHMIN-NEXT: lui a0, 307200
634 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
635 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
636 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
637 ; RV64IZFHMIN-NEXT: beqz a0, .LBB5_2
638 ; RV64IZFHMIN-NEXT: # %bb.1:
639 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
640 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
641 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
642 ; RV64IZFHMIN-NEXT: .LBB5_2:
643 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
644 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
645 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
646 ; RV64IZFHMIN-NEXT: ret
647 ;
648 ; RV32IZHINXMIN-LABEL: test_floor_ui16:
649 ; RV32IZHINXMIN: # %bb.0:
650 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
651 ; RV32IZHINXMIN-NEXT: lui a1, 307200
652 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
653 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
654 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB5_2
655 ; RV32IZHINXMIN-NEXT: # %bb.1:
656 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
657 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
658 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
659 ; RV32IZHINXMIN-NEXT: .LBB5_2:
660 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
661 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
662 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
663 ; RV32IZHINXMIN-NEXT: ret
664 ;
665 ; RV64IZHINXMIN-LABEL: test_floor_ui16:
666 ; RV64IZHINXMIN: # %bb.0:
667 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
668 ; RV64IZHINXMIN-NEXT: lui a1, 307200
669 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
670 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
671 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB5_2
672 ; RV64IZHINXMIN-NEXT: # %bb.1:
673 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
674 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
675 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
676 ; RV64IZHINXMIN-NEXT: .LBB5_2:
677 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
678 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
679 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
680 ; RV64IZHINXMIN-NEXT: ret
681 %a = call half @llvm.floor.f16(half %x)
682 %b = fptoui half %a to i16
683 ret i16 %b
684 }
686 define signext i32 @test_floor_ui32(half %x) {
687 ; CHECKIZFH-LABEL: test_floor_ui32:
688 ; CHECKIZFH: # %bb.0:
689 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rdn
690 ; CHECKIZFH-NEXT: ret
691 ;
692 ; CHECKIZHINX-LABEL: test_floor_ui32:
693 ; CHECKIZHINX: # %bb.0:
694 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI6_0)
695 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI6_0)(a1)
696 ; CHECKIZHINX-NEXT: fabs.h a2, a0
697 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
698 ; CHECKIZHINX-NEXT: beqz a1, .LBB6_2
699 ; CHECKIZHINX-NEXT: # %bb.1:
700 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
701 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
702 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
703 ; CHECKIZHINX-NEXT: .LBB6_2:
704 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
705 ; CHECKIZHINX-NEXT: ret
706 ;
707 ; CHECKIZFHMIN-LABEL: test_floor_ui32:
708 ; CHECKIZFHMIN: # %bb.0:
709 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
710 ; CHECKIZFHMIN-NEXT: lui a0, 307200
711 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
712 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
713 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
714 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB6_2
715 ; CHECKIZFHMIN-NEXT: # %bb.1:
716 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
717 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
718 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
719 ; CHECKIZFHMIN-NEXT: .LBB6_2:
720 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
721 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
722 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
723 ; CHECKIZFHMIN-NEXT: ret
724 ;
725 ; CHECKIZHINXMIN-LABEL: test_floor_ui32:
726 ; CHECKIZHINXMIN: # %bb.0:
727 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
728 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
729 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
730 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
731 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB6_2
732 ; CHECKIZHINXMIN-NEXT: # %bb.1:
733 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
734 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
735 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
736 ; CHECKIZHINXMIN-NEXT: .LBB6_2:
737 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
738 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
739 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
740 ; CHECKIZHINXMIN-NEXT: ret
741 %a = call half @llvm.floor.f16(half %x)
742 %b = fptoui half %a to i32
743 ret i32 %b
744 }
746 define i64 @test_floor_ui64(half %x) {
747 ; RV32IZFH-LABEL: test_floor_ui64:
748 ; RV32IZFH: # %bb.0:
749 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI7_0)
750 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI7_0)(a0)
751 ; RV32IZFH-NEXT: fabs.h fa4, fa0
752 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
753 ; RV32IZFH-NEXT: beqz a0, .LBB7_2
754 ; RV32IZFH-NEXT: # %bb.1:
755 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
756 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rdn
757 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
758 ; RV32IZFH-NEXT: .LBB7_2:
759 ; RV32IZFH-NEXT: addi sp, sp, -16
760 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
761 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
762 ; RV32IZFH-NEXT: .cfi_offset ra, -4
763 ; RV32IZFH-NEXT: call __fixunshfdi
764 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
765 ; RV32IZFH-NEXT: addi sp, sp, 16
766 ; RV32IZFH-NEXT: ret
767 ;
768 ; RV64IZFH-LABEL: test_floor_ui64:
769 ; RV64IZFH: # %bb.0:
770 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
771 ; RV64IZFH-NEXT: ret
772 ;
773 ; RV32IZHINX-LABEL: test_floor_ui64:
774 ; RV32IZHINX: # %bb.0:
775 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
776 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
777 ; RV32IZHINX-NEXT: fabs.h a2, a0
778 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
779 ; RV32IZHINX-NEXT: beqz a1, .LBB7_2
780 ; RV32IZHINX-NEXT: # %bb.1:
781 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rdn
782 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rdn
783 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
784 ; RV32IZHINX-NEXT: .LBB7_2:
785 ; RV32IZHINX-NEXT: addi sp, sp, -16
786 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
787 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
788 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
789 ; RV32IZHINX-NEXT: call __fixunshfdi
790 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
791 ; RV32IZHINX-NEXT: addi sp, sp, 16
792 ; RV32IZHINX-NEXT: ret
793 ;
794 ; RV64IZHINX-LABEL: test_floor_ui64:
795 ; RV64IZHINX: # %bb.0:
796 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI7_0)
797 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI7_0)(a1)
798 ; RV64IZHINX-NEXT: fabs.h a2, a0
799 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
800 ; RV64IZHINX-NEXT: beqz a1, .LBB7_2
801 ; RV64IZHINX-NEXT: # %bb.1:
802 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rdn
803 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rdn
804 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
805 ; RV64IZHINX-NEXT: .LBB7_2:
806 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
807 ; RV64IZHINX-NEXT: ret
808 ;
809 ; RV32IZFHMIN-LABEL: test_floor_ui64:
810 ; RV32IZFHMIN: # %bb.0:
811 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
812 ; RV32IZFHMIN-NEXT: lui a0, 307200
813 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
814 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
815 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
816 ; RV32IZFHMIN-NEXT: beqz a0, .LBB7_2
817 ; RV32IZFHMIN-NEXT: # %bb.1:
818 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
819 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
820 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
821 ; RV32IZFHMIN-NEXT: .LBB7_2:
822 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
823 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
824 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
825 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
826 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
827 ; RV32IZFHMIN-NEXT: call __fixunshfdi
828 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
829 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
830 ; RV32IZFHMIN-NEXT: ret
831 ;
832 ; RV64IZFHMIN-LABEL: test_floor_ui64:
833 ; RV64IZFHMIN: # %bb.0:
834 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
835 ; RV64IZFHMIN-NEXT: lui a0, 307200
836 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
837 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
838 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
839 ; RV64IZFHMIN-NEXT: beqz a0, .LBB7_2
840 ; RV64IZFHMIN-NEXT: # %bb.1:
841 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
842 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
843 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
844 ; RV64IZFHMIN-NEXT: .LBB7_2:
845 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
846 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
847 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
848 ; RV64IZFHMIN-NEXT: ret
849 ;
850 ; RV32IZHINXMIN-LABEL: test_floor_ui64:
851 ; RV32IZHINXMIN: # %bb.0:
852 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
853 ; RV32IZHINXMIN-NEXT: lui a1, 307200
854 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
855 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
856 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB7_2
857 ; RV32IZHINXMIN-NEXT: # %bb.1:
858 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
859 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
860 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
861 ; RV32IZHINXMIN-NEXT: .LBB7_2:
862 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
863 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
864 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
865 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
866 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
867 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
868 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
869 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
870 ; RV32IZHINXMIN-NEXT: ret
871 ;
872 ; RV64IZHINXMIN-LABEL: test_floor_ui64:
873 ; RV64IZHINXMIN: # %bb.0:
874 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
875 ; RV64IZHINXMIN-NEXT: lui a1, 307200
876 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
877 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
878 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB7_2
879 ; RV64IZHINXMIN-NEXT: # %bb.1:
880 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
881 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
882 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
883 ; RV64IZHINXMIN-NEXT: .LBB7_2:
884 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
885 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
886 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
887 ; RV64IZHINXMIN-NEXT: ret
888 %a = call half @llvm.floor.f16(half %x)
889 %b = fptoui half %a to i64
890 ret i64 %b
891 }
893 define signext i8 @test_ceil_si8(half %x) {
894 ; RV32IZFH-LABEL: test_ceil_si8:
895 ; RV32IZFH: # %bb.0:
896 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
897 ; RV32IZFH-NEXT: ret
898 ;
899 ; RV64IZFH-LABEL: test_ceil_si8:
900 ; RV64IZFH: # %bb.0:
901 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
902 ; RV64IZFH-NEXT: ret
903 ;
904 ; RV32IZHINX-LABEL: test_ceil_si8:
905 ; RV32IZHINX: # %bb.0:
906 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI8_0)
907 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI8_0)(a1)
908 ; RV32IZHINX-NEXT: fabs.h a2, a0
909 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
910 ; RV32IZHINX-NEXT: beqz a1, .LBB8_2
911 ; RV32IZHINX-NEXT: # %bb.1:
912 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
913 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
914 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
915 ; RV32IZHINX-NEXT: .LBB8_2:
916 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
917 ; RV32IZHINX-NEXT: ret
918 ;
919 ; RV64IZHINX-LABEL: test_ceil_si8:
920 ; RV64IZHINX: # %bb.0:
921 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI8_0)
922 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI8_0)(a1)
923 ; RV64IZHINX-NEXT: fabs.h a2, a0
924 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
925 ; RV64IZHINX-NEXT: beqz a1, .LBB8_2
926 ; RV64IZHINX-NEXT: # %bb.1:
927 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
928 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
929 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
930 ; RV64IZHINX-NEXT: .LBB8_2:
931 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
932 ; RV64IZHINX-NEXT: ret
933 ;
934 ; RV32IZFHMIN-LABEL: test_ceil_si8:
935 ; RV32IZFHMIN: # %bb.0:
936 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
937 ; RV32IZFHMIN-NEXT: lui a0, 307200
938 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
939 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
940 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
941 ; RV32IZFHMIN-NEXT: beqz a0, .LBB8_2
942 ; RV32IZFHMIN-NEXT: # %bb.1:
943 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
944 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
945 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
946 ; RV32IZFHMIN-NEXT: .LBB8_2:
947 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
948 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
949 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
950 ; RV32IZFHMIN-NEXT: ret
951 ;
952 ; RV64IZFHMIN-LABEL: test_ceil_si8:
953 ; RV64IZFHMIN: # %bb.0:
954 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
955 ; RV64IZFHMIN-NEXT: lui a0, 307200
956 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
957 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
958 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
959 ; RV64IZFHMIN-NEXT: beqz a0, .LBB8_2
960 ; RV64IZFHMIN-NEXT: # %bb.1:
961 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
962 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
963 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
964 ; RV64IZFHMIN-NEXT: .LBB8_2:
965 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
966 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
967 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
968 ; RV64IZFHMIN-NEXT: ret
969 ;
970 ; RV32IZHINXMIN-LABEL: test_ceil_si8:
971 ; RV32IZHINXMIN: # %bb.0:
972 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
973 ; RV32IZHINXMIN-NEXT: lui a1, 307200
974 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
975 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
976 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB8_2
977 ; RV32IZHINXMIN-NEXT: # %bb.1:
978 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
979 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
980 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
981 ; RV32IZHINXMIN-NEXT: .LBB8_2:
982 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
983 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
984 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
985 ; RV32IZHINXMIN-NEXT: ret
986 ;
987 ; RV64IZHINXMIN-LABEL: test_ceil_si8:
988 ; RV64IZHINXMIN: # %bb.0:
989 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
990 ; RV64IZHINXMIN-NEXT: lui a1, 307200
991 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
992 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
993 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB8_2
994 ; RV64IZHINXMIN-NEXT: # %bb.1:
995 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
996 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
997 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
998 ; RV64IZHINXMIN-NEXT: .LBB8_2:
999 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1000 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1001 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1002 ; RV64IZHINXMIN-NEXT: ret
1003 %a = call half @llvm.ceil.f16(half %x)
1004 %b = fptosi half %a to i8
1005 ret i8 %b
1006 }
1008 define signext i16 @test_ceil_si16(half %x) {
1009 ; RV32IZFH-LABEL: test_ceil_si16:
1010 ; RV32IZFH: # %bb.0:
1011 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
1012 ; RV32IZFH-NEXT: ret
1013 ;
1014 ; RV64IZFH-LABEL: test_ceil_si16:
1015 ; RV64IZFH: # %bb.0:
1016 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
1017 ; RV64IZFH-NEXT: ret
1018 ;
1019 ; RV32IZHINX-LABEL: test_ceil_si16:
1020 ; RV32IZHINX: # %bb.0:
1021 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
1022 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
1023 ; RV32IZHINX-NEXT: fabs.h a2, a0
1024 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1025 ; RV32IZHINX-NEXT: beqz a1, .LBB9_2
1026 ; RV32IZHINX-NEXT: # %bb.1:
1027 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1028 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1029 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1030 ; RV32IZHINX-NEXT: .LBB9_2:
1031 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
1032 ; RV32IZHINX-NEXT: ret
1033 ;
1034 ; RV64IZHINX-LABEL: test_ceil_si16:
1035 ; RV64IZHINX: # %bb.0:
1036 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI9_0)
1037 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI9_0)(a1)
1038 ; RV64IZHINX-NEXT: fabs.h a2, a0
1039 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1040 ; RV64IZHINX-NEXT: beqz a1, .LBB9_2
1041 ; RV64IZHINX-NEXT: # %bb.1:
1042 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1043 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1044 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1045 ; RV64IZHINX-NEXT: .LBB9_2:
1046 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1047 ; RV64IZHINX-NEXT: ret
1048 ;
1049 ; RV32IZFHMIN-LABEL: test_ceil_si16:
1050 ; RV32IZFHMIN: # %bb.0:
1051 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1052 ; RV32IZFHMIN-NEXT: lui a0, 307200
1053 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1054 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1055 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1056 ; RV32IZFHMIN-NEXT: beqz a0, .LBB9_2
1057 ; RV32IZFHMIN-NEXT: # %bb.1:
1058 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1059 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1060 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1061 ; RV32IZFHMIN-NEXT: .LBB9_2:
1062 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1063 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1064 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1065 ; RV32IZFHMIN-NEXT: ret
1066 ;
1067 ; RV64IZFHMIN-LABEL: test_ceil_si16:
1068 ; RV64IZFHMIN: # %bb.0:
1069 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1070 ; RV64IZFHMIN-NEXT: lui a0, 307200
1071 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1072 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1073 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1074 ; RV64IZFHMIN-NEXT: beqz a0, .LBB9_2
1075 ; RV64IZFHMIN-NEXT: # %bb.1:
1076 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1077 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1078 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1079 ; RV64IZFHMIN-NEXT: .LBB9_2:
1080 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1081 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1082 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1083 ; RV64IZFHMIN-NEXT: ret
1084 ;
1085 ; RV32IZHINXMIN-LABEL: test_ceil_si16:
1086 ; RV32IZHINXMIN: # %bb.0:
1087 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1088 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1089 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1090 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1091 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB9_2
1092 ; RV32IZHINXMIN-NEXT: # %bb.1:
1093 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1094 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1095 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1096 ; RV32IZHINXMIN-NEXT: .LBB9_2:
1097 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1098 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1099 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1100 ; RV32IZHINXMIN-NEXT: ret
1101 ;
1102 ; RV64IZHINXMIN-LABEL: test_ceil_si16:
1103 ; RV64IZHINXMIN: # %bb.0:
1104 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1105 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1106 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1107 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1108 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB9_2
1109 ; RV64IZHINXMIN-NEXT: # %bb.1:
1110 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1111 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1112 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1113 ; RV64IZHINXMIN-NEXT: .LBB9_2:
1114 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1115 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1116 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1117 ; RV64IZHINXMIN-NEXT: ret
1118 %a = call half @llvm.ceil.f16(half %x)
1119 %b = fptosi half %a to i16
1120 ret i16 %b
1121 }
1123 define signext i32 @test_ceil_si32(half %x) {
1124 ; CHECKIZFH-LABEL: test_ceil_si32:
1125 ; CHECKIZFH: # %bb.0:
1126 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
1127 ; CHECKIZFH-NEXT: ret
1128 ;
1129 ; CHECKIZHINX-LABEL: test_ceil_si32:
1130 ; CHECKIZHINX: # %bb.0:
1131 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI10_0)
1132 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI10_0)(a1)
1133 ; CHECKIZHINX-NEXT: fabs.h a2, a0
1134 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
1135 ; CHECKIZHINX-NEXT: beqz a1, .LBB10_2
1136 ; CHECKIZHINX-NEXT: # %bb.1:
1137 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
1138 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
1139 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
1140 ; CHECKIZHINX-NEXT: .LBB10_2:
1141 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
1142 ; CHECKIZHINX-NEXT: ret
1143 ;
1144 ; CHECKIZFHMIN-LABEL: test_ceil_si32:
1145 ; CHECKIZFHMIN: # %bb.0:
1146 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
1147 ; CHECKIZFHMIN-NEXT: lui a0, 307200
1148 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
1149 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
1150 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
1151 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB10_2
1152 ; CHECKIZFHMIN-NEXT: # %bb.1:
1153 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1154 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1155 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1156 ; CHECKIZFHMIN-NEXT: .LBB10_2:
1157 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
1158 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
1159 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1160 ; CHECKIZFHMIN-NEXT: ret
1161 ;
1162 ; CHECKIZHINXMIN-LABEL: test_ceil_si32:
1163 ; CHECKIZHINXMIN: # %bb.0:
1164 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1165 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
1166 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
1167 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
1168 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB10_2
1169 ; CHECKIZHINXMIN-NEXT: # %bb.1:
1170 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1171 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1172 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1173 ; CHECKIZHINXMIN-NEXT: .LBB10_2:
1174 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1175 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1176 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1177 ; CHECKIZHINXMIN-NEXT: ret
1178 %a = call half @llvm.ceil.f16(half %x)
1179 %b = fptosi half %a to i32
1180 ret i32 %b
1181 }
1183 define i64 @test_ceil_si64(half %x) {
1184 ; RV32IZFH-LABEL: test_ceil_si64:
1185 ; RV32IZFH: # %bb.0:
1186 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI11_0)
1187 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI11_0)(a0)
1188 ; RV32IZFH-NEXT: fabs.h fa4, fa0
1189 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
1190 ; RV32IZFH-NEXT: beqz a0, .LBB11_2
1191 ; RV32IZFH-NEXT: # %bb.1:
1192 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
1193 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
1194 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
1195 ; RV32IZFH-NEXT: .LBB11_2:
1196 ; RV32IZFH-NEXT: addi sp, sp, -16
1197 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
1198 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1199 ; RV32IZFH-NEXT: .cfi_offset ra, -4
1200 ; RV32IZFH-NEXT: call __fixhfdi
1201 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1202 ; RV32IZFH-NEXT: addi sp, sp, 16
1203 ; RV32IZFH-NEXT: ret
1204 ;
1205 ; RV64IZFH-LABEL: test_ceil_si64:
1206 ; RV64IZFH: # %bb.0:
1207 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
1208 ; RV64IZFH-NEXT: ret
1209 ;
1210 ; RV32IZHINX-LABEL: test_ceil_si64:
1211 ; RV32IZHINX: # %bb.0:
1212 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
1213 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
1214 ; RV32IZHINX-NEXT: fabs.h a2, a0
1215 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1216 ; RV32IZHINX-NEXT: beqz a1, .LBB11_2
1217 ; RV32IZHINX-NEXT: # %bb.1:
1218 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1219 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1220 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1221 ; RV32IZHINX-NEXT: .LBB11_2:
1222 ; RV32IZHINX-NEXT: addi sp, sp, -16
1223 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
1224 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1225 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
1226 ; RV32IZHINX-NEXT: call __fixhfdi
1227 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1228 ; RV32IZHINX-NEXT: addi sp, sp, 16
1229 ; RV32IZHINX-NEXT: ret
1230 ;
1231 ; RV64IZHINX-LABEL: test_ceil_si64:
1232 ; RV64IZHINX: # %bb.0:
1233 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI11_0)
1234 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI11_0)(a1)
1235 ; RV64IZHINX-NEXT: fabs.h a2, a0
1236 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1237 ; RV64IZHINX-NEXT: beqz a1, .LBB11_2
1238 ; RV64IZHINX-NEXT: # %bb.1:
1239 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1240 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1241 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1242 ; RV64IZHINX-NEXT: .LBB11_2:
1243 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1244 ; RV64IZHINX-NEXT: ret
1245 ;
1246 ; RV32IZFHMIN-LABEL: test_ceil_si64:
1247 ; RV32IZFHMIN: # %bb.0:
1248 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1249 ; RV32IZFHMIN-NEXT: lui a0, 307200
1250 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1251 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1252 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1253 ; RV32IZFHMIN-NEXT: beqz a0, .LBB11_2
1254 ; RV32IZFHMIN-NEXT: # %bb.1:
1255 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1256 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1257 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1258 ; RV32IZFHMIN-NEXT: .LBB11_2:
1259 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1260 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
1261 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1262 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
1263 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1264 ; RV32IZFHMIN-NEXT: call __fixhfdi
1265 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1266 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1267 ; RV32IZFHMIN-NEXT: ret
1268 ;
1269 ; RV64IZFHMIN-LABEL: test_ceil_si64:
1270 ; RV64IZFHMIN: # %bb.0:
1271 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1272 ; RV64IZFHMIN-NEXT: lui a0, 307200
1273 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1274 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1275 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1276 ; RV64IZFHMIN-NEXT: beqz a0, .LBB11_2
1277 ; RV64IZFHMIN-NEXT: # %bb.1:
1278 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1279 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1280 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1281 ; RV64IZFHMIN-NEXT: .LBB11_2:
1282 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1283 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1284 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1285 ; RV64IZFHMIN-NEXT: ret
1286 ;
1287 ; RV32IZHINXMIN-LABEL: test_ceil_si64:
1288 ; RV32IZHINXMIN: # %bb.0:
1289 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1290 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1291 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1292 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1293 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB11_2
1294 ; RV32IZHINXMIN-NEXT: # %bb.1:
1295 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1296 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1297 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1298 ; RV32IZHINXMIN-NEXT: .LBB11_2:
1299 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1300 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
1301 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1302 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
1303 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1304 ; RV32IZHINXMIN-NEXT: call __fixhfdi
1305 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1306 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1307 ; RV32IZHINXMIN-NEXT: ret
1308 ;
1309 ; RV64IZHINXMIN-LABEL: test_ceil_si64:
1310 ; RV64IZHINXMIN: # %bb.0:
1311 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1312 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1313 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1314 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1315 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB11_2
1316 ; RV64IZHINXMIN-NEXT: # %bb.1:
1317 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1318 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1319 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1320 ; RV64IZHINXMIN-NEXT: .LBB11_2:
1321 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1322 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1323 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1324 ; RV64IZHINXMIN-NEXT: ret
1325 %a = call half @llvm.ceil.f16(half %x)
1326 %b = fptosi half %a to i64
1327 ret i64 %b
1328 }
1330 define zeroext i8 @test_ceil_ui8(half %x) {
1331 ; RV32IZFH-LABEL: test_ceil_ui8:
1332 ; RV32IZFH: # %bb.0:
1333 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
1334 ; RV32IZFH-NEXT: ret
1335 ;
1336 ; RV64IZFH-LABEL: test_ceil_ui8:
1337 ; RV64IZFH: # %bb.0:
1338 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
1339 ; RV64IZFH-NEXT: ret
1340 ;
1341 ; RV32IZHINX-LABEL: test_ceil_ui8:
1342 ; RV32IZHINX: # %bb.0:
1343 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI12_0)
1344 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI12_0)(a1)
1345 ; RV32IZHINX-NEXT: fabs.h a2, a0
1346 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1347 ; RV32IZHINX-NEXT: beqz a1, .LBB12_2
1348 ; RV32IZHINX-NEXT: # %bb.1:
1349 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1350 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1351 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1352 ; RV32IZHINX-NEXT: .LBB12_2:
1353 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
1354 ; RV32IZHINX-NEXT: ret
1355 ;
1356 ; RV64IZHINX-LABEL: test_ceil_ui8:
1357 ; RV64IZHINX: # %bb.0:
1358 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI12_0)
1359 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI12_0)(a1)
1360 ; RV64IZHINX-NEXT: fabs.h a2, a0
1361 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1362 ; RV64IZHINX-NEXT: beqz a1, .LBB12_2
1363 ; RV64IZHINX-NEXT: # %bb.1:
1364 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1365 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1366 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1367 ; RV64IZHINX-NEXT: .LBB12_2:
1368 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
1369 ; RV64IZHINX-NEXT: ret
1370 ;
1371 ; RV32IZFHMIN-LABEL: test_ceil_ui8:
1372 ; RV32IZFHMIN: # %bb.0:
1373 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1374 ; RV32IZFHMIN-NEXT: lui a0, 307200
1375 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1376 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1377 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1378 ; RV32IZFHMIN-NEXT: beqz a0, .LBB12_2
1379 ; RV32IZFHMIN-NEXT: # %bb.1:
1380 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1381 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1382 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1383 ; RV32IZFHMIN-NEXT: .LBB12_2:
1384 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1385 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1386 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1387 ; RV32IZFHMIN-NEXT: ret
1388 ;
1389 ; RV64IZFHMIN-LABEL: test_ceil_ui8:
1390 ; RV64IZFHMIN: # %bb.0:
1391 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1392 ; RV64IZFHMIN-NEXT: lui a0, 307200
1393 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1394 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1395 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1396 ; RV64IZFHMIN-NEXT: beqz a0, .LBB12_2
1397 ; RV64IZFHMIN-NEXT: # %bb.1:
1398 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1399 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1400 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1401 ; RV64IZFHMIN-NEXT: .LBB12_2:
1402 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1403 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1404 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1405 ; RV64IZFHMIN-NEXT: ret
1406 ;
1407 ; RV32IZHINXMIN-LABEL: test_ceil_ui8:
1408 ; RV32IZHINXMIN: # %bb.0:
1409 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1410 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1411 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1412 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1413 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB12_2
1414 ; RV32IZHINXMIN-NEXT: # %bb.1:
1415 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1416 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1417 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1418 ; RV32IZHINXMIN-NEXT: .LBB12_2:
1419 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1420 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1421 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
1422 ; RV32IZHINXMIN-NEXT: ret
1423 ;
1424 ; RV64IZHINXMIN-LABEL: test_ceil_ui8:
1425 ; RV64IZHINXMIN: # %bb.0:
1426 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1427 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1428 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1429 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1430 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB12_2
1431 ; RV64IZHINXMIN-NEXT: # %bb.1:
1432 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1433 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1434 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1435 ; RV64IZHINXMIN-NEXT: .LBB12_2:
1436 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1437 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1438 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
1439 ; RV64IZHINXMIN-NEXT: ret
1440 %a = call half @llvm.ceil.f16(half %x)
1441 %b = fptoui half %a to i8
1442 ret i8 %b
1443 }
1445 define zeroext i16 @test_ceil_ui16(half %x) {
1446 ; RV32IZFH-LABEL: test_ceil_ui16:
1447 ; RV32IZFH: # %bb.0:
1448 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
1449 ; RV32IZFH-NEXT: ret
1450 ;
1451 ; RV64IZFH-LABEL: test_ceil_ui16:
1452 ; RV64IZFH: # %bb.0:
1453 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
1454 ; RV64IZFH-NEXT: ret
1455 ;
1456 ; RV32IZHINX-LABEL: test_ceil_ui16:
1457 ; RV32IZHINX: # %bb.0:
1458 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
1459 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
1460 ; RV32IZHINX-NEXT: fabs.h a2, a0
1461 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1462 ; RV32IZHINX-NEXT: beqz a1, .LBB13_2
1463 ; RV32IZHINX-NEXT: # %bb.1:
1464 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1465 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1466 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1467 ; RV32IZHINX-NEXT: .LBB13_2:
1468 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
1469 ; RV32IZHINX-NEXT: ret
1470 ;
1471 ; RV64IZHINX-LABEL: test_ceil_ui16:
1472 ; RV64IZHINX: # %bb.0:
1473 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI13_0)
1474 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI13_0)(a1)
1475 ; RV64IZHINX-NEXT: fabs.h a2, a0
1476 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1477 ; RV64IZHINX-NEXT: beqz a1, .LBB13_2
1478 ; RV64IZHINX-NEXT: # %bb.1:
1479 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1480 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1481 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1482 ; RV64IZHINX-NEXT: .LBB13_2:
1483 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
1484 ; RV64IZHINX-NEXT: ret
1485 ;
1486 ; RV32IZFHMIN-LABEL: test_ceil_ui16:
1487 ; RV32IZFHMIN: # %bb.0:
1488 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1489 ; RV32IZFHMIN-NEXT: lui a0, 307200
1490 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1491 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1492 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1493 ; RV32IZFHMIN-NEXT: beqz a0, .LBB13_2
1494 ; RV32IZFHMIN-NEXT: # %bb.1:
1495 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1496 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1497 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1498 ; RV32IZFHMIN-NEXT: .LBB13_2:
1499 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1500 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1501 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1502 ; RV32IZFHMIN-NEXT: ret
1503 ;
1504 ; RV64IZFHMIN-LABEL: test_ceil_ui16:
1505 ; RV64IZFHMIN: # %bb.0:
1506 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1507 ; RV64IZFHMIN-NEXT: lui a0, 307200
1508 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1509 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1510 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1511 ; RV64IZFHMIN-NEXT: beqz a0, .LBB13_2
1512 ; RV64IZFHMIN-NEXT: # %bb.1:
1513 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1514 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1515 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1516 ; RV64IZFHMIN-NEXT: .LBB13_2:
1517 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1518 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1519 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1520 ; RV64IZFHMIN-NEXT: ret
1521 ;
1522 ; RV32IZHINXMIN-LABEL: test_ceil_ui16:
1523 ; RV32IZHINXMIN: # %bb.0:
1524 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1525 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1526 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1527 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1528 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB13_2
1529 ; RV32IZHINXMIN-NEXT: # %bb.1:
1530 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1531 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1532 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1533 ; RV32IZHINXMIN-NEXT: .LBB13_2:
1534 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1535 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1536 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
1537 ; RV32IZHINXMIN-NEXT: ret
1538 ;
1539 ; RV64IZHINXMIN-LABEL: test_ceil_ui16:
1540 ; RV64IZHINXMIN: # %bb.0:
1541 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1542 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1543 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1544 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1545 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB13_2
1546 ; RV64IZHINXMIN-NEXT: # %bb.1:
1547 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1548 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1549 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1550 ; RV64IZHINXMIN-NEXT: .LBB13_2:
1551 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1552 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1553 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
1554 ; RV64IZHINXMIN-NEXT: ret
1555 %a = call half @llvm.ceil.f16(half %x)
1556 %b = fptoui half %a to i16
1557 ret i16 %b
1558 }
1560 define signext i32 @test_ceil_ui32(half %x) {
1561 ; CHECKIZFH-LABEL: test_ceil_ui32:
1562 ; CHECKIZFH: # %bb.0:
1563 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rup
1564 ; CHECKIZFH-NEXT: ret
1565 ;
1566 ; CHECKIZHINX-LABEL: test_ceil_ui32:
1567 ; CHECKIZHINX: # %bb.0:
1568 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI14_0)
1569 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI14_0)(a1)
1570 ; CHECKIZHINX-NEXT: fabs.h a2, a0
1571 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
1572 ; CHECKIZHINX-NEXT: beqz a1, .LBB14_2
1573 ; CHECKIZHINX-NEXT: # %bb.1:
1574 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
1575 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
1576 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
1577 ; CHECKIZHINX-NEXT: .LBB14_2:
1578 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
1579 ; CHECKIZHINX-NEXT: ret
1580 ;
1581 ; CHECKIZFHMIN-LABEL: test_ceil_ui32:
1582 ; CHECKIZFHMIN: # %bb.0:
1583 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
1584 ; CHECKIZFHMIN-NEXT: lui a0, 307200
1585 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
1586 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
1587 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
1588 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB14_2
1589 ; CHECKIZFHMIN-NEXT: # %bb.1:
1590 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1591 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1592 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1593 ; CHECKIZFHMIN-NEXT: .LBB14_2:
1594 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
1595 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
1596 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1597 ; CHECKIZFHMIN-NEXT: ret
1598 ;
1599 ; CHECKIZHINXMIN-LABEL: test_ceil_ui32:
1600 ; CHECKIZHINXMIN: # %bb.0:
1601 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1602 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
1603 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
1604 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
1605 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB14_2
1606 ; CHECKIZHINXMIN-NEXT: # %bb.1:
1607 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1608 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1609 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1610 ; CHECKIZHINXMIN-NEXT: .LBB14_2:
1611 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
1612 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
1613 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
1614 ; CHECKIZHINXMIN-NEXT: ret
1615 %a = call half @llvm.ceil.f16(half %x)
1616 %b = fptoui half %a to i32
1617 ret i32 %b
1618 }
1620 define i64 @test_ceil_ui64(half %x) {
1621 ; RV32IZFH-LABEL: test_ceil_ui64:
1622 ; RV32IZFH: # %bb.0:
1623 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI15_0)
1624 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI15_0)(a0)
1625 ; RV32IZFH-NEXT: fabs.h fa4, fa0
1626 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
1627 ; RV32IZFH-NEXT: beqz a0, .LBB15_2
1628 ; RV32IZFH-NEXT: # %bb.1:
1629 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
1630 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rup
1631 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
1632 ; RV32IZFH-NEXT: .LBB15_2:
1633 ; RV32IZFH-NEXT: addi sp, sp, -16
1634 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
1635 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1636 ; RV32IZFH-NEXT: .cfi_offset ra, -4
1637 ; RV32IZFH-NEXT: call __fixunshfdi
1638 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1639 ; RV32IZFH-NEXT: addi sp, sp, 16
1640 ; RV32IZFH-NEXT: ret
1641 ;
1642 ; RV64IZFH-LABEL: test_ceil_ui64:
1643 ; RV64IZFH: # %bb.0:
1644 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
1645 ; RV64IZFH-NEXT: ret
1646 ;
1647 ; RV32IZHINX-LABEL: test_ceil_ui64:
1648 ; RV32IZHINX: # %bb.0:
1649 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
1650 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
1651 ; RV32IZHINX-NEXT: fabs.h a2, a0
1652 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1653 ; RV32IZHINX-NEXT: beqz a1, .LBB15_2
1654 ; RV32IZHINX-NEXT: # %bb.1:
1655 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rup
1656 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rup
1657 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1658 ; RV32IZHINX-NEXT: .LBB15_2:
1659 ; RV32IZHINX-NEXT: addi sp, sp, -16
1660 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
1661 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1662 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
1663 ; RV32IZHINX-NEXT: call __fixunshfdi
1664 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1665 ; RV32IZHINX-NEXT: addi sp, sp, 16
1666 ; RV32IZHINX-NEXT: ret
1667 ;
1668 ; RV64IZHINX-LABEL: test_ceil_ui64:
1669 ; RV64IZHINX: # %bb.0:
1670 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI15_0)
1671 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI15_0)(a1)
1672 ; RV64IZHINX-NEXT: fabs.h a2, a0
1673 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1674 ; RV64IZHINX-NEXT: beqz a1, .LBB15_2
1675 ; RV64IZHINX-NEXT: # %bb.1:
1676 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rup
1677 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rup
1678 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1679 ; RV64IZHINX-NEXT: .LBB15_2:
1680 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
1681 ; RV64IZHINX-NEXT: ret
1682 ;
1683 ; RV32IZFHMIN-LABEL: test_ceil_ui64:
1684 ; RV32IZFHMIN: # %bb.0:
1685 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1686 ; RV32IZFHMIN-NEXT: lui a0, 307200
1687 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1688 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1689 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1690 ; RV32IZFHMIN-NEXT: beqz a0, .LBB15_2
1691 ; RV32IZFHMIN-NEXT: # %bb.1:
1692 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1693 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1694 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1695 ; RV32IZFHMIN-NEXT: .LBB15_2:
1696 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
1697 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
1698 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1699 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
1700 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
1701 ; RV32IZFHMIN-NEXT: call __fixunshfdi
1702 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1703 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
1704 ; RV32IZFHMIN-NEXT: ret
1705 ;
1706 ; RV64IZFHMIN-LABEL: test_ceil_ui64:
1707 ; RV64IZFHMIN: # %bb.0:
1708 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1709 ; RV64IZFHMIN-NEXT: lui a0, 307200
1710 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1711 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1712 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1713 ; RV64IZFHMIN-NEXT: beqz a0, .LBB15_2
1714 ; RV64IZFHMIN-NEXT: # %bb.1:
1715 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
1716 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
1717 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1718 ; RV64IZFHMIN-NEXT: .LBB15_2:
1719 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1720 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1721 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1722 ; RV64IZFHMIN-NEXT: ret
1723 ;
1724 ; RV32IZHINXMIN-LABEL: test_ceil_ui64:
1725 ; RV32IZHINXMIN: # %bb.0:
1726 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1727 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1728 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1729 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1730 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB15_2
1731 ; RV32IZHINXMIN-NEXT: # %bb.1:
1732 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1733 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1734 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1735 ; RV32IZHINXMIN-NEXT: .LBB15_2:
1736 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
1737 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
1738 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1739 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
1740 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1741 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
1742 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1743 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
1744 ; RV32IZHINXMIN-NEXT: ret
1745 ;
1746 ; RV64IZHINXMIN-LABEL: test_ceil_ui64:
1747 ; RV64IZHINXMIN: # %bb.0:
1748 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1749 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1750 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1751 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1752 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB15_2
1753 ; RV64IZHINXMIN-NEXT: # %bb.1:
1754 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
1755 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
1756 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1757 ; RV64IZHINXMIN-NEXT: .LBB15_2:
1758 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1759 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1760 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
1761 ; RV64IZHINXMIN-NEXT: ret
1762 %a = call half @llvm.ceil.f16(half %x)
1763 %b = fptoui half %a to i64
1764 ret i64 %b
1765 }
1767 define signext i8 @test_trunc_si8(half %x) {
1768 ; RV32IZFH-LABEL: test_trunc_si8:
1769 ; RV32IZFH: # %bb.0:
1770 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
1771 ; RV32IZFH-NEXT: ret
1772 ;
1773 ; RV64IZFH-LABEL: test_trunc_si8:
1774 ; RV64IZFH: # %bb.0:
1775 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
1776 ; RV64IZFH-NEXT: ret
1777 ;
1778 ; RV32IZHINX-LABEL: test_trunc_si8:
1779 ; RV32IZHINX: # %bb.0:
1780 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI16_0)
1781 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI16_0)(a1)
1782 ; RV32IZHINX-NEXT: fabs.h a2, a0
1783 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1784 ; RV32IZHINX-NEXT: beqz a1, .LBB16_2
1785 ; RV32IZHINX-NEXT: # %bb.1:
1786 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1787 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1788 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1789 ; RV32IZHINX-NEXT: .LBB16_2:
1790 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
1791 ; RV32IZHINX-NEXT: ret
1792 ;
1793 ; RV64IZHINX-LABEL: test_trunc_si8:
1794 ; RV64IZHINX: # %bb.0:
1795 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI16_0)
1796 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI16_0)(a1)
1797 ; RV64IZHINX-NEXT: fabs.h a2, a0
1798 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1799 ; RV64IZHINX-NEXT: beqz a1, .LBB16_2
1800 ; RV64IZHINX-NEXT: # %bb.1:
1801 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1802 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1803 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1804 ; RV64IZHINX-NEXT: .LBB16_2:
1805 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1806 ; RV64IZHINX-NEXT: ret
1807 ;
1808 ; RV32IZFHMIN-LABEL: test_trunc_si8:
1809 ; RV32IZFHMIN: # %bb.0:
1810 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1811 ; RV32IZFHMIN-NEXT: lui a0, 307200
1812 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1813 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1814 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1815 ; RV32IZFHMIN-NEXT: beqz a0, .LBB16_2
1816 ; RV32IZFHMIN-NEXT: # %bb.1:
1817 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1818 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1819 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1820 ; RV32IZFHMIN-NEXT: .LBB16_2:
1821 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1822 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1823 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1824 ; RV32IZFHMIN-NEXT: ret
1825 ;
1826 ; RV64IZFHMIN-LABEL: test_trunc_si8:
1827 ; RV64IZFHMIN: # %bb.0:
1828 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1829 ; RV64IZFHMIN-NEXT: lui a0, 307200
1830 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1831 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1832 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1833 ; RV64IZFHMIN-NEXT: beqz a0, .LBB16_2
1834 ; RV64IZFHMIN-NEXT: # %bb.1:
1835 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1836 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1837 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1838 ; RV64IZFHMIN-NEXT: .LBB16_2:
1839 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1840 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1841 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1842 ; RV64IZFHMIN-NEXT: ret
1843 ;
1844 ; RV32IZHINXMIN-LABEL: test_trunc_si8:
1845 ; RV32IZHINXMIN: # %bb.0:
1846 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1847 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1848 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1849 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1850 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB16_2
1851 ; RV32IZHINXMIN-NEXT: # %bb.1:
1852 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1853 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1854 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1855 ; RV32IZHINXMIN-NEXT: .LBB16_2:
1856 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1857 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1858 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1859 ; RV32IZHINXMIN-NEXT: ret
1860 ;
1861 ; RV64IZHINXMIN-LABEL: test_trunc_si8:
1862 ; RV64IZHINXMIN: # %bb.0:
1863 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1864 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1865 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1866 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1867 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB16_2
1868 ; RV64IZHINXMIN-NEXT: # %bb.1:
1869 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1870 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1871 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1872 ; RV64IZHINXMIN-NEXT: .LBB16_2:
1873 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1874 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1875 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1876 ; RV64IZHINXMIN-NEXT: ret
1877 %a = call half @llvm.trunc.f16(half %x)
1878 %b = fptosi half %a to i8
1879 ret i8 %b
1880 }
1882 define signext i16 @test_trunc_si16(half %x) {
1883 ; RV32IZFH-LABEL: test_trunc_si16:
1884 ; RV32IZFH: # %bb.0:
1885 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
1886 ; RV32IZFH-NEXT: ret
1887 ;
1888 ; RV64IZFH-LABEL: test_trunc_si16:
1889 ; RV64IZFH: # %bb.0:
1890 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
1891 ; RV64IZFH-NEXT: ret
1892 ;
1893 ; RV32IZHINX-LABEL: test_trunc_si16:
1894 ; RV32IZHINX: # %bb.0:
1895 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
1896 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
1897 ; RV32IZHINX-NEXT: fabs.h a2, a0
1898 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
1899 ; RV32IZHINX-NEXT: beqz a1, .LBB17_2
1900 ; RV32IZHINX-NEXT: # %bb.1:
1901 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1902 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1903 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
1904 ; RV32IZHINX-NEXT: .LBB17_2:
1905 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
1906 ; RV32IZHINX-NEXT: ret
1907 ;
1908 ; RV64IZHINX-LABEL: test_trunc_si16:
1909 ; RV64IZHINX: # %bb.0:
1910 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI17_0)
1911 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI17_0)(a1)
1912 ; RV64IZHINX-NEXT: fabs.h a2, a0
1913 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
1914 ; RV64IZHINX-NEXT: beqz a1, .LBB17_2
1915 ; RV64IZHINX-NEXT: # %bb.1:
1916 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
1917 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
1918 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
1919 ; RV64IZHINX-NEXT: .LBB17_2:
1920 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
1921 ; RV64IZHINX-NEXT: ret
1922 ;
1923 ; RV32IZFHMIN-LABEL: test_trunc_si16:
1924 ; RV32IZFHMIN: # %bb.0:
1925 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1926 ; RV32IZFHMIN-NEXT: lui a0, 307200
1927 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
1928 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
1929 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
1930 ; RV32IZFHMIN-NEXT: beqz a0, .LBB17_2
1931 ; RV32IZFHMIN-NEXT: # %bb.1:
1932 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1933 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1934 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1935 ; RV32IZFHMIN-NEXT: .LBB17_2:
1936 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1937 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1938 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1939 ; RV32IZFHMIN-NEXT: ret
1940 ;
1941 ; RV64IZFHMIN-LABEL: test_trunc_si16:
1942 ; RV64IZFHMIN: # %bb.0:
1943 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
1944 ; RV64IZFHMIN-NEXT: lui a0, 307200
1945 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
1946 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
1947 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
1948 ; RV64IZFHMIN-NEXT: beqz a0, .LBB17_2
1949 ; RV64IZFHMIN-NEXT: # %bb.1:
1950 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
1951 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
1952 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
1953 ; RV64IZFHMIN-NEXT: .LBB17_2:
1954 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
1955 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
1956 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
1957 ; RV64IZFHMIN-NEXT: ret
1958 ;
1959 ; RV32IZHINXMIN-LABEL: test_trunc_si16:
1960 ; RV32IZHINXMIN: # %bb.0:
1961 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1962 ; RV32IZHINXMIN-NEXT: lui a1, 307200
1963 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
1964 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
1965 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB17_2
1966 ; RV32IZHINXMIN-NEXT: # %bb.1:
1967 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1968 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1969 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1970 ; RV32IZHINXMIN-NEXT: .LBB17_2:
1971 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
1972 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
1973 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
1974 ; RV32IZHINXMIN-NEXT: ret
1975 ;
1976 ; RV64IZHINXMIN-LABEL: test_trunc_si16:
1977 ; RV64IZHINXMIN: # %bb.0:
1978 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1979 ; RV64IZHINXMIN-NEXT: lui a1, 307200
1980 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
1981 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
1982 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB17_2
1983 ; RV64IZHINXMIN-NEXT: # %bb.1:
1984 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
1985 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
1986 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
1987 ; RV64IZHINXMIN-NEXT: .LBB17_2:
1988 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
1989 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
1990 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
1991 ; RV64IZHINXMIN-NEXT: ret
1992 %a = call half @llvm.trunc.f16(half %x)
1993 %b = fptosi half %a to i16
1994 ret i16 %b
1995 }
1997 define signext i32 @test_trunc_si32(half %x) {
1998 ; CHECKIZFH-LABEL: test_trunc_si32:
1999 ; CHECKIZFH: # %bb.0:
2000 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
2001 ; CHECKIZFH-NEXT: ret
2002 ;
2003 ; CHECKIZHINX-LABEL: test_trunc_si32:
2004 ; CHECKIZHINX: # %bb.0:
2005 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI18_0)
2006 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI18_0)(a1)
2007 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2008 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2009 ; CHECKIZHINX-NEXT: beqz a1, .LBB18_2
2010 ; CHECKIZHINX-NEXT: # %bb.1:
2011 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2012 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
2013 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2014 ; CHECKIZHINX-NEXT: .LBB18_2:
2015 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
2016 ; CHECKIZHINX-NEXT: ret
2017 ;
2018 ; CHECKIZFHMIN-LABEL: test_trunc_si32:
2019 ; CHECKIZFHMIN: # %bb.0:
2020 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2021 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2022 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2023 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2024 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2025 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB18_2
2026 ; CHECKIZFHMIN-NEXT: # %bb.1:
2027 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2028 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2029 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2030 ; CHECKIZFHMIN-NEXT: .LBB18_2:
2031 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2032 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2033 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2034 ; CHECKIZFHMIN-NEXT: ret
2035 ;
2036 ; CHECKIZHINXMIN-LABEL: test_trunc_si32:
2037 ; CHECKIZHINXMIN: # %bb.0:
2038 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2039 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2040 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2041 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2042 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB18_2
2043 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2044 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2045 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2046 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2047 ; CHECKIZHINXMIN-NEXT: .LBB18_2:
2048 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2049 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2050 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2051 ; CHECKIZHINXMIN-NEXT: ret
2052 %a = call half @llvm.trunc.f16(half %x)
2053 %b = fptosi half %a to i32
2054 ret i32 %b
2055 }
2057 define i64 @test_trunc_si64(half %x) {
2058 ; RV32IZFH-LABEL: test_trunc_si64:
2059 ; RV32IZFH: # %bb.0:
2060 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI19_0)
2061 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI19_0)(a0)
2062 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2063 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2064 ; RV32IZFH-NEXT: beqz a0, .LBB19_2
2065 ; RV32IZFH-NEXT: # %bb.1:
2066 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
2067 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
2068 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2069 ; RV32IZFH-NEXT: .LBB19_2:
2070 ; RV32IZFH-NEXT: addi sp, sp, -16
2071 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
2072 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2073 ; RV32IZFH-NEXT: .cfi_offset ra, -4
2074 ; RV32IZFH-NEXT: call __fixhfdi
2075 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2076 ; RV32IZFH-NEXT: addi sp, sp, 16
2077 ; RV32IZFH-NEXT: ret
2078 ;
2079 ; RV64IZFH-LABEL: test_trunc_si64:
2080 ; RV64IZFH: # %bb.0:
2081 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
2082 ; RV64IZFH-NEXT: ret
2083 ;
2084 ; RV32IZHINX-LABEL: test_trunc_si64:
2085 ; RV32IZHINX: # %bb.0:
2086 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
2087 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
2088 ; RV32IZHINX-NEXT: fabs.h a2, a0
2089 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2090 ; RV32IZHINX-NEXT: beqz a1, .LBB19_2
2091 ; RV32IZHINX-NEXT: # %bb.1:
2092 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2093 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2094 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2095 ; RV32IZHINX-NEXT: .LBB19_2:
2096 ; RV32IZHINX-NEXT: addi sp, sp, -16
2097 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
2098 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2099 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
2100 ; RV32IZHINX-NEXT: call __fixhfdi
2101 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2102 ; RV32IZHINX-NEXT: addi sp, sp, 16
2103 ; RV32IZHINX-NEXT: ret
2104 ;
2105 ; RV64IZHINX-LABEL: test_trunc_si64:
2106 ; RV64IZHINX: # %bb.0:
2107 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI19_0)
2108 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI19_0)(a1)
2109 ; RV64IZHINX-NEXT: fabs.h a2, a0
2110 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2111 ; RV64IZHINX-NEXT: beqz a1, .LBB19_2
2112 ; RV64IZHINX-NEXT: # %bb.1:
2113 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2114 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2115 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2116 ; RV64IZHINX-NEXT: .LBB19_2:
2117 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
2118 ; RV64IZHINX-NEXT: ret
2119 ;
2120 ; RV32IZFHMIN-LABEL: test_trunc_si64:
2121 ; RV32IZFHMIN: # %bb.0:
2122 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2123 ; RV32IZFHMIN-NEXT: lui a0, 307200
2124 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2125 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2126 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2127 ; RV32IZFHMIN-NEXT: beqz a0, .LBB19_2
2128 ; RV32IZFHMIN-NEXT: # %bb.1:
2129 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2130 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2131 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2132 ; RV32IZFHMIN-NEXT: .LBB19_2:
2133 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2134 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2135 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2136 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
2137 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
2138 ; RV32IZFHMIN-NEXT: call __fixhfdi
2139 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2140 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2141 ; RV32IZFHMIN-NEXT: ret
2142 ;
2143 ; RV64IZFHMIN-LABEL: test_trunc_si64:
2144 ; RV64IZFHMIN: # %bb.0:
2145 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2146 ; RV64IZFHMIN-NEXT: lui a0, 307200
2147 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2148 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2149 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2150 ; RV64IZFHMIN-NEXT: beqz a0, .LBB19_2
2151 ; RV64IZFHMIN-NEXT: # %bb.1:
2152 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2153 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2154 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2155 ; RV64IZFHMIN-NEXT: .LBB19_2:
2156 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2157 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2158 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
2159 ; RV64IZFHMIN-NEXT: ret
2160 ;
2161 ; RV32IZHINXMIN-LABEL: test_trunc_si64:
2162 ; RV32IZHINXMIN: # %bb.0:
2163 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2164 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2165 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2166 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2167 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB19_2
2168 ; RV32IZHINXMIN-NEXT: # %bb.1:
2169 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2170 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2171 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2172 ; RV32IZHINXMIN-NEXT: .LBB19_2:
2173 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2174 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2175 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2176 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
2177 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2178 ; RV32IZHINXMIN-NEXT: call __fixhfdi
2179 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2180 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2181 ; RV32IZHINXMIN-NEXT: ret
2182 ;
2183 ; RV64IZHINXMIN-LABEL: test_trunc_si64:
2184 ; RV64IZHINXMIN: # %bb.0:
2185 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2186 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2187 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2188 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2189 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB19_2
2190 ; RV64IZHINXMIN-NEXT: # %bb.1:
2191 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2192 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2193 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2194 ; RV64IZHINXMIN-NEXT: .LBB19_2:
2195 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2196 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2197 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
2198 ; RV64IZHINXMIN-NEXT: ret
2199 %a = call half @llvm.trunc.f16(half %x)
2200 %b = fptosi half %a to i64
2201 ret i64 %b
2202 }
2204 define zeroext i8 @test_trunc_ui8(half %x) {
2205 ; RV32IZFH-LABEL: test_trunc_ui8:
2206 ; RV32IZFH: # %bb.0:
2207 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2208 ; RV32IZFH-NEXT: ret
2209 ;
2210 ; RV64IZFH-LABEL: test_trunc_ui8:
2211 ; RV64IZFH: # %bb.0:
2212 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
2213 ; RV64IZFH-NEXT: ret
2214 ;
2215 ; RV32IZHINX-LABEL: test_trunc_ui8:
2216 ; RV32IZHINX: # %bb.0:
2217 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI20_0)
2218 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
2219 ; RV32IZHINX-NEXT: fabs.h a2, a0
2220 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2221 ; RV32IZHINX-NEXT: beqz a1, .LBB20_2
2222 ; RV32IZHINX-NEXT: # %bb.1:
2223 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2224 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2225 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2226 ; RV32IZHINX-NEXT: .LBB20_2:
2227 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2228 ; RV32IZHINX-NEXT: ret
2229 ;
2230 ; RV64IZHINX-LABEL: test_trunc_ui8:
2231 ; RV64IZHINX: # %bb.0:
2232 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI20_0)
2233 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI20_0)(a1)
2234 ; RV64IZHINX-NEXT: fabs.h a2, a0
2235 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2236 ; RV64IZHINX-NEXT: beqz a1, .LBB20_2
2237 ; RV64IZHINX-NEXT: # %bb.1:
2238 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2239 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2240 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2241 ; RV64IZHINX-NEXT: .LBB20_2:
2242 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
2243 ; RV64IZHINX-NEXT: ret
2244 ;
2245 ; RV32IZFHMIN-LABEL: test_trunc_ui8:
2246 ; RV32IZFHMIN: # %bb.0:
2247 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2248 ; RV32IZFHMIN-NEXT: lui a0, 307200
2249 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2250 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2251 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2252 ; RV32IZFHMIN-NEXT: beqz a0, .LBB20_2
2253 ; RV32IZFHMIN-NEXT: # %bb.1:
2254 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2255 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2256 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2257 ; RV32IZFHMIN-NEXT: .LBB20_2:
2258 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2259 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2260 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2261 ; RV32IZFHMIN-NEXT: ret
2262 ;
2263 ; RV64IZFHMIN-LABEL: test_trunc_ui8:
2264 ; RV64IZFHMIN: # %bb.0:
2265 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2266 ; RV64IZFHMIN-NEXT: lui a0, 307200
2267 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2268 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2269 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2270 ; RV64IZFHMIN-NEXT: beqz a0, .LBB20_2
2271 ; RV64IZFHMIN-NEXT: # %bb.1:
2272 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2273 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2274 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2275 ; RV64IZFHMIN-NEXT: .LBB20_2:
2276 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2277 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2278 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2279 ; RV64IZFHMIN-NEXT: ret
2280 ;
2281 ; RV32IZHINXMIN-LABEL: test_trunc_ui8:
2282 ; RV32IZHINXMIN: # %bb.0:
2283 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2284 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2285 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2286 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2287 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB20_2
2288 ; RV32IZHINXMIN-NEXT: # %bb.1:
2289 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2290 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2291 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2292 ; RV32IZHINXMIN-NEXT: .LBB20_2:
2293 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2294 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2295 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2296 ; RV32IZHINXMIN-NEXT: ret
2297 ;
2298 ; RV64IZHINXMIN-LABEL: test_trunc_ui8:
2299 ; RV64IZHINXMIN: # %bb.0:
2300 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2301 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2302 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2303 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2304 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB20_2
2305 ; RV64IZHINXMIN-NEXT: # %bb.1:
2306 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2307 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2308 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2309 ; RV64IZHINXMIN-NEXT: .LBB20_2:
2310 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2311 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2312 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
2313 ; RV64IZHINXMIN-NEXT: ret
2314 %a = call half @llvm.trunc.f16(half %x)
2315 %b = fptoui half %a to i8
2316 ret i8 %b
2317 }
2319 define zeroext i16 @test_trunc_ui16(half %x) {
2320 ; RV32IZFH-LABEL: test_trunc_ui16:
2321 ; RV32IZFH: # %bb.0:
2322 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2323 ; RV32IZFH-NEXT: ret
2324 ;
2325 ; RV64IZFH-LABEL: test_trunc_ui16:
2326 ; RV64IZFH: # %bb.0:
2327 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
2328 ; RV64IZFH-NEXT: ret
2329 ;
2330 ; RV32IZHINX-LABEL: test_trunc_ui16:
2331 ; RV32IZHINX: # %bb.0:
2332 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
2333 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
2334 ; RV32IZHINX-NEXT: fabs.h a2, a0
2335 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2336 ; RV32IZHINX-NEXT: beqz a1, .LBB21_2
2337 ; RV32IZHINX-NEXT: # %bb.1:
2338 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2339 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2340 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2341 ; RV32IZHINX-NEXT: .LBB21_2:
2342 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2343 ; RV32IZHINX-NEXT: ret
2344 ;
2345 ; RV64IZHINX-LABEL: test_trunc_ui16:
2346 ; RV64IZHINX: # %bb.0:
2347 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI21_0)
2348 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI21_0)(a1)
2349 ; RV64IZHINX-NEXT: fabs.h a2, a0
2350 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2351 ; RV64IZHINX-NEXT: beqz a1, .LBB21_2
2352 ; RV64IZHINX-NEXT: # %bb.1:
2353 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2354 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2355 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2356 ; RV64IZHINX-NEXT: .LBB21_2:
2357 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
2358 ; RV64IZHINX-NEXT: ret
2359 ;
2360 ; RV32IZFHMIN-LABEL: test_trunc_ui16:
2361 ; RV32IZFHMIN: # %bb.0:
2362 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2363 ; RV32IZFHMIN-NEXT: lui a0, 307200
2364 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2365 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2366 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2367 ; RV32IZFHMIN-NEXT: beqz a0, .LBB21_2
2368 ; RV32IZFHMIN-NEXT: # %bb.1:
2369 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2370 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2371 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2372 ; RV32IZFHMIN-NEXT: .LBB21_2:
2373 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2374 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2375 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2376 ; RV32IZFHMIN-NEXT: ret
2377 ;
2378 ; RV64IZFHMIN-LABEL: test_trunc_ui16:
2379 ; RV64IZFHMIN: # %bb.0:
2380 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2381 ; RV64IZFHMIN-NEXT: lui a0, 307200
2382 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2383 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2384 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2385 ; RV64IZFHMIN-NEXT: beqz a0, .LBB21_2
2386 ; RV64IZFHMIN-NEXT: # %bb.1:
2387 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2388 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2389 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2390 ; RV64IZFHMIN-NEXT: .LBB21_2:
2391 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2392 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2393 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2394 ; RV64IZFHMIN-NEXT: ret
2395 ;
2396 ; RV32IZHINXMIN-LABEL: test_trunc_ui16:
2397 ; RV32IZHINXMIN: # %bb.0:
2398 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2399 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2400 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2401 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2402 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB21_2
2403 ; RV32IZHINXMIN-NEXT: # %bb.1:
2404 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2405 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2406 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2407 ; RV32IZHINXMIN-NEXT: .LBB21_2:
2408 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2409 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2410 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2411 ; RV32IZHINXMIN-NEXT: ret
2412 ;
2413 ; RV64IZHINXMIN-LABEL: test_trunc_ui16:
2414 ; RV64IZHINXMIN: # %bb.0:
2415 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2416 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2417 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2418 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2419 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB21_2
2420 ; RV64IZHINXMIN-NEXT: # %bb.1:
2421 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2422 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2423 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2424 ; RV64IZHINXMIN-NEXT: .LBB21_2:
2425 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2426 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2427 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
2428 ; RV64IZHINXMIN-NEXT: ret
2429 %a = call half @llvm.trunc.f16(half %x)
2430 %b = fptoui half %a to i16
2431 ret i16 %b
2432 }
2434 define signext i32 @test_trunc_ui32(half %x) {
2435 ; CHECKIZFH-LABEL: test_trunc_ui32:
2436 ; CHECKIZFH: # %bb.0:
2437 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2438 ; CHECKIZFH-NEXT: ret
2439 ;
2440 ; CHECKIZHINX-LABEL: test_trunc_ui32:
2441 ; CHECKIZHINX: # %bb.0:
2442 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI22_0)
2443 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI22_0)(a1)
2444 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2445 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2446 ; CHECKIZHINX-NEXT: beqz a1, .LBB22_2
2447 ; CHECKIZHINX-NEXT: # %bb.1:
2448 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2449 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
2450 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2451 ; CHECKIZHINX-NEXT: .LBB22_2:
2452 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2453 ; CHECKIZHINX-NEXT: ret
2454 ;
2455 ; CHECKIZFHMIN-LABEL: test_trunc_ui32:
2456 ; CHECKIZFHMIN: # %bb.0:
2457 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2458 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2459 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2460 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2461 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2462 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB22_2
2463 ; CHECKIZFHMIN-NEXT: # %bb.1:
2464 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2465 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2466 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2467 ; CHECKIZFHMIN-NEXT: .LBB22_2:
2468 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2469 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2470 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2471 ; CHECKIZFHMIN-NEXT: ret
2472 ;
2473 ; CHECKIZHINXMIN-LABEL: test_trunc_ui32:
2474 ; CHECKIZHINXMIN: # %bb.0:
2475 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2476 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2477 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2478 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2479 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB22_2
2480 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2481 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2482 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2483 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2484 ; CHECKIZHINXMIN-NEXT: .LBB22_2:
2485 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2486 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2487 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2488 ; CHECKIZHINXMIN-NEXT: ret
2489 %a = call half @llvm.trunc.f16(half %x)
2490 %b = fptoui half %a to i32
2491 ret i32 %b
2492 }
2494 define i64 @test_trunc_ui64(half %x) {
2495 ; RV32IZFH-LABEL: test_trunc_ui64:
2496 ; RV32IZFH: # %bb.0:
2497 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI23_0)
2498 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
2499 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2500 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2501 ; RV32IZFH-NEXT: beqz a0, .LBB23_2
2502 ; RV32IZFH-NEXT: # %bb.1:
2503 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
2504 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rtz
2505 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2506 ; RV32IZFH-NEXT: .LBB23_2:
2507 ; RV32IZFH-NEXT: addi sp, sp, -16
2508 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
2509 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2510 ; RV32IZFH-NEXT: .cfi_offset ra, -4
2511 ; RV32IZFH-NEXT: call __fixunshfdi
2512 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2513 ; RV32IZFH-NEXT: addi sp, sp, 16
2514 ; RV32IZFH-NEXT: ret
2515 ;
2516 ; RV64IZFH-LABEL: test_trunc_ui64:
2517 ; RV64IZFH: # %bb.0:
2518 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
2519 ; RV64IZFH-NEXT: ret
2520 ;
2521 ; RV32IZHINX-LABEL: test_trunc_ui64:
2522 ; RV32IZHINX: # %bb.0:
2523 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
2524 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
2525 ; RV32IZHINX-NEXT: fabs.h a2, a0
2526 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2527 ; RV32IZHINX-NEXT: beqz a1, .LBB23_2
2528 ; RV32IZHINX-NEXT: # %bb.1:
2529 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2530 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2531 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2532 ; RV32IZHINX-NEXT: .LBB23_2:
2533 ; RV32IZHINX-NEXT: addi sp, sp, -16
2534 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
2535 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2536 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
2537 ; RV32IZHINX-NEXT: call __fixunshfdi
2538 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2539 ; RV32IZHINX-NEXT: addi sp, sp, 16
2540 ; RV32IZHINX-NEXT: ret
2541 ;
2542 ; RV64IZHINX-LABEL: test_trunc_ui64:
2543 ; RV64IZHINX: # %bb.0:
2544 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI23_0)
2545 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI23_0)(a1)
2546 ; RV64IZHINX-NEXT: fabs.h a2, a0
2547 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2548 ; RV64IZHINX-NEXT: beqz a1, .LBB23_2
2549 ; RV64IZHINX-NEXT: # %bb.1:
2550 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rtz
2551 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rtz
2552 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2553 ; RV64IZHINX-NEXT: .LBB23_2:
2554 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
2555 ; RV64IZHINX-NEXT: ret
2556 ;
2557 ; RV32IZFHMIN-LABEL: test_trunc_ui64:
2558 ; RV32IZFHMIN: # %bb.0:
2559 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2560 ; RV32IZFHMIN-NEXT: lui a0, 307200
2561 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2562 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2563 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2564 ; RV32IZFHMIN-NEXT: beqz a0, .LBB23_2
2565 ; RV32IZFHMIN-NEXT: # %bb.1:
2566 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2567 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2568 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2569 ; RV32IZFHMIN-NEXT: .LBB23_2:
2570 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
2571 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2572 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2573 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
2574 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
2575 ; RV32IZFHMIN-NEXT: call __fixunshfdi
2576 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2577 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
2578 ; RV32IZFHMIN-NEXT: ret
2579 ;
2580 ; RV64IZFHMIN-LABEL: test_trunc_ui64:
2581 ; RV64IZFHMIN: # %bb.0:
2582 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2583 ; RV64IZFHMIN-NEXT: lui a0, 307200
2584 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2585 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2586 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2587 ; RV64IZFHMIN-NEXT: beqz a0, .LBB23_2
2588 ; RV64IZFHMIN-NEXT: # %bb.1:
2589 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2590 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
2591 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2592 ; RV64IZFHMIN-NEXT: .LBB23_2:
2593 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2594 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2595 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
2596 ; RV64IZFHMIN-NEXT: ret
2597 ;
2598 ; RV32IZHINXMIN-LABEL: test_trunc_ui64:
2599 ; RV32IZHINXMIN: # %bb.0:
2600 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2601 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2602 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2603 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2604 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB23_2
2605 ; RV32IZHINXMIN-NEXT: # %bb.1:
2606 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2607 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2608 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2609 ; RV32IZHINXMIN-NEXT: .LBB23_2:
2610 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2611 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2612 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2613 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
2614 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2615 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
2616 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2617 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2618 ; RV32IZHINXMIN-NEXT: ret
2619 ;
2620 ; RV64IZHINXMIN-LABEL: test_trunc_ui64:
2621 ; RV64IZHINXMIN: # %bb.0:
2622 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2623 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2624 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2625 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2626 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB23_2
2627 ; RV64IZHINXMIN-NEXT: # %bb.1:
2628 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2629 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
2630 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2631 ; RV64IZHINXMIN-NEXT: .LBB23_2:
2632 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2633 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2634 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
2635 ; RV64IZHINXMIN-NEXT: ret
2636 %a = call half @llvm.trunc.f16(half %x)
2637 %b = fptoui half %a to i64
2638 ret i64 %b
2639 }
2641 define signext i8 @test_round_si8(half %x) {
2642 ; RV32IZFH-LABEL: test_round_si8:
2643 ; RV32IZFH: # %bb.0:
2644 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2645 ; RV32IZFH-NEXT: ret
2646 ;
2647 ; RV64IZFH-LABEL: test_round_si8:
2648 ; RV64IZFH: # %bb.0:
2649 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
2650 ; RV64IZFH-NEXT: ret
2651 ;
2652 ; RV32IZHINX-LABEL: test_round_si8:
2653 ; RV32IZHINX: # %bb.0:
2654 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI24_0)
2655 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI24_0)(a1)
2656 ; RV32IZHINX-NEXT: fabs.h a2, a0
2657 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2658 ; RV32IZHINX-NEXT: beqz a1, .LBB24_2
2659 ; RV32IZHINX-NEXT: # %bb.1:
2660 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2661 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2662 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2663 ; RV32IZHINX-NEXT: .LBB24_2:
2664 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
2665 ; RV32IZHINX-NEXT: ret
2666 ;
2667 ; RV64IZHINX-LABEL: test_round_si8:
2668 ; RV64IZHINX: # %bb.0:
2669 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI24_0)
2670 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI24_0)(a1)
2671 ; RV64IZHINX-NEXT: fabs.h a2, a0
2672 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2673 ; RV64IZHINX-NEXT: beqz a1, .LBB24_2
2674 ; RV64IZHINX-NEXT: # %bb.1:
2675 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2676 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2677 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2678 ; RV64IZHINX-NEXT: .LBB24_2:
2679 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
2680 ; RV64IZHINX-NEXT: ret
2681 ;
2682 ; RV32IZFHMIN-LABEL: test_round_si8:
2683 ; RV32IZFHMIN: # %bb.0:
2684 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2685 ; RV32IZFHMIN-NEXT: lui a0, 307200
2686 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2687 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2688 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2689 ; RV32IZFHMIN-NEXT: beqz a0, .LBB24_2
2690 ; RV32IZFHMIN-NEXT: # %bb.1:
2691 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2692 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2693 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2694 ; RV32IZFHMIN-NEXT: .LBB24_2:
2695 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2696 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2697 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2698 ; RV32IZFHMIN-NEXT: ret
2699 ;
2700 ; RV64IZFHMIN-LABEL: test_round_si8:
2701 ; RV64IZFHMIN: # %bb.0:
2702 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2703 ; RV64IZFHMIN-NEXT: lui a0, 307200
2704 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2705 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2706 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2707 ; RV64IZFHMIN-NEXT: beqz a0, .LBB24_2
2708 ; RV64IZFHMIN-NEXT: # %bb.1:
2709 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2710 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2711 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2712 ; RV64IZFHMIN-NEXT: .LBB24_2:
2713 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2714 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2715 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
2716 ; RV64IZFHMIN-NEXT: ret
2717 ;
2718 ; RV32IZHINXMIN-LABEL: test_round_si8:
2719 ; RV32IZHINXMIN: # %bb.0:
2720 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2721 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2722 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2723 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2724 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB24_2
2725 ; RV32IZHINXMIN-NEXT: # %bb.1:
2726 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2727 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2728 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2729 ; RV32IZHINXMIN-NEXT: .LBB24_2:
2730 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2731 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2732 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2733 ; RV32IZHINXMIN-NEXT: ret
2734 ;
2735 ; RV64IZHINXMIN-LABEL: test_round_si8:
2736 ; RV64IZHINXMIN: # %bb.0:
2737 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2738 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2739 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2740 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2741 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB24_2
2742 ; RV64IZHINXMIN-NEXT: # %bb.1:
2743 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2744 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2745 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2746 ; RV64IZHINXMIN-NEXT: .LBB24_2:
2747 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2748 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2749 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
2750 ; RV64IZHINXMIN-NEXT: ret
2751 %a = call half @llvm.round.f16(half %x)
2752 %b = fptosi half %a to i8
2753 ret i8 %b
2754 }
2756 define signext i16 @test_round_si16(half %x) {
2757 ; RV32IZFH-LABEL: test_round_si16:
2758 ; RV32IZFH: # %bb.0:
2759 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2760 ; RV32IZFH-NEXT: ret
2761 ;
2762 ; RV64IZFH-LABEL: test_round_si16:
2763 ; RV64IZFH: # %bb.0:
2764 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
2765 ; RV64IZFH-NEXT: ret
2766 ;
2767 ; RV32IZHINX-LABEL: test_round_si16:
2768 ; RV32IZHINX: # %bb.0:
2769 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI25_0)
2770 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI25_0)(a1)
2771 ; RV32IZHINX-NEXT: fabs.h a2, a0
2772 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2773 ; RV32IZHINX-NEXT: beqz a1, .LBB25_2
2774 ; RV32IZHINX-NEXT: # %bb.1:
2775 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2776 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2777 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2778 ; RV32IZHINX-NEXT: .LBB25_2:
2779 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
2780 ; RV32IZHINX-NEXT: ret
2781 ;
2782 ; RV64IZHINX-LABEL: test_round_si16:
2783 ; RV64IZHINX: # %bb.0:
2784 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI25_0)
2785 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI25_0)(a1)
2786 ; RV64IZHINX-NEXT: fabs.h a2, a0
2787 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2788 ; RV64IZHINX-NEXT: beqz a1, .LBB25_2
2789 ; RV64IZHINX-NEXT: # %bb.1:
2790 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2791 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2792 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2793 ; RV64IZHINX-NEXT: .LBB25_2:
2794 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
2795 ; RV64IZHINX-NEXT: ret
2796 ;
2797 ; RV32IZFHMIN-LABEL: test_round_si16:
2798 ; RV32IZFHMIN: # %bb.0:
2799 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2800 ; RV32IZFHMIN-NEXT: lui a0, 307200
2801 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2802 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
2803 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
2804 ; RV32IZFHMIN-NEXT: beqz a0, .LBB25_2
2805 ; RV32IZFHMIN-NEXT: # %bb.1:
2806 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2807 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2808 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2809 ; RV32IZFHMIN-NEXT: .LBB25_2:
2810 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2811 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2812 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2813 ; RV32IZFHMIN-NEXT: ret
2814 ;
2815 ; RV64IZFHMIN-LABEL: test_round_si16:
2816 ; RV64IZFHMIN: # %bb.0:
2817 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2818 ; RV64IZFHMIN-NEXT: lui a0, 307200
2819 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
2820 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
2821 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
2822 ; RV64IZFHMIN-NEXT: beqz a0, .LBB25_2
2823 ; RV64IZFHMIN-NEXT: # %bb.1:
2824 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2825 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2826 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2827 ; RV64IZFHMIN-NEXT: .LBB25_2:
2828 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2829 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
2830 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
2831 ; RV64IZFHMIN-NEXT: ret
2832 ;
2833 ; RV32IZHINXMIN-LABEL: test_round_si16:
2834 ; RV32IZHINXMIN: # %bb.0:
2835 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2836 ; RV32IZHINXMIN-NEXT: lui a1, 307200
2837 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
2838 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
2839 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB25_2
2840 ; RV32IZHINXMIN-NEXT: # %bb.1:
2841 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2842 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2843 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2844 ; RV32IZHINXMIN-NEXT: .LBB25_2:
2845 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2846 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2847 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2848 ; RV32IZHINXMIN-NEXT: ret
2849 ;
2850 ; RV64IZHINXMIN-LABEL: test_round_si16:
2851 ; RV64IZHINXMIN: # %bb.0:
2852 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2853 ; RV64IZHINXMIN-NEXT: lui a1, 307200
2854 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
2855 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
2856 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB25_2
2857 ; RV64IZHINXMIN-NEXT: # %bb.1:
2858 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2859 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2860 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2861 ; RV64IZHINXMIN-NEXT: .LBB25_2:
2862 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2863 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2864 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
2865 ; RV64IZHINXMIN-NEXT: ret
2866 %a = call half @llvm.round.f16(half %x)
2867 %b = fptosi half %a to i16
2868 ret i16 %b
2869 }
2871 define signext i32 @test_round_si32(half %x) {
2872 ; CHECKIZFH-LABEL: test_round_si32:
2873 ; CHECKIZFH: # %bb.0:
2874 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
2875 ; CHECKIZFH-NEXT: ret
2876 ;
2877 ; CHECKIZHINX-LABEL: test_round_si32:
2878 ; CHECKIZHINX: # %bb.0:
2879 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI26_0)
2880 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI26_0)(a1)
2881 ; CHECKIZHINX-NEXT: fabs.h a2, a0
2882 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
2883 ; CHECKIZHINX-NEXT: beqz a1, .LBB26_2
2884 ; CHECKIZHINX-NEXT: # %bb.1:
2885 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
2886 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
2887 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
2888 ; CHECKIZHINX-NEXT: .LBB26_2:
2889 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
2890 ; CHECKIZHINX-NEXT: ret
2891 ;
2892 ; CHECKIZFHMIN-LABEL: test_round_si32:
2893 ; CHECKIZFHMIN: # %bb.0:
2894 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
2895 ; CHECKIZFHMIN-NEXT: lui a0, 307200
2896 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
2897 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
2898 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
2899 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB26_2
2900 ; CHECKIZFHMIN-NEXT: # %bb.1:
2901 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
2902 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
2903 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
2904 ; CHECKIZFHMIN-NEXT: .LBB26_2:
2905 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
2906 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
2907 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2908 ; CHECKIZFHMIN-NEXT: ret
2909 ;
2910 ; CHECKIZHINXMIN-LABEL: test_round_si32:
2911 ; CHECKIZHINXMIN: # %bb.0:
2912 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2913 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
2914 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
2915 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
2916 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB26_2
2917 ; CHECKIZHINXMIN-NEXT: # %bb.1:
2918 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
2919 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
2920 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
2921 ; CHECKIZHINXMIN-NEXT: .LBB26_2:
2922 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
2923 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
2924 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
2925 ; CHECKIZHINXMIN-NEXT: ret
2926 %a = call half @llvm.round.f16(half %x)
2927 %b = fptosi half %a to i32
2928 ret i32 %b
2929 }
2931 define i64 @test_round_si64(half %x) {
2932 ; RV32IZFH-LABEL: test_round_si64:
2933 ; RV32IZFH: # %bb.0:
2934 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI27_0)
2935 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI27_0)(a0)
2936 ; RV32IZFH-NEXT: fabs.h fa4, fa0
2937 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
2938 ; RV32IZFH-NEXT: beqz a0, .LBB27_2
2939 ; RV32IZFH-NEXT: # %bb.1:
2940 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
2941 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
2942 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
2943 ; RV32IZFH-NEXT: .LBB27_2:
2944 ; RV32IZFH-NEXT: addi sp, sp, -16
2945 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
2946 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2947 ; RV32IZFH-NEXT: .cfi_offset ra, -4
2948 ; RV32IZFH-NEXT: call __fixhfdi
2949 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2950 ; RV32IZFH-NEXT: addi sp, sp, 16
2951 ; RV32IZFH-NEXT: ret
2952 ;
2953 ; RV64IZFH-LABEL: test_round_si64:
2954 ; RV64IZFH: # %bb.0:
2955 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
2956 ; RV64IZFH-NEXT: ret
2957 ;
2958 ; RV32IZHINX-LABEL: test_round_si64:
2959 ; RV32IZHINX: # %bb.0:
2960 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI27_0)
2961 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI27_0)(a1)
2962 ; RV32IZHINX-NEXT: fabs.h a2, a0
2963 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
2964 ; RV32IZHINX-NEXT: beqz a1, .LBB27_2
2965 ; RV32IZHINX-NEXT: # %bb.1:
2966 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2967 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2968 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
2969 ; RV32IZHINX-NEXT: .LBB27_2:
2970 ; RV32IZHINX-NEXT: addi sp, sp, -16
2971 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
2972 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2973 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
2974 ; RV32IZHINX-NEXT: call __fixhfdi
2975 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2976 ; RV32IZHINX-NEXT: addi sp, sp, 16
2977 ; RV32IZHINX-NEXT: ret
2978 ;
2979 ; RV64IZHINX-LABEL: test_round_si64:
2980 ; RV64IZHINX: # %bb.0:
2981 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI27_0)
2982 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI27_0)(a1)
2983 ; RV64IZHINX-NEXT: fabs.h a2, a0
2984 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
2985 ; RV64IZHINX-NEXT: beqz a1, .LBB27_2
2986 ; RV64IZHINX-NEXT: # %bb.1:
2987 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
2988 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
2989 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
2990 ; RV64IZHINX-NEXT: .LBB27_2:
2991 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
2992 ; RV64IZHINX-NEXT: ret
2993 ;
2994 ; RV32IZFHMIN-LABEL: test_round_si64:
2995 ; RV32IZFHMIN: # %bb.0:
2996 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2997 ; RV32IZFHMIN-NEXT: lui a0, 307200
2998 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
2999 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3000 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3001 ; RV32IZFHMIN-NEXT: beqz a0, .LBB27_2
3002 ; RV32IZFHMIN-NEXT: # %bb.1:
3003 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3004 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3005 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3006 ; RV32IZFHMIN-NEXT: .LBB27_2:
3007 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3008 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
3009 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3010 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
3011 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
3012 ; RV32IZFHMIN-NEXT: call __fixhfdi
3013 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3014 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3015 ; RV32IZFHMIN-NEXT: ret
3016 ;
3017 ; RV64IZFHMIN-LABEL: test_round_si64:
3018 ; RV64IZFHMIN: # %bb.0:
3019 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3020 ; RV64IZFHMIN-NEXT: lui a0, 307200
3021 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3022 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3023 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3024 ; RV64IZFHMIN-NEXT: beqz a0, .LBB27_2
3025 ; RV64IZFHMIN-NEXT: # %bb.1:
3026 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3027 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3028 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3029 ; RV64IZFHMIN-NEXT: .LBB27_2:
3030 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3031 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3032 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3033 ; RV64IZFHMIN-NEXT: ret
3034 ;
3035 ; RV32IZHINXMIN-LABEL: test_round_si64:
3036 ; RV32IZHINXMIN: # %bb.0:
3037 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3038 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3039 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3040 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3041 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB27_2
3042 ; RV32IZHINXMIN-NEXT: # %bb.1:
3043 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3044 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3045 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3046 ; RV32IZHINXMIN-NEXT: .LBB27_2:
3047 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3048 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
3049 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3050 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
3051 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3052 ; RV32IZHINXMIN-NEXT: call __fixhfdi
3053 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3054 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3055 ; RV32IZHINXMIN-NEXT: ret
3056 ;
3057 ; RV64IZHINXMIN-LABEL: test_round_si64:
3058 ; RV64IZHINXMIN: # %bb.0:
3059 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3060 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3061 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3062 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3063 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB27_2
3064 ; RV64IZHINXMIN-NEXT: # %bb.1:
3065 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3066 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3067 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3068 ; RV64IZHINXMIN-NEXT: .LBB27_2:
3069 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3070 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3071 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
3072 ; RV64IZHINXMIN-NEXT: ret
3073 %a = call half @llvm.round.f16(half %x)
3074 %b = fptosi half %a to i64
3075 ret i64 %b
3076 }
3078 define zeroext i8 @test_round_ui8(half %x) {
3079 ; RV32IZFH-LABEL: test_round_ui8:
3080 ; RV32IZFH: # %bb.0:
3081 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
3082 ; RV32IZFH-NEXT: ret
3083 ;
3084 ; RV64IZFH-LABEL: test_round_ui8:
3085 ; RV64IZFH: # %bb.0:
3086 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
3087 ; RV64IZFH-NEXT: ret
3088 ;
3089 ; RV32IZHINX-LABEL: test_round_ui8:
3090 ; RV32IZHINX: # %bb.0:
3091 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI28_0)
3092 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI28_0)(a1)
3093 ; RV32IZHINX-NEXT: fabs.h a2, a0
3094 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3095 ; RV32IZHINX-NEXT: beqz a1, .LBB28_2
3096 ; RV32IZHINX-NEXT: # %bb.1:
3097 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3098 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3099 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3100 ; RV32IZHINX-NEXT: .LBB28_2:
3101 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
3102 ; RV32IZHINX-NEXT: ret
3103 ;
3104 ; RV64IZHINX-LABEL: test_round_ui8:
3105 ; RV64IZHINX: # %bb.0:
3106 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI28_0)
3107 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI28_0)(a1)
3108 ; RV64IZHINX-NEXT: fabs.h a2, a0
3109 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3110 ; RV64IZHINX-NEXT: beqz a1, .LBB28_2
3111 ; RV64IZHINX-NEXT: # %bb.1:
3112 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3113 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3114 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3115 ; RV64IZHINX-NEXT: .LBB28_2:
3116 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
3117 ; RV64IZHINX-NEXT: ret
3118 ;
3119 ; RV32IZFHMIN-LABEL: test_round_ui8:
3120 ; RV32IZFHMIN: # %bb.0:
3121 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3122 ; RV32IZFHMIN-NEXT: lui a0, 307200
3123 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3124 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3125 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3126 ; RV32IZFHMIN-NEXT: beqz a0, .LBB28_2
3127 ; RV32IZFHMIN-NEXT: # %bb.1:
3128 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3129 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3130 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3131 ; RV32IZFHMIN-NEXT: .LBB28_2:
3132 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3133 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3134 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
3135 ; RV32IZFHMIN-NEXT: ret
3136 ;
3137 ; RV64IZFHMIN-LABEL: test_round_ui8:
3138 ; RV64IZFHMIN: # %bb.0:
3139 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3140 ; RV64IZFHMIN-NEXT: lui a0, 307200
3141 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3142 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3143 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3144 ; RV64IZFHMIN-NEXT: beqz a0, .LBB28_2
3145 ; RV64IZFHMIN-NEXT: # %bb.1:
3146 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3147 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3148 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3149 ; RV64IZFHMIN-NEXT: .LBB28_2:
3150 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3151 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3152 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
3153 ; RV64IZFHMIN-NEXT: ret
3154 ;
3155 ; RV32IZHINXMIN-LABEL: test_round_ui8:
3156 ; RV32IZHINXMIN: # %bb.0:
3157 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3158 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3159 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3160 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3161 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB28_2
3162 ; RV32IZHINXMIN-NEXT: # %bb.1:
3163 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3164 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3165 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3166 ; RV32IZHINXMIN-NEXT: .LBB28_2:
3167 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3168 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3169 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
3170 ; RV32IZHINXMIN-NEXT: ret
3171 ;
3172 ; RV64IZHINXMIN-LABEL: test_round_ui8:
3173 ; RV64IZHINXMIN: # %bb.0:
3174 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3175 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3176 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3177 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3178 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB28_2
3179 ; RV64IZHINXMIN-NEXT: # %bb.1:
3180 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3181 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3182 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3183 ; RV64IZHINXMIN-NEXT: .LBB28_2:
3184 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3185 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3186 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
3187 ; RV64IZHINXMIN-NEXT: ret
3188 %a = call half @llvm.round.f16(half %x)
3189 %b = fptoui half %a to i8
3190 ret i8 %b
3191 }
3193 define zeroext i16 @test_round_ui16(half %x) {
3194 ; RV32IZFH-LABEL: test_round_ui16:
3195 ; RV32IZFH: # %bb.0:
3196 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
3197 ; RV32IZFH-NEXT: ret
3198 ;
3199 ; RV64IZFH-LABEL: test_round_ui16:
3200 ; RV64IZFH: # %bb.0:
3201 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
3202 ; RV64IZFH-NEXT: ret
3203 ;
3204 ; RV32IZHINX-LABEL: test_round_ui16:
3205 ; RV32IZHINX: # %bb.0:
3206 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI29_0)
3207 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI29_0)(a1)
3208 ; RV32IZHINX-NEXT: fabs.h a2, a0
3209 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3210 ; RV32IZHINX-NEXT: beqz a1, .LBB29_2
3211 ; RV32IZHINX-NEXT: # %bb.1:
3212 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3213 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3214 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3215 ; RV32IZHINX-NEXT: .LBB29_2:
3216 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
3217 ; RV32IZHINX-NEXT: ret
3218 ;
3219 ; RV64IZHINX-LABEL: test_round_ui16:
3220 ; RV64IZHINX: # %bb.0:
3221 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI29_0)
3222 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI29_0)(a1)
3223 ; RV64IZHINX-NEXT: fabs.h a2, a0
3224 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3225 ; RV64IZHINX-NEXT: beqz a1, .LBB29_2
3226 ; RV64IZHINX-NEXT: # %bb.1:
3227 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3228 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3229 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3230 ; RV64IZHINX-NEXT: .LBB29_2:
3231 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
3232 ; RV64IZHINX-NEXT: ret
3233 ;
3234 ; RV32IZFHMIN-LABEL: test_round_ui16:
3235 ; RV32IZFHMIN: # %bb.0:
3236 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3237 ; RV32IZFHMIN-NEXT: lui a0, 307200
3238 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3239 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3240 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3241 ; RV32IZFHMIN-NEXT: beqz a0, .LBB29_2
3242 ; RV32IZFHMIN-NEXT: # %bb.1:
3243 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3244 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3245 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3246 ; RV32IZFHMIN-NEXT: .LBB29_2:
3247 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3248 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3249 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
3250 ; RV32IZFHMIN-NEXT: ret
3251 ;
3252 ; RV64IZFHMIN-LABEL: test_round_ui16:
3253 ; RV64IZFHMIN: # %bb.0:
3254 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3255 ; RV64IZFHMIN-NEXT: lui a0, 307200
3256 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3257 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3258 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3259 ; RV64IZFHMIN-NEXT: beqz a0, .LBB29_2
3260 ; RV64IZFHMIN-NEXT: # %bb.1:
3261 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3262 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3263 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3264 ; RV64IZFHMIN-NEXT: .LBB29_2:
3265 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3266 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3267 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
3268 ; RV64IZFHMIN-NEXT: ret
3269 ;
3270 ; RV32IZHINXMIN-LABEL: test_round_ui16:
3271 ; RV32IZHINXMIN: # %bb.0:
3272 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3273 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3274 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3275 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3276 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB29_2
3277 ; RV32IZHINXMIN-NEXT: # %bb.1:
3278 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3279 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3280 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3281 ; RV32IZHINXMIN-NEXT: .LBB29_2:
3282 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3283 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3284 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
3285 ; RV32IZHINXMIN-NEXT: ret
3286 ;
3287 ; RV64IZHINXMIN-LABEL: test_round_ui16:
3288 ; RV64IZHINXMIN: # %bb.0:
3289 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3290 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3291 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3292 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3293 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB29_2
3294 ; RV64IZHINXMIN-NEXT: # %bb.1:
3295 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3296 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3297 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3298 ; RV64IZHINXMIN-NEXT: .LBB29_2:
3299 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3300 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3301 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
3302 ; RV64IZHINXMIN-NEXT: ret
3303 %a = call half @llvm.round.f16(half %x)
3304 %b = fptoui half %a to i16
3305 ret i16 %b
3306 }
3308 define signext i32 @test_round_ui32(half %x) {
3309 ; CHECKIZFH-LABEL: test_round_ui32:
3310 ; CHECKIZFH: # %bb.0:
3311 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rmm
3312 ; CHECKIZFH-NEXT: ret
3313 ;
3314 ; CHECKIZHINX-LABEL: test_round_ui32:
3315 ; CHECKIZHINX: # %bb.0:
3316 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI30_0)
3317 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI30_0)(a1)
3318 ; CHECKIZHINX-NEXT: fabs.h a2, a0
3319 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
3320 ; CHECKIZHINX-NEXT: beqz a1, .LBB30_2
3321 ; CHECKIZHINX-NEXT: # %bb.1:
3322 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
3323 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
3324 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
3325 ; CHECKIZHINX-NEXT: .LBB30_2:
3326 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
3327 ; CHECKIZHINX-NEXT: ret
3328 ;
3329 ; CHECKIZFHMIN-LABEL: test_round_ui32:
3330 ; CHECKIZFHMIN: # %bb.0:
3331 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
3332 ; CHECKIZFHMIN-NEXT: lui a0, 307200
3333 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
3334 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
3335 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
3336 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB30_2
3337 ; CHECKIZFHMIN-NEXT: # %bb.1:
3338 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3339 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3340 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3341 ; CHECKIZFHMIN-NEXT: .LBB30_2:
3342 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
3343 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
3344 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
3345 ; CHECKIZFHMIN-NEXT: ret
3346 ;
3347 ; CHECKIZHINXMIN-LABEL: test_round_ui32:
3348 ; CHECKIZHINXMIN: # %bb.0:
3349 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3350 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
3351 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
3352 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
3353 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB30_2
3354 ; CHECKIZHINXMIN-NEXT: # %bb.1:
3355 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3356 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3357 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3358 ; CHECKIZHINXMIN-NEXT: .LBB30_2:
3359 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
3360 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3361 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
3362 ; CHECKIZHINXMIN-NEXT: ret
3363 %a = call half @llvm.round.f16(half %x)
3364 %b = fptoui half %a to i32
3365 ret i32 %b
3366 }
3368 define i64 @test_round_ui64(half %x) {
3369 ; RV32IZFH-LABEL: test_round_ui64:
3370 ; RV32IZFH: # %bb.0:
3371 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI31_0)
3372 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI31_0)(a0)
3373 ; RV32IZFH-NEXT: fabs.h fa4, fa0
3374 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
3375 ; RV32IZFH-NEXT: beqz a0, .LBB31_2
3376 ; RV32IZFH-NEXT: # %bb.1:
3377 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
3378 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rmm
3379 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
3380 ; RV32IZFH-NEXT: .LBB31_2:
3381 ; RV32IZFH-NEXT: addi sp, sp, -16
3382 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
3383 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3384 ; RV32IZFH-NEXT: .cfi_offset ra, -4
3385 ; RV32IZFH-NEXT: call __fixunshfdi
3386 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3387 ; RV32IZFH-NEXT: addi sp, sp, 16
3388 ; RV32IZFH-NEXT: ret
3389 ;
3390 ; RV64IZFH-LABEL: test_round_ui64:
3391 ; RV64IZFH: # %bb.0:
3392 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
3393 ; RV64IZFH-NEXT: ret
3394 ;
3395 ; RV32IZHINX-LABEL: test_round_ui64:
3396 ; RV32IZHINX: # %bb.0:
3397 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI31_0)
3398 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI31_0)(a1)
3399 ; RV32IZHINX-NEXT: fabs.h a2, a0
3400 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3401 ; RV32IZHINX-NEXT: beqz a1, .LBB31_2
3402 ; RV32IZHINX-NEXT: # %bb.1:
3403 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3404 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3405 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3406 ; RV32IZHINX-NEXT: .LBB31_2:
3407 ; RV32IZHINX-NEXT: addi sp, sp, -16
3408 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
3409 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3410 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
3411 ; RV32IZHINX-NEXT: call __fixunshfdi
3412 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3413 ; RV32IZHINX-NEXT: addi sp, sp, 16
3414 ; RV32IZHINX-NEXT: ret
3415 ;
3416 ; RV64IZHINX-LABEL: test_round_ui64:
3417 ; RV64IZHINX: # %bb.0:
3418 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI31_0)
3419 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI31_0)(a1)
3420 ; RV64IZHINX-NEXT: fabs.h a2, a0
3421 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3422 ; RV64IZHINX-NEXT: beqz a1, .LBB31_2
3423 ; RV64IZHINX-NEXT: # %bb.1:
3424 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rmm
3425 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rmm
3426 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3427 ; RV64IZHINX-NEXT: .LBB31_2:
3428 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
3429 ; RV64IZHINX-NEXT: ret
3430 ;
3431 ; RV32IZFHMIN-LABEL: test_round_ui64:
3432 ; RV32IZFHMIN: # %bb.0:
3433 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3434 ; RV32IZFHMIN-NEXT: lui a0, 307200
3435 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3436 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3437 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3438 ; RV32IZFHMIN-NEXT: beqz a0, .LBB31_2
3439 ; RV32IZFHMIN-NEXT: # %bb.1:
3440 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3441 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3442 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3443 ; RV32IZFHMIN-NEXT: .LBB31_2:
3444 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3445 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
3446 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3447 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
3448 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
3449 ; RV32IZFHMIN-NEXT: call __fixunshfdi
3450 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3451 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3452 ; RV32IZFHMIN-NEXT: ret
3453 ;
3454 ; RV64IZFHMIN-LABEL: test_round_ui64:
3455 ; RV64IZFHMIN: # %bb.0:
3456 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3457 ; RV64IZFHMIN-NEXT: lui a0, 307200
3458 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3459 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3460 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3461 ; RV64IZFHMIN-NEXT: beqz a0, .LBB31_2
3462 ; RV64IZFHMIN-NEXT: # %bb.1:
3463 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
3464 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
3465 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3466 ; RV64IZFHMIN-NEXT: .LBB31_2:
3467 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3468 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3469 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
3470 ; RV64IZFHMIN-NEXT: ret
3471 ;
3472 ; RV32IZHINXMIN-LABEL: test_round_ui64:
3473 ; RV32IZHINXMIN: # %bb.0:
3474 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3475 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3476 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3477 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3478 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB31_2
3479 ; RV32IZHINXMIN-NEXT: # %bb.1:
3480 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3481 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3482 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3483 ; RV32IZHINXMIN-NEXT: .LBB31_2:
3484 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3485 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
3486 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3487 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
3488 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3489 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
3490 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3491 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3492 ; RV32IZHINXMIN-NEXT: ret
3493 ;
3494 ; RV64IZHINXMIN-LABEL: test_round_ui64:
3495 ; RV64IZHINXMIN: # %bb.0:
3496 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3497 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3498 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3499 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3500 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB31_2
3501 ; RV64IZHINXMIN-NEXT: # %bb.1:
3502 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
3503 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
3504 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3505 ; RV64IZHINXMIN-NEXT: .LBB31_2:
3506 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3507 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3508 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
3509 ; RV64IZHINXMIN-NEXT: ret
3510 %a = call half @llvm.round.f16(half %x)
3511 %b = fptoui half %a to i64
3512 ret i64 %b
3513 }
3515 define signext i8 @test_roundeven_si8(half %x) {
3516 ; RV32IZFH-LABEL: test_roundeven_si8:
3517 ; RV32IZFH: # %bb.0:
3518 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
3519 ; RV32IZFH-NEXT: ret
3520 ;
3521 ; RV64IZFH-LABEL: test_roundeven_si8:
3522 ; RV64IZFH: # %bb.0:
3523 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
3524 ; RV64IZFH-NEXT: ret
3525 ;
3526 ; RV32IZHINX-LABEL: test_roundeven_si8:
3527 ; RV32IZHINX: # %bb.0:
3528 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI32_0)
3529 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI32_0)(a1)
3530 ; RV32IZHINX-NEXT: fabs.h a2, a0
3531 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3532 ; RV32IZHINX-NEXT: beqz a1, .LBB32_2
3533 ; RV32IZHINX-NEXT: # %bb.1:
3534 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3535 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3536 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3537 ; RV32IZHINX-NEXT: .LBB32_2:
3538 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
3539 ; RV32IZHINX-NEXT: ret
3540 ;
3541 ; RV64IZHINX-LABEL: test_roundeven_si8:
3542 ; RV64IZHINX: # %bb.0:
3543 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI32_0)
3544 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI32_0)(a1)
3545 ; RV64IZHINX-NEXT: fabs.h a2, a0
3546 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3547 ; RV64IZHINX-NEXT: beqz a1, .LBB32_2
3548 ; RV64IZHINX-NEXT: # %bb.1:
3549 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3550 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3551 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3552 ; RV64IZHINX-NEXT: .LBB32_2:
3553 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
3554 ; RV64IZHINX-NEXT: ret
3555 ;
3556 ; RV32IZFHMIN-LABEL: test_roundeven_si8:
3557 ; RV32IZFHMIN: # %bb.0:
3558 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3559 ; RV32IZFHMIN-NEXT: lui a0, 307200
3560 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3561 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3562 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3563 ; RV32IZFHMIN-NEXT: beqz a0, .LBB32_2
3564 ; RV32IZFHMIN-NEXT: # %bb.1:
3565 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3566 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3567 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3568 ; RV32IZFHMIN-NEXT: .LBB32_2:
3569 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3570 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3571 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3572 ; RV32IZFHMIN-NEXT: ret
3573 ;
3574 ; RV64IZFHMIN-LABEL: test_roundeven_si8:
3575 ; RV64IZFHMIN: # %bb.0:
3576 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3577 ; RV64IZFHMIN-NEXT: lui a0, 307200
3578 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3579 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3580 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3581 ; RV64IZFHMIN-NEXT: beqz a0, .LBB32_2
3582 ; RV64IZFHMIN-NEXT: # %bb.1:
3583 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3584 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3585 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3586 ; RV64IZFHMIN-NEXT: .LBB32_2:
3587 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3588 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3589 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3590 ; RV64IZFHMIN-NEXT: ret
3591 ;
3592 ; RV32IZHINXMIN-LABEL: test_roundeven_si8:
3593 ; RV32IZHINXMIN: # %bb.0:
3594 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3595 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3596 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3597 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3598 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB32_2
3599 ; RV32IZHINXMIN-NEXT: # %bb.1:
3600 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3601 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3602 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3603 ; RV32IZHINXMIN-NEXT: .LBB32_2:
3604 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3605 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3606 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3607 ; RV32IZHINXMIN-NEXT: ret
3608 ;
3609 ; RV64IZHINXMIN-LABEL: test_roundeven_si8:
3610 ; RV64IZHINXMIN: # %bb.0:
3611 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3612 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3613 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3614 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3615 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB32_2
3616 ; RV64IZHINXMIN-NEXT: # %bb.1:
3617 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3618 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3619 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3620 ; RV64IZHINXMIN-NEXT: .LBB32_2:
3621 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3622 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3623 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
3624 ; RV64IZHINXMIN-NEXT: ret
3625 %a = call half @llvm.roundeven.f16(half %x)
3626 %b = fptosi half %a to i8
3627 ret i8 %b
3628 }
3630 define signext i16 @test_roundeven_si16(half %x) {
3631 ; RV32IZFH-LABEL: test_roundeven_si16:
3632 ; RV32IZFH: # %bb.0:
3633 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
3634 ; RV32IZFH-NEXT: ret
3635 ;
3636 ; RV64IZFH-LABEL: test_roundeven_si16:
3637 ; RV64IZFH: # %bb.0:
3638 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
3639 ; RV64IZFH-NEXT: ret
3640 ;
3641 ; RV32IZHINX-LABEL: test_roundeven_si16:
3642 ; RV32IZHINX: # %bb.0:
3643 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI33_0)
3644 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI33_0)(a1)
3645 ; RV32IZHINX-NEXT: fabs.h a2, a0
3646 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3647 ; RV32IZHINX-NEXT: beqz a1, .LBB33_2
3648 ; RV32IZHINX-NEXT: # %bb.1:
3649 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3650 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3651 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3652 ; RV32IZHINX-NEXT: .LBB33_2:
3653 ; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
3654 ; RV32IZHINX-NEXT: ret
3655 ;
3656 ; RV64IZHINX-LABEL: test_roundeven_si16:
3657 ; RV64IZHINX: # %bb.0:
3658 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI33_0)
3659 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI33_0)(a1)
3660 ; RV64IZHINX-NEXT: fabs.h a2, a0
3661 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3662 ; RV64IZHINX-NEXT: beqz a1, .LBB33_2
3663 ; RV64IZHINX-NEXT: # %bb.1:
3664 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3665 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3666 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3667 ; RV64IZHINX-NEXT: .LBB33_2:
3668 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
3669 ; RV64IZHINX-NEXT: ret
3670 ;
3671 ; RV32IZFHMIN-LABEL: test_roundeven_si16:
3672 ; RV32IZFHMIN: # %bb.0:
3673 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3674 ; RV32IZFHMIN-NEXT: lui a0, 307200
3675 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3676 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3677 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3678 ; RV32IZFHMIN-NEXT: beqz a0, .LBB33_2
3679 ; RV32IZFHMIN-NEXT: # %bb.1:
3680 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3681 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3682 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3683 ; RV32IZFHMIN-NEXT: .LBB33_2:
3684 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3685 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3686 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3687 ; RV32IZFHMIN-NEXT: ret
3688 ;
3689 ; RV64IZFHMIN-LABEL: test_roundeven_si16:
3690 ; RV64IZFHMIN: # %bb.0:
3691 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3692 ; RV64IZFHMIN-NEXT: lui a0, 307200
3693 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3694 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3695 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3696 ; RV64IZFHMIN-NEXT: beqz a0, .LBB33_2
3697 ; RV64IZFHMIN-NEXT: # %bb.1:
3698 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3699 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3700 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3701 ; RV64IZFHMIN-NEXT: .LBB33_2:
3702 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3703 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3704 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3705 ; RV64IZFHMIN-NEXT: ret
3706 ;
3707 ; RV32IZHINXMIN-LABEL: test_roundeven_si16:
3708 ; RV32IZHINXMIN: # %bb.0:
3709 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3710 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3711 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3712 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3713 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB33_2
3714 ; RV32IZHINXMIN-NEXT: # %bb.1:
3715 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3716 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3717 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3718 ; RV32IZHINXMIN-NEXT: .LBB33_2:
3719 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3720 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3721 ; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3722 ; RV32IZHINXMIN-NEXT: ret
3723 ;
3724 ; RV64IZHINXMIN-LABEL: test_roundeven_si16:
3725 ; RV64IZHINXMIN: # %bb.0:
3726 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3727 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3728 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3729 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3730 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB33_2
3731 ; RV64IZHINXMIN-NEXT: # %bb.1:
3732 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3733 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3734 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3735 ; RV64IZHINXMIN-NEXT: .LBB33_2:
3736 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3737 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3738 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
3739 ; RV64IZHINXMIN-NEXT: ret
3740 %a = call half @llvm.roundeven.f16(half %x)
3741 %b = fptosi half %a to i16
3742 ret i16 %b
3743 }
3745 define signext i32 @test_roundeven_si32(half %x) {
3746 ; CHECKIZFH-LABEL: test_roundeven_si32:
3747 ; CHECKIZFH: # %bb.0:
3748 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
3749 ; CHECKIZFH-NEXT: ret
3750 ;
3751 ; CHECKIZHINX-LABEL: test_roundeven_si32:
3752 ; CHECKIZHINX: # %bb.0:
3753 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI34_0)
3754 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI34_0)(a1)
3755 ; CHECKIZHINX-NEXT: fabs.h a2, a0
3756 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
3757 ; CHECKIZHINX-NEXT: beqz a1, .LBB34_2
3758 ; CHECKIZHINX-NEXT: # %bb.1:
3759 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
3760 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
3761 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
3762 ; CHECKIZHINX-NEXT: .LBB34_2:
3763 ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz
3764 ; CHECKIZHINX-NEXT: ret
3765 ;
3766 ; CHECKIZFHMIN-LABEL: test_roundeven_si32:
3767 ; CHECKIZFHMIN: # %bb.0:
3768 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
3769 ; CHECKIZFHMIN-NEXT: lui a0, 307200
3770 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
3771 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
3772 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
3773 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB34_2
3774 ; CHECKIZFHMIN-NEXT: # %bb.1:
3775 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3776 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3777 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3778 ; CHECKIZFHMIN-NEXT: .LBB34_2:
3779 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
3780 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
3781 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
3782 ; CHECKIZFHMIN-NEXT: ret
3783 ;
3784 ; CHECKIZHINXMIN-LABEL: test_roundeven_si32:
3785 ; CHECKIZHINXMIN: # %bb.0:
3786 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3787 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
3788 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
3789 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
3790 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB34_2
3791 ; CHECKIZHINXMIN-NEXT: # %bb.1:
3792 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3793 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3794 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3795 ; CHECKIZHINXMIN-NEXT: .LBB34_2:
3796 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
3797 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
3798 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
3799 ; CHECKIZHINXMIN-NEXT: ret
3800 %a = call half @llvm.roundeven.f16(half %x)
3801 %b = fptosi half %a to i32
3802 ret i32 %b
3803 }
3805 define i64 @test_roundeven_si64(half %x) {
3806 ; RV32IZFH-LABEL: test_roundeven_si64:
3807 ; RV32IZFH: # %bb.0:
3808 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI35_0)
3809 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI35_0)(a0)
3810 ; RV32IZFH-NEXT: fabs.h fa4, fa0
3811 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
3812 ; RV32IZFH-NEXT: beqz a0, .LBB35_2
3813 ; RV32IZFH-NEXT: # %bb.1:
3814 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
3815 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
3816 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
3817 ; RV32IZFH-NEXT: .LBB35_2:
3818 ; RV32IZFH-NEXT: addi sp, sp, -16
3819 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
3820 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3821 ; RV32IZFH-NEXT: .cfi_offset ra, -4
3822 ; RV32IZFH-NEXT: call __fixhfdi
3823 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3824 ; RV32IZFH-NEXT: addi sp, sp, 16
3825 ; RV32IZFH-NEXT: ret
3826 ;
3827 ; RV64IZFH-LABEL: test_roundeven_si64:
3828 ; RV64IZFH: # %bb.0:
3829 ; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
3830 ; RV64IZFH-NEXT: ret
3831 ;
3832 ; RV32IZHINX-LABEL: test_roundeven_si64:
3833 ; RV32IZHINX: # %bb.0:
3834 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI35_0)
3835 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI35_0)(a1)
3836 ; RV32IZHINX-NEXT: fabs.h a2, a0
3837 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3838 ; RV32IZHINX-NEXT: beqz a1, .LBB35_2
3839 ; RV32IZHINX-NEXT: # %bb.1:
3840 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3841 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3842 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3843 ; RV32IZHINX-NEXT: .LBB35_2:
3844 ; RV32IZHINX-NEXT: addi sp, sp, -16
3845 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
3846 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3847 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
3848 ; RV32IZHINX-NEXT: call __fixhfdi
3849 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3850 ; RV32IZHINX-NEXT: addi sp, sp, 16
3851 ; RV32IZHINX-NEXT: ret
3852 ;
3853 ; RV64IZHINX-LABEL: test_roundeven_si64:
3854 ; RV64IZHINX: # %bb.0:
3855 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI35_0)
3856 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI35_0)(a1)
3857 ; RV64IZHINX-NEXT: fabs.h a2, a0
3858 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3859 ; RV64IZHINX-NEXT: beqz a1, .LBB35_2
3860 ; RV64IZHINX-NEXT: # %bb.1:
3861 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3862 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3863 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3864 ; RV64IZHINX-NEXT: .LBB35_2:
3865 ; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
3866 ; RV64IZHINX-NEXT: ret
3867 ;
3868 ; RV32IZFHMIN-LABEL: test_roundeven_si64:
3869 ; RV32IZFHMIN: # %bb.0:
3870 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3871 ; RV32IZFHMIN-NEXT: lui a0, 307200
3872 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3873 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3874 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
3875 ; RV32IZFHMIN-NEXT: beqz a0, .LBB35_2
3876 ; RV32IZFHMIN-NEXT: # %bb.1:
3877 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3878 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3879 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3880 ; RV32IZFHMIN-NEXT: .LBB35_2:
3881 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
3882 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
3883 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3884 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
3885 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
3886 ; RV32IZFHMIN-NEXT: call __fixhfdi
3887 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3888 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
3889 ; RV32IZFHMIN-NEXT: ret
3890 ;
3891 ; RV64IZFHMIN-LABEL: test_roundeven_si64:
3892 ; RV64IZFHMIN: # %bb.0:
3893 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3894 ; RV64IZFHMIN-NEXT: lui a0, 307200
3895 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
3896 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
3897 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
3898 ; RV64IZFHMIN-NEXT: beqz a0, .LBB35_2
3899 ; RV64IZFHMIN-NEXT: # %bb.1:
3900 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
3901 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
3902 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
3903 ; RV64IZFHMIN-NEXT: .LBB35_2:
3904 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
3905 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
3906 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
3907 ; RV64IZFHMIN-NEXT: ret
3908 ;
3909 ; RV32IZHINXMIN-LABEL: test_roundeven_si64:
3910 ; RV32IZHINXMIN: # %bb.0:
3911 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3912 ; RV32IZHINXMIN-NEXT: lui a1, 307200
3913 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
3914 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
3915 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB35_2
3916 ; RV32IZHINXMIN-NEXT: # %bb.1:
3917 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3918 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3919 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3920 ; RV32IZHINXMIN-NEXT: .LBB35_2:
3921 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3922 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
3923 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3924 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
3925 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3926 ; RV32IZHINXMIN-NEXT: call __fixhfdi
3927 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3928 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3929 ; RV32IZHINXMIN-NEXT: ret
3930 ;
3931 ; RV64IZHINXMIN-LABEL: test_roundeven_si64:
3932 ; RV64IZHINXMIN: # %bb.0:
3933 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3934 ; RV64IZHINXMIN-NEXT: lui a1, 307200
3935 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
3936 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
3937 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB35_2
3938 ; RV64IZHINXMIN-NEXT: # %bb.1:
3939 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
3940 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
3941 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
3942 ; RV64IZHINXMIN-NEXT: .LBB35_2:
3943 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3944 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3945 ; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
3946 ; RV64IZHINXMIN-NEXT: ret
3947 %a = call half @llvm.roundeven.f16(half %x)
3948 %b = fptosi half %a to i64
3949 ret i64 %b
3950 }
3952 define zeroext i8 @test_roundeven_ui8(half %x) {
3953 ; RV32IZFH-LABEL: test_roundeven_ui8:
3954 ; RV32IZFH: # %bb.0:
3955 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
3956 ; RV32IZFH-NEXT: ret
3957 ;
3958 ; RV64IZFH-LABEL: test_roundeven_ui8:
3959 ; RV64IZFH: # %bb.0:
3960 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
3961 ; RV64IZFH-NEXT: ret
3962 ;
3963 ; RV32IZHINX-LABEL: test_roundeven_ui8:
3964 ; RV32IZHINX: # %bb.0:
3965 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI36_0)
3966 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI36_0)(a1)
3967 ; RV32IZHINX-NEXT: fabs.h a2, a0
3968 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
3969 ; RV32IZHINX-NEXT: beqz a1, .LBB36_2
3970 ; RV32IZHINX-NEXT: # %bb.1:
3971 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
3972 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
3973 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
3974 ; RV32IZHINX-NEXT: .LBB36_2:
3975 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
3976 ; RV32IZHINX-NEXT: ret
3977 ;
3978 ; RV64IZHINX-LABEL: test_roundeven_ui8:
3979 ; RV64IZHINX: # %bb.0:
3980 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI36_0)
3981 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI36_0)(a1)
3982 ; RV64IZHINX-NEXT: fabs.h a2, a0
3983 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
3984 ; RV64IZHINX-NEXT: beqz a1, .LBB36_2
3985 ; RV64IZHINX-NEXT: # %bb.1:
3986 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
3987 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
3988 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
3989 ; RV64IZHINX-NEXT: .LBB36_2:
3990 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
3991 ; RV64IZHINX-NEXT: ret
3992 ;
3993 ; RV32IZFHMIN-LABEL: test_roundeven_ui8:
3994 ; RV32IZFHMIN: # %bb.0:
3995 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
3996 ; RV32IZFHMIN-NEXT: lui a0, 307200
3997 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
3998 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
3999 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
4000 ; RV32IZFHMIN-NEXT: beqz a0, .LBB36_2
4001 ; RV32IZFHMIN-NEXT: # %bb.1:
4002 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4003 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4004 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4005 ; RV32IZFHMIN-NEXT: .LBB36_2:
4006 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4007 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4008 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
4009 ; RV32IZFHMIN-NEXT: ret
4010 ;
4011 ; RV64IZFHMIN-LABEL: test_roundeven_ui8:
4012 ; RV64IZFHMIN: # %bb.0:
4013 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4014 ; RV64IZFHMIN-NEXT: lui a0, 307200
4015 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4016 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4017 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4018 ; RV64IZFHMIN-NEXT: beqz a0, .LBB36_2
4019 ; RV64IZFHMIN-NEXT: # %bb.1:
4020 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4021 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4022 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4023 ; RV64IZFHMIN-NEXT: .LBB36_2:
4024 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4025 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4026 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
4027 ; RV64IZFHMIN-NEXT: ret
4028 ;
4029 ; RV32IZHINXMIN-LABEL: test_roundeven_ui8:
4030 ; RV32IZHINXMIN: # %bb.0:
4031 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4032 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4033 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4034 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4035 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB36_2
4036 ; RV32IZHINXMIN-NEXT: # %bb.1:
4037 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4038 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4039 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4040 ; RV32IZHINXMIN-NEXT: .LBB36_2:
4041 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4042 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4043 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
4044 ; RV32IZHINXMIN-NEXT: ret
4045 ;
4046 ; RV64IZHINXMIN-LABEL: test_roundeven_ui8:
4047 ; RV64IZHINXMIN: # %bb.0:
4048 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4049 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4050 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4051 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4052 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB36_2
4053 ; RV64IZHINXMIN-NEXT: # %bb.1:
4054 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4055 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4056 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4057 ; RV64IZHINXMIN-NEXT: .LBB36_2:
4058 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4059 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4060 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
4061 ; RV64IZHINXMIN-NEXT: ret
4062 %a = call half @llvm.roundeven.f16(half %x)
4063 %b = fptoui half %a to i8
4064 ret i8 %b
4065 }
4067 define zeroext i16 @test_roundeven_ui16(half %x) {
4068 ; RV32IZFH-LABEL: test_roundeven_ui16:
4069 ; RV32IZFH: # %bb.0:
4070 ; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
4071 ; RV32IZFH-NEXT: ret
4072 ;
4073 ; RV64IZFH-LABEL: test_roundeven_ui16:
4074 ; RV64IZFH: # %bb.0:
4075 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
4076 ; RV64IZFH-NEXT: ret
4077 ;
4078 ; RV32IZHINX-LABEL: test_roundeven_ui16:
4079 ; RV32IZHINX: # %bb.0:
4080 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI37_0)
4081 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI37_0)(a1)
4082 ; RV32IZHINX-NEXT: fabs.h a2, a0
4083 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
4084 ; RV32IZHINX-NEXT: beqz a1, .LBB37_2
4085 ; RV32IZHINX-NEXT: # %bb.1:
4086 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
4087 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
4088 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
4089 ; RV32IZHINX-NEXT: .LBB37_2:
4090 ; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
4091 ; RV32IZHINX-NEXT: ret
4092 ;
4093 ; RV64IZHINX-LABEL: test_roundeven_ui16:
4094 ; RV64IZHINX: # %bb.0:
4095 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI37_0)
4096 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI37_0)(a1)
4097 ; RV64IZHINX-NEXT: fabs.h a2, a0
4098 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
4099 ; RV64IZHINX-NEXT: beqz a1, .LBB37_2
4100 ; RV64IZHINX-NEXT: # %bb.1:
4101 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
4102 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
4103 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
4104 ; RV64IZHINX-NEXT: .LBB37_2:
4105 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
4106 ; RV64IZHINX-NEXT: ret
4107 ;
4108 ; RV32IZFHMIN-LABEL: test_roundeven_ui16:
4109 ; RV32IZFHMIN: # %bb.0:
4110 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4111 ; RV32IZFHMIN-NEXT: lui a0, 307200
4112 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
4113 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
4114 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
4115 ; RV32IZFHMIN-NEXT: beqz a0, .LBB37_2
4116 ; RV32IZFHMIN-NEXT: # %bb.1:
4117 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4118 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4119 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4120 ; RV32IZFHMIN-NEXT: .LBB37_2:
4121 ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4122 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4123 ; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
4124 ; RV32IZFHMIN-NEXT: ret
4125 ;
4126 ; RV64IZFHMIN-LABEL: test_roundeven_ui16:
4127 ; RV64IZFHMIN: # %bb.0:
4128 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4129 ; RV64IZFHMIN-NEXT: lui a0, 307200
4130 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4131 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4132 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4133 ; RV64IZFHMIN-NEXT: beqz a0, .LBB37_2
4134 ; RV64IZFHMIN-NEXT: # %bb.1:
4135 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4136 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4137 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4138 ; RV64IZFHMIN-NEXT: .LBB37_2:
4139 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4140 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4141 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
4142 ; RV64IZFHMIN-NEXT: ret
4143 ;
4144 ; RV32IZHINXMIN-LABEL: test_roundeven_ui16:
4145 ; RV32IZHINXMIN: # %bb.0:
4146 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4147 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4148 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4149 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4150 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB37_2
4151 ; RV32IZHINXMIN-NEXT: # %bb.1:
4152 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4153 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4154 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4155 ; RV32IZHINXMIN-NEXT: .LBB37_2:
4156 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4157 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4158 ; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
4159 ; RV32IZHINXMIN-NEXT: ret
4160 ;
4161 ; RV64IZHINXMIN-LABEL: test_roundeven_ui16:
4162 ; RV64IZHINXMIN: # %bb.0:
4163 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4164 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4165 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4166 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4167 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB37_2
4168 ; RV64IZHINXMIN-NEXT: # %bb.1:
4169 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4170 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4171 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4172 ; RV64IZHINXMIN-NEXT: .LBB37_2:
4173 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4174 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4175 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
4176 ; RV64IZHINXMIN-NEXT: ret
4177 %a = call half @llvm.roundeven.f16(half %x)
4178 %b = fptoui half %a to i16
4179 ret i16 %b
4180 }
4182 define signext i32 @test_roundeven_ui32(half %x) {
4183 ; CHECKIZFH-LABEL: test_roundeven_ui32:
4184 ; CHECKIZFH: # %bb.0:
4185 ; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rne
4186 ; CHECKIZFH-NEXT: ret
4187 ;
4188 ; CHECKIZHINX-LABEL: test_roundeven_ui32:
4189 ; CHECKIZHINX: # %bb.0:
4190 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI38_0)
4191 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI38_0)(a1)
4192 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4193 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4194 ; CHECKIZHINX-NEXT: beqz a1, .LBB38_2
4195 ; CHECKIZHINX-NEXT: # %bb.1:
4196 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
4197 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
4198 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4199 ; CHECKIZHINX-NEXT: .LBB38_2:
4200 ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
4201 ; CHECKIZHINX-NEXT: ret
4202 ;
4203 ; CHECKIZFHMIN-LABEL: test_roundeven_ui32:
4204 ; CHECKIZFHMIN: # %bb.0:
4205 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4206 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4207 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4208 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4209 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4210 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB38_2
4211 ; CHECKIZFHMIN-NEXT: # %bb.1:
4212 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4213 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4214 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4215 ; CHECKIZFHMIN-NEXT: .LBB38_2:
4216 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa5, fa5
4217 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa5
4218 ; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
4219 ; CHECKIZFHMIN-NEXT: ret
4220 ;
4221 ; CHECKIZHINXMIN-LABEL: test_roundeven_ui32:
4222 ; CHECKIZHINXMIN: # %bb.0:
4223 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4224 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4225 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4226 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4227 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB38_2
4228 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4229 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4230 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4231 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4232 ; CHECKIZHINXMIN-NEXT: .LBB38_2:
4233 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4234 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4235 ; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
4236 ; CHECKIZHINXMIN-NEXT: ret
4237 %a = call half @llvm.roundeven.f16(half %x)
4238 %b = fptoui half %a to i32
4239 ret i32 %b
4240 }
4242 define i64 @test_roundeven_ui64(half %x) {
4243 ; RV32IZFH-LABEL: test_roundeven_ui64:
4244 ; RV32IZFH: # %bb.0:
4245 ; RV32IZFH-NEXT: lui a0, %hi(.LCPI39_0)
4246 ; RV32IZFH-NEXT: flh fa5, %lo(.LCPI39_0)(a0)
4247 ; RV32IZFH-NEXT: fabs.h fa4, fa0
4248 ; RV32IZFH-NEXT: flt.h a0, fa4, fa5
4249 ; RV32IZFH-NEXT: beqz a0, .LBB39_2
4250 ; RV32IZFH-NEXT: # %bb.1:
4251 ; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
4252 ; RV32IZFH-NEXT: fcvt.h.w fa5, a0, rne
4253 ; RV32IZFH-NEXT: fsgnj.h fa0, fa5, fa0
4254 ; RV32IZFH-NEXT: .LBB39_2:
4255 ; RV32IZFH-NEXT: addi sp, sp, -16
4256 ; RV32IZFH-NEXT: .cfi_def_cfa_offset 16
4257 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4258 ; RV32IZFH-NEXT: .cfi_offset ra, -4
4259 ; RV32IZFH-NEXT: call __fixunshfdi
4260 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4261 ; RV32IZFH-NEXT: addi sp, sp, 16
4262 ; RV32IZFH-NEXT: ret
4263 ;
4264 ; RV64IZFH-LABEL: test_roundeven_ui64:
4265 ; RV64IZFH: # %bb.0:
4266 ; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
4267 ; RV64IZFH-NEXT: ret
4268 ;
4269 ; RV32IZHINX-LABEL: test_roundeven_ui64:
4270 ; RV32IZHINX: # %bb.0:
4271 ; RV32IZHINX-NEXT: lui a1, %hi(.LCPI39_0)
4272 ; RV32IZHINX-NEXT: lh a1, %lo(.LCPI39_0)(a1)
4273 ; RV32IZHINX-NEXT: fabs.h a2, a0
4274 ; RV32IZHINX-NEXT: flt.h a1, a2, a1
4275 ; RV32IZHINX-NEXT: beqz a1, .LBB39_2
4276 ; RV32IZHINX-NEXT: # %bb.1:
4277 ; RV32IZHINX-NEXT: fcvt.w.h a1, a0, rne
4278 ; RV32IZHINX-NEXT: fcvt.h.w a1, a1, rne
4279 ; RV32IZHINX-NEXT: fsgnj.h a0, a1, a0
4280 ; RV32IZHINX-NEXT: .LBB39_2:
4281 ; RV32IZHINX-NEXT: addi sp, sp, -16
4282 ; RV32IZHINX-NEXT: .cfi_def_cfa_offset 16
4283 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4284 ; RV32IZHINX-NEXT: .cfi_offset ra, -4
4285 ; RV32IZHINX-NEXT: call __fixunshfdi
4286 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4287 ; RV32IZHINX-NEXT: addi sp, sp, 16
4288 ; RV32IZHINX-NEXT: ret
4289 ;
4290 ; RV64IZHINX-LABEL: test_roundeven_ui64:
4291 ; RV64IZHINX: # %bb.0:
4292 ; RV64IZHINX-NEXT: lui a1, %hi(.LCPI39_0)
4293 ; RV64IZHINX-NEXT: lh a1, %lo(.LCPI39_0)(a1)
4294 ; RV64IZHINX-NEXT: fabs.h a2, a0
4295 ; RV64IZHINX-NEXT: flt.h a1, a2, a1
4296 ; RV64IZHINX-NEXT: beqz a1, .LBB39_2
4297 ; RV64IZHINX-NEXT: # %bb.1:
4298 ; RV64IZHINX-NEXT: fcvt.w.h a1, a0, rne
4299 ; RV64IZHINX-NEXT: fcvt.h.w a1, a1, rne
4300 ; RV64IZHINX-NEXT: fsgnj.h a0, a1, a0
4301 ; RV64IZHINX-NEXT: .LBB39_2:
4302 ; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
4303 ; RV64IZHINX-NEXT: ret
4304 ;
4305 ; RV32IZFHMIN-LABEL: test_roundeven_ui64:
4306 ; RV32IZFHMIN: # %bb.0:
4307 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4308 ; RV32IZFHMIN-NEXT: lui a0, 307200
4309 ; RV32IZFHMIN-NEXT: fmv.w.x fa4, a0
4310 ; RV32IZFHMIN-NEXT: fabs.s fa3, fa5
4311 ; RV32IZFHMIN-NEXT: flt.s a0, fa3, fa4
4312 ; RV32IZFHMIN-NEXT: beqz a0, .LBB39_2
4313 ; RV32IZFHMIN-NEXT: # %bb.1:
4314 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4315 ; RV32IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4316 ; RV32IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4317 ; RV32IZFHMIN-NEXT: .LBB39_2:
4318 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
4319 ; RV32IZFHMIN-NEXT: .cfi_def_cfa_offset 16
4320 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4321 ; RV32IZFHMIN-NEXT: .cfi_offset ra, -4
4322 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
4323 ; RV32IZFHMIN-NEXT: call __fixunshfdi
4324 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4325 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
4326 ; RV32IZFHMIN-NEXT: ret
4327 ;
4328 ; RV64IZFHMIN-LABEL: test_roundeven_ui64:
4329 ; RV64IZFHMIN: # %bb.0:
4330 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
4331 ; RV64IZFHMIN-NEXT: lui a0, 307200
4332 ; RV64IZFHMIN-NEXT: fmv.w.x fa4, a0
4333 ; RV64IZFHMIN-NEXT: fabs.s fa3, fa5
4334 ; RV64IZFHMIN-NEXT: flt.s a0, fa3, fa4
4335 ; RV64IZFHMIN-NEXT: beqz a0, .LBB39_2
4336 ; RV64IZFHMIN-NEXT: # %bb.1:
4337 ; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4338 ; RV64IZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4339 ; RV64IZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4340 ; RV64IZFHMIN-NEXT: .LBB39_2:
4341 ; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
4342 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
4343 ; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
4344 ; RV64IZFHMIN-NEXT: ret
4345 ;
4346 ; RV32IZHINXMIN-LABEL: test_roundeven_ui64:
4347 ; RV32IZHINXMIN: # %bb.0:
4348 ; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
4349 ; RV32IZHINXMIN-NEXT: lui a1, 307200
4350 ; RV32IZHINXMIN-NEXT: fabs.s a2, a0
4351 ; RV32IZHINXMIN-NEXT: flt.s a1, a2, a1
4352 ; RV32IZHINXMIN-NEXT: beqz a1, .LBB39_2
4353 ; RV32IZHINXMIN-NEXT: # %bb.1:
4354 ; RV32IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4355 ; RV32IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4356 ; RV32IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4357 ; RV32IZHINXMIN-NEXT: .LBB39_2:
4358 ; RV32IZHINXMIN-NEXT: addi sp, sp, -16
4359 ; RV32IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
4360 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4361 ; RV32IZHINXMIN-NEXT: .cfi_offset ra, -4
4362 ; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
4363 ; RV32IZHINXMIN-NEXT: call __fixunshfdi
4364 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4365 ; RV32IZHINXMIN-NEXT: addi sp, sp, 16
4366 ; RV32IZHINXMIN-NEXT: ret
4367 ;
4368 ; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
4369 ; RV64IZHINXMIN: # %bb.0:
4370 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4371 ; RV64IZHINXMIN-NEXT: lui a1, 307200
4372 ; RV64IZHINXMIN-NEXT: fabs.s a2, a0
4373 ; RV64IZHINXMIN-NEXT: flt.s a1, a2, a1
4374 ; RV64IZHINXMIN-NEXT: beqz a1, .LBB39_2
4375 ; RV64IZHINXMIN-NEXT: # %bb.1:
4376 ; RV64IZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4377 ; RV64IZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4378 ; RV64IZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4379 ; RV64IZHINXMIN-NEXT: .LBB39_2:
4380 ; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
4381 ; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
4382 ; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
4383 ; RV64IZHINXMIN-NEXT: ret
4384 %a = call half @llvm.roundeven.f16(half %x)
4385 %b = fptoui half %a to i64
4386 ret i64 %b
4387 }
4389 define half @test_floor_half(half %x) {
4390 ; RV32IFD-LABEL: test_floor_half:
4391 ; RV32IFD: # %bb.0:
4392 ; RV32IFD-NEXT: addi sp, sp, -16
4393 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4394 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4395 ; RV32IFD-NEXT: .cfi_offset ra, -4
4396 ; RV32IFD-NEXT: call floor@plt
4397 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4398 ; RV32IFD-NEXT: addi sp, sp, 16
4399 ; RV32IFD-NEXT: ret
4400 ;
4401 ; RV64IFD-LABEL: test_floor_half:
4402 ; RV64IFD: # %bb.0:
4403 ; RV64IFD-NEXT: addi sp, sp, -16
4404 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4405 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4406 ; RV64IFD-NEXT: .cfi_offset ra, -8
4407 ; RV64IFD-NEXT: call floor@plt
4408 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4409 ; RV64IFD-NEXT: addi sp, sp, 16
4410 ; RV64IFD-NEXT: ret
4411 ; CHECKIZFH-LABEL: test_floor_half:
4412 ; CHECKIZFH: # %bb.0:
4413 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI40_0)
4414 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI40_0)(a0)
4415 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4416 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4417 ; CHECKIZFH-NEXT: beqz a0, .LBB40_2
4418 ; CHECKIZFH-NEXT: # %bb.1:
4419 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
4420 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rdn
4421 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4422 ; CHECKIZFH-NEXT: .LBB40_2:
4423 ; CHECKIZFH-NEXT: ret
4424 ;
4425 ; CHECKIZHINX-LABEL: test_floor_half:
4426 ; CHECKIZHINX: # %bb.0:
4427 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI40_0)
4428 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI40_0)(a1)
4429 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4430 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4431 ; CHECKIZHINX-NEXT: beqz a1, .LBB40_2
4432 ; CHECKIZHINX-NEXT: # %bb.1:
4433 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rdn
4434 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rdn
4435 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4436 ; CHECKIZHINX-NEXT: .LBB40_2:
4437 ; CHECKIZHINX-NEXT: ret
4438 ;
4439 ; CHECKIZFHMIN-LABEL: test_floor_half:
4440 ; CHECKIZFHMIN: # %bb.0:
4441 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4442 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4443 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4444 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4445 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4446 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB40_2
4447 ; CHECKIZFHMIN-NEXT: # %bb.1:
4448 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rdn
4449 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rdn
4450 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4451 ; CHECKIZFHMIN-NEXT: .LBB40_2:
4452 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4453 ; CHECKIZFHMIN-NEXT: ret
4454 ;
4455 ; CHECKIZHINXMIN-LABEL: test_floor_half:
4456 ; CHECKIZHINXMIN: # %bb.0:
4457 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4458 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4459 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4460 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4461 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB40_2
4462 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4463 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rdn
4464 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rdn
4465 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4466 ; CHECKIZHINXMIN-NEXT: .LBB40_2:
4467 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4468 ; CHECKIZHINXMIN-NEXT: ret
4469 %a = call half @llvm.floor.f16(half %x)
4470 ret half %a
4471 }
4473 define half @test_ceil_half(half %x) {
4474 ; RV32IFD-LABEL: test_ceil_half:
4475 ; RV32IFD: # %bb.0:
4476 ; RV32IFD-NEXT: addi sp, sp, -16
4477 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4478 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4479 ; RV32IFD-NEXT: .cfi_offset ra, -4
4480 ; RV32IFD-NEXT: call ceil@plt
4481 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4482 ; RV32IFD-NEXT: addi sp, sp, 16
4483 ; RV32IFD-NEXT: ret
4484 ;
4485 ; RV64IFD-LABEL: test_ceil_half:
4486 ; RV64IFD: # %bb.0:
4487 ; RV64IFD-NEXT: addi sp, sp, -16
4488 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4489 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4490 ; RV64IFD-NEXT: .cfi_offset ra, -8
4491 ; RV64IFD-NEXT: call ceil@plt
4492 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4493 ; RV64IFD-NEXT: addi sp, sp, 16
4494 ; RV64IFD-NEXT: ret
4495 ; CHECKIZFH-LABEL: test_ceil_half:
4496 ; CHECKIZFH: # %bb.0:
4497 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI41_0)
4498 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI41_0)(a0)
4499 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4500 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4501 ; CHECKIZFH-NEXT: beqz a0, .LBB41_2
4502 ; CHECKIZFH-NEXT: # %bb.1:
4503 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
4504 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rup
4505 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4506 ; CHECKIZFH-NEXT: .LBB41_2:
4507 ; CHECKIZFH-NEXT: ret
4508 ;
4509 ; CHECKIZHINX-LABEL: test_ceil_half:
4510 ; CHECKIZHINX: # %bb.0:
4511 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI41_0)
4512 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI41_0)(a1)
4513 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4514 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4515 ; CHECKIZHINX-NEXT: beqz a1, .LBB41_2
4516 ; CHECKIZHINX-NEXT: # %bb.1:
4517 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rup
4518 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rup
4519 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4520 ; CHECKIZHINX-NEXT: .LBB41_2:
4521 ; CHECKIZHINX-NEXT: ret
4522 ;
4523 ; CHECKIZFHMIN-LABEL: test_ceil_half:
4524 ; CHECKIZFHMIN: # %bb.0:
4525 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4526 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4527 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4528 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4529 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4530 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB41_2
4531 ; CHECKIZFHMIN-NEXT: # %bb.1:
4532 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rup
4533 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rup
4534 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4535 ; CHECKIZFHMIN-NEXT: .LBB41_2:
4536 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4537 ; CHECKIZFHMIN-NEXT: ret
4538 ;
4539 ; CHECKIZHINXMIN-LABEL: test_ceil_half:
4540 ; CHECKIZHINXMIN: # %bb.0:
4541 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4542 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4543 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4544 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4545 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB41_2
4546 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4547 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rup
4548 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rup
4549 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4550 ; CHECKIZHINXMIN-NEXT: .LBB41_2:
4551 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4552 ; CHECKIZHINXMIN-NEXT: ret
4553 %a = call half @llvm.ceil.f16(half %x)
4554 ret half %a
4555 }
4557 define half @test_trunc_half(half %x) {
4558 ; RV32IFD-LABEL: test_trunc_half:
4559 ; RV32IFD: # %bb.0:
4560 ; RV32IFD-NEXT: addi sp, sp, -16
4561 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4562 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4563 ; RV32IFD-NEXT: .cfi_offset ra, -4
4564 ; RV32IFD-NEXT: call trunc@plt
4565 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4566 ; RV32IFD-NEXT: addi sp, sp, 16
4567 ; RV32IFD-NEXT: ret
4568 ;
4569 ; RV64IFD-LABEL: test_trunc_half:
4570 ; RV64IFD: # %bb.0:
4571 ; RV64IFD-NEXT: addi sp, sp, -16
4572 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4573 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4574 ; RV64IFD-NEXT: .cfi_offset ra, -8
4575 ; RV64IFD-NEXT: call trunc@plt
4576 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4577 ; RV64IFD-NEXT: addi sp, sp, 16
4578 ; RV64IFD-NEXT: ret
4579 ; CHECKIZFH-LABEL: test_trunc_half:
4580 ; CHECKIZFH: # %bb.0:
4581 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI42_0)
4582 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI42_0)(a0)
4583 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4584 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4585 ; CHECKIZFH-NEXT: beqz a0, .LBB42_2
4586 ; CHECKIZFH-NEXT: # %bb.1:
4587 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
4588 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rtz
4589 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4590 ; CHECKIZFH-NEXT: .LBB42_2:
4591 ; CHECKIZFH-NEXT: ret
4592 ;
4593 ; CHECKIZHINX-LABEL: test_trunc_half:
4594 ; CHECKIZHINX: # %bb.0:
4595 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI42_0)
4596 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI42_0)(a1)
4597 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4598 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4599 ; CHECKIZHINX-NEXT: beqz a1, .LBB42_2
4600 ; CHECKIZHINX-NEXT: # %bb.1:
4601 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
4602 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rtz
4603 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4604 ; CHECKIZHINX-NEXT: .LBB42_2:
4605 ; CHECKIZHINX-NEXT: ret
4606 ;
4607 ; CHECKIZFHMIN-LABEL: test_trunc_half:
4608 ; CHECKIZFHMIN: # %bb.0:
4609 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4610 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4611 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4612 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4613 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4614 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB42_2
4615 ; CHECKIZFHMIN-NEXT: # %bb.1:
4616 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
4617 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rtz
4618 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4619 ; CHECKIZFHMIN-NEXT: .LBB42_2:
4620 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4621 ; CHECKIZFHMIN-NEXT: ret
4622 ;
4623 ; CHECKIZHINXMIN-LABEL: test_trunc_half:
4624 ; CHECKIZHINXMIN: # %bb.0:
4625 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4626 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4627 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4628 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4629 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB42_2
4630 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4631 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
4632 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rtz
4633 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4634 ; CHECKIZHINXMIN-NEXT: .LBB42_2:
4635 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4636 ; CHECKIZHINXMIN-NEXT: ret
4637 %a = call half @llvm.trunc.f16(half %x)
4638 ret half %a
4639 }
4641 define half @test_round_half(half %x) {
4642 ; RV32IFD-LABEL: test_round_half:
4643 ; RV32IFD: # %bb.0:
4644 ; RV32IFD-NEXT: addi sp, sp, -16
4645 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4646 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4647 ; RV32IFD-NEXT: .cfi_offset ra, -4
4648 ; RV32IFD-NEXT: call round@plt
4649 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4650 ; RV32IFD-NEXT: addi sp, sp, 16
4651 ; RV32IFD-NEXT: ret
4652 ;
4653 ; RV64IFD-LABEL: test_round_half:
4654 ; RV64IFD: # %bb.0:
4655 ; RV64IFD-NEXT: addi sp, sp, -16
4656 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4657 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4658 ; RV64IFD-NEXT: .cfi_offset ra, -8
4659 ; RV64IFD-NEXT: call round@plt
4660 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4661 ; RV64IFD-NEXT: addi sp, sp, 16
4662 ; RV64IFD-NEXT: ret
4663 ; CHECKIZFH-LABEL: test_round_half:
4664 ; CHECKIZFH: # %bb.0:
4665 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI43_0)
4666 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI43_0)(a0)
4667 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4668 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4669 ; CHECKIZFH-NEXT: beqz a0, .LBB43_2
4670 ; CHECKIZFH-NEXT: # %bb.1:
4671 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
4672 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rmm
4673 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4674 ; CHECKIZFH-NEXT: .LBB43_2:
4675 ; CHECKIZFH-NEXT: ret
4676 ;
4677 ; CHECKIZHINX-LABEL: test_round_half:
4678 ; CHECKIZHINX: # %bb.0:
4679 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI43_0)
4680 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI43_0)(a1)
4681 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4682 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4683 ; CHECKIZHINX-NEXT: beqz a1, .LBB43_2
4684 ; CHECKIZHINX-NEXT: # %bb.1:
4685 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rmm
4686 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rmm
4687 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4688 ; CHECKIZHINX-NEXT: .LBB43_2:
4689 ; CHECKIZHINX-NEXT: ret
4690 ;
4691 ; CHECKIZFHMIN-LABEL: test_round_half:
4692 ; CHECKIZFHMIN: # %bb.0:
4693 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4694 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4695 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4696 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4697 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4698 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB43_2
4699 ; CHECKIZFHMIN-NEXT: # %bb.1:
4700 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
4701 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rmm
4702 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4703 ; CHECKIZFHMIN-NEXT: .LBB43_2:
4704 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4705 ; CHECKIZFHMIN-NEXT: ret
4706 ;
4707 ; CHECKIZHINXMIN-LABEL: test_round_half:
4708 ; CHECKIZHINXMIN: # %bb.0:
4709 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4710 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4711 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4712 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4713 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB43_2
4714 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4715 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rmm
4716 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rmm
4717 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4718 ; CHECKIZHINXMIN-NEXT: .LBB43_2:
4719 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4720 ; CHECKIZHINXMIN-NEXT: ret
4721 %a = call half @llvm.round.f16(half %x)
4722 ret half %a
4723 }
4725 define half @test_roundeven_half(half %x) {
4726 ; RV32IFD-LABEL: test_roundeven_half:
4727 ; RV32IFD: # %bb.0:
4728 ; RV32IFD-NEXT: addi sp, sp, -16
4729 ; RV32IFD-NEXT: .cfi_def_cfa_offset 16
4730 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
4731 ; RV32IFD-NEXT: .cfi_offset ra, -4
4732 ; RV32IFD-NEXT: call roundeven@plt
4733 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
4734 ; RV32IFD-NEXT: addi sp, sp, 16
4735 ; RV32IFD-NEXT: ret
4736 ;
4737 ; RV64IFD-LABEL: test_roundeven_half:
4738 ; RV64IFD: # %bb.0:
4739 ; RV64IFD-NEXT: addi sp, sp, -16
4740 ; RV64IFD-NEXT: .cfi_def_cfa_offset 16
4741 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
4742 ; RV64IFD-NEXT: .cfi_offset ra, -8
4743 ; RV64IFD-NEXT: call roundeven@plt
4744 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4745 ; RV64IFD-NEXT: addi sp, sp, 16
4746 ; RV64IFD-NEXT: ret
4747 ; CHECKIZFH-LABEL: test_roundeven_half:
4748 ; CHECKIZFH: # %bb.0:
4749 ; CHECKIZFH-NEXT: lui a0, %hi(.LCPI44_0)
4750 ; CHECKIZFH-NEXT: flh fa5, %lo(.LCPI44_0)(a0)
4751 ; CHECKIZFH-NEXT: fabs.h fa4, fa0
4752 ; CHECKIZFH-NEXT: flt.h a0, fa4, fa5
4753 ; CHECKIZFH-NEXT: beqz a0, .LBB44_2
4754 ; CHECKIZFH-NEXT: # %bb.1:
4755 ; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
4756 ; CHECKIZFH-NEXT: fcvt.h.w fa5, a0, rne
4757 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa5, fa0
4758 ; CHECKIZFH-NEXT: .LBB44_2:
4759 ; CHECKIZFH-NEXT: ret
4760 ;
4761 ; CHECKIZHINX-LABEL: test_roundeven_half:
4762 ; CHECKIZHINX: # %bb.0:
4763 ; CHECKIZHINX-NEXT: lui a1, %hi(.LCPI44_0)
4764 ; CHECKIZHINX-NEXT: lh a1, %lo(.LCPI44_0)(a1)
4765 ; CHECKIZHINX-NEXT: fabs.h a2, a0
4766 ; CHECKIZHINX-NEXT: flt.h a1, a2, a1
4767 ; CHECKIZHINX-NEXT: beqz a1, .LBB44_2
4768 ; CHECKIZHINX-NEXT: # %bb.1:
4769 ; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rne
4770 ; CHECKIZHINX-NEXT: fcvt.h.w a1, a1, rne
4771 ; CHECKIZHINX-NEXT: fsgnj.h a0, a1, a0
4772 ; CHECKIZHINX-NEXT: .LBB44_2:
4773 ; CHECKIZHINX-NEXT: ret
4774 ;
4775 ; CHECKIZFHMIN-LABEL: test_roundeven_half:
4776 ; CHECKIZFHMIN: # %bb.0:
4777 ; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
4778 ; CHECKIZFHMIN-NEXT: lui a0, 307200
4779 ; CHECKIZFHMIN-NEXT: fmv.w.x fa4, a0
4780 ; CHECKIZFHMIN-NEXT: fabs.s fa3, fa5
4781 ; CHECKIZFHMIN-NEXT: flt.s a0, fa3, fa4
4782 ; CHECKIZFHMIN-NEXT: beqz a0, .LBB44_2
4783 ; CHECKIZFHMIN-NEXT: # %bb.1:
4784 ; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rne
4785 ; CHECKIZFHMIN-NEXT: fcvt.s.w fa4, a0, rne
4786 ; CHECKIZFHMIN-NEXT: fsgnj.s fa5, fa4, fa5
4787 ; CHECKIZFHMIN-NEXT: .LBB44_2:
4788 ; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
4789 ; CHECKIZFHMIN-NEXT: ret
4790 ;
4791 ; CHECKIZHINXMIN-LABEL: test_roundeven_half:
4792 ; CHECKIZHINXMIN: # %bb.0:
4793 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
4794 ; CHECKIZHINXMIN-NEXT: lui a1, 307200
4795 ; CHECKIZHINXMIN-NEXT: fabs.s a2, a0
4796 ; CHECKIZHINXMIN-NEXT: flt.s a1, a2, a1
4797 ; CHECKIZHINXMIN-NEXT: beqz a1, .LBB44_2
4798 ; CHECKIZHINXMIN-NEXT: # %bb.1:
4799 ; CHECKIZHINXMIN-NEXT: fcvt.w.s a1, a0, rne
4800 ; CHECKIZHINXMIN-NEXT: fcvt.s.w a1, a1, rne
4801 ; CHECKIZHINXMIN-NEXT: fsgnj.s a0, a1, a0
4802 ; CHECKIZHINXMIN-NEXT: .LBB44_2:
4803 ; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
4804 ; CHECKIZHINXMIN-NEXT: ret
4805 %a = call half @llvm.roundeven.f16(half %x)
4806 ret half %a
4807 }
4809 declare half @llvm.floor.f16(half)
4810 declare half @llvm.ceil.f16(half)
4811 declare half @llvm.trunc.f16(half)
4812 declare half @llvm.round.f16(half)
4813 declare half @llvm.roundeven.f16(half)