| blob | 14f2777fdd06d2cbfd81d516224f7fa479800256 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV32I %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefix=RV32IM %s
6 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7 ; RUN: | FileCheck -check-prefix=RV64I %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
9 ; RUN: | FileCheck -check-prefix=RV64IM %s
11 define signext i32 @square(i32 %a) nounwind {
12 ; RV32I-LABEL: square:
13 ; RV32I: # %bb.0:
14 ; RV32I-NEXT: addi sp, sp, -16
15 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
16 ; RV32I-NEXT: mv a1, a0
17 ; RV32I-NEXT: call __mulsi3
18 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
19 ; RV32I-NEXT: addi sp, sp, 16
20 ; RV32I-NEXT: ret
21 ;
22 ; RV32IM-LABEL: square:
23 ; RV32IM: # %bb.0:
24 ; RV32IM-NEXT: mul a0, a0, a0
25 ; RV32IM-NEXT: ret
26 ;
27 ; RV64I-LABEL: square:
28 ; RV64I: # %bb.0:
29 ; RV64I-NEXT: addi sp, sp, -16
30 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
31 ; RV64I-NEXT: mv a1, a0
32 ; RV64I-NEXT: call __muldi3
33 ; RV64I-NEXT: sext.w a0, a0
34 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
35 ; RV64I-NEXT: addi sp, sp, 16
36 ; RV64I-NEXT: ret
37 ;
38 ; RV64IM-LABEL: square:
39 ; RV64IM: # %bb.0:
40 ; RV64IM-NEXT: mulw a0, a0, a0
41 ; RV64IM-NEXT: ret
42 %1 = mul i32 %a, %a
43 ret i32 %1
44 }
46 define signext i32 @mul(i32 %a, i32 %b) nounwind {
47 ; RV32I-LABEL: mul:
48 ; RV32I: # %bb.0:
49 ; RV32I-NEXT: addi sp, sp, -16
50 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
51 ; RV32I-NEXT: call __mulsi3
52 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
53 ; RV32I-NEXT: addi sp, sp, 16
54 ; RV32I-NEXT: ret
55 ;
56 ; RV32IM-LABEL: mul:
57 ; RV32IM: # %bb.0:
58 ; RV32IM-NEXT: mul a0, a0, a1
59 ; RV32IM-NEXT: ret
60 ;
61 ; RV64I-LABEL: mul:
62 ; RV64I: # %bb.0:
63 ; RV64I-NEXT: addi sp, sp, -16
64 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
65 ; RV64I-NEXT: call __muldi3
66 ; RV64I-NEXT: sext.w a0, a0
67 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
68 ; RV64I-NEXT: addi sp, sp, 16
69 ; RV64I-NEXT: ret
70 ;
71 ; RV64IM-LABEL: mul:
72 ; RV64IM: # %bb.0:
73 ; RV64IM-NEXT: mulw a0, a0, a1
74 ; RV64IM-NEXT: ret
75 %1 = mul i32 %a, %b
76 ret i32 %1
77 }
79 define signext i32 @mul_constant(i32 %a) nounwind {
80 ; RV32I-LABEL: mul_constant:
81 ; RV32I: # %bb.0:
82 ; RV32I-NEXT: slli a1, a0, 2
83 ; RV32I-NEXT: add a0, a1, a0
84 ; RV32I-NEXT: ret
85 ;
86 ; RV32IM-LABEL: mul_constant:
87 ; RV32IM: # %bb.0:
88 ; RV32IM-NEXT: slli a1, a0, 2
89 ; RV32IM-NEXT: add a0, a1, a0
90 ; RV32IM-NEXT: ret
91 ;
92 ; RV64I-LABEL: mul_constant:
93 ; RV64I: # %bb.0:
94 ; RV64I-NEXT: slli a1, a0, 2
95 ; RV64I-NEXT: addw a0, a1, a0
96 ; RV64I-NEXT: ret
97 ;
98 ; RV64IM-LABEL: mul_constant:
99 ; RV64IM: # %bb.0:
100 ; RV64IM-NEXT: slli a1, a0, 2
101 ; RV64IM-NEXT: addw a0, a1, a0
102 ; RV64IM-NEXT: ret
103 %1 = mul i32 %a, 5
104 ret i32 %1
105 }
107 define i32 @mul_pow2(i32 %a) nounwind {
108 ; RV32I-LABEL: mul_pow2:
109 ; RV32I: # %bb.0:
110 ; RV32I-NEXT: slli a0, a0, 3
111 ; RV32I-NEXT: ret
112 ;
113 ; RV32IM-LABEL: mul_pow2:
114 ; RV32IM: # %bb.0:
115 ; RV32IM-NEXT: slli a0, a0, 3
116 ; RV32IM-NEXT: ret
117 ;
118 ; RV64I-LABEL: mul_pow2:
119 ; RV64I: # %bb.0:
120 ; RV64I-NEXT: slliw a0, a0, 3
121 ; RV64I-NEXT: ret
122 ;
123 ; RV64IM-LABEL: mul_pow2:
124 ; RV64IM: # %bb.0:
125 ; RV64IM-NEXT: slliw a0, a0, 3
126 ; RV64IM-NEXT: ret
127 %1 = mul i32 %a, 8
128 ret i32 %1
129 }
131 define i64 @mul64(i64 %a, i64 %b) nounwind {
132 ; RV32I-LABEL: mul64:
133 ; RV32I: # %bb.0:
134 ; RV32I-NEXT: addi sp, sp, -16
135 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
136 ; RV32I-NEXT: call __muldi3
137 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
138 ; RV32I-NEXT: addi sp, sp, 16
139 ; RV32I-NEXT: ret
140 ;
141 ; RV32IM-LABEL: mul64:
142 ; RV32IM: # %bb.0:
143 ; RV32IM-NEXT: mul a3, a0, a3
144 ; RV32IM-NEXT: mulhu a4, a0, a2
145 ; RV32IM-NEXT: add a3, a4, a3
146 ; RV32IM-NEXT: mul a1, a1, a2
147 ; RV32IM-NEXT: add a1, a3, a1
148 ; RV32IM-NEXT: mul a0, a0, a2
149 ; RV32IM-NEXT: ret
150 ;
151 ; RV64I-LABEL: mul64:
152 ; RV64I: # %bb.0:
153 ; RV64I-NEXT: tail __muldi3
154 ;
155 ; RV64IM-LABEL: mul64:
156 ; RV64IM: # %bb.0:
157 ; RV64IM-NEXT: mul a0, a0, a1
158 ; RV64IM-NEXT: ret
159 %1 = mul i64 %a, %b
160 ret i64 %1
161 }
163 define i64 @mul64_constant(i64 %a) nounwind {
164 ; RV32I-LABEL: mul64_constant:
165 ; RV32I: # %bb.0:
166 ; RV32I-NEXT: slli a3, a0, 2
167 ; RV32I-NEXT: add a2, a3, a0
168 ; RV32I-NEXT: sltu a3, a2, a3
169 ; RV32I-NEXT: srli a0, a0, 30
170 ; RV32I-NEXT: slli a4, a1, 2
171 ; RV32I-NEXT: or a0, a4, a0
172 ; RV32I-NEXT: add a0, a0, a1
173 ; RV32I-NEXT: add a1, a0, a3
174 ; RV32I-NEXT: mv a0, a2
175 ; RV32I-NEXT: ret
176 ;
177 ; RV32IM-LABEL: mul64_constant:
178 ; RV32IM: # %bb.0:
179 ; RV32IM-NEXT: li a2, 5
180 ; RV32IM-NEXT: mulhu a2, a0, a2
181 ; RV32IM-NEXT: slli a3, a1, 2
182 ; RV32IM-NEXT: add a1, a3, a1
183 ; RV32IM-NEXT: add a1, a2, a1
184 ; RV32IM-NEXT: slli a2, a0, 2
185 ; RV32IM-NEXT: add a0, a2, a0
186 ; RV32IM-NEXT: ret
187 ;
188 ; RV64I-LABEL: mul64_constant:
189 ; RV64I: # %bb.0:
190 ; RV64I-NEXT: slli a1, a0, 2
191 ; RV64I-NEXT: add a0, a1, a0
192 ; RV64I-NEXT: ret
193 ;
194 ; RV64IM-LABEL: mul64_constant:
195 ; RV64IM: # %bb.0:
196 ; RV64IM-NEXT: slli a1, a0, 2
197 ; RV64IM-NEXT: add a0, a1, a0
198 ; RV64IM-NEXT: ret
199 %1 = mul i64 %a, 5
200 ret i64 %1
201 }
203 define i32 @mulhs(i32 %a, i32 %b) nounwind {
204 ; RV32I-LABEL: mulhs:
205 ; RV32I: # %bb.0:
206 ; RV32I-NEXT: addi sp, sp, -16
207 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
208 ; RV32I-NEXT: mv a2, a1
209 ; RV32I-NEXT: srai a1, a0, 31
210 ; RV32I-NEXT: srai a3, a2, 31
211 ; RV32I-NEXT: call __muldi3
212 ; RV32I-NEXT: mv a0, a1
213 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
214 ; RV32I-NEXT: addi sp, sp, 16
215 ; RV32I-NEXT: ret
216 ;
217 ; RV32IM-LABEL: mulhs:
218 ; RV32IM: # %bb.0:
219 ; RV32IM-NEXT: mulh a0, a0, a1
220 ; RV32IM-NEXT: ret
221 ;
222 ; RV64I-LABEL: mulhs:
223 ; RV64I: # %bb.0:
224 ; RV64I-NEXT: addi sp, sp, -16
225 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
226 ; RV64I-NEXT: sext.w a0, a0
227 ; RV64I-NEXT: sext.w a1, a1
228 ; RV64I-NEXT: call __muldi3
229 ; RV64I-NEXT: srli a0, a0, 32
230 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
231 ; RV64I-NEXT: addi sp, sp, 16
232 ; RV64I-NEXT: ret
233 ;
234 ; RV64IM-LABEL: mulhs:
235 ; RV64IM: # %bb.0:
236 ; RV64IM-NEXT: sext.w a0, a0
237 ; RV64IM-NEXT: sext.w a1, a1
238 ; RV64IM-NEXT: mul a0, a0, a1
239 ; RV64IM-NEXT: srli a0, a0, 32
240 ; RV64IM-NEXT: ret
241 %1 = sext i32 %a to i64
242 %2 = sext i32 %b to i64
243 %3 = mul i64 %1, %2
244 %4 = lshr i64 %3, 32
245 %5 = trunc i64 %4 to i32
246 ret i32 %5
247 }
249 define i32 @mulhs_positive_constant(i32 %a) nounwind {
250 ; RV32I-LABEL: mulhs_positive_constant:
251 ; RV32I: # %bb.0:
252 ; RV32I-NEXT: srai a1, a0, 31
253 ; RV32I-NEXT: slli a2, a0, 2
254 ; RV32I-NEXT: add a3, a2, a0
255 ; RV32I-NEXT: sltu a2, a3, a2
256 ; RV32I-NEXT: srli a0, a0, 30
257 ; RV32I-NEXT: slli a3, a1, 2
258 ; RV32I-NEXT: or a0, a3, a0
259 ; RV32I-NEXT: add a0, a0, a1
260 ; RV32I-NEXT: add a0, a0, a2
261 ; RV32I-NEXT: ret
262 ;
263 ; RV32IM-LABEL: mulhs_positive_constant:
264 ; RV32IM: # %bb.0:
265 ; RV32IM-NEXT: li a1, 5
266 ; RV32IM-NEXT: mulh a0, a0, a1
267 ; RV32IM-NEXT: ret
268 ;
269 ; RV64I-LABEL: mulhs_positive_constant:
270 ; RV64I: # %bb.0:
271 ; RV64I-NEXT: sext.w a0, a0
272 ; RV64I-NEXT: slli a1, a0, 2
273 ; RV64I-NEXT: add a0, a1, a0
274 ; RV64I-NEXT: srli a0, a0, 32
275 ; RV64I-NEXT: ret
276 ;
277 ; RV64IM-LABEL: mulhs_positive_constant:
278 ; RV64IM: # %bb.0:
279 ; RV64IM-NEXT: sext.w a0, a0
280 ; RV64IM-NEXT: slli a1, a0, 2
281 ; RV64IM-NEXT: add a0, a1, a0
282 ; RV64IM-NEXT: srli a0, a0, 32
283 ; RV64IM-NEXT: ret
284 %1 = sext i32 %a to i64
285 %2 = mul i64 %1, 5
286 %3 = lshr i64 %2, 32
287 %4 = trunc i64 %3 to i32
288 ret i32 %4
289 }
291 define i32 @mulhs_negative_constant(i32 %a) nounwind {
292 ; RV32I-LABEL: mulhs_negative_constant:
293 ; RV32I: # %bb.0:
294 ; RV32I-NEXT: srai a1, a0, 31
295 ; RV32I-NEXT: slli a2, a0, 2
296 ; RV32I-NEXT: add a3, a2, a0
297 ; RV32I-NEXT: sltu a2, a3, a2
298 ; RV32I-NEXT: srli a0, a0, 30
299 ; RV32I-NEXT: slli a4, a1, 2
300 ; RV32I-NEXT: or a0, a4, a0
301 ; RV32I-NEXT: add a0, a0, a1
302 ; RV32I-NEXT: snez a1, a3
303 ; RV32I-NEXT: add a1, a2, a1
304 ; RV32I-NEXT: add a0, a0, a1
305 ; RV32I-NEXT: neg a0, a0
306 ; RV32I-NEXT: ret
307 ;
308 ; RV32IM-LABEL: mulhs_negative_constant:
309 ; RV32IM: # %bb.0:
310 ; RV32IM-NEXT: li a1, -5
311 ; RV32IM-NEXT: mulh a0, a0, a1
312 ; RV32IM-NEXT: ret
313 ;
314 ; RV64I-LABEL: mulhs_negative_constant:
315 ; RV64I: # %bb.0:
316 ; RV64I-NEXT: sext.w a0, a0
317 ; RV64I-NEXT: slli a1, a0, 2
318 ; RV64I-NEXT: neg a0, a0
319 ; RV64I-NEXT: sub a0, a0, a1
320 ; RV64I-NEXT: srli a0, a0, 32
321 ; RV64I-NEXT: ret
322 ;
323 ; RV64IM-LABEL: mulhs_negative_constant:
324 ; RV64IM: # %bb.0:
325 ; RV64IM-NEXT: sext.w a0, a0
326 ; RV64IM-NEXT: slli a1, a0, 2
327 ; RV64IM-NEXT: neg a0, a0
328 ; RV64IM-NEXT: sub a0, a0, a1
329 ; RV64IM-NEXT: srli a0, a0, 32
330 ; RV64IM-NEXT: ret
331 %1 = sext i32 %a to i64
332 %2 = mul i64 %1, -5
333 %3 = lshr i64 %2, 32
334 %4 = trunc i64 %3 to i32
335 ret i32 %4
336 }
338 define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {
339 ; RV32I-LABEL: mulhu:
340 ; RV32I: # %bb.0:
341 ; RV32I-NEXT: addi sp, sp, -16
342 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
343 ; RV32I-NEXT: mv a2, a1
344 ; RV32I-NEXT: li a1, 0
345 ; RV32I-NEXT: li a3, 0
346 ; RV32I-NEXT: call __muldi3
347 ; RV32I-NEXT: mv a0, a1
348 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
349 ; RV32I-NEXT: addi sp, sp, 16
350 ; RV32I-NEXT: ret
351 ;
352 ; RV32IM-LABEL: mulhu:
353 ; RV32IM: # %bb.0:
354 ; RV32IM-NEXT: mulhu a0, a0, a1
355 ; RV32IM-NEXT: ret
356 ;
357 ; RV64I-LABEL: mulhu:
358 ; RV64I: # %bb.0:
359 ; RV64I-NEXT: addi sp, sp, -16
360 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
361 ; RV64I-NEXT: call __muldi3
362 ; RV64I-NEXT: srli a0, a0, 32
363 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
364 ; RV64I-NEXT: addi sp, sp, 16
365 ; RV64I-NEXT: ret
366 ;
367 ; RV64IM-LABEL: mulhu:
368 ; RV64IM: # %bb.0:
369 ; RV64IM-NEXT: mul a0, a0, a1
370 ; RV64IM-NEXT: srli a0, a0, 32
371 ; RV64IM-NEXT: ret
372 %1 = zext i32 %a to i64
373 %2 = zext i32 %b to i64
374 %3 = mul i64 %1, %2
375 %4 = lshr i64 %3, 32
376 %5 = trunc i64 %4 to i32
377 ret i32 %5
378 }
380 define i32 @mulhsu(i32 %a, i32 %b) nounwind {
381 ; RV32I-LABEL: mulhsu:
382 ; RV32I: # %bb.0:
383 ; RV32I-NEXT: addi sp, sp, -16
384 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
385 ; RV32I-NEXT: mv a2, a1
386 ; RV32I-NEXT: srai a3, a1, 31
387 ; RV32I-NEXT: li a1, 0
388 ; RV32I-NEXT: call __muldi3
389 ; RV32I-NEXT: mv a0, a1
390 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
391 ; RV32I-NEXT: addi sp, sp, 16
392 ; RV32I-NEXT: ret
393 ;
394 ; RV32IM-LABEL: mulhsu:
395 ; RV32IM: # %bb.0:
396 ; RV32IM-NEXT: mulhsu a0, a1, a0
397 ; RV32IM-NEXT: ret
398 ;
399 ; RV64I-LABEL: mulhsu:
400 ; RV64I: # %bb.0:
401 ; RV64I-NEXT: addi sp, sp, -16
402 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
403 ; RV64I-NEXT: slli a0, a0, 32
404 ; RV64I-NEXT: srli a0, a0, 32
405 ; RV64I-NEXT: sext.w a1, a1
406 ; RV64I-NEXT: call __muldi3
407 ; RV64I-NEXT: srli a0, a0, 32
408 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
409 ; RV64I-NEXT: addi sp, sp, 16
410 ; RV64I-NEXT: ret
411 ;
412 ; RV64IM-LABEL: mulhsu:
413 ; RV64IM: # %bb.0:
414 ; RV64IM-NEXT: slli a0, a0, 32
415 ; RV64IM-NEXT: srli a0, a0, 32
416 ; RV64IM-NEXT: sext.w a1, a1
417 ; RV64IM-NEXT: mul a0, a0, a1
418 ; RV64IM-NEXT: srli a0, a0, 32
419 ; RV64IM-NEXT: ret
420 %1 = zext i32 %a to i64
421 %2 = sext i32 %b to i64
422 %3 = mul i64 %1, %2
423 %4 = lshr i64 %3, 32
424 %5 = trunc i64 %4 to i32
425 ret i32 %5
426 }
428 define i32 @mulhu_constant(i32 %a) nounwind {
429 ; RV32I-LABEL: mulhu_constant:
430 ; RV32I: # %bb.0:
431 ; RV32I-NEXT: slli a1, a0, 2
432 ; RV32I-NEXT: add a2, a1, a0
433 ; RV32I-NEXT: sltu a1, a2, a1
434 ; RV32I-NEXT: srli a0, a0, 30
435 ; RV32I-NEXT: add a0, a0, a1
436 ; RV32I-NEXT: ret
437 ;
438 ; RV32IM-LABEL: mulhu_constant:
439 ; RV32IM: # %bb.0:
440 ; RV32IM-NEXT: li a1, 5
441 ; RV32IM-NEXT: mulhu a0, a0, a1
442 ; RV32IM-NEXT: ret
443 ;
444 ; RV64I-LABEL: mulhu_constant:
445 ; RV64I: # %bb.0:
446 ; RV64I-NEXT: slli a0, a0, 32
447 ; RV64I-NEXT: srli a1, a0, 32
448 ; RV64I-NEXT: srli a0, a0, 30
449 ; RV64I-NEXT: add a0, a0, a1
450 ; RV64I-NEXT: srli a0, a0, 32
451 ; RV64I-NEXT: ret
452 ;
453 ; RV64IM-LABEL: mulhu_constant:
454 ; RV64IM: # %bb.0:
455 ; RV64IM-NEXT: slli a0, a0, 32
456 ; RV64IM-NEXT: srli a1, a0, 32
457 ; RV64IM-NEXT: srli a0, a0, 30
458 ; RV64IM-NEXT: add a0, a0, a1
459 ; RV64IM-NEXT: srli a0, a0, 32
460 ; RV64IM-NEXT: ret
461 %1 = zext i32 %a to i64
462 %2 = mul i64 %1, 5
463 %3 = lshr i64 %2, 32
464 %4 = trunc i64 %3 to i32
465 ret i32 %4
466 }
468 define i32 @muli32_p14(i32 %a) nounwind {
469 ; RV32I-LABEL: muli32_p14:
470 ; RV32I: # %bb.0:
471 ; RV32I-NEXT: li a1, 14
472 ; RV32I-NEXT: tail __mulsi3
473 ;
474 ; RV32IM-LABEL: muli32_p14:
475 ; RV32IM: # %bb.0:
476 ; RV32IM-NEXT: slli a1, a0, 1
477 ; RV32IM-NEXT: slli a0, a0, 4
478 ; RV32IM-NEXT: sub a0, a0, a1
479 ; RV32IM-NEXT: ret
480 ;
481 ; RV64I-LABEL: muli32_p14:
482 ; RV64I: # %bb.0:
483 ; RV64I-NEXT: slli a1, a0, 1
484 ; RV64I-NEXT: slli a0, a0, 4
485 ; RV64I-NEXT: sub a0, a0, a1
486 ; RV64I-NEXT: ret
487 ;
488 ; RV64IM-LABEL: muli32_p14:
489 ; RV64IM: # %bb.0:
490 ; RV64IM-NEXT: slli a1, a0, 1
491 ; RV64IM-NEXT: slli a0, a0, 4
492 ; RV64IM-NEXT: subw a0, a0, a1
493 ; RV64IM-NEXT: ret
494 %1 = mul i32 %a, 14
495 ret i32 %1
496 }
498 define i32 @muli32_p28(i32 %a) nounwind {
499 ; RV32I-LABEL: muli32_p28:
500 ; RV32I: # %bb.0:
501 ; RV32I-NEXT: li a1, 28
502 ; RV32I-NEXT: tail __mulsi3
503 ;
504 ; RV32IM-LABEL: muli32_p28:
505 ; RV32IM: # %bb.0:
506 ; RV32IM-NEXT: slli a1, a0, 2
507 ; RV32IM-NEXT: slli a0, a0, 5
508 ; RV32IM-NEXT: sub a0, a0, a1
509 ; RV32IM-NEXT: ret
510 ;
511 ; RV64I-LABEL: muli32_p28:
512 ; RV64I: # %bb.0:
513 ; RV64I-NEXT: slli a1, a0, 2
514 ; RV64I-NEXT: slli a0, a0, 5
515 ; RV64I-NEXT: sub a0, a0, a1
516 ; RV64I-NEXT: ret
517 ;
518 ; RV64IM-LABEL: muli32_p28:
519 ; RV64IM: # %bb.0:
520 ; RV64IM-NEXT: slli a1, a0, 2
521 ; RV64IM-NEXT: slli a0, a0, 5
522 ; RV64IM-NEXT: subw a0, a0, a1
523 ; RV64IM-NEXT: ret
524 %1 = mul i32 %a, 28
525 ret i32 %1
526 }
528 define i32 @muli32_p30(i32 %a) nounwind {
529 ; RV32I-LABEL: muli32_p30:
530 ; RV32I: # %bb.0:
531 ; RV32I-NEXT: li a1, 30
532 ; RV32I-NEXT: tail __mulsi3
533 ;
534 ; RV32IM-LABEL: muli32_p30:
535 ; RV32IM: # %bb.0:
536 ; RV32IM-NEXT: slli a1, a0, 1
537 ; RV32IM-NEXT: slli a0, a0, 5
538 ; RV32IM-NEXT: sub a0, a0, a1
539 ; RV32IM-NEXT: ret
540 ;
541 ; RV64I-LABEL: muli32_p30:
542 ; RV64I: # %bb.0:
543 ; RV64I-NEXT: slli a1, a0, 1
544 ; RV64I-NEXT: slli a0, a0, 5
545 ; RV64I-NEXT: sub a0, a0, a1
546 ; RV64I-NEXT: ret
547 ;
548 ; RV64IM-LABEL: muli32_p30:
549 ; RV64IM: # %bb.0:
550 ; RV64IM-NEXT: slli a1, a0, 1
551 ; RV64IM-NEXT: slli a0, a0, 5
552 ; RV64IM-NEXT: subw a0, a0, a1
553 ; RV64IM-NEXT: ret
554 %1 = mul i32 %a, 30
555 ret i32 %1
556 }
558 define i32 @muli32_p56(i32 %a) nounwind {
559 ; RV32I-LABEL: muli32_p56:
560 ; RV32I: # %bb.0:
561 ; RV32I-NEXT: li a1, 56
562 ; RV32I-NEXT: tail __mulsi3
563 ;
564 ; RV32IM-LABEL: muli32_p56:
565 ; RV32IM: # %bb.0:
566 ; RV32IM-NEXT: slli a1, a0, 3
567 ; RV32IM-NEXT: slli a0, a0, 6
568 ; RV32IM-NEXT: sub a0, a0, a1
569 ; RV32IM-NEXT: ret
570 ;
571 ; RV64I-LABEL: muli32_p56:
572 ; RV64I: # %bb.0:
573 ; RV64I-NEXT: slli a1, a0, 3
574 ; RV64I-NEXT: slli a0, a0, 6
575 ; RV64I-NEXT: sub a0, a0, a1
576 ; RV64I-NEXT: ret
577 ;
578 ; RV64IM-LABEL: muli32_p56:
579 ; RV64IM: # %bb.0:
580 ; RV64IM-NEXT: slli a1, a0, 3
581 ; RV64IM-NEXT: slli a0, a0, 6
582 ; RV64IM-NEXT: subw a0, a0, a1
583 ; RV64IM-NEXT: ret
584 %1 = mul i32 %a, 56
585 ret i32 %1
586 }
588 define i32 @muli32_p60(i32 %a) nounwind {
589 ; RV32I-LABEL: muli32_p60:
590 ; RV32I: # %bb.0:
591 ; RV32I-NEXT: li a1, 60
592 ; RV32I-NEXT: tail __mulsi3
593 ;
594 ; RV32IM-LABEL: muli32_p60:
595 ; RV32IM: # %bb.0:
596 ; RV32IM-NEXT: slli a1, a0, 2
597 ; RV32IM-NEXT: slli a0, a0, 6
598 ; RV32IM-NEXT: sub a0, a0, a1
599 ; RV32IM-NEXT: ret
600 ;
601 ; RV64I-LABEL: muli32_p60:
602 ; RV64I: # %bb.0:
603 ; RV64I-NEXT: slli a1, a0, 2
604 ; RV64I-NEXT: slli a0, a0, 6
605 ; RV64I-NEXT: sub a0, a0, a1
606 ; RV64I-NEXT: ret
607 ;
608 ; RV64IM-LABEL: muli32_p60:
609 ; RV64IM: # %bb.0:
610 ; RV64IM-NEXT: slli a1, a0, 2
611 ; RV64IM-NEXT: slli a0, a0, 6
612 ; RV64IM-NEXT: subw a0, a0, a1
613 ; RV64IM-NEXT: ret
614 %1 = mul i32 %a, 60
615 ret i32 %1
616 }
618 define i32 @muli32_p62(i32 %a) nounwind {
619 ; RV32I-LABEL: muli32_p62:
620 ; RV32I: # %bb.0:
621 ; RV32I-NEXT: li a1, 62
622 ; RV32I-NEXT: tail __mulsi3
623 ;
624 ; RV32IM-LABEL: muli32_p62:
625 ; RV32IM: # %bb.0:
626 ; RV32IM-NEXT: slli a1, a0, 1
627 ; RV32IM-NEXT: slli a0, a0, 6
628 ; RV32IM-NEXT: sub a0, a0, a1
629 ; RV32IM-NEXT: ret
630 ;
631 ; RV64I-LABEL: muli32_p62:
632 ; RV64I: # %bb.0:
633 ; RV64I-NEXT: slli a1, a0, 1
634 ; RV64I-NEXT: slli a0, a0, 6
635 ; RV64I-NEXT: sub a0, a0, a1
636 ; RV64I-NEXT: ret
637 ;
638 ; RV64IM-LABEL: muli32_p62:
639 ; RV64IM: # %bb.0:
640 ; RV64IM-NEXT: slli a1, a0, 1
641 ; RV64IM-NEXT: slli a0, a0, 6
642 ; RV64IM-NEXT: subw a0, a0, a1
643 ; RV64IM-NEXT: ret
644 %1 = mul i32 %a, 62
645 ret i32 %1
646 }
648 define i32 @muli32_p65(i32 %a) nounwind {
649 ; RV32I-LABEL: muli32_p65:
650 ; RV32I: # %bb.0:
651 ; RV32I-NEXT: slli a1, a0, 6
652 ; RV32I-NEXT: add a0, a1, a0
653 ; RV32I-NEXT: ret
654 ;
655 ; RV32IM-LABEL: muli32_p65:
656 ; RV32IM: # %bb.0:
657 ; RV32IM-NEXT: slli a1, a0, 6
658 ; RV32IM-NEXT: add a0, a1, a0
659 ; RV32IM-NEXT: ret
660 ;
661 ; RV64I-LABEL: muli32_p65:
662 ; RV64I: # %bb.0:
663 ; RV64I-NEXT: slli a1, a0, 6
664 ; RV64I-NEXT: addw a0, a1, a0
665 ; RV64I-NEXT: ret
666 ;
667 ; RV64IM-LABEL: muli32_p65:
668 ; RV64IM: # %bb.0:
669 ; RV64IM-NEXT: slli a1, a0, 6
670 ; RV64IM-NEXT: addw a0, a1, a0
671 ; RV64IM-NEXT: ret
672 %1 = mul i32 %a, 65
673 ret i32 %1
674 }
676 define i32 @muli32_p63(i32 %a) nounwind {
677 ; RV32I-LABEL: muli32_p63:
678 ; RV32I: # %bb.0:
679 ; RV32I-NEXT: slli a1, a0, 6
680 ; RV32I-NEXT: sub a0, a1, a0
681 ; RV32I-NEXT: ret
682 ;
683 ; RV32IM-LABEL: muli32_p63:
684 ; RV32IM: # %bb.0:
685 ; RV32IM-NEXT: slli a1, a0, 6
686 ; RV32IM-NEXT: sub a0, a1, a0
687 ; RV32IM-NEXT: ret
688 ;
689 ; RV64I-LABEL: muli32_p63:
690 ; RV64I: # %bb.0:
691 ; RV64I-NEXT: slli a1, a0, 6
692 ; RV64I-NEXT: subw a0, a1, a0
693 ; RV64I-NEXT: ret
694 ;
695 ; RV64IM-LABEL: muli32_p63:
696 ; RV64IM: # %bb.0:
697 ; RV64IM-NEXT: slli a1, a0, 6
698 ; RV64IM-NEXT: subw a0, a1, a0
699 ; RV64IM-NEXT: ret
700 %1 = mul i32 %a, 63
701 ret i32 %1
702 }
704 define i64 @muli64_p65(i64 %a) nounwind {
705 ; RV32I-LABEL: muli64_p65:
706 ; RV32I: # %bb.0:
707 ; RV32I-NEXT: slli a3, a0, 6
708 ; RV32I-NEXT: add a2, a3, a0
709 ; RV32I-NEXT: sltu a3, a2, a3
710 ; RV32I-NEXT: srli a0, a0, 26
711 ; RV32I-NEXT: slli a4, a1, 6
712 ; RV32I-NEXT: or a0, a4, a0
713 ; RV32I-NEXT: add a0, a0, a1
714 ; RV32I-NEXT: add a1, a0, a3
715 ; RV32I-NEXT: mv a0, a2
716 ; RV32I-NEXT: ret
717 ;
718 ; RV32IM-LABEL: muli64_p65:
719 ; RV32IM: # %bb.0:
720 ; RV32IM-NEXT: li a2, 65
721 ; RV32IM-NEXT: mulhu a2, a0, a2
722 ; RV32IM-NEXT: slli a3, a1, 6
723 ; RV32IM-NEXT: add a1, a3, a1
724 ; RV32IM-NEXT: add a1, a2, a1
725 ; RV32IM-NEXT: slli a2, a0, 6
726 ; RV32IM-NEXT: add a0, a2, a0
727 ; RV32IM-NEXT: ret
728 ;
729 ; RV64I-LABEL: muli64_p65:
730 ; RV64I: # %bb.0:
731 ; RV64I-NEXT: slli a1, a0, 6
732 ; RV64I-NEXT: add a0, a1, a0
733 ; RV64I-NEXT: ret
734 ;
735 ; RV64IM-LABEL: muli64_p65:
736 ; RV64IM: # %bb.0:
737 ; RV64IM-NEXT: slli a1, a0, 6
738 ; RV64IM-NEXT: add a0, a1, a0
739 ; RV64IM-NEXT: ret
740 %1 = mul i64 %a, 65
741 ret i64 %1
742 }
744 define i64 @muli64_p63(i64 %a) nounwind {
745 ; RV32I-LABEL: muli64_p63:
746 ; RV32I: # %bb.0:
747 ; RV32I-NEXT: slli a2, a0, 6
748 ; RV32I-NEXT: sltu a3, a2, a0
749 ; RV32I-NEXT: srli a4, a0, 26
750 ; RV32I-NEXT: slli a5, a1, 6
751 ; RV32I-NEXT: or a4, a5, a4
752 ; RV32I-NEXT: sub a1, a4, a1
753 ; RV32I-NEXT: sub a1, a1, a3
754 ; RV32I-NEXT: sub a0, a2, a0
755 ; RV32I-NEXT: ret
756 ;
757 ; RV32IM-LABEL: muli64_p63:
758 ; RV32IM: # %bb.0:
759 ; RV32IM-NEXT: li a2, 63
760 ; RV32IM-NEXT: mulhu a2, a0, a2
761 ; RV32IM-NEXT: slli a3, a1, 6
762 ; RV32IM-NEXT: sub a1, a3, a1
763 ; RV32IM-NEXT: add a1, a2, a1
764 ; RV32IM-NEXT: slli a2, a0, 6
765 ; RV32IM-NEXT: sub a0, a2, a0
766 ; RV32IM-NEXT: ret
767 ;
768 ; RV64I-LABEL: muli64_p63:
769 ; RV64I: # %bb.0:
770 ; RV64I-NEXT: slli a1, a0, 6
771 ; RV64I-NEXT: sub a0, a1, a0
772 ; RV64I-NEXT: ret
773 ;
774 ; RV64IM-LABEL: muli64_p63:
775 ; RV64IM: # %bb.0:
776 ; RV64IM-NEXT: slli a1, a0, 6
777 ; RV64IM-NEXT: sub a0, a1, a0
778 ; RV64IM-NEXT: ret
779 %1 = mul i64 %a, 63
780 ret i64 %1
781 }
785 define i32 @muli32_m63(i32 %a) nounwind {
786 ; RV32I-LABEL: muli32_m63:
787 ; RV32I: # %bb.0:
788 ; RV32I-NEXT: slli a1, a0, 6
789 ; RV32I-NEXT: sub a0, a0, a1
790 ; RV32I-NEXT: ret
791 ;
792 ; RV32IM-LABEL: muli32_m63:
793 ; RV32IM: # %bb.0:
794 ; RV32IM-NEXT: slli a1, a0, 6
795 ; RV32IM-NEXT: sub a0, a0, a1
796 ; RV32IM-NEXT: ret
797 ;
798 ; RV64I-LABEL: muli32_m63:
799 ; RV64I: # %bb.0:
800 ; RV64I-NEXT: slli a1, a0, 6
801 ; RV64I-NEXT: subw a0, a0, a1
802 ; RV64I-NEXT: ret
803 ;
804 ; RV64IM-LABEL: muli32_m63:
805 ; RV64IM: # %bb.0:
806 ; RV64IM-NEXT: slli a1, a0, 6
807 ; RV64IM-NEXT: subw a0, a0, a1
808 ; RV64IM-NEXT: ret
809 %1 = mul i32 %a, -63
810 ret i32 %1
811 }
813 define i32 @muli32_m65(i32 %a) nounwind {
814 ; RV32I-LABEL: muli32_m65:
815 ; RV32I: # %bb.0:
816 ; RV32I-NEXT: slli a1, a0, 6
817 ; RV32I-NEXT: neg a0, a0
818 ; RV32I-NEXT: sub a0, a0, a1
819 ; RV32I-NEXT: ret
820 ;
821 ; RV32IM-LABEL: muli32_m65:
822 ; RV32IM: # %bb.0:
823 ; RV32IM-NEXT: slli a1, a0, 6
824 ; RV32IM-NEXT: neg a0, a0
825 ; RV32IM-NEXT: sub a0, a0, a1
826 ; RV32IM-NEXT: ret
827 ;
828 ; RV64I-LABEL: muli32_m65:
829 ; RV64I: # %bb.0:
830 ; RV64I-NEXT: slli a1, a0, 6
831 ; RV64I-NEXT: negw a0, a0
832 ; RV64I-NEXT: subw a0, a0, a1
833 ; RV64I-NEXT: ret
834 ;
835 ; RV64IM-LABEL: muli32_m65:
836 ; RV64IM: # %bb.0:
837 ; RV64IM-NEXT: slli a1, a0, 6
838 ; RV64IM-NEXT: negw a0, a0
839 ; RV64IM-NEXT: subw a0, a0, a1
840 ; RV64IM-NEXT: ret
841 %1 = mul i32 %a, -65
842 ret i32 %1
843 }
845 define i64 @muli64_m63(i64 %a) nounwind {
846 ; RV32I-LABEL: muli64_m63:
847 ; RV32I: # %bb.0:
848 ; RV32I-NEXT: slli a2, a0, 6
849 ; RV32I-NEXT: sltu a3, a0, a2
850 ; RV32I-NEXT: srli a4, a0, 26
851 ; RV32I-NEXT: slli a5, a1, 6
852 ; RV32I-NEXT: or a4, a5, a4
853 ; RV32I-NEXT: sub a1, a1, a4
854 ; RV32I-NEXT: sub a1, a1, a3
855 ; RV32I-NEXT: sub a0, a0, a2
856 ; RV32I-NEXT: ret
857 ;
858 ; RV32IM-LABEL: muli64_m63:
859 ; RV32IM: # %bb.0:
860 ; RV32IM-NEXT: slli a2, a1, 6
861 ; RV32IM-NEXT: sub a1, a1, a2
862 ; RV32IM-NEXT: li a2, -63
863 ; RV32IM-NEXT: mulhu a2, a0, a2
864 ; RV32IM-NEXT: sub a2, a2, a0
865 ; RV32IM-NEXT: add a1, a2, a1
866 ; RV32IM-NEXT: slli a2, a0, 6
867 ; RV32IM-NEXT: sub a0, a0, a2
868 ; RV32IM-NEXT: ret
869 ;
870 ; RV64I-LABEL: muli64_m63:
871 ; RV64I: # %bb.0:
872 ; RV64I-NEXT: slli a1, a0, 6
873 ; RV64I-NEXT: sub a0, a0, a1
874 ; RV64I-NEXT: ret
875 ;
876 ; RV64IM-LABEL: muli64_m63:
877 ; RV64IM: # %bb.0:
878 ; RV64IM-NEXT: slli a1, a0, 6
879 ; RV64IM-NEXT: sub a0, a0, a1
880 ; RV64IM-NEXT: ret
881 %1 = mul i64 %a, -63
882 ret i64 %1
883 }
885 define i64 @muli64_m65(i64 %a) nounwind {
886 ; RV32I-LABEL: muli64_m65:
887 ; RV32I: # %bb.0:
888 ; RV32I-NEXT: slli a2, a0, 6
889 ; RV32I-NEXT: add a3, a2, a0
890 ; RV32I-NEXT: sltu a2, a3, a2
891 ; RV32I-NEXT: srli a0, a0, 26
892 ; RV32I-NEXT: slli a4, a1, 6
893 ; RV32I-NEXT: or a0, a4, a0
894 ; RV32I-NEXT: add a0, a0, a1
895 ; RV32I-NEXT: add a0, a0, a2
896 ; RV32I-NEXT: snez a1, a3
897 ; RV32I-NEXT: neg a1, a1
898 ; RV32I-NEXT: sub a1, a1, a0
899 ; RV32I-NEXT: neg a0, a3
900 ; RV32I-NEXT: ret
901 ;
902 ; RV32IM-LABEL: muli64_m65:
903 ; RV32IM: # %bb.0:
904 ; RV32IM-NEXT: slli a2, a1, 6
905 ; RV32IM-NEXT: add a1, a2, a1
906 ; RV32IM-NEXT: li a2, -65
907 ; RV32IM-NEXT: mulhu a2, a0, a2
908 ; RV32IM-NEXT: sub a2, a2, a0
909 ; RV32IM-NEXT: sub a1, a2, a1
910 ; RV32IM-NEXT: slli a2, a0, 6
911 ; RV32IM-NEXT: neg a0, a0
912 ; RV32IM-NEXT: sub a0, a0, a2
913 ; RV32IM-NEXT: ret
914 ;
915 ; RV64I-LABEL: muli64_m65:
916 ; RV64I: # %bb.0:
917 ; RV64I-NEXT: slli a1, a0, 6
918 ; RV64I-NEXT: neg a0, a0
919 ; RV64I-NEXT: sub a0, a0, a1
920 ; RV64I-NEXT: ret
921 ;
922 ; RV64IM-LABEL: muli64_m65:
923 ; RV64IM: # %bb.0:
924 ; RV64IM-NEXT: slli a1, a0, 6
925 ; RV64IM-NEXT: neg a0, a0
926 ; RV64IM-NEXT: sub a0, a0, a1
927 ; RV64IM-NEXT: ret
928 %1 = mul i64 %a, -65
929 ret i64 %1
930 }
932 define i32 @muli32_p384(i32 %a) nounwind {
933 ; RV32I-LABEL: muli32_p384:
934 ; RV32I: # %bb.0:
935 ; RV32I-NEXT: li a1, 384
936 ; RV32I-NEXT: tail __mulsi3
937 ;
938 ; RV32IM-LABEL: muli32_p384:
939 ; RV32IM: # %bb.0:
940 ; RV32IM-NEXT: slli a1, a0, 7
941 ; RV32IM-NEXT: slli a0, a0, 9
942 ; RV32IM-NEXT: sub a0, a0, a1
943 ; RV32IM-NEXT: ret
944 ;
945 ; RV64I-LABEL: muli32_p384:
946 ; RV64I: # %bb.0:
947 ; RV64I-NEXT: slli a1, a0, 7
948 ; RV64I-NEXT: slli a0, a0, 9
949 ; RV64I-NEXT: sub a0, a0, a1
950 ; RV64I-NEXT: ret
951 ;
952 ; RV64IM-LABEL: muli32_p384:
953 ; RV64IM: # %bb.0:
954 ; RV64IM-NEXT: slli a1, a0, 7
955 ; RV64IM-NEXT: slli a0, a0, 9
956 ; RV64IM-NEXT: subw a0, a0, a1
957 ; RV64IM-NEXT: ret
958 %1 = mul i32 %a, 384
959 ret i32 %1
960 }
962 define i32 @muli32_p12288(i32 %a) nounwind {
963 ; RV32I-LABEL: muli32_p12288:
964 ; RV32I: # %bb.0:
965 ; RV32I-NEXT: lui a1, 3
966 ; RV32I-NEXT: tail __mulsi3
967 ;
968 ; RV32IM-LABEL: muli32_p12288:
969 ; RV32IM: # %bb.0:
970 ; RV32IM-NEXT: slli a1, a0, 12
971 ; RV32IM-NEXT: slli a0, a0, 14
972 ; RV32IM-NEXT: sub a0, a0, a1
973 ; RV32IM-NEXT: ret
974 ;
975 ; RV64I-LABEL: muli32_p12288:
976 ; RV64I: # %bb.0:
977 ; RV64I-NEXT: slli a1, a0, 12
978 ; RV64I-NEXT: slli a0, a0, 14
979 ; RV64I-NEXT: sub a0, a0, a1
980 ; RV64I-NEXT: ret
981 ;
982 ; RV64IM-LABEL: muli32_p12288:
983 ; RV64IM: # %bb.0:
984 ; RV64IM-NEXT: slli a1, a0, 12
985 ; RV64IM-NEXT: slli a0, a0, 14
986 ; RV64IM-NEXT: subw a0, a0, a1
987 ; RV64IM-NEXT: ret
988 %1 = mul i32 %a, 12288
989 ret i32 %1
990 }
992 define i32 @muli32_p4352(i32 %a) nounwind {
993 ; RV32I-LABEL: muli32_p4352:
994 ; RV32I: # %bb.0:
995 ; RV32I-NEXT: slli a1, a0, 8
996 ; RV32I-NEXT: slli a0, a0, 12
997 ; RV32I-NEXT: add a0, a0, a1
998 ; RV32I-NEXT: ret
999 ;
1000 ; RV32IM-LABEL: muli32_p4352:
1001 ; RV32IM: # %bb.0:
1002 ; RV32IM-NEXT: slli a1, a0, 8
1003 ; RV32IM-NEXT: slli a0, a0, 12
1004 ; RV32IM-NEXT: add a0, a0, a1
1005 ; RV32IM-NEXT: ret
1006 ;
1007 ; RV64I-LABEL: muli32_p4352:
1008 ; RV64I: # %bb.0:
1009 ; RV64I-NEXT: slli a1, a0, 8
1010 ; RV64I-NEXT: slli a0, a0, 12
1011 ; RV64I-NEXT: addw a0, a0, a1
1012 ; RV64I-NEXT: ret
1013 ;
1014 ; RV64IM-LABEL: muli32_p4352:
1015 ; RV64IM: # %bb.0:
1016 ; RV64IM-NEXT: slli a1, a0, 8
1017 ; RV64IM-NEXT: slli a0, a0, 12
1018 ; RV64IM-NEXT: addw a0, a0, a1
1019 ; RV64IM-NEXT: ret
1020 %1 = mul i32 %a, 4352
1021 ret i32 %1
1022 }
1024 define i32 @muli32_p3840(i32 %a) nounwind {
1025 ; RV32I-LABEL: muli32_p3840:
1026 ; RV32I: # %bb.0:
1027 ; RV32I-NEXT: slli a1, a0, 8
1028 ; RV32I-NEXT: slli a0, a0, 12
1029 ; RV32I-NEXT: sub a0, a0, a1
1030 ; RV32I-NEXT: ret
1031 ;
1032 ; RV32IM-LABEL: muli32_p3840:
1033 ; RV32IM: # %bb.0:
1034 ; RV32IM-NEXT: slli a1, a0, 8
1035 ; RV32IM-NEXT: slli a0, a0, 12
1036 ; RV32IM-NEXT: sub a0, a0, a1
1037 ; RV32IM-NEXT: ret
1038 ;
1039 ; RV64I-LABEL: muli32_p3840:
1040 ; RV64I: # %bb.0:
1041 ; RV64I-NEXT: slli a1, a0, 8
1042 ; RV64I-NEXT: slli a0, a0, 12
1043 ; RV64I-NEXT: subw a0, a0, a1
1044 ; RV64I-NEXT: ret
1045 ;
1046 ; RV64IM-LABEL: muli32_p3840:
1047 ; RV64IM: # %bb.0:
1048 ; RV64IM-NEXT: slli a1, a0, 8
1049 ; RV64IM-NEXT: slli a0, a0, 12
1050 ; RV64IM-NEXT: subw a0, a0, a1
1051 ; RV64IM-NEXT: ret
1052 %1 = mul i32 %a, 3840
1053 ret i32 %1
1054 }
1056 define i32 @muli32_m3840(i32 %a) nounwind {
1057 ; RV32I-LABEL: muli32_m3840:
1058 ; RV32I: # %bb.0:
1059 ; RV32I-NEXT: slli a1, a0, 12
1060 ; RV32I-NEXT: slli a0, a0, 8
1061 ; RV32I-NEXT: sub a0, a0, a1
1062 ; RV32I-NEXT: ret
1063 ;
1064 ; RV32IM-LABEL: muli32_m3840:
1065 ; RV32IM: # %bb.0:
1066 ; RV32IM-NEXT: slli a1, a0, 12
1067 ; RV32IM-NEXT: slli a0, a0, 8
1068 ; RV32IM-NEXT: sub a0, a0, a1
1069 ; RV32IM-NEXT: ret
1070 ;
1071 ; RV64I-LABEL: muli32_m3840:
1072 ; RV64I: # %bb.0:
1073 ; RV64I-NEXT: slli a1, a0, 12
1074 ; RV64I-NEXT: slli a0, a0, 8
1075 ; RV64I-NEXT: subw a0, a0, a1
1076 ; RV64I-NEXT: ret
1077 ;
1078 ; RV64IM-LABEL: muli32_m3840:
1079 ; RV64IM: # %bb.0:
1080 ; RV64IM-NEXT: slli a1, a0, 12
1081 ; RV64IM-NEXT: slli a0, a0, 8
1082 ; RV64IM-NEXT: subw a0, a0, a1
1083 ; RV64IM-NEXT: ret
1084 %1 = mul i32 %a, -3840
1085 ret i32 %1
1086 }
1088 define i32 @muli32_m4352(i32 %a) nounwind {
1089 ; RV32I-LABEL: muli32_m4352:
1090 ; RV32I: # %bb.0:
1091 ; RV32I-NEXT: li a1, -17
1092 ; RV32I-NEXT: slli a1, a1, 8
1093 ; RV32I-NEXT: tail __mulsi3
1094 ;
1095 ; RV32IM-LABEL: muli32_m4352:
1096 ; RV32IM: # %bb.0:
1097 ; RV32IM-NEXT: li a1, -17
1098 ; RV32IM-NEXT: slli a1, a1, 8
1099 ; RV32IM-NEXT: mul a0, a0, a1
1100 ; RV32IM-NEXT: ret
1101 ;
1102 ; RV64I-LABEL: muli32_m4352:
1103 ; RV64I: # %bb.0:
1104 ; RV64I-NEXT: addi sp, sp, -16
1105 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1106 ; RV64I-NEXT: li a1, -17
1107 ; RV64I-NEXT: slli a1, a1, 8
1108 ; RV64I-NEXT: call __muldi3
1109 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1110 ; RV64I-NEXT: addi sp, sp, 16
1111 ; RV64I-NEXT: ret
1112 ;
1113 ; RV64IM-LABEL: muli32_m4352:
1114 ; RV64IM: # %bb.0:
1115 ; RV64IM-NEXT: li a1, -17
1116 ; RV64IM-NEXT: slli a1, a1, 8
1117 ; RV64IM-NEXT: mulw a0, a0, a1
1118 ; RV64IM-NEXT: ret
1119 %1 = mul i32 %a, -4352
1120 ret i32 %1
1121 }
1123 define i64 @muli64_p4352(i64 %a) nounwind {
1124 ; RV32I-LABEL: muli64_p4352:
1125 ; RV32I: # %bb.0:
1126 ; RV32I-NEXT: srli a2, a0, 24
1127 ; RV32I-NEXT: slli a3, a1, 8
1128 ; RV32I-NEXT: or a2, a3, a2
1129 ; RV32I-NEXT: srli a3, a0, 20
1130 ; RV32I-NEXT: slli a1, a1, 12
1131 ; RV32I-NEXT: or a1, a1, a3
1132 ; RV32I-NEXT: add a1, a1, a2
1133 ; RV32I-NEXT: slli a2, a0, 8
1134 ; RV32I-NEXT: slli a3, a0, 12
1135 ; RV32I-NEXT: add a0, a3, a2
1136 ; RV32I-NEXT: sltu a2, a0, a3
1137 ; RV32I-NEXT: add a1, a1, a2
1138 ; RV32I-NEXT: ret
1139 ;
1140 ; RV32IM-LABEL: muli64_p4352:
1141 ; RV32IM: # %bb.0:
1142 ; RV32IM-NEXT: li a2, 17
1143 ; RV32IM-NEXT: slli a2, a2, 8
1144 ; RV32IM-NEXT: mul a1, a1, a2
1145 ; RV32IM-NEXT: mulhu a3, a0, a2
1146 ; RV32IM-NEXT: add a1, a3, a1
1147 ; RV32IM-NEXT: mul a0, a0, a2
1148 ; RV32IM-NEXT: ret
1149 ;
1150 ; RV64I-LABEL: muli64_p4352:
1151 ; RV64I: # %bb.0:
1152 ; RV64I-NEXT: slli a1, a0, 8
1153 ; RV64I-NEXT: slli a0, a0, 12
1154 ; RV64I-NEXT: add a0, a0, a1
1155 ; RV64I-NEXT: ret
1156 ;
1157 ; RV64IM-LABEL: muli64_p4352:
1158 ; RV64IM: # %bb.0:
1159 ; RV64IM-NEXT: slli a1, a0, 8
1160 ; RV64IM-NEXT: slli a0, a0, 12
1161 ; RV64IM-NEXT: add a0, a0, a1
1162 ; RV64IM-NEXT: ret
1163 %1 = mul i64 %a, 4352
1164 ret i64 %1
1165 }
1167 define i64 @muli64_p3840(i64 %a) nounwind {
1168 ; RV32I-LABEL: muli64_p3840:
1169 ; RV32I: # %bb.0:
1170 ; RV32I-NEXT: srli a2, a0, 24
1171 ; RV32I-NEXT: slli a3, a1, 8
1172 ; RV32I-NEXT: or a2, a3, a2
1173 ; RV32I-NEXT: srli a3, a0, 20
1174 ; RV32I-NEXT: slli a1, a1, 12
1175 ; RV32I-NEXT: or a1, a1, a3
1176 ; RV32I-NEXT: sub a1, a1, a2
1177 ; RV32I-NEXT: slli a2, a0, 8
1178 ; RV32I-NEXT: slli a0, a0, 12
1179 ; RV32I-NEXT: sltu a3, a0, a2
1180 ; RV32I-NEXT: sub a1, a1, a3
1181 ; RV32I-NEXT: sub a0, a0, a2
1182 ; RV32I-NEXT: ret
1183 ;
1184 ; RV32IM-LABEL: muli64_p3840:
1185 ; RV32IM: # %bb.0:
1186 ; RV32IM-NEXT: slli a2, a1, 8
1187 ; RV32IM-NEXT: slli a1, a1, 12
1188 ; RV32IM-NEXT: sub a1, a1, a2
1189 ; RV32IM-NEXT: li a2, 15
1190 ; RV32IM-NEXT: slli a2, a2, 8
1191 ; RV32IM-NEXT: mulhu a2, a0, a2
1192 ; RV32IM-NEXT: add a1, a2, a1
1193 ; RV32IM-NEXT: slli a2, a0, 8
1194 ; RV32IM-NEXT: slli a0, a0, 12
1195 ; RV32IM-NEXT: sub a0, a0, a2
1196 ; RV32IM-NEXT: ret
1197 ;
1198 ; RV64I-LABEL: muli64_p3840:
1199 ; RV64I: # %bb.0:
1200 ; RV64I-NEXT: slli a1, a0, 8
1201 ; RV64I-NEXT: slli a0, a0, 12
1202 ; RV64I-NEXT: sub a0, a0, a1
1203 ; RV64I-NEXT: ret
1204 ;
1205 ; RV64IM-LABEL: muli64_p3840:
1206 ; RV64IM: # %bb.0:
1207 ; RV64IM-NEXT: slli a1, a0, 8
1208 ; RV64IM-NEXT: slli a0, a0, 12
1209 ; RV64IM-NEXT: sub a0, a0, a1
1210 ; RV64IM-NEXT: ret
1211 %1 = mul i64 %a, 3840
1212 ret i64 %1
1213 }
1215 define i64 @muli64_m4352(i64 %a) nounwind {
1216 ; RV32I-LABEL: muli64_m4352:
1217 ; RV32I: # %bb.0:
1218 ; RV32I-NEXT: addi sp, sp, -16
1219 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1220 ; RV32I-NEXT: li a2, -17
1221 ; RV32I-NEXT: slli a2, a2, 8
1222 ; RV32I-NEXT: li a3, -1
1223 ; RV32I-NEXT: call __muldi3
1224 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1225 ; RV32I-NEXT: addi sp, sp, 16
1226 ; RV32I-NEXT: ret
1227 ;
1228 ; RV32IM-LABEL: muli64_m4352:
1229 ; RV32IM: # %bb.0:
1230 ; RV32IM-NEXT: li a2, -17
1231 ; RV32IM-NEXT: slli a2, a2, 8
1232 ; RV32IM-NEXT: mul a1, a1, a2
1233 ; RV32IM-NEXT: mulhu a3, a0, a2
1234 ; RV32IM-NEXT: sub a3, a3, a0
1235 ; RV32IM-NEXT: add a1, a3, a1
1236 ; RV32IM-NEXT: mul a0, a0, a2
1237 ; RV32IM-NEXT: ret
1238 ;
1239 ; RV64I-LABEL: muli64_m4352:
1240 ; RV64I: # %bb.0:
1241 ; RV64I-NEXT: li a1, -17
1242 ; RV64I-NEXT: slli a1, a1, 8
1243 ; RV64I-NEXT: tail __muldi3
1244 ;
1245 ; RV64IM-LABEL: muli64_m4352:
1246 ; RV64IM: # %bb.0:
1247 ; RV64IM-NEXT: li a1, -17
1248 ; RV64IM-NEXT: slli a1, a1, 8
1249 ; RV64IM-NEXT: mul a0, a0, a1
1250 ; RV64IM-NEXT: ret
1251 %1 = mul i64 %a, -4352
1252 ret i64 %1
1253 }
1255 define i64 @muli64_m3840(i64 %a) nounwind {
1256 ; RV32I-LABEL: muli64_m3840:
1257 ; RV32I: # %bb.0:
1258 ; RV32I-NEXT: srli a2, a0, 20
1259 ; RV32I-NEXT: slli a3, a1, 12
1260 ; RV32I-NEXT: or a2, a3, a2
1261 ; RV32I-NEXT: srli a3, a0, 24
1262 ; RV32I-NEXT: slli a1, a1, 8
1263 ; RV32I-NEXT: or a1, a1, a3
1264 ; RV32I-NEXT: sub a1, a1, a2
1265 ; RV32I-NEXT: slli a2, a0, 12
1266 ; RV32I-NEXT: slli a0, a0, 8
1267 ; RV32I-NEXT: sltu a3, a0, a2
1268 ; RV32I-NEXT: sub a1, a1, a3
1269 ; RV32I-NEXT: sub a0, a0, a2
1270 ; RV32I-NEXT: ret
1271 ;
1272 ; RV32IM-LABEL: muli64_m3840:
1273 ; RV32IM: # %bb.0:
1274 ; RV32IM-NEXT: li a2, -15
1275 ; RV32IM-NEXT: slli a2, a2, 8
1276 ; RV32IM-NEXT: mul a1, a1, a2
1277 ; RV32IM-NEXT: mulhu a3, a0, a2
1278 ; RV32IM-NEXT: sub a3, a3, a0
1279 ; RV32IM-NEXT: add a1, a3, a1
1280 ; RV32IM-NEXT: mul a0, a0, a2
1281 ; RV32IM-NEXT: ret
1282 ;
1283 ; RV64I-LABEL: muli64_m3840:
1284 ; RV64I: # %bb.0:
1285 ; RV64I-NEXT: slli a1, a0, 12
1286 ; RV64I-NEXT: slli a0, a0, 8
1287 ; RV64I-NEXT: sub a0, a0, a1
1288 ; RV64I-NEXT: ret
1289 ;
1290 ; RV64IM-LABEL: muli64_m3840:
1291 ; RV64IM: # %bb.0:
1292 ; RV64IM-NEXT: slli a1, a0, 12
1293 ; RV64IM-NEXT: slli a0, a0, 8
1294 ; RV64IM-NEXT: sub a0, a0, a1
1295 ; RV64IM-NEXT: ret
1296 %1 = mul i64 %a, -3840
1297 ret i64 %1
1298 }
1300 define i128 @muli128_m3840(i128 %a) nounwind {
1301 ; RV32I-LABEL: muli128_m3840:
1302 ; RV32I: # %bb.0:
1303 ; RV32I-NEXT: lw a4, 4(a1)
1304 ; RV32I-NEXT: lw a3, 8(a1)
1305 ; RV32I-NEXT: lw a6, 0(a1)
1306 ; RV32I-NEXT: lw a5, 12(a1)
1307 ; RV32I-NEXT: srli a1, a4, 20
1308 ; RV32I-NEXT: slli a2, a3, 12
1309 ; RV32I-NEXT: or a1, a2, a1
1310 ; RV32I-NEXT: srli a2, a4, 24
1311 ; RV32I-NEXT: slli a7, a3, 8
1312 ; RV32I-NEXT: or a2, a7, a2
1313 ; RV32I-NEXT: sltu t0, a2, a1
1314 ; RV32I-NEXT: srli a7, a3, 20
1315 ; RV32I-NEXT: slli t1, a5, 12
1316 ; RV32I-NEXT: or a7, t1, a7
1317 ; RV32I-NEXT: srli a3, a3, 24
1318 ; RV32I-NEXT: slli a5, a5, 8
1319 ; RV32I-NEXT: or a3, a5, a3
1320 ; RV32I-NEXT: sub t1, a3, a7
1321 ; RV32I-NEXT: srli a3, a6, 20
1322 ; RV32I-NEXT: slli a5, a4, 12
1323 ; RV32I-NEXT: or a3, a5, a3
1324 ; RV32I-NEXT: srli a5, a6, 24
1325 ; RV32I-NEXT: slli a4, a4, 8
1326 ; RV32I-NEXT: or a5, a4, a5
1327 ; RV32I-NEXT: slli a4, a6, 12
1328 ; RV32I-NEXT: slli a6, a6, 8
1329 ; RV32I-NEXT: sltu a7, a6, a4
1330 ; RV32I-NEXT: sub t0, t1, t0
1331 ; RV32I-NEXT: mv t1, a7
1332 ; RV32I-NEXT: beq a5, a3, .LBB36_2
1333 ; RV32I-NEXT: # %bb.1:
1334 ; RV32I-NEXT: sltu t1, a5, a3
1335 ; RV32I-NEXT: .LBB36_2:
1336 ; RV32I-NEXT: sub a2, a2, a1
1337 ; RV32I-NEXT: sltu a1, a2, t1
1338 ; RV32I-NEXT: sub a1, t0, a1
1339 ; RV32I-NEXT: sub a2, a2, t1
1340 ; RV32I-NEXT: sub a5, a5, a3
1341 ; RV32I-NEXT: sub a3, a5, a7
1342 ; RV32I-NEXT: sub a4, a6, a4
1343 ; RV32I-NEXT: sw a4, 0(a0)
1344 ; RV32I-NEXT: sw a3, 4(a0)
1345 ; RV32I-NEXT: sw a2, 8(a0)
1346 ; RV32I-NEXT: sw a1, 12(a0)
1347 ; RV32I-NEXT: ret
1348 ;
1349 ; RV32IM-LABEL: muli128_m3840:
1350 ; RV32IM: # %bb.0:
1351 ; RV32IM-NEXT: addi sp, sp, -16
1352 ; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
1353 ; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
1354 ; RV32IM-NEXT: lw a2, 12(a1)
1355 ; RV32IM-NEXT: lw a3, 8(a1)
1356 ; RV32IM-NEXT: lw a4, 0(a1)
1357 ; RV32IM-NEXT: lw a1, 4(a1)
1358 ; RV32IM-NEXT: li a5, -15
1359 ; RV32IM-NEXT: slli a5, a5, 8
1360 ; RV32IM-NEXT: mulhu a6, a4, a5
1361 ; RV32IM-NEXT: mul a7, a1, a5
1362 ; RV32IM-NEXT: add a6, a7, a6
1363 ; RV32IM-NEXT: sltu a7, a6, a7
1364 ; RV32IM-NEXT: mulhu t0, a1, a5
1365 ; RV32IM-NEXT: add a7, t0, a7
1366 ; RV32IM-NEXT: sub a6, a6, a4
1367 ; RV32IM-NEXT: neg t0, a4
1368 ; RV32IM-NEXT: sltu t1, a6, t0
1369 ; RV32IM-NEXT: li t2, -1
1370 ; RV32IM-NEXT: mulhu t3, a4, t2
1371 ; RV32IM-NEXT: add t1, t3, t1
1372 ; RV32IM-NEXT: add t1, a7, t1
1373 ; RV32IM-NEXT: sub t4, t1, a1
1374 ; RV32IM-NEXT: mul t5, a3, a5
1375 ; RV32IM-NEXT: sub t5, t5, a4
1376 ; RV32IM-NEXT: add t6, t4, t5
1377 ; RV32IM-NEXT: sltu s0, t6, t4
1378 ; RV32IM-NEXT: neg s1, a1
1379 ; RV32IM-NEXT: sltu t4, t4, s1
1380 ; RV32IM-NEXT: sltu a7, t1, a7
1381 ; RV32IM-NEXT: mulhu t1, a1, t2
1382 ; RV32IM-NEXT: add a7, t1, a7
1383 ; RV32IM-NEXT: add a7, a7, t4
1384 ; RV32IM-NEXT: sltu t0, t5, t0
1385 ; RV32IM-NEXT: mul a2, a2, a5
1386 ; RV32IM-NEXT: mulhu t1, a3, a5
1387 ; RV32IM-NEXT: sub a3, t1, a3
1388 ; RV32IM-NEXT: add a2, a3, a2
1389 ; RV32IM-NEXT: add a1, a4, a1
1390 ; RV32IM-NEXT: sub a1, t3, a1
1391 ; RV32IM-NEXT: add a1, a1, a2
1392 ; RV32IM-NEXT: add a1, a1, t0
1393 ; RV32IM-NEXT: add a1, a7, a1
1394 ; RV32IM-NEXT: add a1, a1, s0
1395 ; RV32IM-NEXT: mul a2, a4, a5
1396 ; RV32IM-NEXT: sw a2, 0(a0)
1397 ; RV32IM-NEXT: sw a6, 4(a0)
1398 ; RV32IM-NEXT: sw t6, 8(a0)
1399 ; RV32IM-NEXT: sw a1, 12(a0)
1400 ; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
1401 ; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
1402 ; RV32IM-NEXT: addi sp, sp, 16
1403 ; RV32IM-NEXT: ret
1404 ;
1405 ; RV64I-LABEL: muli128_m3840:
1406 ; RV64I: # %bb.0:
1407 ; RV64I-NEXT: srli a2, a0, 52
1408 ; RV64I-NEXT: slli a3, a1, 12
1409 ; RV64I-NEXT: or a2, a3, a2
1410 ; RV64I-NEXT: srli a3, a0, 56
1411 ; RV64I-NEXT: slli a1, a1, 8
1412 ; RV64I-NEXT: or a1, a1, a3
1413 ; RV64I-NEXT: sub a1, a1, a2
1414 ; RV64I-NEXT: slli a2, a0, 12
1415 ; RV64I-NEXT: slli a0, a0, 8
1416 ; RV64I-NEXT: sltu a3, a0, a2
1417 ; RV64I-NEXT: sub a1, a1, a3
1418 ; RV64I-NEXT: sub a0, a0, a2
1419 ; RV64I-NEXT: ret
1420 ;
1421 ; RV64IM-LABEL: muli128_m3840:
1422 ; RV64IM: # %bb.0:
1423 ; RV64IM-NEXT: li a2, -15
1424 ; RV64IM-NEXT: slli a2, a2, 8
1425 ; RV64IM-NEXT: mul a1, a1, a2
1426 ; RV64IM-NEXT: mulhu a3, a0, a2
1427 ; RV64IM-NEXT: sub a3, a3, a0
1428 ; RV64IM-NEXT: add a1, a3, a1
1429 ; RV64IM-NEXT: mul a0, a0, a2
1430 ; RV64IM-NEXT: ret
1431 %1 = mul i128 %a, -3840
1432 ret i128 %1
1433 }
1435 define i128 @muli128_m63(i128 %a) nounwind {
1436 ; RV32I-LABEL: muli128_m63:
1437 ; RV32I: # %bb.0:
1438 ; RV32I-NEXT: lw a2, 0(a1)
1439 ; RV32I-NEXT: lw a4, 12(a1)
1440 ; RV32I-NEXT: lw a6, 8(a1)
1441 ; RV32I-NEXT: lw a1, 4(a1)
1442 ; RV32I-NEXT: slli a3, a2, 6
1443 ; RV32I-NEXT: sltu a5, a2, a3
1444 ; RV32I-NEXT: srli a7, a2, 26
1445 ; RV32I-NEXT: slli t0, a1, 6
1446 ; RV32I-NEXT: or a7, t0, a7
1447 ; RV32I-NEXT: mv t0, a5
1448 ; RV32I-NEXT: beq a1, a7, .LBB37_2
1449 ; RV32I-NEXT: # %bb.1:
1450 ; RV32I-NEXT: sltu t0, a1, a7
1451 ; RV32I-NEXT: .LBB37_2:
1452 ; RV32I-NEXT: srli t1, a1, 26
1453 ; RV32I-NEXT: slli t2, a6, 6
1454 ; RV32I-NEXT: or t1, t2, t1
1455 ; RV32I-NEXT: sub t2, a6, t1
1456 ; RV32I-NEXT: sltu t3, t2, t0
1457 ; RV32I-NEXT: sltu t1, a6, t1
1458 ; RV32I-NEXT: srli a6, a6, 26
1459 ; RV32I-NEXT: slli t4, a4, 6
1460 ; RV32I-NEXT: or a6, t4, a6
1461 ; RV32I-NEXT: sub a4, a4, a6
1462 ; RV32I-NEXT: sub a4, a4, t1
1463 ; RV32I-NEXT: sub a4, a4, t3
1464 ; RV32I-NEXT: sub a6, t2, t0
1465 ; RV32I-NEXT: sub a1, a1, a7
1466 ; RV32I-NEXT: sub a1, a1, a5
1467 ; RV32I-NEXT: sub a2, a2, a3
1468 ; RV32I-NEXT: sw a2, 0(a0)
1469 ; RV32I-NEXT: sw a1, 4(a0)
1470 ; RV32I-NEXT: sw a6, 8(a0)
1471 ; RV32I-NEXT: sw a4, 12(a0)
1472 ; RV32I-NEXT: ret
1473 ;
1474 ; RV32IM-LABEL: muli128_m63:
1475 ; RV32IM: # %bb.0:
1476 ; RV32IM-NEXT: addi sp, sp, -16
1477 ; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
1478 ; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
1479 ; RV32IM-NEXT: lw a2, 12(a1)
1480 ; RV32IM-NEXT: lw a3, 0(a1)
1481 ; RV32IM-NEXT: lw a4, 4(a1)
1482 ; RV32IM-NEXT: lw a1, 8(a1)
1483 ; RV32IM-NEXT: li a5, -63
1484 ; RV32IM-NEXT: mulhu a6, a3, a5
1485 ; RV32IM-NEXT: slli a7, a4, 6
1486 ; RV32IM-NEXT: sub a7, a4, a7
1487 ; RV32IM-NEXT: add a6, a7, a6
1488 ; RV32IM-NEXT: sltu a7, a6, a7
1489 ; RV32IM-NEXT: mulhu t0, a4, a5
1490 ; RV32IM-NEXT: add a7, t0, a7
1491 ; RV32IM-NEXT: sub a6, a6, a3
1492 ; RV32IM-NEXT: neg t0, a3
1493 ; RV32IM-NEXT: sltu t1, a6, t0
1494 ; RV32IM-NEXT: li t2, -1
1495 ; RV32IM-NEXT: mulhu t3, a3, t2
1496 ; RV32IM-NEXT: add t1, t3, t1
1497 ; RV32IM-NEXT: add t1, a7, t1
1498 ; RV32IM-NEXT: sub t4, t1, a4
1499 ; RV32IM-NEXT: slli t5, a1, 6
1500 ; RV32IM-NEXT: sub t6, a1, a3
1501 ; RV32IM-NEXT: sub t5, t6, t5
1502 ; RV32IM-NEXT: add t6, t4, t5
1503 ; RV32IM-NEXT: sltu s0, t6, t4
1504 ; RV32IM-NEXT: neg s1, a4
1505 ; RV32IM-NEXT: sltu t4, t4, s1
1506 ; RV32IM-NEXT: sltu a7, t1, a7
1507 ; RV32IM-NEXT: mulhu t1, a4, t2
1508 ; RV32IM-NEXT: add a7, t1, a7
1509 ; RV32IM-NEXT: add a7, a7, t4
1510 ; RV32IM-NEXT: sltu t0, t5, t0
1511 ; RV32IM-NEXT: slli t1, a2, 6
1512 ; RV32IM-NEXT: sub a2, a2, t1
1513 ; RV32IM-NEXT: mulhu a5, a1, a5
1514 ; RV32IM-NEXT: sub a5, a5, a1
1515 ; RV32IM-NEXT: add a2, a5, a2
1516 ; RV32IM-NEXT: add a4, a3, a4
1517 ; RV32IM-NEXT: sub a1, t3, a4
1518 ; RV32IM-NEXT: add a1, a1, a2
1519 ; RV32IM-NEXT: add a1, a1, t0
1520 ; RV32IM-NEXT: add a1, a7, a1
1521 ; RV32IM-NEXT: add a1, a1, s0
1522 ; RV32IM-NEXT: slli a2, a3, 6
1523 ; RV32IM-NEXT: sub a3, a3, a2
1524 ; RV32IM-NEXT: sw a3, 0(a0)
1525 ; RV32IM-NEXT: sw a6, 4(a0)
1526 ; RV32IM-NEXT: sw t6, 8(a0)
1527 ; RV32IM-NEXT: sw a1, 12(a0)
1528 ; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
1529 ; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
1530 ; RV32IM-NEXT: addi sp, sp, 16
1531 ; RV32IM-NEXT: ret
1532 ;
1533 ; RV64I-LABEL: muli128_m63:
1534 ; RV64I: # %bb.0:
1535 ; RV64I-NEXT: slli a2, a0, 6
1536 ; RV64I-NEXT: sltu a3, a0, a2
1537 ; RV64I-NEXT: srli a4, a0, 58
1538 ; RV64I-NEXT: slli a5, a1, 6
1539 ; RV64I-NEXT: or a4, a5, a4
1540 ; RV64I-NEXT: sub a1, a1, a4
1541 ; RV64I-NEXT: sub a1, a1, a3
1542 ; RV64I-NEXT: sub a0, a0, a2
1543 ; RV64I-NEXT: ret
1544 ;
1545 ; RV64IM-LABEL: muli128_m63:
1546 ; RV64IM: # %bb.0:
1547 ; RV64IM-NEXT: slli a2, a1, 6
1548 ; RV64IM-NEXT: sub a1, a1, a2
1549 ; RV64IM-NEXT: li a2, -63
1550 ; RV64IM-NEXT: mulhu a2, a0, a2
1551 ; RV64IM-NEXT: sub a2, a2, a0
1552 ; RV64IM-NEXT: add a1, a2, a1
1553 ; RV64IM-NEXT: slli a2, a0, 6
1554 ; RV64IM-NEXT: sub a0, a0, a2
1555 ; RV64IM-NEXT: ret
1556 %1 = mul i128 %a, -63
1557 ret i128 %1
1558 }
1560 define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
1561 ; RV32I-LABEL: mulhsu_i64:
1562 ; RV32I: # %bb.0:
1563 ; RV32I-NEXT: addi sp, sp, -48
1564 ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
1565 ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
1566 ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
1567 ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
1568 ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
1569 ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
1570 ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
1571 ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
1572 ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
1573 ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
1574 ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
1575 ; RV32I-NEXT: mv s2, a3
1576 ; RV32I-NEXT: mv s3, a2
1577 ; RV32I-NEXT: mv s0, a1
1578 ; RV32I-NEXT: mv s1, a0
1579 ; RV32I-NEXT: srai s4, a3, 31
1580 ; RV32I-NEXT: li a1, 0
1581 ; RV32I-NEXT: li a3, 0
1582 ; RV32I-NEXT: call __muldi3
1583 ; RV32I-NEXT: mv s5, a1
1584 ; RV32I-NEXT: mv a0, s0
1585 ; RV32I-NEXT: li a1, 0
1586 ; RV32I-NEXT: mv a2, s3
1587 ; RV32I-NEXT: li a3, 0
1588 ; RV32I-NEXT: call __muldi3
1589 ; RV32I-NEXT: add s5, a0, s5
1590 ; RV32I-NEXT: sltu a0, s5, a0
1591 ; RV32I-NEXT: add s7, a1, a0
1592 ; RV32I-NEXT: mv a0, s1
1593 ; RV32I-NEXT: li a1, 0
1594 ; RV32I-NEXT: mv a2, s2
1595 ; RV32I-NEXT: li a3, 0
1596 ; RV32I-NEXT: call __muldi3
1597 ; RV32I-NEXT: add s5, a0, s5
1598 ; RV32I-NEXT: sltu a0, s5, a0
1599 ; RV32I-NEXT: add a0, a1, a0
1600 ; RV32I-NEXT: add s8, s7, a0
1601 ; RV32I-NEXT: mv a0, s0
1602 ; RV32I-NEXT: li a1, 0
1603 ; RV32I-NEXT: mv a2, s2
1604 ; RV32I-NEXT: li a3, 0
1605 ; RV32I-NEXT: call __muldi3
1606 ; RV32I-NEXT: mv s5, a0
1607 ; RV32I-NEXT: mv s6, a1
1608 ; RV32I-NEXT: add s9, a0, s8
1609 ; RV32I-NEXT: mv a0, s3
1610 ; RV32I-NEXT: mv a1, s2
1611 ; RV32I-NEXT: li a2, 0
1612 ; RV32I-NEXT: li a3, 0
1613 ; RV32I-NEXT: call __muldi3
1614 ; RV32I-NEXT: mv s2, a0
1615 ; RV32I-NEXT: mv s3, a1
1616 ; RV32I-NEXT: mv a0, s4
1617 ; RV32I-NEXT: mv a1, s4
1618 ; RV32I-NEXT: mv a2, s1
1619 ; RV32I-NEXT: mv a3, s0
1620 ; RV32I-NEXT: call __muldi3
1621 ; RV32I-NEXT: add s2, a0, s2
1622 ; RV32I-NEXT: add a2, s9, s2
1623 ; RV32I-NEXT: sltu a3, a2, s9
1624 ; RV32I-NEXT: sltu a4, s9, s5
1625 ; RV32I-NEXT: sltu a5, s8, s7
1626 ; RV32I-NEXT: add a5, s6, a5
1627 ; RV32I-NEXT: add a4, a5, a4
1628 ; RV32I-NEXT: add a1, a1, s3
1629 ; RV32I-NEXT: sltu a0, s2, a0
1630 ; RV32I-NEXT: add a0, a1, a0
1631 ; RV32I-NEXT: add a0, a4, a0
1632 ; RV32I-NEXT: add a1, a0, a3
1633 ; RV32I-NEXT: mv a0, a2
1634 ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
1635 ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
1636 ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
1637 ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
1638 ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
1639 ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
1640 ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
1641 ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
1642 ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
1643 ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
1644 ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
1645 ; RV32I-NEXT: addi sp, sp, 48
1646 ; RV32I-NEXT: ret
1647 ;
1648 ; RV32IM-LABEL: mulhsu_i64:
1649 ; RV32IM: # %bb.0:
1650 ; RV32IM-NEXT: srai a4, a3, 31
1651 ; RV32IM-NEXT: mulhu a5, a0, a2
1652 ; RV32IM-NEXT: mul a6, a1, a2
1653 ; RV32IM-NEXT: add a5, a6, a5
1654 ; RV32IM-NEXT: sltu a6, a5, a6
1655 ; RV32IM-NEXT: mulhu a2, a1, a2
1656 ; RV32IM-NEXT: add a6, a2, a6
1657 ; RV32IM-NEXT: mul a2, a0, a3
1658 ; RV32IM-NEXT: add a5, a2, a5
1659 ; RV32IM-NEXT: sltu a2, a5, a2
1660 ; RV32IM-NEXT: mulhu a5, a0, a3
1661 ; RV32IM-NEXT: add a2, a5, a2
1662 ; RV32IM-NEXT: add a5, a6, a2
1663 ; RV32IM-NEXT: mul a7, a1, a3
1664 ; RV32IM-NEXT: add t0, a7, a5
1665 ; RV32IM-NEXT: mul t1, a4, a0
1666 ; RV32IM-NEXT: add a2, t0, t1
1667 ; RV32IM-NEXT: sltu t2, a2, t0
1668 ; RV32IM-NEXT: sltu a7, t0, a7
1669 ; RV32IM-NEXT: sltu a5, a5, a6
1670 ; RV32IM-NEXT: mulhu a3, a1, a3
1671 ; RV32IM-NEXT: add a3, a3, a5
1672 ; RV32IM-NEXT: add a3, a3, a7
1673 ; RV32IM-NEXT: mul a1, a4, a1
1674 ; RV32IM-NEXT: mulhu a0, a4, a0
1675 ; RV32IM-NEXT: add a0, a0, a1
1676 ; RV32IM-NEXT: add a0, a0, t1
1677 ; RV32IM-NEXT: add a0, a3, a0
1678 ; RV32IM-NEXT: add a1, a0, t2
1679 ; RV32IM-NEXT: mv a0, a2
1680 ; RV32IM-NEXT: ret
1681 ;
1682 ; RV64I-LABEL: mulhsu_i64:
1683 ; RV64I: # %bb.0:
1684 ; RV64I-NEXT: addi sp, sp, -16
1685 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1686 ; RV64I-NEXT: mv a2, a1
1687 ; RV64I-NEXT: srai a3, a1, 63
1688 ; RV64I-NEXT: li a1, 0
1689 ; RV64I-NEXT: call __multi3
1690 ; RV64I-NEXT: mv a0, a1
1691 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1692 ; RV64I-NEXT: addi sp, sp, 16
1693 ; RV64I-NEXT: ret
1694 ;
1695 ; RV64IM-LABEL: mulhsu_i64:
1696 ; RV64IM: # %bb.0:
1697 ; RV64IM-NEXT: mulhsu a0, a1, a0
1698 ; RV64IM-NEXT: ret
1699 %1 = zext i64 %a to i128
1700 %2 = sext i64 %b to i128
1701 %3 = mul i128 %1, %2
1702 %4 = lshr i128 %3, 64
1703 %5 = trunc i128 %4 to i64
1704 ret i64 %5
1705 }
1707 define i8 @muladd_demand(i8 %x, i8 %y) nounwind {
1708 ; RV32I-LABEL: muladd_demand:
1709 ; RV32I: # %bb.0:
1710 ; RV32I-NEXT: slli a0, a0, 1
1711 ; RV32I-NEXT: sub a0, a1, a0
1712 ; RV32I-NEXT: andi a0, a0, 15
1713 ; RV32I-NEXT: ret
1714 ;
1715 ; RV32IM-LABEL: muladd_demand:
1716 ; RV32IM: # %bb.0:
1717 ; RV32IM-NEXT: slli a0, a0, 1
1718 ; RV32IM-NEXT: sub a0, a1, a0
1719 ; RV32IM-NEXT: andi a0, a0, 15
1720 ; RV32IM-NEXT: ret
1721 ;
1722 ; RV64I-LABEL: muladd_demand:
1723 ; RV64I: # %bb.0:
1724 ; RV64I-NEXT: slli a0, a0, 1
1725 ; RV64I-NEXT: subw a0, a1, a0
1726 ; RV64I-NEXT: andi a0, a0, 15
1727 ; RV64I-NEXT: ret
1728 ;
1729 ; RV64IM-LABEL: muladd_demand:
1730 ; RV64IM: # %bb.0:
1731 ; RV64IM-NEXT: slli a0, a0, 1
1732 ; RV64IM-NEXT: subw a0, a1, a0
1733 ; RV64IM-NEXT: andi a0, a0, 15
1734 ; RV64IM-NEXT: ret
1735 %m = mul i8 %x, 14
1736 %a = add i8 %y, %m
1737 %r = and i8 %a, 15
1738 ret i8 %r
1739 }
1741 define i8 @mulsub_demand(i8 %x, i8 %y) nounwind {
1742 ; RV32I-LABEL: mulsub_demand:
1743 ; RV32I: # %bb.0:
1744 ; RV32I-NEXT: slli a0, a0, 1
1745 ; RV32I-NEXT: add a0, a1, a0
1746 ; RV32I-NEXT: andi a0, a0, 15
1747 ; RV32I-NEXT: ret
1748 ;
1749 ; RV32IM-LABEL: mulsub_demand:
1750 ; RV32IM: # %bb.0:
1751 ; RV32IM-NEXT: slli a0, a0, 1
1752 ; RV32IM-NEXT: add a0, a1, a0
1753 ; RV32IM-NEXT: andi a0, a0, 15
1754 ; RV32IM-NEXT: ret
1755 ;
1756 ; RV64I-LABEL: mulsub_demand:
1757 ; RV64I: # %bb.0:
1758 ; RV64I-NEXT: slli a0, a0, 1
1759 ; RV64I-NEXT: add a0, a1, a0
1760 ; RV64I-NEXT: andi a0, a0, 15
1761 ; RV64I-NEXT: ret
1762 ;
1763 ; RV64IM-LABEL: mulsub_demand:
1764 ; RV64IM: # %bb.0:
1765 ; RV64IM-NEXT: slli a0, a0, 1
1766 ; RV64IM-NEXT: add a0, a1, a0
1767 ; RV64IM-NEXT: andi a0, a0, 15
1768 ; RV64IM-NEXT: ret
1769 %m = mul i8 %x, 14
1770 %a = sub i8 %y, %m
1771 %r = and i8 %a, 15
1772 ret i8 %r
1773 }
1775 define i8 @muladd_demand_2(i8 %x, i8 %y) nounwind {
1776 ; RV32I-LABEL: muladd_demand_2:
1777 ; RV32I: # %bb.0:
1778 ; RV32I-NEXT: slli a0, a0, 1
1779 ; RV32I-NEXT: sub a1, a1, a0
1780 ; RV32I-NEXT: ori a0, a1, -16
1781 ; RV32I-NEXT: ret
1782 ;
1783 ; RV32IM-LABEL: muladd_demand_2:
1784 ; RV32IM: # %bb.0:
1785 ; RV32IM-NEXT: slli a0, a0, 1
1786 ; RV32IM-NEXT: sub a1, a1, a0
1787 ; RV32IM-NEXT: ori a0, a1, -16
1788 ; RV32IM-NEXT: ret
1789 ;
1790 ; RV64I-LABEL: muladd_demand_2:
1791 ; RV64I: # %bb.0:
1792 ; RV64I-NEXT: slli a0, a0, 1
1793 ; RV64I-NEXT: subw a1, a1, a0
1794 ; RV64I-NEXT: ori a0, a1, -16
1795 ; RV64I-NEXT: ret
1796 ;
1797 ; RV64IM-LABEL: muladd_demand_2:
1798 ; RV64IM: # %bb.0:
1799 ; RV64IM-NEXT: slli a0, a0, 1
1800 ; RV64IM-NEXT: subw a1, a1, a0
1801 ; RV64IM-NEXT: ori a0, a1, -16
1802 ; RV64IM-NEXT: ret
1803 %m = mul i8 %x, 14
1804 %a = add i8 %y, %m
1805 %r = or i8 %a, 240
1806 ret i8 %r
1807 }
1809 define i8 @mulsub_demand_2(i8 %x, i8 %y) nounwind {
1810 ; RV32I-LABEL: mulsub_demand_2:
1811 ; RV32I: # %bb.0:
1812 ; RV32I-NEXT: slli a0, a0, 1
1813 ; RV32I-NEXT: add a0, a1, a0
1814 ; RV32I-NEXT: ori a0, a0, -16
1815 ; RV32I-NEXT: ret
1816 ;
1817 ; RV32IM-LABEL: mulsub_demand_2:
1818 ; RV32IM: # %bb.0:
1819 ; RV32IM-NEXT: slli a0, a0, 1
1820 ; RV32IM-NEXT: add a0, a1, a0
1821 ; RV32IM-NEXT: ori a0, a0, -16
1822 ; RV32IM-NEXT: ret
1823 ;
1824 ; RV64I-LABEL: mulsub_demand_2:
1825 ; RV64I: # %bb.0:
1826 ; RV64I-NEXT: slli a0, a0, 1
1827 ; RV64I-NEXT: add a0, a1, a0
1828 ; RV64I-NEXT: ori a0, a0, -16
1829 ; RV64I-NEXT: ret
1830 ;
1831 ; RV64IM-LABEL: mulsub_demand_2:
1832 ; RV64IM: # %bb.0:
1833 ; RV64IM-NEXT: slli a0, a0, 1
1834 ; RV64IM-NEXT: add a0, a1, a0
1835 ; RV64IM-NEXT: ori a0, a0, -16
1836 ; RV64IM-NEXT: ret
1837 %m = mul i8 %x, 14
1838 %a = sub i8 %y, %m
1839 %r = or i8 %a, 240
1840 ret i8 %r
1841 }
1843 define i64 @muland_demand(i64 %x) nounwind {
1844 ; RV32I-LABEL: muland_demand:
1845 ; RV32I: # %bb.0:
1846 ; RV32I-NEXT: addi sp, sp, -16
1847 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1848 ; RV32I-NEXT: andi a0, a0, -8
1849 ; RV32I-NEXT: slli a1, a1, 2
1850 ; RV32I-NEXT: srli a1, a1, 2
1851 ; RV32I-NEXT: li a2, 12
1852 ; RV32I-NEXT: li a3, 0
1853 ; RV32I-NEXT: call __muldi3
1854 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1855 ; RV32I-NEXT: addi sp, sp, 16
1856 ; RV32I-NEXT: ret
1857 ;
1858 ; RV32IM-LABEL: muland_demand:
1859 ; RV32IM: # %bb.0:
1860 ; RV32IM-NEXT: andi a0, a0, -8
1861 ; RV32IM-NEXT: slli a2, a1, 2
1862 ; RV32IM-NEXT: slli a1, a1, 4
1863 ; RV32IM-NEXT: sub a1, a1, a2
1864 ; RV32IM-NEXT: li a2, 12
1865 ; RV32IM-NEXT: mulhu a2, a0, a2
1866 ; RV32IM-NEXT: add a1, a2, a1
1867 ; RV32IM-NEXT: slli a2, a0, 2
1868 ; RV32IM-NEXT: slli a0, a0, 4
1869 ; RV32IM-NEXT: sub a0, a0, a2
1870 ; RV32IM-NEXT: ret
1871 ;
1872 ; RV64I-LABEL: muland_demand:
1873 ; RV64I: # %bb.0:
1874 ; RV64I-NEXT: li a1, -29
1875 ; RV64I-NEXT: srli a1, a1, 2
1876 ; RV64I-NEXT: and a0, a0, a1
1877 ; RV64I-NEXT: li a1, 12
1878 ; RV64I-NEXT: tail __muldi3
1879 ;
1880 ; RV64IM-LABEL: muland_demand:
1881 ; RV64IM: # %bb.0:
1882 ; RV64IM-NEXT: andi a0, a0, -8
1883 ; RV64IM-NEXT: slli a1, a0, 2
1884 ; RV64IM-NEXT: slli a0, a0, 4
1885 ; RV64IM-NEXT: sub a0, a0, a1
1886 ; RV64IM-NEXT: ret
1887 %and = and i64 %x, 4611686018427387896
1888 %mul = mul i64 %and, 12
1889 ret i64 %mul
1890 }
1892 define i64 @mulzext_demand(i32 signext %x) nounwind {
1893 ; RV32I-LABEL: mulzext_demand:
1894 ; RV32I: # %bb.0:
1895 ; RV32I-NEXT: addi sp, sp, -16
1896 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1897 ; RV32I-NEXT: li a3, 3
1898 ; RV32I-NEXT: li a2, 0
1899 ; RV32I-NEXT: call __muldi3
1900 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1901 ; RV32I-NEXT: addi sp, sp, 16
1902 ; RV32I-NEXT: ret
1903 ;
1904 ; RV32IM-LABEL: mulzext_demand:
1905 ; RV32IM: # %bb.0:
1906 ; RV32IM-NEXT: slli a1, a0, 1
1907 ; RV32IM-NEXT: add a1, a1, a0
1908 ; RV32IM-NEXT: li a0, 0
1909 ; RV32IM-NEXT: ret
1910 ;
1911 ; RV64I-LABEL: mulzext_demand:
1912 ; RV64I: # %bb.0:
1913 ; RV64I-NEXT: li a1, 3
1914 ; RV64I-NEXT: slli a1, a1, 32
1915 ; RV64I-NEXT: tail __muldi3
1916 ;
1917 ; RV64IM-LABEL: mulzext_demand:
1918 ; RV64IM: # %bb.0:
1919 ; RV64IM-NEXT: slli a1, a0, 32
1920 ; RV64IM-NEXT: slli a0, a0, 34
1921 ; RV64IM-NEXT: sub a0, a0, a1
1922 ; RV64IM-NEXT: ret
1923 %ext = zext i32 %x to i64
1924 %mul = mul i64 %ext, 12884901888
1925 ret i64 %mul
1926 }
1928 define i32 @mulfshl_demand(i32 signext %x) nounwind {
1929 ; RV32I-LABEL: mulfshl_demand:
1930 ; RV32I: # %bb.0:
1931 ; RV32I-NEXT: srli a0, a0, 11
1932 ; RV32I-NEXT: lui a1, 92808
1933 ; RV32I-NEXT: tail __mulsi3
1934 ;
1935 ; RV32IM-LABEL: mulfshl_demand:
1936 ; RV32IM: # %bb.0:
1937 ; RV32IM-NEXT: srli a0, a0, 11
1938 ; RV32IM-NEXT: lui a1, 92808
1939 ; RV32IM-NEXT: mul a0, a0, a1
1940 ; RV32IM-NEXT: ret
1941 ;
1942 ; RV64I-LABEL: mulfshl_demand:
1943 ; RV64I: # %bb.0:
1944 ; RV64I-NEXT: addi sp, sp, -16
1945 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1946 ; RV64I-NEXT: srliw a0, a0, 11
1947 ; RV64I-NEXT: lui a1, 92808
1948 ; RV64I-NEXT: call __muldi3
1949 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1950 ; RV64I-NEXT: addi sp, sp, 16
1951 ; RV64I-NEXT: ret
1952 ;
1953 ; RV64IM-LABEL: mulfshl_demand:
1954 ; RV64IM: # %bb.0:
1955 ; RV64IM-NEXT: srliw a0, a0, 11
1956 ; RV64IM-NEXT: lui a1, 92808
1957 ; RV64IM-NEXT: mulw a0, a0, a1
1958 ; RV64IM-NEXT: ret
1959 %fshl = tail call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 21)
1960 %mul = mul i32 %fshl, 380141568
1961 ret i32 %mul
1962 }
1964 define i32 @mulor_demand(i32 signext %x, i32 signext %y) nounwind {
1965 ; RV32I-LABEL: mulor_demand:
1966 ; RV32I: # %bb.0:
1967 ; RV32I-NEXT: lui a1, 92808
1968 ; RV32I-NEXT: tail __mulsi3
1969 ;
1970 ; RV32IM-LABEL: mulor_demand:
1971 ; RV32IM: # %bb.0:
1972 ; RV32IM-NEXT: lui a1, 92808
1973 ; RV32IM-NEXT: mul a0, a0, a1
1974 ; RV32IM-NEXT: ret
1975 ;
1976 ; RV64I-LABEL: mulor_demand:
1977 ; RV64I: # %bb.0:
1978 ; RV64I-NEXT: addi sp, sp, -16
1979 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1980 ; RV64I-NEXT: lui a1, 92808
1981 ; RV64I-NEXT: call __muldi3
1982 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1983 ; RV64I-NEXT: addi sp, sp, 16
1984 ; RV64I-NEXT: ret
1985 ;
1986 ; RV64IM-LABEL: mulor_demand:
1987 ; RV64IM: # %bb.0:
1988 ; RV64IM-NEXT: lui a1, 92808
1989 ; RV64IM-NEXT: mulw a0, a0, a1
1990 ; RV64IM-NEXT: ret
1991 %mul1 = mul i32 %y, 10485760
1992 %or = or disjoint i32 %mul1, %x
1993 %mul2 = mul i32 %or, 380141568
1994 ret i32 %mul2
1995 }