| blob | 4c5c36fc72d14db86ff8948afd22230b4297c55a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh < %s | FileCheck %s -check-prefix=CHECK-RV64
3 ; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh < %s | FileCheck %s -check-prefix=CHECK-RV32
4 ; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+c < %s | FileCheck %s -check-prefix=CHECK-RV64C
5 ; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+c < %s | FileCheck %s -check-prefix=CHECK-RV32C
6 ; RUN: llc -mtriple=riscv64 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV64V
7 ; RUN: llc -mtriple=riscv32 -mattr=+zihintntl,+f,+d,+zfh,+v < %s | FileCheck %s -check-prefix=CHECK-RV32V
9 define i64 @test_nontemporal_load_i64(ptr %p) {
10 ; CHECK-RV64-LABEL: test_nontemporal_load_i64:
11 ; CHECK-RV64: # %bb.0:
12 ; CHECK-RV64-NEXT: ntl.all
13 ; CHECK-RV64-NEXT: ld a0, 0(a0)
14 ; CHECK-RV64-NEXT: ret
15 ;
16 ; CHECK-RV32-LABEL: test_nontemporal_load_i64:
17 ; CHECK-RV32: # %bb.0:
18 ; CHECK-RV32-NEXT: ntl.all
19 ; CHECK-RV32-NEXT: lw a2, 0(a0)
20 ; CHECK-RV32-NEXT: ntl.all
21 ; CHECK-RV32-NEXT: lw a1, 4(a0)
22 ; CHECK-RV32-NEXT: mv a0, a2
23 ; CHECK-RV32-NEXT: ret
24 ;
25 ; CHECK-RV64C-LABEL: test_nontemporal_load_i64:
26 ; CHECK-RV64C: # %bb.0:
27 ; CHECK-RV64C-NEXT: c.ntl.all
28 ; CHECK-RV64C-NEXT: ld a0, 0(a0)
29 ; CHECK-RV64C-NEXT: ret
30 ;
31 ; CHECK-RV32C-LABEL: test_nontemporal_load_i64:
32 ; CHECK-RV32C: # %bb.0:
33 ; CHECK-RV32C-NEXT: c.ntl.all
34 ; CHECK-RV32C-NEXT: lw a2, 0(a0)
35 ; CHECK-RV32C-NEXT: c.ntl.all
36 ; CHECK-RV32C-NEXT: lw a1, 4(a0)
37 ; CHECK-RV32C-NEXT: mv a0, a2
38 ; CHECK-RV32C-NEXT: ret
39 ;
40 ; CHECK-RV64V-LABEL: test_nontemporal_load_i64:
41 ; CHECK-RV64V: # %bb.0:
42 ; CHECK-RV64V-NEXT: ntl.all
43 ; CHECK-RV64V-NEXT: ld a0, 0(a0)
44 ; CHECK-RV64V-NEXT: ret
45 ;
46 ; CHECK-RV32V-LABEL: test_nontemporal_load_i64:
47 ; CHECK-RV32V: # %bb.0:
48 ; CHECK-RV32V-NEXT: ntl.all
49 ; CHECK-RV32V-NEXT: lw a2, 0(a0)
50 ; CHECK-RV32V-NEXT: ntl.all
51 ; CHECK-RV32V-NEXT: lw a1, 4(a0)
52 ; CHECK-RV32V-NEXT: mv a0, a2
53 ; CHECK-RV32V-NEXT: ret
55 %1 = load i64, ptr %p, !nontemporal !0
56 ret i64 %1
57 }
59 define i32 @test_nontemporal_load_i32(ptr %p) {
60 ; CHECK-RV64-LABEL: test_nontemporal_load_i32:
61 ; CHECK-RV64: # %bb.0:
62 ; CHECK-RV64-NEXT: ntl.all
63 ; CHECK-RV64-NEXT: lw a0, 0(a0)
64 ; CHECK-RV64-NEXT: ret
65 ;
66 ; CHECK-RV32-LABEL: test_nontemporal_load_i32:
67 ; CHECK-RV32: # %bb.0:
68 ; CHECK-RV32-NEXT: ntl.all
69 ; CHECK-RV32-NEXT: lw a0, 0(a0)
70 ; CHECK-RV32-NEXT: ret
71 ;
72 ; CHECK-RV64C-LABEL: test_nontemporal_load_i32:
73 ; CHECK-RV64C: # %bb.0:
74 ; CHECK-RV64C-NEXT: c.ntl.all
75 ; CHECK-RV64C-NEXT: lw a0, 0(a0)
76 ; CHECK-RV64C-NEXT: ret
77 ;
78 ; CHECK-RV32C-LABEL: test_nontemporal_load_i32:
79 ; CHECK-RV32C: # %bb.0:
80 ; CHECK-RV32C-NEXT: c.ntl.all
81 ; CHECK-RV32C-NEXT: lw a0, 0(a0)
82 ; CHECK-RV32C-NEXT: ret
83 ;
84 ; CHECK-RV64V-LABEL: test_nontemporal_load_i32:
85 ; CHECK-RV64V: # %bb.0:
86 ; CHECK-RV64V-NEXT: ntl.all
87 ; CHECK-RV64V-NEXT: lw a0, 0(a0)
88 ; CHECK-RV64V-NEXT: ret
89 ;
90 ; CHECK-RV32V-LABEL: test_nontemporal_load_i32:
91 ; CHECK-RV32V: # %bb.0:
92 ; CHECK-RV32V-NEXT: ntl.all
93 ; CHECK-RV32V-NEXT: lw a0, 0(a0)
94 ; CHECK-RV32V-NEXT: ret
96 %1 = load i32, ptr %p, !nontemporal !0
97 ret i32 %1
98 }
100 define i16 @test_nontemporal_load_i16(ptr %p) {
101 ; CHECK-RV64-LABEL: test_nontemporal_load_i16:
102 ; CHECK-RV64: # %bb.0:
103 ; CHECK-RV64-NEXT: ntl.all
104 ; CHECK-RV64-NEXT: lh a0, 0(a0)
105 ; CHECK-RV64-NEXT: ret
106 ;
107 ; CHECK-RV32-LABEL: test_nontemporal_load_i16:
108 ; CHECK-RV32: # %bb.0:
109 ; CHECK-RV32-NEXT: ntl.all
110 ; CHECK-RV32-NEXT: lh a0, 0(a0)
111 ; CHECK-RV32-NEXT: ret
112 ;
113 ; CHECK-RV64C-LABEL: test_nontemporal_load_i16:
114 ; CHECK-RV64C: # %bb.0:
115 ; CHECK-RV64C-NEXT: c.ntl.all
116 ; CHECK-RV64C-NEXT: lh a0, 0(a0)
117 ; CHECK-RV64C-NEXT: ret
118 ;
119 ; CHECK-RV32C-LABEL: test_nontemporal_load_i16:
120 ; CHECK-RV32C: # %bb.0:
121 ; CHECK-RV32C-NEXT: c.ntl.all
122 ; CHECK-RV32C-NEXT: lh a0, 0(a0)
123 ; CHECK-RV32C-NEXT: ret
124 ;
125 ; CHECK-RV64V-LABEL: test_nontemporal_load_i16:
126 ; CHECK-RV64V: # %bb.0:
127 ; CHECK-RV64V-NEXT: ntl.all
128 ; CHECK-RV64V-NEXT: lh a0, 0(a0)
129 ; CHECK-RV64V-NEXT: ret
130 ;
131 ; CHECK-RV32V-LABEL: test_nontemporal_load_i16:
132 ; CHECK-RV32V: # %bb.0:
133 ; CHECK-RV32V-NEXT: ntl.all
134 ; CHECK-RV32V-NEXT: lh a0, 0(a0)
135 ; CHECK-RV32V-NEXT: ret
137 %1 = load i16, ptr %p, !nontemporal !0
138 ret i16 %1
139 }
141 define i8 @test_nontemporal_load_i8(ptr %p) {
142 ; CHECK-RV64-LABEL: test_nontemporal_load_i8:
143 ; CHECK-RV64: # %bb.0:
144 ; CHECK-RV64-NEXT: ntl.all
145 ; CHECK-RV64-NEXT: lbu a0, 0(a0)
146 ; CHECK-RV64-NEXT: ret
147 ;
148 ; CHECK-RV32-LABEL: test_nontemporal_load_i8:
149 ; CHECK-RV32: # %bb.0:
150 ; CHECK-RV32-NEXT: ntl.all
151 ; CHECK-RV32-NEXT: lbu a0, 0(a0)
152 ; CHECK-RV32-NEXT: ret
153 ;
154 ; CHECK-RV64C-LABEL: test_nontemporal_load_i8:
155 ; CHECK-RV64C: # %bb.0:
156 ; CHECK-RV64C-NEXT: c.ntl.all
157 ; CHECK-RV64C-NEXT: lbu a0, 0(a0)
158 ; CHECK-RV64C-NEXT: ret
159 ;
160 ; CHECK-RV32C-LABEL: test_nontemporal_load_i8:
161 ; CHECK-RV32C: # %bb.0:
162 ; CHECK-RV32C-NEXT: c.ntl.all
163 ; CHECK-RV32C-NEXT: lbu a0, 0(a0)
164 ; CHECK-RV32C-NEXT: ret
165 ;
166 ; CHECK-RV64V-LABEL: test_nontemporal_load_i8:
167 ; CHECK-RV64V: # %bb.0:
168 ; CHECK-RV64V-NEXT: ntl.all
169 ; CHECK-RV64V-NEXT: lbu a0, 0(a0)
170 ; CHECK-RV64V-NEXT: ret
171 ;
172 ; CHECK-RV32V-LABEL: test_nontemporal_load_i8:
173 ; CHECK-RV32V: # %bb.0:
174 ; CHECK-RV32V-NEXT: ntl.all
175 ; CHECK-RV32V-NEXT: lbu a0, 0(a0)
176 ; CHECK-RV32V-NEXT: ret
178 %1 = load i8, ptr %p, !nontemporal !0
179 ret i8 %1
180 }
182 define half @test_nontemporal_load_half(ptr %p) nounwind {
183 ; CHECK-RV64-LABEL: test_nontemporal_load_half:
184 ; CHECK-RV64: # %bb.0:
185 ; CHECK-RV64-NEXT: ntl.all
186 ; CHECK-RV64-NEXT: flh fa5, 0(a0)
187 ; CHECK-RV64-NEXT: ntl.all
188 ; CHECK-RV64-NEXT: flh fa4, 6(a0)
189 ; CHECK-RV64-NEXT: fadd.h fa0, fa5, fa4
190 ; CHECK-RV64-NEXT: ret
191 ;
192 ; CHECK-RV32-LABEL: test_nontemporal_load_half:
193 ; CHECK-RV32: # %bb.0:
194 ; CHECK-RV32-NEXT: ntl.all
195 ; CHECK-RV32-NEXT: flh fa5, 0(a0)
196 ; CHECK-RV32-NEXT: ntl.all
197 ; CHECK-RV32-NEXT: flh fa4, 6(a0)
198 ; CHECK-RV32-NEXT: fadd.h fa0, fa5, fa4
199 ; CHECK-RV32-NEXT: ret
200 ;
201 ; CHECK-RV64C-LABEL: test_nontemporal_load_half:
202 ; CHECK-RV64C: # %bb.0:
203 ; CHECK-RV64C-NEXT: c.ntl.all
204 ; CHECK-RV64C-NEXT: flh fa5, 0(a0)
205 ; CHECK-RV64C-NEXT: c.ntl.all
206 ; CHECK-RV64C-NEXT: flh fa4, 6(a0)
207 ; CHECK-RV64C-NEXT: fadd.h fa0, fa5, fa4
208 ; CHECK-RV64C-NEXT: ret
209 ;
210 ; CHECK-RV32C-LABEL: test_nontemporal_load_half:
211 ; CHECK-RV32C: # %bb.0:
212 ; CHECK-RV32C-NEXT: c.ntl.all
213 ; CHECK-RV32C-NEXT: flh fa5, 0(a0)
214 ; CHECK-RV32C-NEXT: c.ntl.all
215 ; CHECK-RV32C-NEXT: flh fa4, 6(a0)
216 ; CHECK-RV32C-NEXT: fadd.h fa0, fa5, fa4
217 ; CHECK-RV32C-NEXT: ret
218 ;
219 ; CHECK-RV64V-LABEL: test_nontemporal_load_half:
220 ; CHECK-RV64V: # %bb.0:
221 ; CHECK-RV64V-NEXT: ntl.all
222 ; CHECK-RV64V-NEXT: flh fa5, 0(a0)
223 ; CHECK-RV64V-NEXT: ntl.all
224 ; CHECK-RV64V-NEXT: flh fa4, 6(a0)
225 ; CHECK-RV64V-NEXT: fadd.h fa0, fa5, fa4
226 ; CHECK-RV64V-NEXT: ret
227 ;
228 ; CHECK-RV32V-LABEL: test_nontemporal_load_half:
229 ; CHECK-RV32V: # %bb.0:
230 ; CHECK-RV32V-NEXT: ntl.all
231 ; CHECK-RV32V-NEXT: flh fa5, 0(a0)
232 ; CHECK-RV32V-NEXT: ntl.all
233 ; CHECK-RV32V-NEXT: flh fa4, 6(a0)
234 ; CHECK-RV32V-NEXT: fadd.h fa0, fa5, fa4
235 ; CHECK-RV32V-NEXT: ret
237 %1 = load half, ptr %p, !nontemporal !0
238 %2 = getelementptr half, ptr %p, i32 3
239 %3 = load half, ptr %2, !nontemporal !0
240 %4 = fadd half %1, %3
241 ret half %4
242 }
244 define float @test_nontemporal_load_float(ptr %p) {
245 ; CHECK-RV64-LABEL: test_nontemporal_load_float:
246 ; CHECK-RV64: # %bb.0:
247 ; CHECK-RV64-NEXT: ntl.all
248 ; CHECK-RV64-NEXT: flw fa0, 0(a0)
249 ; CHECK-RV64-NEXT: ret
250 ;
251 ; CHECK-RV32-LABEL: test_nontemporal_load_float:
252 ; CHECK-RV32: # %bb.0:
253 ; CHECK-RV32-NEXT: ntl.all
254 ; CHECK-RV32-NEXT: flw fa0, 0(a0)
255 ; CHECK-RV32-NEXT: ret
256 ;
257 ; CHECK-RV64C-LABEL: test_nontemporal_load_float:
258 ; CHECK-RV64C: # %bb.0:
259 ; CHECK-RV64C-NEXT: c.ntl.all
260 ; CHECK-RV64C-NEXT: flw fa0, 0(a0)
261 ; CHECK-RV64C-NEXT: ret
262 ;
263 ; CHECK-RV32C-LABEL: test_nontemporal_load_float:
264 ; CHECK-RV32C: # %bb.0:
265 ; CHECK-RV32C-NEXT: c.ntl.all
266 ; CHECK-RV32C-NEXT: flw fa0, 0(a0)
267 ; CHECK-RV32C-NEXT: ret
268 ;
269 ; CHECK-RV64V-LABEL: test_nontemporal_load_float:
270 ; CHECK-RV64V: # %bb.0:
271 ; CHECK-RV64V-NEXT: ntl.all
272 ; CHECK-RV64V-NEXT: flw fa0, 0(a0)
273 ; CHECK-RV64V-NEXT: ret
274 ;
275 ; CHECK-RV32V-LABEL: test_nontemporal_load_float:
276 ; CHECK-RV32V: # %bb.0:
277 ; CHECK-RV32V-NEXT: ntl.all
278 ; CHECK-RV32V-NEXT: flw fa0, 0(a0)
279 ; CHECK-RV32V-NEXT: ret
281 %1 = load float, ptr %p, !nontemporal !0
282 ret float %1
283 }
285 define double @test_nontemporal_load_double(ptr %p) {
286 ; CHECK-RV64-LABEL: test_nontemporal_load_double:
287 ; CHECK-RV64: # %bb.0:
288 ; CHECK-RV64-NEXT: ntl.all
289 ; CHECK-RV64-NEXT: fld fa0, 0(a0)
290 ; CHECK-RV64-NEXT: ret
291 ;
292 ; CHECK-RV32-LABEL: test_nontemporal_load_double:
293 ; CHECK-RV32: # %bb.0:
294 ; CHECK-RV32-NEXT: ntl.all
295 ; CHECK-RV32-NEXT: fld fa0, 0(a0)
296 ; CHECK-RV32-NEXT: ret
297 ;
298 ; CHECK-RV64C-LABEL: test_nontemporal_load_double:
299 ; CHECK-RV64C: # %bb.0:
300 ; CHECK-RV64C-NEXT: c.ntl.all
301 ; CHECK-RV64C-NEXT: fld fa0, 0(a0)
302 ; CHECK-RV64C-NEXT: ret
303 ;
304 ; CHECK-RV32C-LABEL: test_nontemporal_load_double:
305 ; CHECK-RV32C: # %bb.0:
306 ; CHECK-RV32C-NEXT: c.ntl.all
307 ; CHECK-RV32C-NEXT: fld fa0, 0(a0)
308 ; CHECK-RV32C-NEXT: ret
309 ;
310 ; CHECK-RV64V-LABEL: test_nontemporal_load_double:
311 ; CHECK-RV64V: # %bb.0:
312 ; CHECK-RV64V-NEXT: ntl.all
313 ; CHECK-RV64V-NEXT: fld fa0, 0(a0)
314 ; CHECK-RV64V-NEXT: ret
315 ;
316 ; CHECK-RV32V-LABEL: test_nontemporal_load_double:
317 ; CHECK-RV32V: # %bb.0:
318 ; CHECK-RV32V-NEXT: ntl.all
319 ; CHECK-RV32V-NEXT: fld fa0, 0(a0)
320 ; CHECK-RV32V-NEXT: ret
322 %1 = load double, ptr %p, !nontemporal !0
323 ret double %1
324 }
326 define <16 x i8> @test_nontemporal_load_v16i8(ptr %p) {
327 ; CHECK-RV64-LABEL: test_nontemporal_load_v16i8:
328 ; CHECK-RV64: # %bb.0:
329 ; CHECK-RV64-NEXT: ntl.all
330 ; CHECK-RV64-NEXT: ld a2, 8(a1)
331 ; CHECK-RV64-NEXT: ntl.all
332 ; CHECK-RV64-NEXT: ld a1, 0(a1)
333 ; CHECK-RV64-NEXT: sd a2, 8(a0)
334 ; CHECK-RV64-NEXT: sd a1, 0(a0)
335 ; CHECK-RV64-NEXT: ret
336 ;
337 ; CHECK-RV32-LABEL: test_nontemporal_load_v16i8:
338 ; CHECK-RV32: # %bb.0:
339 ; CHECK-RV32-NEXT: ntl.all
340 ; CHECK-RV32-NEXT: lw a2, 12(a1)
341 ; CHECK-RV32-NEXT: ntl.all
342 ; CHECK-RV32-NEXT: lw a3, 8(a1)
343 ; CHECK-RV32-NEXT: ntl.all
344 ; CHECK-RV32-NEXT: lw a4, 4(a1)
345 ; CHECK-RV32-NEXT: ntl.all
346 ; CHECK-RV32-NEXT: lw a1, 0(a1)
347 ; CHECK-RV32-NEXT: sw a2, 12(a0)
348 ; CHECK-RV32-NEXT: sw a3, 8(a0)
349 ; CHECK-RV32-NEXT: sw a4, 4(a0)
350 ; CHECK-RV32-NEXT: sw a1, 0(a0)
351 ; CHECK-RV32-NEXT: ret
352 ;
353 ; CHECK-RV64C-LABEL: test_nontemporal_load_v16i8:
354 ; CHECK-RV64C: # %bb.0:
355 ; CHECK-RV64C-NEXT: c.ntl.all
356 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
357 ; CHECK-RV64C-NEXT: c.ntl.all
358 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
359 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
360 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
361 ; CHECK-RV64C-NEXT: ret
362 ;
363 ; CHECK-RV32C-LABEL: test_nontemporal_load_v16i8:
364 ; CHECK-RV32C: # %bb.0:
365 ; CHECK-RV32C-NEXT: c.ntl.all
366 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
367 ; CHECK-RV32C-NEXT: c.ntl.all
368 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
369 ; CHECK-RV32C-NEXT: c.ntl.all
370 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
371 ; CHECK-RV32C-NEXT: c.ntl.all
372 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
373 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
374 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
375 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
376 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
377 ; CHECK-RV32C-NEXT: ret
378 ;
379 ; CHECK-RV64V-LABEL: test_nontemporal_load_v16i8:
380 ; CHECK-RV64V: # %bb.0:
381 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
382 ; CHECK-RV64V-NEXT: ntl.all
383 ; CHECK-RV64V-NEXT: vle8.v v8, (a0)
384 ; CHECK-RV64V-NEXT: ret
385 ;
386 ; CHECK-RV32V-LABEL: test_nontemporal_load_v16i8:
387 ; CHECK-RV32V: # %bb.0:
388 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
389 ; CHECK-RV32V-NEXT: ntl.all
390 ; CHECK-RV32V-NEXT: vle8.v v8, (a0)
391 ; CHECK-RV32V-NEXT: ret
393 %1 = load <16 x i8>, ptr %p, !nontemporal !0
394 ret <16 x i8> %1
395 }
397 define <8 x i16> @test_nontemporal_load_v8i16(ptr %p) {
398 ; CHECK-RV64-LABEL: test_nontemporal_load_v8i16:
399 ; CHECK-RV64: # %bb.0:
400 ; CHECK-RV64-NEXT: ntl.all
401 ; CHECK-RV64-NEXT: ld a2, 8(a1)
402 ; CHECK-RV64-NEXT: ntl.all
403 ; CHECK-RV64-NEXT: ld a1, 0(a1)
404 ; CHECK-RV64-NEXT: sd a2, 8(a0)
405 ; CHECK-RV64-NEXT: sd a1, 0(a0)
406 ; CHECK-RV64-NEXT: ret
407 ;
408 ; CHECK-RV32-LABEL: test_nontemporal_load_v8i16:
409 ; CHECK-RV32: # %bb.0:
410 ; CHECK-RV32-NEXT: ntl.all
411 ; CHECK-RV32-NEXT: lw a2, 12(a1)
412 ; CHECK-RV32-NEXT: ntl.all
413 ; CHECK-RV32-NEXT: lw a3, 8(a1)
414 ; CHECK-RV32-NEXT: ntl.all
415 ; CHECK-RV32-NEXT: lw a4, 4(a1)
416 ; CHECK-RV32-NEXT: ntl.all
417 ; CHECK-RV32-NEXT: lw a1, 0(a1)
418 ; CHECK-RV32-NEXT: sw a2, 12(a0)
419 ; CHECK-RV32-NEXT: sw a3, 8(a0)
420 ; CHECK-RV32-NEXT: sw a4, 4(a0)
421 ; CHECK-RV32-NEXT: sw a1, 0(a0)
422 ; CHECK-RV32-NEXT: ret
423 ;
424 ; CHECK-RV64C-LABEL: test_nontemporal_load_v8i16:
425 ; CHECK-RV64C: # %bb.0:
426 ; CHECK-RV64C-NEXT: c.ntl.all
427 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
428 ; CHECK-RV64C-NEXT: c.ntl.all
429 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
430 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
431 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
432 ; CHECK-RV64C-NEXT: ret
433 ;
434 ; CHECK-RV32C-LABEL: test_nontemporal_load_v8i16:
435 ; CHECK-RV32C: # %bb.0:
436 ; CHECK-RV32C-NEXT: c.ntl.all
437 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
438 ; CHECK-RV32C-NEXT: c.ntl.all
439 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
440 ; CHECK-RV32C-NEXT: c.ntl.all
441 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
442 ; CHECK-RV32C-NEXT: c.ntl.all
443 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
444 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
445 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
446 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
447 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
448 ; CHECK-RV32C-NEXT: ret
449 ;
450 ; CHECK-RV64V-LABEL: test_nontemporal_load_v8i16:
451 ; CHECK-RV64V: # %bb.0:
452 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
453 ; CHECK-RV64V-NEXT: ntl.all
454 ; CHECK-RV64V-NEXT: vle16.v v8, (a0)
455 ; CHECK-RV64V-NEXT: ret
456 ;
457 ; CHECK-RV32V-LABEL: test_nontemporal_load_v8i16:
458 ; CHECK-RV32V: # %bb.0:
459 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
460 ; CHECK-RV32V-NEXT: ntl.all
461 ; CHECK-RV32V-NEXT: vle16.v v8, (a0)
462 ; CHECK-RV32V-NEXT: ret
464 %1 = load <8 x i16>, ptr %p, !nontemporal !0
465 ret <8 x i16> %1
466 }
468 define <4 x i32> @test_nontemporal_load_v4i32(ptr %p) {
469 ; CHECK-RV64-LABEL: test_nontemporal_load_v4i32:
470 ; CHECK-RV64: # %bb.0:
471 ; CHECK-RV64-NEXT: ntl.all
472 ; CHECK-RV64-NEXT: ld a2, 8(a1)
473 ; CHECK-RV64-NEXT: ntl.all
474 ; CHECK-RV64-NEXT: ld a1, 0(a1)
475 ; CHECK-RV64-NEXT: sd a2, 8(a0)
476 ; CHECK-RV64-NEXT: sd a1, 0(a0)
477 ; CHECK-RV64-NEXT: ret
478 ;
479 ; CHECK-RV32-LABEL: test_nontemporal_load_v4i32:
480 ; CHECK-RV32: # %bb.0:
481 ; CHECK-RV32-NEXT: ntl.all
482 ; CHECK-RV32-NEXT: lw a2, 12(a1)
483 ; CHECK-RV32-NEXT: ntl.all
484 ; CHECK-RV32-NEXT: lw a3, 8(a1)
485 ; CHECK-RV32-NEXT: ntl.all
486 ; CHECK-RV32-NEXT: lw a4, 4(a1)
487 ; CHECK-RV32-NEXT: ntl.all
488 ; CHECK-RV32-NEXT: lw a1, 0(a1)
489 ; CHECK-RV32-NEXT: sw a2, 12(a0)
490 ; CHECK-RV32-NEXT: sw a3, 8(a0)
491 ; CHECK-RV32-NEXT: sw a4, 4(a0)
492 ; CHECK-RV32-NEXT: sw a1, 0(a0)
493 ; CHECK-RV32-NEXT: ret
494 ;
495 ; CHECK-RV64C-LABEL: test_nontemporal_load_v4i32:
496 ; CHECK-RV64C: # %bb.0:
497 ; CHECK-RV64C-NEXT: c.ntl.all
498 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
499 ; CHECK-RV64C-NEXT: c.ntl.all
500 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
501 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
502 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
503 ; CHECK-RV64C-NEXT: ret
504 ;
505 ; CHECK-RV32C-LABEL: test_nontemporal_load_v4i32:
506 ; CHECK-RV32C: # %bb.0:
507 ; CHECK-RV32C-NEXT: c.ntl.all
508 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
509 ; CHECK-RV32C-NEXT: c.ntl.all
510 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
511 ; CHECK-RV32C-NEXT: c.ntl.all
512 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
513 ; CHECK-RV32C-NEXT: c.ntl.all
514 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
515 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
516 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
517 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
518 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
519 ; CHECK-RV32C-NEXT: ret
520 ;
521 ; CHECK-RV64V-LABEL: test_nontemporal_load_v4i32:
522 ; CHECK-RV64V: # %bb.0:
523 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
524 ; CHECK-RV64V-NEXT: ntl.all
525 ; CHECK-RV64V-NEXT: vle32.v v8, (a0)
526 ; CHECK-RV64V-NEXT: ret
527 ;
528 ; CHECK-RV32V-LABEL: test_nontemporal_load_v4i32:
529 ; CHECK-RV32V: # %bb.0:
530 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
531 ; CHECK-RV32V-NEXT: ntl.all
532 ; CHECK-RV32V-NEXT: vle32.v v8, (a0)
533 ; CHECK-RV32V-NEXT: ret
535 %1 = load <4 x i32>, ptr %p, !nontemporal !0
536 ret <4 x i32> %1
537 }
539 define <2 x i64> @test_nontemporal_load_v2i64(ptr %p) {
540 ; CHECK-RV64-LABEL: test_nontemporal_load_v2i64:
541 ; CHECK-RV64: # %bb.0:
542 ; CHECK-RV64-NEXT: ntl.all
543 ; CHECK-RV64-NEXT: ld a2, 0(a0)
544 ; CHECK-RV64-NEXT: ntl.all
545 ; CHECK-RV64-NEXT: ld a1, 8(a0)
546 ; CHECK-RV64-NEXT: mv a0, a2
547 ; CHECK-RV64-NEXT: ret
548 ;
549 ; CHECK-RV32-LABEL: test_nontemporal_load_v2i64:
550 ; CHECK-RV32: # %bb.0:
551 ; CHECK-RV32-NEXT: ntl.all
552 ; CHECK-RV32-NEXT: lw a2, 12(a1)
553 ; CHECK-RV32-NEXT: ntl.all
554 ; CHECK-RV32-NEXT: lw a3, 8(a1)
555 ; CHECK-RV32-NEXT: ntl.all
556 ; CHECK-RV32-NEXT: lw a4, 4(a1)
557 ; CHECK-RV32-NEXT: ntl.all
558 ; CHECK-RV32-NEXT: lw a1, 0(a1)
559 ; CHECK-RV32-NEXT: sw a2, 12(a0)
560 ; CHECK-RV32-NEXT: sw a3, 8(a0)
561 ; CHECK-RV32-NEXT: sw a4, 4(a0)
562 ; CHECK-RV32-NEXT: sw a1, 0(a0)
563 ; CHECK-RV32-NEXT: ret
564 ;
565 ; CHECK-RV64C-LABEL: test_nontemporal_load_v2i64:
566 ; CHECK-RV64C: # %bb.0:
567 ; CHECK-RV64C-NEXT: c.ntl.all
568 ; CHECK-RV64C-NEXT: ld a2, 0(a0)
569 ; CHECK-RV64C-NEXT: c.ntl.all
570 ; CHECK-RV64C-NEXT: ld a1, 8(a0)
571 ; CHECK-RV64C-NEXT: mv a0, a2
572 ; CHECK-RV64C-NEXT: ret
573 ;
574 ; CHECK-RV32C-LABEL: test_nontemporal_load_v2i64:
575 ; CHECK-RV32C: # %bb.0:
576 ; CHECK-RV32C-NEXT: c.ntl.all
577 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
578 ; CHECK-RV32C-NEXT: c.ntl.all
579 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
580 ; CHECK-RV32C-NEXT: c.ntl.all
581 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
582 ; CHECK-RV32C-NEXT: c.ntl.all
583 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
584 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
585 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
586 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
587 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
588 ; CHECK-RV32C-NEXT: ret
589 ;
590 ; CHECK-RV64V-LABEL: test_nontemporal_load_v2i64:
591 ; CHECK-RV64V: # %bb.0:
592 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
593 ; CHECK-RV64V-NEXT: ntl.all
594 ; CHECK-RV64V-NEXT: vle64.v v8, (a0)
595 ; CHECK-RV64V-NEXT: ret
596 ;
597 ; CHECK-RV32V-LABEL: test_nontemporal_load_v2i64:
598 ; CHECK-RV32V: # %bb.0:
599 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
600 ; CHECK-RV32V-NEXT: ntl.all
601 ; CHECK-RV32V-NEXT: vle64.v v8, (a0)
602 ; CHECK-RV32V-NEXT: ret
604 %1 = load <2 x i64>, ptr %p, !nontemporal !0
605 ret <2 x i64> %1
606 }
608 define void @test_nontemporal_store_i64(ptr %p, i64 %v) {
609 ; CHECK-RV64-LABEL: test_nontemporal_store_i64:
610 ; CHECK-RV64: # %bb.0:
611 ; CHECK-RV64-NEXT: ntl.all
612 ; CHECK-RV64-NEXT: sd a1, 0(a0)
613 ; CHECK-RV64-NEXT: ret
614 ;
615 ; CHECK-RV32-LABEL: test_nontemporal_store_i64:
616 ; CHECK-RV32: # %bb.0:
617 ; CHECK-RV32-NEXT: ntl.all
618 ; CHECK-RV32-NEXT: sw a2, 4(a0)
619 ; CHECK-RV32-NEXT: ntl.all
620 ; CHECK-RV32-NEXT: sw a1, 0(a0)
621 ; CHECK-RV32-NEXT: ret
622 ;
623 ; CHECK-RV64C-LABEL: test_nontemporal_store_i64:
624 ; CHECK-RV64C: # %bb.0:
625 ; CHECK-RV64C-NEXT: c.ntl.all
626 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
627 ; CHECK-RV64C-NEXT: ret
628 ;
629 ; CHECK-RV32C-LABEL: test_nontemporal_store_i64:
630 ; CHECK-RV32C: # %bb.0:
631 ; CHECK-RV32C-NEXT: c.ntl.all
632 ; CHECK-RV32C-NEXT: sw a2, 4(a0)
633 ; CHECK-RV32C-NEXT: c.ntl.all
634 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
635 ; CHECK-RV32C-NEXT: ret
636 ;
637 ; CHECK-RV64V-LABEL: test_nontemporal_store_i64:
638 ; CHECK-RV64V: # %bb.0:
639 ; CHECK-RV64V-NEXT: ntl.all
640 ; CHECK-RV64V-NEXT: sd a1, 0(a0)
641 ; CHECK-RV64V-NEXT: ret
642 ;
643 ; CHECK-RV32V-LABEL: test_nontemporal_store_i64:
644 ; CHECK-RV32V: # %bb.0:
645 ; CHECK-RV32V-NEXT: ntl.all
646 ; CHECK-RV32V-NEXT: sw a2, 4(a0)
647 ; CHECK-RV32V-NEXT: ntl.all
648 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
649 ; CHECK-RV32V-NEXT: ret
651 store i64 %v, ptr %p, !nontemporal !0
652 ret void
653 }
655 define void @test_nontemporal_store_i32(ptr %p, i32 %v) {
656 ; CHECK-RV64-LABEL: test_nontemporal_store_i32:
657 ; CHECK-RV64: # %bb.0:
658 ; CHECK-RV64-NEXT: ntl.all
659 ; CHECK-RV64-NEXT: sw a1, 0(a0)
660 ; CHECK-RV64-NEXT: ret
661 ;
662 ; CHECK-RV32-LABEL: test_nontemporal_store_i32:
663 ; CHECK-RV32: # %bb.0:
664 ; CHECK-RV32-NEXT: ntl.all
665 ; CHECK-RV32-NEXT: sw a1, 0(a0)
666 ; CHECK-RV32-NEXT: ret
667 ;
668 ; CHECK-RV64C-LABEL: test_nontemporal_store_i32:
669 ; CHECK-RV64C: # %bb.0:
670 ; CHECK-RV64C-NEXT: c.ntl.all
671 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
672 ; CHECK-RV64C-NEXT: ret
673 ;
674 ; CHECK-RV32C-LABEL: test_nontemporal_store_i32:
675 ; CHECK-RV32C: # %bb.0:
676 ; CHECK-RV32C-NEXT: c.ntl.all
677 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
678 ; CHECK-RV32C-NEXT: ret
679 ;
680 ; CHECK-RV64V-LABEL: test_nontemporal_store_i32:
681 ; CHECK-RV64V: # %bb.0:
682 ; CHECK-RV64V-NEXT: ntl.all
683 ; CHECK-RV64V-NEXT: sw a1, 0(a0)
684 ; CHECK-RV64V-NEXT: ret
685 ;
686 ; CHECK-RV32V-LABEL: test_nontemporal_store_i32:
687 ; CHECK-RV32V: # %bb.0:
688 ; CHECK-RV32V-NEXT: ntl.all
689 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
690 ; CHECK-RV32V-NEXT: ret
692 store i32 %v, ptr %p, !nontemporal !0
693 ret void
694 }
696 define void @test_nontemporal_store_i16(ptr %p, i16 %v) {
697 ; CHECK-RV64-LABEL: test_nontemporal_store_i16:
698 ; CHECK-RV64: # %bb.0:
699 ; CHECK-RV64-NEXT: ntl.all
700 ; CHECK-RV64-NEXT: sh a1, 0(a0)
701 ; CHECK-RV64-NEXT: ret
702 ;
703 ; CHECK-RV32-LABEL: test_nontemporal_store_i16:
704 ; CHECK-RV32: # %bb.0:
705 ; CHECK-RV32-NEXT: ntl.all
706 ; CHECK-RV32-NEXT: sh a1, 0(a0)
707 ; CHECK-RV32-NEXT: ret
708 ;
709 ; CHECK-RV64C-LABEL: test_nontemporal_store_i16:
710 ; CHECK-RV64C: # %bb.0:
711 ; CHECK-RV64C-NEXT: c.ntl.all
712 ; CHECK-RV64C-NEXT: sh a1, 0(a0)
713 ; CHECK-RV64C-NEXT: ret
714 ;
715 ; CHECK-RV32C-LABEL: test_nontemporal_store_i16:
716 ; CHECK-RV32C: # %bb.0:
717 ; CHECK-RV32C-NEXT: c.ntl.all
718 ; CHECK-RV32C-NEXT: sh a1, 0(a0)
719 ; CHECK-RV32C-NEXT: ret
720 ;
721 ; CHECK-RV64V-LABEL: test_nontemporal_store_i16:
722 ; CHECK-RV64V: # %bb.0:
723 ; CHECK-RV64V-NEXT: ntl.all
724 ; CHECK-RV64V-NEXT: sh a1, 0(a0)
725 ; CHECK-RV64V-NEXT: ret
726 ;
727 ; CHECK-RV32V-LABEL: test_nontemporal_store_i16:
728 ; CHECK-RV32V: # %bb.0:
729 ; CHECK-RV32V-NEXT: ntl.all
730 ; CHECK-RV32V-NEXT: sh a1, 0(a0)
731 ; CHECK-RV32V-NEXT: ret
733 store i16 %v, ptr %p, !nontemporal !0
734 ret void
735 }
737 define void @test_nontemporal_store_i8(ptr %p, i8 %v) {
738 ; CHECK-RV64-LABEL: test_nontemporal_store_i8:
739 ; CHECK-RV64: # %bb.0:
740 ; CHECK-RV64-NEXT: ntl.all
741 ; CHECK-RV64-NEXT: sb a1, 0(a0)
742 ; CHECK-RV64-NEXT: ret
743 ;
744 ; CHECK-RV32-LABEL: test_nontemporal_store_i8:
745 ; CHECK-RV32: # %bb.0:
746 ; CHECK-RV32-NEXT: ntl.all
747 ; CHECK-RV32-NEXT: sb a1, 0(a0)
748 ; CHECK-RV32-NEXT: ret
749 ;
750 ; CHECK-RV64C-LABEL: test_nontemporal_store_i8:
751 ; CHECK-RV64C: # %bb.0:
752 ; CHECK-RV64C-NEXT: c.ntl.all
753 ; CHECK-RV64C-NEXT: sb a1, 0(a0)
754 ; CHECK-RV64C-NEXT: ret
755 ;
756 ; CHECK-RV32C-LABEL: test_nontemporal_store_i8:
757 ; CHECK-RV32C: # %bb.0:
758 ; CHECK-RV32C-NEXT: c.ntl.all
759 ; CHECK-RV32C-NEXT: sb a1, 0(a0)
760 ; CHECK-RV32C-NEXT: ret
761 ;
762 ; CHECK-RV64V-LABEL: test_nontemporal_store_i8:
763 ; CHECK-RV64V: # %bb.0:
764 ; CHECK-RV64V-NEXT: ntl.all
765 ; CHECK-RV64V-NEXT: sb a1, 0(a0)
766 ; CHECK-RV64V-NEXT: ret
767 ;
768 ; CHECK-RV32V-LABEL: test_nontemporal_store_i8:
769 ; CHECK-RV32V: # %bb.0:
770 ; CHECK-RV32V-NEXT: ntl.all
771 ; CHECK-RV32V-NEXT: sb a1, 0(a0)
772 ; CHECK-RV32V-NEXT: ret
774 store i8 %v, ptr %p, !nontemporal !0
775 ret void
776 }
778 define void @test_nontemporal_store_half(ptr %p, half %v) {
779 ; CHECK-RV64-LABEL: test_nontemporal_store_half:
780 ; CHECK-RV64: # %bb.0:
781 ; CHECK-RV64-NEXT: ntl.all
782 ; CHECK-RV64-NEXT: fsh fa0, 0(a0)
783 ; CHECK-RV64-NEXT: ret
784 ;
785 ; CHECK-RV32-LABEL: test_nontemporal_store_half:
786 ; CHECK-RV32: # %bb.0:
787 ; CHECK-RV32-NEXT: ntl.all
788 ; CHECK-RV32-NEXT: fsh fa0, 0(a0)
789 ; CHECK-RV32-NEXT: ret
790 ;
791 ; CHECK-RV64C-LABEL: test_nontemporal_store_half:
792 ; CHECK-RV64C: # %bb.0:
793 ; CHECK-RV64C-NEXT: c.ntl.all
794 ; CHECK-RV64C-NEXT: fsh fa0, 0(a0)
795 ; CHECK-RV64C-NEXT: ret
796 ;
797 ; CHECK-RV32C-LABEL: test_nontemporal_store_half:
798 ; CHECK-RV32C: # %bb.0:
799 ; CHECK-RV32C-NEXT: c.ntl.all
800 ; CHECK-RV32C-NEXT: fsh fa0, 0(a0)
801 ; CHECK-RV32C-NEXT: ret
802 ;
803 ; CHECK-RV64V-LABEL: test_nontemporal_store_half:
804 ; CHECK-RV64V: # %bb.0:
805 ; CHECK-RV64V-NEXT: ntl.all
806 ; CHECK-RV64V-NEXT: fsh fa0, 0(a0)
807 ; CHECK-RV64V-NEXT: ret
808 ;
809 ; CHECK-RV32V-LABEL: test_nontemporal_store_half:
810 ; CHECK-RV32V: # %bb.0:
811 ; CHECK-RV32V-NEXT: ntl.all
812 ; CHECK-RV32V-NEXT: fsh fa0, 0(a0)
813 ; CHECK-RV32V-NEXT: ret
815 store half %v, ptr %p, !nontemporal !0
816 ret void
817 }
819 define void @test_nontemporal_store_float(ptr %p, float %v) {
820 ; CHECK-RV64-LABEL: test_nontemporal_store_float:
821 ; CHECK-RV64: # %bb.0:
822 ; CHECK-RV64-NEXT: ntl.all
823 ; CHECK-RV64-NEXT: fsw fa0, 0(a0)
824 ; CHECK-RV64-NEXT: ret
825 ;
826 ; CHECK-RV32-LABEL: test_nontemporal_store_float:
827 ; CHECK-RV32: # %bb.0:
828 ; CHECK-RV32-NEXT: ntl.all
829 ; CHECK-RV32-NEXT: fsw fa0, 0(a0)
830 ; CHECK-RV32-NEXT: ret
831 ;
832 ; CHECK-RV64C-LABEL: test_nontemporal_store_float:
833 ; CHECK-RV64C: # %bb.0:
834 ; CHECK-RV64C-NEXT: c.ntl.all
835 ; CHECK-RV64C-NEXT: fsw fa0, 0(a0)
836 ; CHECK-RV64C-NEXT: ret
837 ;
838 ; CHECK-RV32C-LABEL: test_nontemporal_store_float:
839 ; CHECK-RV32C: # %bb.0:
840 ; CHECK-RV32C-NEXT: c.ntl.all
841 ; CHECK-RV32C-NEXT: fsw fa0, 0(a0)
842 ; CHECK-RV32C-NEXT: ret
843 ;
844 ; CHECK-RV64V-LABEL: test_nontemporal_store_float:
845 ; CHECK-RV64V: # %bb.0:
846 ; CHECK-RV64V-NEXT: ntl.all
847 ; CHECK-RV64V-NEXT: fsw fa0, 0(a0)
848 ; CHECK-RV64V-NEXT: ret
849 ;
850 ; CHECK-RV32V-LABEL: test_nontemporal_store_float:
851 ; CHECK-RV32V: # %bb.0:
852 ; CHECK-RV32V-NEXT: ntl.all
853 ; CHECK-RV32V-NEXT: fsw fa0, 0(a0)
854 ; CHECK-RV32V-NEXT: ret
856 store float %v, ptr %p, !nontemporal !0
857 ret void
858 }
860 define void @test_nontemporal_store_double(ptr %p, double %v) {
861 ; CHECK-RV64-LABEL: test_nontemporal_store_double:
862 ; CHECK-RV64: # %bb.0:
863 ; CHECK-RV64-NEXT: ntl.all
864 ; CHECK-RV64-NEXT: fsd fa0, 0(a0)
865 ; CHECK-RV64-NEXT: ret
866 ;
867 ; CHECK-RV32-LABEL: test_nontemporal_store_double:
868 ; CHECK-RV32: # %bb.0:
869 ; CHECK-RV32-NEXT: ntl.all
870 ; CHECK-RV32-NEXT: fsd fa0, 0(a0)
871 ; CHECK-RV32-NEXT: ret
872 ;
873 ; CHECK-RV64C-LABEL: test_nontemporal_store_double:
874 ; CHECK-RV64C: # %bb.0:
875 ; CHECK-RV64C-NEXT: c.ntl.all
876 ; CHECK-RV64C-NEXT: fsd fa0, 0(a0)
877 ; CHECK-RV64C-NEXT: ret
878 ;
879 ; CHECK-RV32C-LABEL: test_nontemporal_store_double:
880 ; CHECK-RV32C: # %bb.0:
881 ; CHECK-RV32C-NEXT: c.ntl.all
882 ; CHECK-RV32C-NEXT: fsd fa0, 0(a0)
883 ; CHECK-RV32C-NEXT: ret
884 ;
885 ; CHECK-RV64V-LABEL: test_nontemporal_store_double:
886 ; CHECK-RV64V: # %bb.0:
887 ; CHECK-RV64V-NEXT: ntl.all
888 ; CHECK-RV64V-NEXT: fsd fa0, 0(a0)
889 ; CHECK-RV64V-NEXT: ret
890 ;
891 ; CHECK-RV32V-LABEL: test_nontemporal_store_double:
892 ; CHECK-RV32V: # %bb.0:
893 ; CHECK-RV32V-NEXT: ntl.all
894 ; CHECK-RV32V-NEXT: fsd fa0, 0(a0)
895 ; CHECK-RV32V-NEXT: ret
897 store double %v, ptr %p, !nontemporal !0
898 ret void
899 }
901 define void @test_nontemporal_store_v16i8(ptr %p, <16 x i8> %v) {
902 ; CHECK-RV64-LABEL: test_nontemporal_store_v16i8:
903 ; CHECK-RV64: # %bb.0:
904 ; CHECK-RV64-NEXT: addi sp, sp, -16
905 ; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
906 ; CHECK-RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
907 ; CHECK-RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
908 ; CHECK-RV64-NEXT: .cfi_offset s0, -8
909 ; CHECK-RV64-NEXT: .cfi_offset s1, -16
910 ; CHECK-RV64-NEXT: lbu a2, 0(a1)
911 ; CHECK-RV64-NEXT: lbu a3, 8(a1)
912 ; CHECK-RV64-NEXT: lbu a4, 16(a1)
913 ; CHECK-RV64-NEXT: lbu a5, 24(a1)
914 ; CHECK-RV64-NEXT: lbu a6, 32(a1)
915 ; CHECK-RV64-NEXT: lbu a7, 40(a1)
916 ; CHECK-RV64-NEXT: lbu t0, 48(a1)
917 ; CHECK-RV64-NEXT: lbu t1, 56(a1)
918 ; CHECK-RV64-NEXT: lbu t2, 64(a1)
919 ; CHECK-RV64-NEXT: lbu t3, 72(a1)
920 ; CHECK-RV64-NEXT: lbu t4, 80(a1)
921 ; CHECK-RV64-NEXT: lbu t5, 88(a1)
922 ; CHECK-RV64-NEXT: lbu t6, 120(a1)
923 ; CHECK-RV64-NEXT: lbu s0, 112(a1)
924 ; CHECK-RV64-NEXT: lbu s1, 104(a1)
925 ; CHECK-RV64-NEXT: lbu a1, 96(a1)
926 ; CHECK-RV64-NEXT: ntl.all
927 ; CHECK-RV64-NEXT: sb t6, 15(a0)
928 ; CHECK-RV64-NEXT: ntl.all
929 ; CHECK-RV64-NEXT: sb s0, 14(a0)
930 ; CHECK-RV64-NEXT: ntl.all
931 ; CHECK-RV64-NEXT: sb s1, 13(a0)
932 ; CHECK-RV64-NEXT: ntl.all
933 ; CHECK-RV64-NEXT: sb a1, 12(a0)
934 ; CHECK-RV64-NEXT: ntl.all
935 ; CHECK-RV64-NEXT: sb t5, 11(a0)
936 ; CHECK-RV64-NEXT: ntl.all
937 ; CHECK-RV64-NEXT: sb t4, 10(a0)
938 ; CHECK-RV64-NEXT: ntl.all
939 ; CHECK-RV64-NEXT: sb t3, 9(a0)
940 ; CHECK-RV64-NEXT: ntl.all
941 ; CHECK-RV64-NEXT: sb t2, 8(a0)
942 ; CHECK-RV64-NEXT: ntl.all
943 ; CHECK-RV64-NEXT: sb t1, 7(a0)
944 ; CHECK-RV64-NEXT: ntl.all
945 ; CHECK-RV64-NEXT: sb t0, 6(a0)
946 ; CHECK-RV64-NEXT: ntl.all
947 ; CHECK-RV64-NEXT: sb a7, 5(a0)
948 ; CHECK-RV64-NEXT: ntl.all
949 ; CHECK-RV64-NEXT: sb a6, 4(a0)
950 ; CHECK-RV64-NEXT: ntl.all
951 ; CHECK-RV64-NEXT: sb a5, 3(a0)
952 ; CHECK-RV64-NEXT: ntl.all
953 ; CHECK-RV64-NEXT: sb a4, 2(a0)
954 ; CHECK-RV64-NEXT: ntl.all
955 ; CHECK-RV64-NEXT: sb a3, 1(a0)
956 ; CHECK-RV64-NEXT: ntl.all
957 ; CHECK-RV64-NEXT: sb a2, 0(a0)
958 ; CHECK-RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
959 ; CHECK-RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
960 ; CHECK-RV64-NEXT: addi sp, sp, 16
961 ; CHECK-RV64-NEXT: ret
962 ;
963 ; CHECK-RV32-LABEL: test_nontemporal_store_v16i8:
964 ; CHECK-RV32: # %bb.0:
965 ; CHECK-RV32-NEXT: addi sp, sp, -16
966 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
967 ; CHECK-RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
968 ; CHECK-RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
969 ; CHECK-RV32-NEXT: .cfi_offset s0, -4
970 ; CHECK-RV32-NEXT: .cfi_offset s1, -8
971 ; CHECK-RV32-NEXT: lbu a2, 0(a1)
972 ; CHECK-RV32-NEXT: lbu a3, 4(a1)
973 ; CHECK-RV32-NEXT: lbu a4, 8(a1)
974 ; CHECK-RV32-NEXT: lbu a5, 12(a1)
975 ; CHECK-RV32-NEXT: lbu a6, 16(a1)
976 ; CHECK-RV32-NEXT: lbu a7, 20(a1)
977 ; CHECK-RV32-NEXT: lbu t0, 24(a1)
978 ; CHECK-RV32-NEXT: lbu t1, 28(a1)
979 ; CHECK-RV32-NEXT: lbu t2, 32(a1)
980 ; CHECK-RV32-NEXT: lbu t3, 36(a1)
981 ; CHECK-RV32-NEXT: lbu t4, 40(a1)
982 ; CHECK-RV32-NEXT: lbu t5, 44(a1)
983 ; CHECK-RV32-NEXT: lbu t6, 60(a1)
984 ; CHECK-RV32-NEXT: lbu s0, 56(a1)
985 ; CHECK-RV32-NEXT: lbu s1, 52(a1)
986 ; CHECK-RV32-NEXT: lbu a1, 48(a1)
987 ; CHECK-RV32-NEXT: ntl.all
988 ; CHECK-RV32-NEXT: sb t6, 15(a0)
989 ; CHECK-RV32-NEXT: ntl.all
990 ; CHECK-RV32-NEXT: sb s0, 14(a0)
991 ; CHECK-RV32-NEXT: ntl.all
992 ; CHECK-RV32-NEXT: sb s1, 13(a0)
993 ; CHECK-RV32-NEXT: ntl.all
994 ; CHECK-RV32-NEXT: sb a1, 12(a0)
995 ; CHECK-RV32-NEXT: ntl.all
996 ; CHECK-RV32-NEXT: sb t5, 11(a0)
997 ; CHECK-RV32-NEXT: ntl.all
998 ; CHECK-RV32-NEXT: sb t4, 10(a0)
999 ; CHECK-RV32-NEXT: ntl.all
1000 ; CHECK-RV32-NEXT: sb t3, 9(a0)
1001 ; CHECK-RV32-NEXT: ntl.all
1002 ; CHECK-RV32-NEXT: sb t2, 8(a0)
1003 ; CHECK-RV32-NEXT: ntl.all
1004 ; CHECK-RV32-NEXT: sb t1, 7(a0)
1005 ; CHECK-RV32-NEXT: ntl.all
1006 ; CHECK-RV32-NEXT: sb t0, 6(a0)
1007 ; CHECK-RV32-NEXT: ntl.all
1008 ; CHECK-RV32-NEXT: sb a7, 5(a0)
1009 ; CHECK-RV32-NEXT: ntl.all
1010 ; CHECK-RV32-NEXT: sb a6, 4(a0)
1011 ; CHECK-RV32-NEXT: ntl.all
1012 ; CHECK-RV32-NEXT: sb a5, 3(a0)
1013 ; CHECK-RV32-NEXT: ntl.all
1014 ; CHECK-RV32-NEXT: sb a4, 2(a0)
1015 ; CHECK-RV32-NEXT: ntl.all
1016 ; CHECK-RV32-NEXT: sb a3, 1(a0)
1017 ; CHECK-RV32-NEXT: ntl.all
1018 ; CHECK-RV32-NEXT: sb a2, 0(a0)
1019 ; CHECK-RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
1020 ; CHECK-RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
1021 ; CHECK-RV32-NEXT: addi sp, sp, 16
1022 ; CHECK-RV32-NEXT: ret
1023 ;
1024 ; CHECK-RV64C-LABEL: test_nontemporal_store_v16i8:
1025 ; CHECK-RV64C: # %bb.0:
1026 ; CHECK-RV64C-NEXT: addi sp, sp, -16
1027 ; CHECK-RV64C-NEXT: .cfi_def_cfa_offset 16
1028 ; CHECK-RV64C-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
1029 ; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
1030 ; CHECK-RV64C-NEXT: .cfi_offset s0, -8
1031 ; CHECK-RV64C-NEXT: .cfi_offset s1, -16
1032 ; CHECK-RV64C-NEXT: lbu a6, 0(a1)
1033 ; CHECK-RV64C-NEXT: lbu a7, 8(a1)
1034 ; CHECK-RV64C-NEXT: lbu t0, 16(a1)
1035 ; CHECK-RV64C-NEXT: lbu t1, 24(a1)
1036 ; CHECK-RV64C-NEXT: lbu t2, 32(a1)
1037 ; CHECK-RV64C-NEXT: lbu t3, 40(a1)
1038 ; CHECK-RV64C-NEXT: lbu t4, 48(a1)
1039 ; CHECK-RV64C-NEXT: lbu t5, 56(a1)
1040 ; CHECK-RV64C-NEXT: lbu t6, 64(a1)
1041 ; CHECK-RV64C-NEXT: lbu a3, 72(a1)
1042 ; CHECK-RV64C-NEXT: lbu a4, 80(a1)
1043 ; CHECK-RV64C-NEXT: lbu a5, 88(a1)
1044 ; CHECK-RV64C-NEXT: lbu a2, 120(a1)
1045 ; CHECK-RV64C-NEXT: lbu s0, 112(a1)
1046 ; CHECK-RV64C-NEXT: lbu s1, 104(a1)
1047 ; CHECK-RV64C-NEXT: lbu a1, 96(a1)
1048 ; CHECK-RV64C-NEXT: c.ntl.all
1049 ; CHECK-RV64C-NEXT: sb a2, 15(a0)
1050 ; CHECK-RV64C-NEXT: c.ntl.all
1051 ; CHECK-RV64C-NEXT: sb s0, 14(a0)
1052 ; CHECK-RV64C-NEXT: c.ntl.all
1053 ; CHECK-RV64C-NEXT: sb s1, 13(a0)
1054 ; CHECK-RV64C-NEXT: c.ntl.all
1055 ; CHECK-RV64C-NEXT: sb a1, 12(a0)
1056 ; CHECK-RV64C-NEXT: c.ntl.all
1057 ; CHECK-RV64C-NEXT: sb a5, 11(a0)
1058 ; CHECK-RV64C-NEXT: c.ntl.all
1059 ; CHECK-RV64C-NEXT: sb a4, 10(a0)
1060 ; CHECK-RV64C-NEXT: c.ntl.all
1061 ; CHECK-RV64C-NEXT: sb a3, 9(a0)
1062 ; CHECK-RV64C-NEXT: c.ntl.all
1063 ; CHECK-RV64C-NEXT: sb t6, 8(a0)
1064 ; CHECK-RV64C-NEXT: c.ntl.all
1065 ; CHECK-RV64C-NEXT: sb t5, 7(a0)
1066 ; CHECK-RV64C-NEXT: c.ntl.all
1067 ; CHECK-RV64C-NEXT: sb t4, 6(a0)
1068 ; CHECK-RV64C-NEXT: c.ntl.all
1069 ; CHECK-RV64C-NEXT: sb t3, 5(a0)
1070 ; CHECK-RV64C-NEXT: c.ntl.all
1071 ; CHECK-RV64C-NEXT: sb t2, 4(a0)
1072 ; CHECK-RV64C-NEXT: c.ntl.all
1073 ; CHECK-RV64C-NEXT: sb t1, 3(a0)
1074 ; CHECK-RV64C-NEXT: c.ntl.all
1075 ; CHECK-RV64C-NEXT: sb t0, 2(a0)
1076 ; CHECK-RV64C-NEXT: c.ntl.all
1077 ; CHECK-RV64C-NEXT: sb a7, 1(a0)
1078 ; CHECK-RV64C-NEXT: c.ntl.all
1079 ; CHECK-RV64C-NEXT: sb a6, 0(a0)
1080 ; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
1081 ; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
1082 ; CHECK-RV64C-NEXT: addi sp, sp, 16
1083 ; CHECK-RV64C-NEXT: ret
1084 ;
1085 ; CHECK-RV32C-LABEL: test_nontemporal_store_v16i8:
1086 ; CHECK-RV32C: # %bb.0:
1087 ; CHECK-RV32C-NEXT: addi sp, sp, -16
1088 ; CHECK-RV32C-NEXT: .cfi_def_cfa_offset 16
1089 ; CHECK-RV32C-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
1090 ; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
1091 ; CHECK-RV32C-NEXT: .cfi_offset s0, -4
1092 ; CHECK-RV32C-NEXT: .cfi_offset s1, -8
1093 ; CHECK-RV32C-NEXT: lbu a6, 0(a1)
1094 ; CHECK-RV32C-NEXT: lbu a7, 4(a1)
1095 ; CHECK-RV32C-NEXT: lbu t0, 8(a1)
1096 ; CHECK-RV32C-NEXT: lbu t1, 12(a1)
1097 ; CHECK-RV32C-NEXT: lbu t2, 16(a1)
1098 ; CHECK-RV32C-NEXT: lbu t3, 20(a1)
1099 ; CHECK-RV32C-NEXT: lbu t4, 24(a1)
1100 ; CHECK-RV32C-NEXT: lbu t5, 28(a1)
1101 ; CHECK-RV32C-NEXT: lbu t6, 32(a1)
1102 ; CHECK-RV32C-NEXT: lbu a3, 36(a1)
1103 ; CHECK-RV32C-NEXT: lbu a4, 40(a1)
1104 ; CHECK-RV32C-NEXT: lbu a5, 44(a1)
1105 ; CHECK-RV32C-NEXT: lbu a2, 60(a1)
1106 ; CHECK-RV32C-NEXT: lbu s0, 56(a1)
1107 ; CHECK-RV32C-NEXT: lbu s1, 52(a1)
1108 ; CHECK-RV32C-NEXT: lbu a1, 48(a1)
1109 ; CHECK-RV32C-NEXT: c.ntl.all
1110 ; CHECK-RV32C-NEXT: sb a2, 15(a0)
1111 ; CHECK-RV32C-NEXT: c.ntl.all
1112 ; CHECK-RV32C-NEXT: sb s0, 14(a0)
1113 ; CHECK-RV32C-NEXT: c.ntl.all
1114 ; CHECK-RV32C-NEXT: sb s1, 13(a0)
1115 ; CHECK-RV32C-NEXT: c.ntl.all
1116 ; CHECK-RV32C-NEXT: sb a1, 12(a0)
1117 ; CHECK-RV32C-NEXT: c.ntl.all
1118 ; CHECK-RV32C-NEXT: sb a5, 11(a0)
1119 ; CHECK-RV32C-NEXT: c.ntl.all
1120 ; CHECK-RV32C-NEXT: sb a4, 10(a0)
1121 ; CHECK-RV32C-NEXT: c.ntl.all
1122 ; CHECK-RV32C-NEXT: sb a3, 9(a0)
1123 ; CHECK-RV32C-NEXT: c.ntl.all
1124 ; CHECK-RV32C-NEXT: sb t6, 8(a0)
1125 ; CHECK-RV32C-NEXT: c.ntl.all
1126 ; CHECK-RV32C-NEXT: sb t5, 7(a0)
1127 ; CHECK-RV32C-NEXT: c.ntl.all
1128 ; CHECK-RV32C-NEXT: sb t4, 6(a0)
1129 ; CHECK-RV32C-NEXT: c.ntl.all
1130 ; CHECK-RV32C-NEXT: sb t3, 5(a0)
1131 ; CHECK-RV32C-NEXT: c.ntl.all
1132 ; CHECK-RV32C-NEXT: sb t2, 4(a0)
1133 ; CHECK-RV32C-NEXT: c.ntl.all
1134 ; CHECK-RV32C-NEXT: sb t1, 3(a0)
1135 ; CHECK-RV32C-NEXT: c.ntl.all
1136 ; CHECK-RV32C-NEXT: sb t0, 2(a0)
1137 ; CHECK-RV32C-NEXT: c.ntl.all
1138 ; CHECK-RV32C-NEXT: sb a7, 1(a0)
1139 ; CHECK-RV32C-NEXT: c.ntl.all
1140 ; CHECK-RV32C-NEXT: sb a6, 0(a0)
1141 ; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
1142 ; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
1143 ; CHECK-RV32C-NEXT: addi sp, sp, 16
1144 ; CHECK-RV32C-NEXT: ret
1145 ;
1146 ; CHECK-RV64V-LABEL: test_nontemporal_store_v16i8:
1147 ; CHECK-RV64V: # %bb.0:
1148 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1149 ; CHECK-RV64V-NEXT: ntl.all
1150 ; CHECK-RV64V-NEXT: vse8.v v8, (a0)
1151 ; CHECK-RV64V-NEXT: ret
1152 ;
1153 ; CHECK-RV32V-LABEL: test_nontemporal_store_v16i8:
1154 ; CHECK-RV32V: # %bb.0:
1155 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1156 ; CHECK-RV32V-NEXT: ntl.all
1157 ; CHECK-RV32V-NEXT: vse8.v v8, (a0)
1158 ; CHECK-RV32V-NEXT: ret
1159 store <16 x i8> %v, ptr %p, !nontemporal !0
1160 ret void
1161 }
1163 define void @test_nontemporal_store_v8i16(ptr %p, <8 x i16> %v) {
1164 ; CHECK-RV64-LABEL: test_nontemporal_store_v8i16:
1165 ; CHECK-RV64: # %bb.0:
1166 ; CHECK-RV64-NEXT: lh a2, 0(a1)
1167 ; CHECK-RV64-NEXT: lh a3, 8(a1)
1168 ; CHECK-RV64-NEXT: lh a4, 16(a1)
1169 ; CHECK-RV64-NEXT: lh a5, 24(a1)
1170 ; CHECK-RV64-NEXT: lh a6, 56(a1)
1171 ; CHECK-RV64-NEXT: lh a7, 48(a1)
1172 ; CHECK-RV64-NEXT: lh t0, 40(a1)
1173 ; CHECK-RV64-NEXT: lh a1, 32(a1)
1174 ; CHECK-RV64-NEXT: ntl.all
1175 ; CHECK-RV64-NEXT: sh a6, 14(a0)
1176 ; CHECK-RV64-NEXT: ntl.all
1177 ; CHECK-RV64-NEXT: sh a7, 12(a0)
1178 ; CHECK-RV64-NEXT: ntl.all
1179 ; CHECK-RV64-NEXT: sh t0, 10(a0)
1180 ; CHECK-RV64-NEXT: ntl.all
1181 ; CHECK-RV64-NEXT: sh a1, 8(a0)
1182 ; CHECK-RV64-NEXT: ntl.all
1183 ; CHECK-RV64-NEXT: sh a5, 6(a0)
1184 ; CHECK-RV64-NEXT: ntl.all
1185 ; CHECK-RV64-NEXT: sh a4, 4(a0)
1186 ; CHECK-RV64-NEXT: ntl.all
1187 ; CHECK-RV64-NEXT: sh a3, 2(a0)
1188 ; CHECK-RV64-NEXT: ntl.all
1189 ; CHECK-RV64-NEXT: sh a2, 0(a0)
1190 ; CHECK-RV64-NEXT: ret
1191 ;
1192 ; CHECK-RV32-LABEL: test_nontemporal_store_v8i16:
1193 ; CHECK-RV32: # %bb.0:
1194 ; CHECK-RV32-NEXT: lh a2, 0(a1)
1195 ; CHECK-RV32-NEXT: lh a3, 4(a1)
1196 ; CHECK-RV32-NEXT: lh a4, 8(a1)
1197 ; CHECK-RV32-NEXT: lh a5, 12(a1)
1198 ; CHECK-RV32-NEXT: lh a6, 28(a1)
1199 ; CHECK-RV32-NEXT: lh a7, 24(a1)
1200 ; CHECK-RV32-NEXT: lh t0, 20(a1)
1201 ; CHECK-RV32-NEXT: lh a1, 16(a1)
1202 ; CHECK-RV32-NEXT: ntl.all
1203 ; CHECK-RV32-NEXT: sh a6, 14(a0)
1204 ; CHECK-RV32-NEXT: ntl.all
1205 ; CHECK-RV32-NEXT: sh a7, 12(a0)
1206 ; CHECK-RV32-NEXT: ntl.all
1207 ; CHECK-RV32-NEXT: sh t0, 10(a0)
1208 ; CHECK-RV32-NEXT: ntl.all
1209 ; CHECK-RV32-NEXT: sh a1, 8(a0)
1210 ; CHECK-RV32-NEXT: ntl.all
1211 ; CHECK-RV32-NEXT: sh a5, 6(a0)
1212 ; CHECK-RV32-NEXT: ntl.all
1213 ; CHECK-RV32-NEXT: sh a4, 4(a0)
1214 ; CHECK-RV32-NEXT: ntl.all
1215 ; CHECK-RV32-NEXT: sh a3, 2(a0)
1216 ; CHECK-RV32-NEXT: ntl.all
1217 ; CHECK-RV32-NEXT: sh a2, 0(a0)
1218 ; CHECK-RV32-NEXT: ret
1219 ;
1220 ; CHECK-RV64C-LABEL: test_nontemporal_store_v8i16:
1221 ; CHECK-RV64C: # %bb.0:
1222 ; CHECK-RV64C-NEXT: lh a6, 0(a1)
1223 ; CHECK-RV64C-NEXT: lh a7, 8(a1)
1224 ; CHECK-RV64C-NEXT: lh t0, 16(a1)
1225 ; CHECK-RV64C-NEXT: lh a5, 24(a1)
1226 ; CHECK-RV64C-NEXT: lh a2, 56(a1)
1227 ; CHECK-RV64C-NEXT: lh a3, 48(a1)
1228 ; CHECK-RV64C-NEXT: lh a4, 40(a1)
1229 ; CHECK-RV64C-NEXT: lh a1, 32(a1)
1230 ; CHECK-RV64C-NEXT: c.ntl.all
1231 ; CHECK-RV64C-NEXT: sh a2, 14(a0)
1232 ; CHECK-RV64C-NEXT: c.ntl.all
1233 ; CHECK-RV64C-NEXT: sh a3, 12(a0)
1234 ; CHECK-RV64C-NEXT: c.ntl.all
1235 ; CHECK-RV64C-NEXT: sh a4, 10(a0)
1236 ; CHECK-RV64C-NEXT: c.ntl.all
1237 ; CHECK-RV64C-NEXT: sh a1, 8(a0)
1238 ; CHECK-RV64C-NEXT: c.ntl.all
1239 ; CHECK-RV64C-NEXT: sh a5, 6(a0)
1240 ; CHECK-RV64C-NEXT: c.ntl.all
1241 ; CHECK-RV64C-NEXT: sh t0, 4(a0)
1242 ; CHECK-RV64C-NEXT: c.ntl.all
1243 ; CHECK-RV64C-NEXT: sh a7, 2(a0)
1244 ; CHECK-RV64C-NEXT: c.ntl.all
1245 ; CHECK-RV64C-NEXT: sh a6, 0(a0)
1246 ; CHECK-RV64C-NEXT: ret
1247 ;
1248 ; CHECK-RV32C-LABEL: test_nontemporal_store_v8i16:
1249 ; CHECK-RV32C: # %bb.0:
1250 ; CHECK-RV32C-NEXT: lh a6, 0(a1)
1251 ; CHECK-RV32C-NEXT: lh a7, 4(a1)
1252 ; CHECK-RV32C-NEXT: lh t0, 8(a1)
1253 ; CHECK-RV32C-NEXT: lh a5, 12(a1)
1254 ; CHECK-RV32C-NEXT: lh a2, 28(a1)
1255 ; CHECK-RV32C-NEXT: lh a3, 24(a1)
1256 ; CHECK-RV32C-NEXT: lh a4, 20(a1)
1257 ; CHECK-RV32C-NEXT: lh a1, 16(a1)
1258 ; CHECK-RV32C-NEXT: c.ntl.all
1259 ; CHECK-RV32C-NEXT: sh a2, 14(a0)
1260 ; CHECK-RV32C-NEXT: c.ntl.all
1261 ; CHECK-RV32C-NEXT: sh a3, 12(a0)
1262 ; CHECK-RV32C-NEXT: c.ntl.all
1263 ; CHECK-RV32C-NEXT: sh a4, 10(a0)
1264 ; CHECK-RV32C-NEXT: c.ntl.all
1265 ; CHECK-RV32C-NEXT: sh a1, 8(a0)
1266 ; CHECK-RV32C-NEXT: c.ntl.all
1267 ; CHECK-RV32C-NEXT: sh a5, 6(a0)
1268 ; CHECK-RV32C-NEXT: c.ntl.all
1269 ; CHECK-RV32C-NEXT: sh t0, 4(a0)
1270 ; CHECK-RV32C-NEXT: c.ntl.all
1271 ; CHECK-RV32C-NEXT: sh a7, 2(a0)
1272 ; CHECK-RV32C-NEXT: c.ntl.all
1273 ; CHECK-RV32C-NEXT: sh a6, 0(a0)
1274 ; CHECK-RV32C-NEXT: ret
1275 ;
1276 ; CHECK-RV64V-LABEL: test_nontemporal_store_v8i16:
1277 ; CHECK-RV64V: # %bb.0:
1278 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
1279 ; CHECK-RV64V-NEXT: ntl.all
1280 ; CHECK-RV64V-NEXT: vse16.v v8, (a0)
1281 ; CHECK-RV64V-NEXT: ret
1282 ;
1283 ; CHECK-RV32V-LABEL: test_nontemporal_store_v8i16:
1284 ; CHECK-RV32V: # %bb.0:
1285 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
1286 ; CHECK-RV32V-NEXT: ntl.all
1287 ; CHECK-RV32V-NEXT: vse16.v v8, (a0)
1288 ; CHECK-RV32V-NEXT: ret
1289 store <8 x i16> %v, ptr %p, !nontemporal !0
1290 ret void
1291 }
1293 define void @test_nontemporal_store_v4i32(ptr %p, <4 x i32> %v) {
1294 ; CHECK-RV64-LABEL: test_nontemporal_store_v4i32:
1295 ; CHECK-RV64: # %bb.0:
1296 ; CHECK-RV64-NEXT: lw a2, 24(a1)
1297 ; CHECK-RV64-NEXT: lw a3, 16(a1)
1298 ; CHECK-RV64-NEXT: lw a4, 8(a1)
1299 ; CHECK-RV64-NEXT: lw a1, 0(a1)
1300 ; CHECK-RV64-NEXT: ntl.all
1301 ; CHECK-RV64-NEXT: sw a2, 12(a0)
1302 ; CHECK-RV64-NEXT: ntl.all
1303 ; CHECK-RV64-NEXT: sw a3, 8(a0)
1304 ; CHECK-RV64-NEXT: ntl.all
1305 ; CHECK-RV64-NEXT: sw a4, 4(a0)
1306 ; CHECK-RV64-NEXT: ntl.all
1307 ; CHECK-RV64-NEXT: sw a1, 0(a0)
1308 ; CHECK-RV64-NEXT: ret
1309 ;
1310 ; CHECK-RV32-LABEL: test_nontemporal_store_v4i32:
1311 ; CHECK-RV32: # %bb.0:
1312 ; CHECK-RV32-NEXT: lw a2, 12(a1)
1313 ; CHECK-RV32-NEXT: lw a3, 8(a1)
1314 ; CHECK-RV32-NEXT: lw a4, 4(a1)
1315 ; CHECK-RV32-NEXT: lw a1, 0(a1)
1316 ; CHECK-RV32-NEXT: ntl.all
1317 ; CHECK-RV32-NEXT: sw a2, 12(a0)
1318 ; CHECK-RV32-NEXT: ntl.all
1319 ; CHECK-RV32-NEXT: sw a3, 8(a0)
1320 ; CHECK-RV32-NEXT: ntl.all
1321 ; CHECK-RV32-NEXT: sw a4, 4(a0)
1322 ; CHECK-RV32-NEXT: ntl.all
1323 ; CHECK-RV32-NEXT: sw a1, 0(a0)
1324 ; CHECK-RV32-NEXT: ret
1325 ;
1326 ; CHECK-RV64C-LABEL: test_nontemporal_store_v4i32:
1327 ; CHECK-RV64C: # %bb.0:
1328 ; CHECK-RV64C-NEXT: lw a2, 24(a1)
1329 ; CHECK-RV64C-NEXT: lw a3, 16(a1)
1330 ; CHECK-RV64C-NEXT: lw a4, 8(a1)
1331 ; CHECK-RV64C-NEXT: lw a1, 0(a1)
1332 ; CHECK-RV64C-NEXT: c.ntl.all
1333 ; CHECK-RV64C-NEXT: sw a2, 12(a0)
1334 ; CHECK-RV64C-NEXT: c.ntl.all
1335 ; CHECK-RV64C-NEXT: sw a3, 8(a0)
1336 ; CHECK-RV64C-NEXT: c.ntl.all
1337 ; CHECK-RV64C-NEXT: sw a4, 4(a0)
1338 ; CHECK-RV64C-NEXT: c.ntl.all
1339 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
1340 ; CHECK-RV64C-NEXT: ret
1341 ;
1342 ; CHECK-RV32C-LABEL: test_nontemporal_store_v4i32:
1343 ; CHECK-RV32C: # %bb.0:
1344 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
1345 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
1346 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
1347 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
1348 ; CHECK-RV32C-NEXT: c.ntl.all
1349 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
1350 ; CHECK-RV32C-NEXT: c.ntl.all
1351 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
1352 ; CHECK-RV32C-NEXT: c.ntl.all
1353 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
1354 ; CHECK-RV32C-NEXT: c.ntl.all
1355 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
1356 ; CHECK-RV32C-NEXT: ret
1357 ;
1358 ; CHECK-RV64V-LABEL: test_nontemporal_store_v4i32:
1359 ; CHECK-RV64V: # %bb.0:
1360 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
1361 ; CHECK-RV64V-NEXT: ntl.all
1362 ; CHECK-RV64V-NEXT: vse32.v v8, (a0)
1363 ; CHECK-RV64V-NEXT: ret
1364 ;
1365 ; CHECK-RV32V-LABEL: test_nontemporal_store_v4i32:
1366 ; CHECK-RV32V: # %bb.0:
1367 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
1368 ; CHECK-RV32V-NEXT: ntl.all
1369 ; CHECK-RV32V-NEXT: vse32.v v8, (a0)
1370 ; CHECK-RV32V-NEXT: ret
1371 store <4 x i32> %v, ptr %p, !nontemporal !0
1372 ret void
1373 }
1375 define void @test_nontemporal_store_v2i64(ptr %p, <2 x i64> %v) {
1376 ; CHECK-RV64-LABEL: test_nontemporal_store_v2i64:
1377 ; CHECK-RV64: # %bb.0:
1378 ; CHECK-RV64-NEXT: ntl.all
1379 ; CHECK-RV64-NEXT: sd a2, 8(a0)
1380 ; CHECK-RV64-NEXT: ntl.all
1381 ; CHECK-RV64-NEXT: sd a1, 0(a0)
1382 ; CHECK-RV64-NEXT: ret
1383 ;
1384 ; CHECK-RV32-LABEL: test_nontemporal_store_v2i64:
1385 ; CHECK-RV32: # %bb.0:
1386 ; CHECK-RV32-NEXT: lw a2, 12(a1)
1387 ; CHECK-RV32-NEXT: lw a3, 8(a1)
1388 ; CHECK-RV32-NEXT: lw a4, 4(a1)
1389 ; CHECK-RV32-NEXT: lw a1, 0(a1)
1390 ; CHECK-RV32-NEXT: ntl.all
1391 ; CHECK-RV32-NEXT: sw a2, 12(a0)
1392 ; CHECK-RV32-NEXT: ntl.all
1393 ; CHECK-RV32-NEXT: sw a3, 8(a0)
1394 ; CHECK-RV32-NEXT: ntl.all
1395 ; CHECK-RV32-NEXT: sw a4, 4(a0)
1396 ; CHECK-RV32-NEXT: ntl.all
1397 ; CHECK-RV32-NEXT: sw a1, 0(a0)
1398 ; CHECK-RV32-NEXT: ret
1399 ;
1400 ; CHECK-RV64C-LABEL: test_nontemporal_store_v2i64:
1401 ; CHECK-RV64C: # %bb.0:
1402 ; CHECK-RV64C-NEXT: c.ntl.all
1403 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
1404 ; CHECK-RV64C-NEXT: c.ntl.all
1405 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
1406 ; CHECK-RV64C-NEXT: ret
1407 ;
1408 ; CHECK-RV32C-LABEL: test_nontemporal_store_v2i64:
1409 ; CHECK-RV32C: # %bb.0:
1410 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
1411 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
1412 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
1413 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
1414 ; CHECK-RV32C-NEXT: c.ntl.all
1415 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
1416 ; CHECK-RV32C-NEXT: c.ntl.all
1417 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
1418 ; CHECK-RV32C-NEXT: c.ntl.all
1419 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
1420 ; CHECK-RV32C-NEXT: c.ntl.all
1421 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
1422 ; CHECK-RV32C-NEXT: ret
1423 ;
1424 ; CHECK-RV64V-LABEL: test_nontemporal_store_v2i64:
1425 ; CHECK-RV64V: # %bb.0:
1426 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1427 ; CHECK-RV64V-NEXT: ntl.all
1428 ; CHECK-RV64V-NEXT: vse64.v v8, (a0)
1429 ; CHECK-RV64V-NEXT: ret
1430 ;
1431 ; CHECK-RV32V-LABEL: test_nontemporal_store_v2i64:
1432 ; CHECK-RV32V: # %bb.0:
1433 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1434 ; CHECK-RV32V-NEXT: ntl.all
1435 ; CHECK-RV32V-NEXT: vse64.v v8, (a0)
1436 ; CHECK-RV32V-NEXT: ret
1437 store <2 x i64> %v, ptr %p, !nontemporal !0
1438 ret void
1439 }
1441 define i64 @test_nontemporal_P1_load_i64(ptr %p) {
1442 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_i64:
1443 ; CHECK-RV64: # %bb.0:
1444 ; CHECK-RV64-NEXT: ntl.p1
1445 ; CHECK-RV64-NEXT: ld a0, 0(a0)
1446 ; CHECK-RV64-NEXT: ret
1447 ;
1448 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_i64:
1449 ; CHECK-RV32: # %bb.0:
1450 ; CHECK-RV32-NEXT: ntl.p1
1451 ; CHECK-RV32-NEXT: lw a2, 0(a0)
1452 ; CHECK-RV32-NEXT: ntl.p1
1453 ; CHECK-RV32-NEXT: lw a1, 4(a0)
1454 ; CHECK-RV32-NEXT: mv a0, a2
1455 ; CHECK-RV32-NEXT: ret
1456 ;
1457 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_i64:
1458 ; CHECK-RV64C: # %bb.0:
1459 ; CHECK-RV64C-NEXT: c.ntl.p1
1460 ; CHECK-RV64C-NEXT: ld a0, 0(a0)
1461 ; CHECK-RV64C-NEXT: ret
1462 ;
1463 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_i64:
1464 ; CHECK-RV32C: # %bb.0:
1465 ; CHECK-RV32C-NEXT: c.ntl.p1
1466 ; CHECK-RV32C-NEXT: lw a2, 0(a0)
1467 ; CHECK-RV32C-NEXT: c.ntl.p1
1468 ; CHECK-RV32C-NEXT: lw a1, 4(a0)
1469 ; CHECK-RV32C-NEXT: mv a0, a2
1470 ; CHECK-RV32C-NEXT: ret
1471 ;
1472 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_i64:
1473 ; CHECK-RV64V: # %bb.0:
1474 ; CHECK-RV64V-NEXT: ntl.p1
1475 ; CHECK-RV64V-NEXT: ld a0, 0(a0)
1476 ; CHECK-RV64V-NEXT: ret
1477 ;
1478 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_i64:
1479 ; CHECK-RV32V: # %bb.0:
1480 ; CHECK-RV32V-NEXT: ntl.p1
1481 ; CHECK-RV32V-NEXT: lw a2, 0(a0)
1482 ; CHECK-RV32V-NEXT: ntl.p1
1483 ; CHECK-RV32V-NEXT: lw a1, 4(a0)
1484 ; CHECK-RV32V-NEXT: mv a0, a2
1485 ; CHECK-RV32V-NEXT: ret
1486 %1 = load i64, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1487 ret i64 %1
1488 }
1490 define i32 @test_nontemporal_P1_load_i32(ptr %p) {
1491 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_i32:
1492 ; CHECK-RV64: # %bb.0:
1493 ; CHECK-RV64-NEXT: ntl.p1
1494 ; CHECK-RV64-NEXT: lw a0, 0(a0)
1495 ; CHECK-RV64-NEXT: ret
1496 ;
1497 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_i32:
1498 ; CHECK-RV32: # %bb.0:
1499 ; CHECK-RV32-NEXT: ntl.p1
1500 ; CHECK-RV32-NEXT: lw a0, 0(a0)
1501 ; CHECK-RV32-NEXT: ret
1502 ;
1503 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_i32:
1504 ; CHECK-RV64C: # %bb.0:
1505 ; CHECK-RV64C-NEXT: c.ntl.p1
1506 ; CHECK-RV64C-NEXT: lw a0, 0(a0)
1507 ; CHECK-RV64C-NEXT: ret
1508 ;
1509 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_i32:
1510 ; CHECK-RV32C: # %bb.0:
1511 ; CHECK-RV32C-NEXT: c.ntl.p1
1512 ; CHECK-RV32C-NEXT: lw a0, 0(a0)
1513 ; CHECK-RV32C-NEXT: ret
1514 ;
1515 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_i32:
1516 ; CHECK-RV64V: # %bb.0:
1517 ; CHECK-RV64V-NEXT: ntl.p1
1518 ; CHECK-RV64V-NEXT: lw a0, 0(a0)
1519 ; CHECK-RV64V-NEXT: ret
1520 ;
1521 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_i32:
1522 ; CHECK-RV32V: # %bb.0:
1523 ; CHECK-RV32V-NEXT: ntl.p1
1524 ; CHECK-RV32V-NEXT: lw a0, 0(a0)
1525 ; CHECK-RV32V-NEXT: ret
1526 %1 = load i32, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1527 ret i32 %1
1528 }
1530 define i16 @test_nontemporal_P1_load_i16(ptr %p) {
1531 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_i16:
1532 ; CHECK-RV64: # %bb.0:
1533 ; CHECK-RV64-NEXT: ntl.p1
1534 ; CHECK-RV64-NEXT: lh a0, 0(a0)
1535 ; CHECK-RV64-NEXT: ret
1536 ;
1537 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_i16:
1538 ; CHECK-RV32: # %bb.0:
1539 ; CHECK-RV32-NEXT: ntl.p1
1540 ; CHECK-RV32-NEXT: lh a0, 0(a0)
1541 ; CHECK-RV32-NEXT: ret
1542 ;
1543 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_i16:
1544 ; CHECK-RV64C: # %bb.0:
1545 ; CHECK-RV64C-NEXT: c.ntl.p1
1546 ; CHECK-RV64C-NEXT: lh a0, 0(a0)
1547 ; CHECK-RV64C-NEXT: ret
1548 ;
1549 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_i16:
1550 ; CHECK-RV32C: # %bb.0:
1551 ; CHECK-RV32C-NEXT: c.ntl.p1
1552 ; CHECK-RV32C-NEXT: lh a0, 0(a0)
1553 ; CHECK-RV32C-NEXT: ret
1554 ;
1555 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_i16:
1556 ; CHECK-RV64V: # %bb.0:
1557 ; CHECK-RV64V-NEXT: ntl.p1
1558 ; CHECK-RV64V-NEXT: lh a0, 0(a0)
1559 ; CHECK-RV64V-NEXT: ret
1560 ;
1561 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_i16:
1562 ; CHECK-RV32V: # %bb.0:
1563 ; CHECK-RV32V-NEXT: ntl.p1
1564 ; CHECK-RV32V-NEXT: lh a0, 0(a0)
1565 ; CHECK-RV32V-NEXT: ret
1566 %1 = load i16, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1567 ret i16 %1
1568 }
1570 define i8 @test_nontemporal_P1_load_i8(ptr %p) {
1571 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_i8:
1572 ; CHECK-RV64: # %bb.0:
1573 ; CHECK-RV64-NEXT: ntl.p1
1574 ; CHECK-RV64-NEXT: lbu a0, 0(a0)
1575 ; CHECK-RV64-NEXT: ret
1576 ;
1577 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_i8:
1578 ; CHECK-RV32: # %bb.0:
1579 ; CHECK-RV32-NEXT: ntl.p1
1580 ; CHECK-RV32-NEXT: lbu a0, 0(a0)
1581 ; CHECK-RV32-NEXT: ret
1582 ;
1583 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_i8:
1584 ; CHECK-RV64C: # %bb.0:
1585 ; CHECK-RV64C-NEXT: c.ntl.p1
1586 ; CHECK-RV64C-NEXT: lbu a0, 0(a0)
1587 ; CHECK-RV64C-NEXT: ret
1588 ;
1589 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_i8:
1590 ; CHECK-RV32C: # %bb.0:
1591 ; CHECK-RV32C-NEXT: c.ntl.p1
1592 ; CHECK-RV32C-NEXT: lbu a0, 0(a0)
1593 ; CHECK-RV32C-NEXT: ret
1594 ;
1595 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_i8:
1596 ; CHECK-RV64V: # %bb.0:
1597 ; CHECK-RV64V-NEXT: ntl.p1
1598 ; CHECK-RV64V-NEXT: lbu a0, 0(a0)
1599 ; CHECK-RV64V-NEXT: ret
1600 ;
1601 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_i8:
1602 ; CHECK-RV32V: # %bb.0:
1603 ; CHECK-RV32V-NEXT: ntl.p1
1604 ; CHECK-RV32V-NEXT: lbu a0, 0(a0)
1605 ; CHECK-RV32V-NEXT: ret
1606 %1 = load i8, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1607 ret i8 %1
1608 }
1610 define half @test_nontemporal_P1_load_half(ptr %p) nounwind {
1611 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_half:
1612 ; CHECK-RV64: # %bb.0:
1613 ; CHECK-RV64-NEXT: ntl.p1
1614 ; CHECK-RV64-NEXT: flh fa5, 0(a0)
1615 ; CHECK-RV64-NEXT: ntl.p1
1616 ; CHECK-RV64-NEXT: flh fa4, 6(a0)
1617 ; CHECK-RV64-NEXT: fadd.h fa0, fa5, fa4
1618 ; CHECK-RV64-NEXT: ret
1619 ;
1620 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_half:
1621 ; CHECK-RV32: # %bb.0:
1622 ; CHECK-RV32-NEXT: ntl.p1
1623 ; CHECK-RV32-NEXT: flh fa5, 0(a0)
1624 ; CHECK-RV32-NEXT: ntl.p1
1625 ; CHECK-RV32-NEXT: flh fa4, 6(a0)
1626 ; CHECK-RV32-NEXT: fadd.h fa0, fa5, fa4
1627 ; CHECK-RV32-NEXT: ret
1628 ;
1629 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_half:
1630 ; CHECK-RV64C: # %bb.0:
1631 ; CHECK-RV64C-NEXT: c.ntl.p1
1632 ; CHECK-RV64C-NEXT: flh fa5, 0(a0)
1633 ; CHECK-RV64C-NEXT: c.ntl.p1
1634 ; CHECK-RV64C-NEXT: flh fa4, 6(a0)
1635 ; CHECK-RV64C-NEXT: fadd.h fa0, fa5, fa4
1636 ; CHECK-RV64C-NEXT: ret
1637 ;
1638 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_half:
1639 ; CHECK-RV32C: # %bb.0:
1640 ; CHECK-RV32C-NEXT: c.ntl.p1
1641 ; CHECK-RV32C-NEXT: flh fa5, 0(a0)
1642 ; CHECK-RV32C-NEXT: c.ntl.p1
1643 ; CHECK-RV32C-NEXT: flh fa4, 6(a0)
1644 ; CHECK-RV32C-NEXT: fadd.h fa0, fa5, fa4
1645 ; CHECK-RV32C-NEXT: ret
1646 ;
1647 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_half:
1648 ; CHECK-RV64V: # %bb.0:
1649 ; CHECK-RV64V-NEXT: ntl.p1
1650 ; CHECK-RV64V-NEXT: flh fa5, 0(a0)
1651 ; CHECK-RV64V-NEXT: ntl.p1
1652 ; CHECK-RV64V-NEXT: flh fa4, 6(a0)
1653 ; CHECK-RV64V-NEXT: fadd.h fa0, fa5, fa4
1654 ; CHECK-RV64V-NEXT: ret
1655 ;
1656 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_half:
1657 ; CHECK-RV32V: # %bb.0:
1658 ; CHECK-RV32V-NEXT: ntl.p1
1659 ; CHECK-RV32V-NEXT: flh fa5, 0(a0)
1660 ; CHECK-RV32V-NEXT: ntl.p1
1661 ; CHECK-RV32V-NEXT: flh fa4, 6(a0)
1662 ; CHECK-RV32V-NEXT: fadd.h fa0, fa5, fa4
1663 ; CHECK-RV32V-NEXT: ret
1664 %1 = load half, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1665 %2 = getelementptr half, ptr %p, i32 3
1666 %3 = load half, ptr %2, !nontemporal !0, !riscv-nontemporal-domain !1
1667 %4 = fadd half %1, %3
1668 ret half %4
1669 }
1671 define float @test_nontemporal_P1_load_float(ptr %p) {
1672 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_float:
1673 ; CHECK-RV64: # %bb.0:
1674 ; CHECK-RV64-NEXT: ntl.p1
1675 ; CHECK-RV64-NEXT: flw fa0, 0(a0)
1676 ; CHECK-RV64-NEXT: ret
1677 ;
1678 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_float:
1679 ; CHECK-RV32: # %bb.0:
1680 ; CHECK-RV32-NEXT: ntl.p1
1681 ; CHECK-RV32-NEXT: flw fa0, 0(a0)
1682 ; CHECK-RV32-NEXT: ret
1683 ;
1684 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_float:
1685 ; CHECK-RV64C: # %bb.0:
1686 ; CHECK-RV64C-NEXT: c.ntl.p1
1687 ; CHECK-RV64C-NEXT: flw fa0, 0(a0)
1688 ; CHECK-RV64C-NEXT: ret
1689 ;
1690 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_float:
1691 ; CHECK-RV32C: # %bb.0:
1692 ; CHECK-RV32C-NEXT: c.ntl.p1
1693 ; CHECK-RV32C-NEXT: flw fa0, 0(a0)
1694 ; CHECK-RV32C-NEXT: ret
1695 ;
1696 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_float:
1697 ; CHECK-RV64V: # %bb.0:
1698 ; CHECK-RV64V-NEXT: ntl.p1
1699 ; CHECK-RV64V-NEXT: flw fa0, 0(a0)
1700 ; CHECK-RV64V-NEXT: ret
1701 ;
1702 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_float:
1703 ; CHECK-RV32V: # %bb.0:
1704 ; CHECK-RV32V-NEXT: ntl.p1
1705 ; CHECK-RV32V-NEXT: flw fa0, 0(a0)
1706 ; CHECK-RV32V-NEXT: ret
1707 %1 = load float, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1708 ret float %1
1709 }
1711 define double @test_nontemporal_P1_load_double(ptr %p) {
1712 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_double:
1713 ; CHECK-RV64: # %bb.0:
1714 ; CHECK-RV64-NEXT: ntl.p1
1715 ; CHECK-RV64-NEXT: fld fa0, 0(a0)
1716 ; CHECK-RV64-NEXT: ret
1717 ;
1718 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_double:
1719 ; CHECK-RV32: # %bb.0:
1720 ; CHECK-RV32-NEXT: ntl.p1
1721 ; CHECK-RV32-NEXT: fld fa0, 0(a0)
1722 ; CHECK-RV32-NEXT: ret
1723 ;
1724 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_double:
1725 ; CHECK-RV64C: # %bb.0:
1726 ; CHECK-RV64C-NEXT: c.ntl.p1
1727 ; CHECK-RV64C-NEXT: fld fa0, 0(a0)
1728 ; CHECK-RV64C-NEXT: ret
1729 ;
1730 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_double:
1731 ; CHECK-RV32C: # %bb.0:
1732 ; CHECK-RV32C-NEXT: c.ntl.p1
1733 ; CHECK-RV32C-NEXT: fld fa0, 0(a0)
1734 ; CHECK-RV32C-NEXT: ret
1735 ;
1736 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_double:
1737 ; CHECK-RV64V: # %bb.0:
1738 ; CHECK-RV64V-NEXT: ntl.p1
1739 ; CHECK-RV64V-NEXT: fld fa0, 0(a0)
1740 ; CHECK-RV64V-NEXT: ret
1741 ;
1742 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_double:
1743 ; CHECK-RV32V: # %bb.0:
1744 ; CHECK-RV32V-NEXT: ntl.p1
1745 ; CHECK-RV32V-NEXT: fld fa0, 0(a0)
1746 ; CHECK-RV32V-NEXT: ret
1747 %1 = load double, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1748 ret double %1
1749 }
1751 define <16 x i8> @test_nontemporal_P1_load_v16i8(ptr %p) {
1752 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_v16i8:
1753 ; CHECK-RV64: # %bb.0:
1754 ; CHECK-RV64-NEXT: ntl.p1
1755 ; CHECK-RV64-NEXT: ld a2, 8(a1)
1756 ; CHECK-RV64-NEXT: ntl.p1
1757 ; CHECK-RV64-NEXT: ld a1, 0(a1)
1758 ; CHECK-RV64-NEXT: sd a2, 8(a0)
1759 ; CHECK-RV64-NEXT: sd a1, 0(a0)
1760 ; CHECK-RV64-NEXT: ret
1761 ;
1762 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_v16i8:
1763 ; CHECK-RV32: # %bb.0:
1764 ; CHECK-RV32-NEXT: ntl.p1
1765 ; CHECK-RV32-NEXT: lw a2, 12(a1)
1766 ; CHECK-RV32-NEXT: ntl.p1
1767 ; CHECK-RV32-NEXT: lw a3, 8(a1)
1768 ; CHECK-RV32-NEXT: ntl.p1
1769 ; CHECK-RV32-NEXT: lw a4, 4(a1)
1770 ; CHECK-RV32-NEXT: ntl.p1
1771 ; CHECK-RV32-NEXT: lw a1, 0(a1)
1772 ; CHECK-RV32-NEXT: sw a2, 12(a0)
1773 ; CHECK-RV32-NEXT: sw a3, 8(a0)
1774 ; CHECK-RV32-NEXT: sw a4, 4(a0)
1775 ; CHECK-RV32-NEXT: sw a1, 0(a0)
1776 ; CHECK-RV32-NEXT: ret
1777 ;
1778 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_v16i8:
1779 ; CHECK-RV64C: # %bb.0:
1780 ; CHECK-RV64C-NEXT: c.ntl.p1
1781 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
1782 ; CHECK-RV64C-NEXT: c.ntl.p1
1783 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
1784 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
1785 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
1786 ; CHECK-RV64C-NEXT: ret
1787 ;
1788 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_v16i8:
1789 ; CHECK-RV32C: # %bb.0:
1790 ; CHECK-RV32C-NEXT: c.ntl.p1
1791 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
1792 ; CHECK-RV32C-NEXT: c.ntl.p1
1793 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
1794 ; CHECK-RV32C-NEXT: c.ntl.p1
1795 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
1796 ; CHECK-RV32C-NEXT: c.ntl.p1
1797 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
1798 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
1799 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
1800 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
1801 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
1802 ; CHECK-RV32C-NEXT: ret
1803 ;
1804 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_v16i8:
1805 ; CHECK-RV64V: # %bb.0:
1806 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1807 ; CHECK-RV64V-NEXT: ntl.p1
1808 ; CHECK-RV64V-NEXT: vle8.v v8, (a0)
1809 ; CHECK-RV64V-NEXT: ret
1810 ;
1811 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_v16i8:
1812 ; CHECK-RV32V: # %bb.0:
1813 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1814 ; CHECK-RV32V-NEXT: ntl.p1
1815 ; CHECK-RV32V-NEXT: vle8.v v8, (a0)
1816 ; CHECK-RV32V-NEXT: ret
1817 %1 = load <16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1818 ret <16 x i8> %1
1819 }
1821 define <8 x i16> @test_nontemporal_P1_load_v8i16(ptr %p) {
1822 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_v8i16:
1823 ; CHECK-RV64: # %bb.0:
1824 ; CHECK-RV64-NEXT: ntl.p1
1825 ; CHECK-RV64-NEXT: ld a2, 8(a1)
1826 ; CHECK-RV64-NEXT: ntl.p1
1827 ; CHECK-RV64-NEXT: ld a1, 0(a1)
1828 ; CHECK-RV64-NEXT: sd a2, 8(a0)
1829 ; CHECK-RV64-NEXT: sd a1, 0(a0)
1830 ; CHECK-RV64-NEXT: ret
1831 ;
1832 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_v8i16:
1833 ; CHECK-RV32: # %bb.0:
1834 ; CHECK-RV32-NEXT: ntl.p1
1835 ; CHECK-RV32-NEXT: lw a2, 12(a1)
1836 ; CHECK-RV32-NEXT: ntl.p1
1837 ; CHECK-RV32-NEXT: lw a3, 8(a1)
1838 ; CHECK-RV32-NEXT: ntl.p1
1839 ; CHECK-RV32-NEXT: lw a4, 4(a1)
1840 ; CHECK-RV32-NEXT: ntl.p1
1841 ; CHECK-RV32-NEXT: lw a1, 0(a1)
1842 ; CHECK-RV32-NEXT: sw a2, 12(a0)
1843 ; CHECK-RV32-NEXT: sw a3, 8(a0)
1844 ; CHECK-RV32-NEXT: sw a4, 4(a0)
1845 ; CHECK-RV32-NEXT: sw a1, 0(a0)
1846 ; CHECK-RV32-NEXT: ret
1847 ;
1848 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_v8i16:
1849 ; CHECK-RV64C: # %bb.0:
1850 ; CHECK-RV64C-NEXT: c.ntl.p1
1851 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
1852 ; CHECK-RV64C-NEXT: c.ntl.p1
1853 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
1854 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
1855 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
1856 ; CHECK-RV64C-NEXT: ret
1857 ;
1858 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_v8i16:
1859 ; CHECK-RV32C: # %bb.0:
1860 ; CHECK-RV32C-NEXT: c.ntl.p1
1861 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
1862 ; CHECK-RV32C-NEXT: c.ntl.p1
1863 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
1864 ; CHECK-RV32C-NEXT: c.ntl.p1
1865 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
1866 ; CHECK-RV32C-NEXT: c.ntl.p1
1867 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
1868 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
1869 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
1870 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
1871 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
1872 ; CHECK-RV32C-NEXT: ret
1873 ;
1874 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_v8i16:
1875 ; CHECK-RV64V: # %bb.0:
1876 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
1877 ; CHECK-RV64V-NEXT: ntl.p1
1878 ; CHECK-RV64V-NEXT: vle16.v v8, (a0)
1879 ; CHECK-RV64V-NEXT: ret
1880 ;
1881 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_v8i16:
1882 ; CHECK-RV32V: # %bb.0:
1883 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
1884 ; CHECK-RV32V-NEXT: ntl.p1
1885 ; CHECK-RV32V-NEXT: vle16.v v8, (a0)
1886 ; CHECK-RV32V-NEXT: ret
1887 %1 = load <8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1888 ret <8 x i16> %1
1889 }
1891 define <4 x i32> @test_nontemporal_P1_load_v4i32(ptr %p) {
1892 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_v4i32:
1893 ; CHECK-RV64: # %bb.0:
1894 ; CHECK-RV64-NEXT: ntl.p1
1895 ; CHECK-RV64-NEXT: ld a2, 8(a1)
1896 ; CHECK-RV64-NEXT: ntl.p1
1897 ; CHECK-RV64-NEXT: ld a1, 0(a1)
1898 ; CHECK-RV64-NEXT: sd a2, 8(a0)
1899 ; CHECK-RV64-NEXT: sd a1, 0(a0)
1900 ; CHECK-RV64-NEXT: ret
1901 ;
1902 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_v4i32:
1903 ; CHECK-RV32: # %bb.0:
1904 ; CHECK-RV32-NEXT: ntl.p1
1905 ; CHECK-RV32-NEXT: lw a2, 12(a1)
1906 ; CHECK-RV32-NEXT: ntl.p1
1907 ; CHECK-RV32-NEXT: lw a3, 8(a1)
1908 ; CHECK-RV32-NEXT: ntl.p1
1909 ; CHECK-RV32-NEXT: lw a4, 4(a1)
1910 ; CHECK-RV32-NEXT: ntl.p1
1911 ; CHECK-RV32-NEXT: lw a1, 0(a1)
1912 ; CHECK-RV32-NEXT: sw a2, 12(a0)
1913 ; CHECK-RV32-NEXT: sw a3, 8(a0)
1914 ; CHECK-RV32-NEXT: sw a4, 4(a0)
1915 ; CHECK-RV32-NEXT: sw a1, 0(a0)
1916 ; CHECK-RV32-NEXT: ret
1917 ;
1918 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_v4i32:
1919 ; CHECK-RV64C: # %bb.0:
1920 ; CHECK-RV64C-NEXT: c.ntl.p1
1921 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
1922 ; CHECK-RV64C-NEXT: c.ntl.p1
1923 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
1924 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
1925 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
1926 ; CHECK-RV64C-NEXT: ret
1927 ;
1928 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_v4i32:
1929 ; CHECK-RV32C: # %bb.0:
1930 ; CHECK-RV32C-NEXT: c.ntl.p1
1931 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
1932 ; CHECK-RV32C-NEXT: c.ntl.p1
1933 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
1934 ; CHECK-RV32C-NEXT: c.ntl.p1
1935 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
1936 ; CHECK-RV32C-NEXT: c.ntl.p1
1937 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
1938 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
1939 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
1940 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
1941 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
1942 ; CHECK-RV32C-NEXT: ret
1943 ;
1944 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_v4i32:
1945 ; CHECK-RV64V: # %bb.0:
1946 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
1947 ; CHECK-RV64V-NEXT: ntl.p1
1948 ; CHECK-RV64V-NEXT: vle32.v v8, (a0)
1949 ; CHECK-RV64V-NEXT: ret
1950 ;
1951 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_v4i32:
1952 ; CHECK-RV32V: # %bb.0:
1953 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
1954 ; CHECK-RV32V-NEXT: ntl.p1
1955 ; CHECK-RV32V-NEXT: vle32.v v8, (a0)
1956 ; CHECK-RV32V-NEXT: ret
1957 %1 = load <4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
1958 ret <4 x i32> %1
1959 }
1961 define <2 x i64> @test_nontemporal_P1_load_v2i64(ptr %p) {
1962 ; CHECK-RV64-LABEL: test_nontemporal_P1_load_v2i64:
1963 ; CHECK-RV64: # %bb.0:
1964 ; CHECK-RV64-NEXT: ntl.p1
1965 ; CHECK-RV64-NEXT: ld a2, 0(a0)
1966 ; CHECK-RV64-NEXT: ntl.p1
1967 ; CHECK-RV64-NEXT: ld a1, 8(a0)
1968 ; CHECK-RV64-NEXT: mv a0, a2
1969 ; CHECK-RV64-NEXT: ret
1970 ;
1971 ; CHECK-RV32-LABEL: test_nontemporal_P1_load_v2i64:
1972 ; CHECK-RV32: # %bb.0:
1973 ; CHECK-RV32-NEXT: ntl.p1
1974 ; CHECK-RV32-NEXT: lw a2, 12(a1)
1975 ; CHECK-RV32-NEXT: ntl.p1
1976 ; CHECK-RV32-NEXT: lw a3, 8(a1)
1977 ; CHECK-RV32-NEXT: ntl.p1
1978 ; CHECK-RV32-NEXT: lw a4, 4(a1)
1979 ; CHECK-RV32-NEXT: ntl.p1
1980 ; CHECK-RV32-NEXT: lw a1, 0(a1)
1981 ; CHECK-RV32-NEXT: sw a2, 12(a0)
1982 ; CHECK-RV32-NEXT: sw a3, 8(a0)
1983 ; CHECK-RV32-NEXT: sw a4, 4(a0)
1984 ; CHECK-RV32-NEXT: sw a1, 0(a0)
1985 ; CHECK-RV32-NEXT: ret
1986 ;
1987 ; CHECK-RV64C-LABEL: test_nontemporal_P1_load_v2i64:
1988 ; CHECK-RV64C: # %bb.0:
1989 ; CHECK-RV64C-NEXT: c.ntl.p1
1990 ; CHECK-RV64C-NEXT: ld a2, 0(a0)
1991 ; CHECK-RV64C-NEXT: c.ntl.p1
1992 ; CHECK-RV64C-NEXT: ld a1, 8(a0)
1993 ; CHECK-RV64C-NEXT: mv a0, a2
1994 ; CHECK-RV64C-NEXT: ret
1995 ;
1996 ; CHECK-RV32C-LABEL: test_nontemporal_P1_load_v2i64:
1997 ; CHECK-RV32C: # %bb.0:
1998 ; CHECK-RV32C-NEXT: c.ntl.p1
1999 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
2000 ; CHECK-RV32C-NEXT: c.ntl.p1
2001 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
2002 ; CHECK-RV32C-NEXT: c.ntl.p1
2003 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
2004 ; CHECK-RV32C-NEXT: c.ntl.p1
2005 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
2006 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
2007 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
2008 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
2009 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
2010 ; CHECK-RV32C-NEXT: ret
2011 ;
2012 ; CHECK-RV64V-LABEL: test_nontemporal_P1_load_v2i64:
2013 ; CHECK-RV64V: # %bb.0:
2014 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
2015 ; CHECK-RV64V-NEXT: ntl.p1
2016 ; CHECK-RV64V-NEXT: vle64.v v8, (a0)
2017 ; CHECK-RV64V-NEXT: ret
2018 ;
2019 ; CHECK-RV32V-LABEL: test_nontemporal_P1_load_v2i64:
2020 ; CHECK-RV32V: # %bb.0:
2021 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
2022 ; CHECK-RV32V-NEXT: ntl.p1
2023 ; CHECK-RV32V-NEXT: vle64.v v8, (a0)
2024 ; CHECK-RV32V-NEXT: ret
2025 %1 = load <2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2026 ret <2 x i64> %1
2027 }
2029 define void @test_nontemporal_P1_store_i64(ptr %p, i64 %v) {
2030 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_i64:
2031 ; CHECK-RV64: # %bb.0:
2032 ; CHECK-RV64-NEXT: ntl.p1
2033 ; CHECK-RV64-NEXT: sd a1, 0(a0)
2034 ; CHECK-RV64-NEXT: ret
2035 ;
2036 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_i64:
2037 ; CHECK-RV32: # %bb.0:
2038 ; CHECK-RV32-NEXT: ntl.p1
2039 ; CHECK-RV32-NEXT: sw a2, 4(a0)
2040 ; CHECK-RV32-NEXT: ntl.p1
2041 ; CHECK-RV32-NEXT: sw a1, 0(a0)
2042 ; CHECK-RV32-NEXT: ret
2043 ;
2044 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_i64:
2045 ; CHECK-RV64C: # %bb.0:
2046 ; CHECK-RV64C-NEXT: c.ntl.p1
2047 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
2048 ; CHECK-RV64C-NEXT: ret
2049 ;
2050 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_i64:
2051 ; CHECK-RV32C: # %bb.0:
2052 ; CHECK-RV32C-NEXT: c.ntl.p1
2053 ; CHECK-RV32C-NEXT: sw a2, 4(a0)
2054 ; CHECK-RV32C-NEXT: c.ntl.p1
2055 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
2056 ; CHECK-RV32C-NEXT: ret
2057 ;
2058 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_i64:
2059 ; CHECK-RV64V: # %bb.0:
2060 ; CHECK-RV64V-NEXT: ntl.p1
2061 ; CHECK-RV64V-NEXT: sd a1, 0(a0)
2062 ; CHECK-RV64V-NEXT: ret
2063 ;
2064 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_i64:
2065 ; CHECK-RV32V: # %bb.0:
2066 ; CHECK-RV32V-NEXT: ntl.p1
2067 ; CHECK-RV32V-NEXT: sw a2, 4(a0)
2068 ; CHECK-RV32V-NEXT: ntl.p1
2069 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
2070 ; CHECK-RV32V-NEXT: ret
2071 store i64 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2072 ret void
2073 }
2075 define void @test_nontemporal_P1_store_i32(ptr %p, i32 %v) {
2076 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_i32:
2077 ; CHECK-RV64: # %bb.0:
2078 ; CHECK-RV64-NEXT: ntl.p1
2079 ; CHECK-RV64-NEXT: sw a1, 0(a0)
2080 ; CHECK-RV64-NEXT: ret
2081 ;
2082 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_i32:
2083 ; CHECK-RV32: # %bb.0:
2084 ; CHECK-RV32-NEXT: ntl.p1
2085 ; CHECK-RV32-NEXT: sw a1, 0(a0)
2086 ; CHECK-RV32-NEXT: ret
2087 ;
2088 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_i32:
2089 ; CHECK-RV64C: # %bb.0:
2090 ; CHECK-RV64C-NEXT: c.ntl.p1
2091 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
2092 ; CHECK-RV64C-NEXT: ret
2093 ;
2094 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_i32:
2095 ; CHECK-RV32C: # %bb.0:
2096 ; CHECK-RV32C-NEXT: c.ntl.p1
2097 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
2098 ; CHECK-RV32C-NEXT: ret
2099 ;
2100 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_i32:
2101 ; CHECK-RV64V: # %bb.0:
2102 ; CHECK-RV64V-NEXT: ntl.p1
2103 ; CHECK-RV64V-NEXT: sw a1, 0(a0)
2104 ; CHECK-RV64V-NEXT: ret
2105 ;
2106 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_i32:
2107 ; CHECK-RV32V: # %bb.0:
2108 ; CHECK-RV32V-NEXT: ntl.p1
2109 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
2110 ; CHECK-RV32V-NEXT: ret
2111 store i32 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2112 ret void
2113 }
2115 define void @test_nontemporal_P1_store_i16(ptr %p, i16 %v) {
2116 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_i16:
2117 ; CHECK-RV64: # %bb.0:
2118 ; CHECK-RV64-NEXT: ntl.p1
2119 ; CHECK-RV64-NEXT: sh a1, 0(a0)
2120 ; CHECK-RV64-NEXT: ret
2121 ;
2122 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_i16:
2123 ; CHECK-RV32: # %bb.0:
2124 ; CHECK-RV32-NEXT: ntl.p1
2125 ; CHECK-RV32-NEXT: sh a1, 0(a0)
2126 ; CHECK-RV32-NEXT: ret
2127 ;
2128 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_i16:
2129 ; CHECK-RV64C: # %bb.0:
2130 ; CHECK-RV64C-NEXT: c.ntl.p1
2131 ; CHECK-RV64C-NEXT: sh a1, 0(a0)
2132 ; CHECK-RV64C-NEXT: ret
2133 ;
2134 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_i16:
2135 ; CHECK-RV32C: # %bb.0:
2136 ; CHECK-RV32C-NEXT: c.ntl.p1
2137 ; CHECK-RV32C-NEXT: sh a1, 0(a0)
2138 ; CHECK-RV32C-NEXT: ret
2139 ;
2140 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_i16:
2141 ; CHECK-RV64V: # %bb.0:
2142 ; CHECK-RV64V-NEXT: ntl.p1
2143 ; CHECK-RV64V-NEXT: sh a1, 0(a0)
2144 ; CHECK-RV64V-NEXT: ret
2145 ;
2146 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_i16:
2147 ; CHECK-RV32V: # %bb.0:
2148 ; CHECK-RV32V-NEXT: ntl.p1
2149 ; CHECK-RV32V-NEXT: sh a1, 0(a0)
2150 ; CHECK-RV32V-NEXT: ret
2151 store i16 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2152 ret void
2153 }
2155 define void @test_nontemporal_P1_store_i8(ptr %p, i8 %v) {
2156 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_i8:
2157 ; CHECK-RV64: # %bb.0:
2158 ; CHECK-RV64-NEXT: ntl.p1
2159 ; CHECK-RV64-NEXT: sb a1, 0(a0)
2160 ; CHECK-RV64-NEXT: ret
2161 ;
2162 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_i8:
2163 ; CHECK-RV32: # %bb.0:
2164 ; CHECK-RV32-NEXT: ntl.p1
2165 ; CHECK-RV32-NEXT: sb a1, 0(a0)
2166 ; CHECK-RV32-NEXT: ret
2167 ;
2168 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_i8:
2169 ; CHECK-RV64C: # %bb.0:
2170 ; CHECK-RV64C-NEXT: c.ntl.p1
2171 ; CHECK-RV64C-NEXT: sb a1, 0(a0)
2172 ; CHECK-RV64C-NEXT: ret
2173 ;
2174 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_i8:
2175 ; CHECK-RV32C: # %bb.0:
2176 ; CHECK-RV32C-NEXT: c.ntl.p1
2177 ; CHECK-RV32C-NEXT: sb a1, 0(a0)
2178 ; CHECK-RV32C-NEXT: ret
2179 ;
2180 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_i8:
2181 ; CHECK-RV64V: # %bb.0:
2182 ; CHECK-RV64V-NEXT: ntl.p1
2183 ; CHECK-RV64V-NEXT: sb a1, 0(a0)
2184 ; CHECK-RV64V-NEXT: ret
2185 ;
2186 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_i8:
2187 ; CHECK-RV32V: # %bb.0:
2188 ; CHECK-RV32V-NEXT: ntl.p1
2189 ; CHECK-RV32V-NEXT: sb a1, 0(a0)
2190 ; CHECK-RV32V-NEXT: ret
2191 store i8 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2192 ret void
2193 }
2195 define void @test_nontemporal_P1_store_half(ptr %p, half %v) {
2196 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_half:
2197 ; CHECK-RV64: # %bb.0:
2198 ; CHECK-RV64-NEXT: ntl.p1
2199 ; CHECK-RV64-NEXT: fsh fa0, 0(a0)
2200 ; CHECK-RV64-NEXT: ret
2201 ;
2202 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_half:
2203 ; CHECK-RV32: # %bb.0:
2204 ; CHECK-RV32-NEXT: ntl.p1
2205 ; CHECK-RV32-NEXT: fsh fa0, 0(a0)
2206 ; CHECK-RV32-NEXT: ret
2207 ;
2208 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_half:
2209 ; CHECK-RV64C: # %bb.0:
2210 ; CHECK-RV64C-NEXT: c.ntl.p1
2211 ; CHECK-RV64C-NEXT: fsh fa0, 0(a0)
2212 ; CHECK-RV64C-NEXT: ret
2213 ;
2214 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_half:
2215 ; CHECK-RV32C: # %bb.0:
2216 ; CHECK-RV32C-NEXT: c.ntl.p1
2217 ; CHECK-RV32C-NEXT: fsh fa0, 0(a0)
2218 ; CHECK-RV32C-NEXT: ret
2219 ;
2220 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_half:
2221 ; CHECK-RV64V: # %bb.0:
2222 ; CHECK-RV64V-NEXT: ntl.p1
2223 ; CHECK-RV64V-NEXT: fsh fa0, 0(a0)
2224 ; CHECK-RV64V-NEXT: ret
2225 ;
2226 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_half:
2227 ; CHECK-RV32V: # %bb.0:
2228 ; CHECK-RV32V-NEXT: ntl.p1
2229 ; CHECK-RV32V-NEXT: fsh fa0, 0(a0)
2230 ; CHECK-RV32V-NEXT: ret
2231 store half %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2232 ret void
2233 }
2235 define void @test_nontemporal_P1_store_float(ptr %p, float %v) {
2236 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_float:
2237 ; CHECK-RV64: # %bb.0:
2238 ; CHECK-RV64-NEXT: ntl.p1
2239 ; CHECK-RV64-NEXT: fsw fa0, 0(a0)
2240 ; CHECK-RV64-NEXT: ret
2241 ;
2242 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_float:
2243 ; CHECK-RV32: # %bb.0:
2244 ; CHECK-RV32-NEXT: ntl.p1
2245 ; CHECK-RV32-NEXT: fsw fa0, 0(a0)
2246 ; CHECK-RV32-NEXT: ret
2247 ;
2248 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_float:
2249 ; CHECK-RV64C: # %bb.0:
2250 ; CHECK-RV64C-NEXT: c.ntl.p1
2251 ; CHECK-RV64C-NEXT: fsw fa0, 0(a0)
2252 ; CHECK-RV64C-NEXT: ret
2253 ;
2254 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_float:
2255 ; CHECK-RV32C: # %bb.0:
2256 ; CHECK-RV32C-NEXT: c.ntl.p1
2257 ; CHECK-RV32C-NEXT: fsw fa0, 0(a0)
2258 ; CHECK-RV32C-NEXT: ret
2259 ;
2260 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_float:
2261 ; CHECK-RV64V: # %bb.0:
2262 ; CHECK-RV64V-NEXT: ntl.p1
2263 ; CHECK-RV64V-NEXT: fsw fa0, 0(a0)
2264 ; CHECK-RV64V-NEXT: ret
2265 ;
2266 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_float:
2267 ; CHECK-RV32V: # %bb.0:
2268 ; CHECK-RV32V-NEXT: ntl.p1
2269 ; CHECK-RV32V-NEXT: fsw fa0, 0(a0)
2270 ; CHECK-RV32V-NEXT: ret
2271 store float %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2272 ret void
2273 }
2275 define void @test_nontemporal_P1_store_double(ptr %p, double %v) {
2276 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_double:
2277 ; CHECK-RV64: # %bb.0:
2278 ; CHECK-RV64-NEXT: ntl.p1
2279 ; CHECK-RV64-NEXT: fsd fa0, 0(a0)
2280 ; CHECK-RV64-NEXT: ret
2281 ;
2282 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_double:
2283 ; CHECK-RV32: # %bb.0:
2284 ; CHECK-RV32-NEXT: ntl.p1
2285 ; CHECK-RV32-NEXT: fsd fa0, 0(a0)
2286 ; CHECK-RV32-NEXT: ret
2287 ;
2288 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_double:
2289 ; CHECK-RV64C: # %bb.0:
2290 ; CHECK-RV64C-NEXT: c.ntl.p1
2291 ; CHECK-RV64C-NEXT: fsd fa0, 0(a0)
2292 ; CHECK-RV64C-NEXT: ret
2293 ;
2294 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_double:
2295 ; CHECK-RV32C: # %bb.0:
2296 ; CHECK-RV32C-NEXT: c.ntl.p1
2297 ; CHECK-RV32C-NEXT: fsd fa0, 0(a0)
2298 ; CHECK-RV32C-NEXT: ret
2299 ;
2300 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_double:
2301 ; CHECK-RV64V: # %bb.0:
2302 ; CHECK-RV64V-NEXT: ntl.p1
2303 ; CHECK-RV64V-NEXT: fsd fa0, 0(a0)
2304 ; CHECK-RV64V-NEXT: ret
2305 ;
2306 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_double:
2307 ; CHECK-RV32V: # %bb.0:
2308 ; CHECK-RV32V-NEXT: ntl.p1
2309 ; CHECK-RV32V-NEXT: fsd fa0, 0(a0)
2310 ; CHECK-RV32V-NEXT: ret
2311 store double %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2312 ret void
2313 }
2315 define void @test_nontemporal_P1_store_v16i8(ptr %p, <16 x i8> %v) {
2316 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_v16i8:
2317 ; CHECK-RV64: # %bb.0:
2318 ; CHECK-RV64-NEXT: addi sp, sp, -16
2319 ; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
2320 ; CHECK-RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
2321 ; CHECK-RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
2322 ; CHECK-RV64-NEXT: .cfi_offset s0, -8
2323 ; CHECK-RV64-NEXT: .cfi_offset s1, -16
2324 ; CHECK-RV64-NEXT: lbu a2, 0(a1)
2325 ; CHECK-RV64-NEXT: lbu a3, 8(a1)
2326 ; CHECK-RV64-NEXT: lbu a4, 16(a1)
2327 ; CHECK-RV64-NEXT: lbu a5, 24(a1)
2328 ; CHECK-RV64-NEXT: lbu a6, 32(a1)
2329 ; CHECK-RV64-NEXT: lbu a7, 40(a1)
2330 ; CHECK-RV64-NEXT: lbu t0, 48(a1)
2331 ; CHECK-RV64-NEXT: lbu t1, 56(a1)
2332 ; CHECK-RV64-NEXT: lbu t2, 64(a1)
2333 ; CHECK-RV64-NEXT: lbu t3, 72(a1)
2334 ; CHECK-RV64-NEXT: lbu t4, 80(a1)
2335 ; CHECK-RV64-NEXT: lbu t5, 88(a1)
2336 ; CHECK-RV64-NEXT: lbu t6, 120(a1)
2337 ; CHECK-RV64-NEXT: lbu s0, 112(a1)
2338 ; CHECK-RV64-NEXT: lbu s1, 104(a1)
2339 ; CHECK-RV64-NEXT: lbu a1, 96(a1)
2340 ; CHECK-RV64-NEXT: ntl.p1
2341 ; CHECK-RV64-NEXT: sb t6, 15(a0)
2342 ; CHECK-RV64-NEXT: ntl.p1
2343 ; CHECK-RV64-NEXT: sb s0, 14(a0)
2344 ; CHECK-RV64-NEXT: ntl.p1
2345 ; CHECK-RV64-NEXT: sb s1, 13(a0)
2346 ; CHECK-RV64-NEXT: ntl.p1
2347 ; CHECK-RV64-NEXT: sb a1, 12(a0)
2348 ; CHECK-RV64-NEXT: ntl.p1
2349 ; CHECK-RV64-NEXT: sb t5, 11(a0)
2350 ; CHECK-RV64-NEXT: ntl.p1
2351 ; CHECK-RV64-NEXT: sb t4, 10(a0)
2352 ; CHECK-RV64-NEXT: ntl.p1
2353 ; CHECK-RV64-NEXT: sb t3, 9(a0)
2354 ; CHECK-RV64-NEXT: ntl.p1
2355 ; CHECK-RV64-NEXT: sb t2, 8(a0)
2356 ; CHECK-RV64-NEXT: ntl.p1
2357 ; CHECK-RV64-NEXT: sb t1, 7(a0)
2358 ; CHECK-RV64-NEXT: ntl.p1
2359 ; CHECK-RV64-NEXT: sb t0, 6(a0)
2360 ; CHECK-RV64-NEXT: ntl.p1
2361 ; CHECK-RV64-NEXT: sb a7, 5(a0)
2362 ; CHECK-RV64-NEXT: ntl.p1
2363 ; CHECK-RV64-NEXT: sb a6, 4(a0)
2364 ; CHECK-RV64-NEXT: ntl.p1
2365 ; CHECK-RV64-NEXT: sb a5, 3(a0)
2366 ; CHECK-RV64-NEXT: ntl.p1
2367 ; CHECK-RV64-NEXT: sb a4, 2(a0)
2368 ; CHECK-RV64-NEXT: ntl.p1
2369 ; CHECK-RV64-NEXT: sb a3, 1(a0)
2370 ; CHECK-RV64-NEXT: ntl.p1
2371 ; CHECK-RV64-NEXT: sb a2, 0(a0)
2372 ; CHECK-RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
2373 ; CHECK-RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
2374 ; CHECK-RV64-NEXT: addi sp, sp, 16
2375 ; CHECK-RV64-NEXT: ret
2376 ;
2377 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_v16i8:
2378 ; CHECK-RV32: # %bb.0:
2379 ; CHECK-RV32-NEXT: addi sp, sp, -16
2380 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
2381 ; CHECK-RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
2382 ; CHECK-RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
2383 ; CHECK-RV32-NEXT: .cfi_offset s0, -4
2384 ; CHECK-RV32-NEXT: .cfi_offset s1, -8
2385 ; CHECK-RV32-NEXT: lbu a2, 0(a1)
2386 ; CHECK-RV32-NEXT: lbu a3, 4(a1)
2387 ; CHECK-RV32-NEXT: lbu a4, 8(a1)
2388 ; CHECK-RV32-NEXT: lbu a5, 12(a1)
2389 ; CHECK-RV32-NEXT: lbu a6, 16(a1)
2390 ; CHECK-RV32-NEXT: lbu a7, 20(a1)
2391 ; CHECK-RV32-NEXT: lbu t0, 24(a1)
2392 ; CHECK-RV32-NEXT: lbu t1, 28(a1)
2393 ; CHECK-RV32-NEXT: lbu t2, 32(a1)
2394 ; CHECK-RV32-NEXT: lbu t3, 36(a1)
2395 ; CHECK-RV32-NEXT: lbu t4, 40(a1)
2396 ; CHECK-RV32-NEXT: lbu t5, 44(a1)
2397 ; CHECK-RV32-NEXT: lbu t6, 60(a1)
2398 ; CHECK-RV32-NEXT: lbu s0, 56(a1)
2399 ; CHECK-RV32-NEXT: lbu s1, 52(a1)
2400 ; CHECK-RV32-NEXT: lbu a1, 48(a1)
2401 ; CHECK-RV32-NEXT: ntl.p1
2402 ; CHECK-RV32-NEXT: sb t6, 15(a0)
2403 ; CHECK-RV32-NEXT: ntl.p1
2404 ; CHECK-RV32-NEXT: sb s0, 14(a0)
2405 ; CHECK-RV32-NEXT: ntl.p1
2406 ; CHECK-RV32-NEXT: sb s1, 13(a0)
2407 ; CHECK-RV32-NEXT: ntl.p1
2408 ; CHECK-RV32-NEXT: sb a1, 12(a0)
2409 ; CHECK-RV32-NEXT: ntl.p1
2410 ; CHECK-RV32-NEXT: sb t5, 11(a0)
2411 ; CHECK-RV32-NEXT: ntl.p1
2412 ; CHECK-RV32-NEXT: sb t4, 10(a0)
2413 ; CHECK-RV32-NEXT: ntl.p1
2414 ; CHECK-RV32-NEXT: sb t3, 9(a0)
2415 ; CHECK-RV32-NEXT: ntl.p1
2416 ; CHECK-RV32-NEXT: sb t2, 8(a0)
2417 ; CHECK-RV32-NEXT: ntl.p1
2418 ; CHECK-RV32-NEXT: sb t1, 7(a0)
2419 ; CHECK-RV32-NEXT: ntl.p1
2420 ; CHECK-RV32-NEXT: sb t0, 6(a0)
2421 ; CHECK-RV32-NEXT: ntl.p1
2422 ; CHECK-RV32-NEXT: sb a7, 5(a0)
2423 ; CHECK-RV32-NEXT: ntl.p1
2424 ; CHECK-RV32-NEXT: sb a6, 4(a0)
2425 ; CHECK-RV32-NEXT: ntl.p1
2426 ; CHECK-RV32-NEXT: sb a5, 3(a0)
2427 ; CHECK-RV32-NEXT: ntl.p1
2428 ; CHECK-RV32-NEXT: sb a4, 2(a0)
2429 ; CHECK-RV32-NEXT: ntl.p1
2430 ; CHECK-RV32-NEXT: sb a3, 1(a0)
2431 ; CHECK-RV32-NEXT: ntl.p1
2432 ; CHECK-RV32-NEXT: sb a2, 0(a0)
2433 ; CHECK-RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
2434 ; CHECK-RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
2435 ; CHECK-RV32-NEXT: addi sp, sp, 16
2436 ; CHECK-RV32-NEXT: ret
2437 ;
2438 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_v16i8:
2439 ; CHECK-RV64C: # %bb.0:
2440 ; CHECK-RV64C-NEXT: addi sp, sp, -16
2441 ; CHECK-RV64C-NEXT: .cfi_def_cfa_offset 16
2442 ; CHECK-RV64C-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
2443 ; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
2444 ; CHECK-RV64C-NEXT: .cfi_offset s0, -8
2445 ; CHECK-RV64C-NEXT: .cfi_offset s1, -16
2446 ; CHECK-RV64C-NEXT: lbu a6, 0(a1)
2447 ; CHECK-RV64C-NEXT: lbu a7, 8(a1)
2448 ; CHECK-RV64C-NEXT: lbu t0, 16(a1)
2449 ; CHECK-RV64C-NEXT: lbu t1, 24(a1)
2450 ; CHECK-RV64C-NEXT: lbu t2, 32(a1)
2451 ; CHECK-RV64C-NEXT: lbu t3, 40(a1)
2452 ; CHECK-RV64C-NEXT: lbu t4, 48(a1)
2453 ; CHECK-RV64C-NEXT: lbu t5, 56(a1)
2454 ; CHECK-RV64C-NEXT: lbu t6, 64(a1)
2455 ; CHECK-RV64C-NEXT: lbu a3, 72(a1)
2456 ; CHECK-RV64C-NEXT: lbu a4, 80(a1)
2457 ; CHECK-RV64C-NEXT: lbu a5, 88(a1)
2458 ; CHECK-RV64C-NEXT: lbu a2, 120(a1)
2459 ; CHECK-RV64C-NEXT: lbu s0, 112(a1)
2460 ; CHECK-RV64C-NEXT: lbu s1, 104(a1)
2461 ; CHECK-RV64C-NEXT: lbu a1, 96(a1)
2462 ; CHECK-RV64C-NEXT: c.ntl.p1
2463 ; CHECK-RV64C-NEXT: sb a2, 15(a0)
2464 ; CHECK-RV64C-NEXT: c.ntl.p1
2465 ; CHECK-RV64C-NEXT: sb s0, 14(a0)
2466 ; CHECK-RV64C-NEXT: c.ntl.p1
2467 ; CHECK-RV64C-NEXT: sb s1, 13(a0)
2468 ; CHECK-RV64C-NEXT: c.ntl.p1
2469 ; CHECK-RV64C-NEXT: sb a1, 12(a0)
2470 ; CHECK-RV64C-NEXT: c.ntl.p1
2471 ; CHECK-RV64C-NEXT: sb a5, 11(a0)
2472 ; CHECK-RV64C-NEXT: c.ntl.p1
2473 ; CHECK-RV64C-NEXT: sb a4, 10(a0)
2474 ; CHECK-RV64C-NEXT: c.ntl.p1
2475 ; CHECK-RV64C-NEXT: sb a3, 9(a0)
2476 ; CHECK-RV64C-NEXT: c.ntl.p1
2477 ; CHECK-RV64C-NEXT: sb t6, 8(a0)
2478 ; CHECK-RV64C-NEXT: c.ntl.p1
2479 ; CHECK-RV64C-NEXT: sb t5, 7(a0)
2480 ; CHECK-RV64C-NEXT: c.ntl.p1
2481 ; CHECK-RV64C-NEXT: sb t4, 6(a0)
2482 ; CHECK-RV64C-NEXT: c.ntl.p1
2483 ; CHECK-RV64C-NEXT: sb t3, 5(a0)
2484 ; CHECK-RV64C-NEXT: c.ntl.p1
2485 ; CHECK-RV64C-NEXT: sb t2, 4(a0)
2486 ; CHECK-RV64C-NEXT: c.ntl.p1
2487 ; CHECK-RV64C-NEXT: sb t1, 3(a0)
2488 ; CHECK-RV64C-NEXT: c.ntl.p1
2489 ; CHECK-RV64C-NEXT: sb t0, 2(a0)
2490 ; CHECK-RV64C-NEXT: c.ntl.p1
2491 ; CHECK-RV64C-NEXT: sb a7, 1(a0)
2492 ; CHECK-RV64C-NEXT: c.ntl.p1
2493 ; CHECK-RV64C-NEXT: sb a6, 0(a0)
2494 ; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
2495 ; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
2496 ; CHECK-RV64C-NEXT: addi sp, sp, 16
2497 ; CHECK-RV64C-NEXT: ret
2498 ;
2499 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_v16i8:
2500 ; CHECK-RV32C: # %bb.0:
2501 ; CHECK-RV32C-NEXT: addi sp, sp, -16
2502 ; CHECK-RV32C-NEXT: .cfi_def_cfa_offset 16
2503 ; CHECK-RV32C-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
2504 ; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
2505 ; CHECK-RV32C-NEXT: .cfi_offset s0, -4
2506 ; CHECK-RV32C-NEXT: .cfi_offset s1, -8
2507 ; CHECK-RV32C-NEXT: lbu a6, 0(a1)
2508 ; CHECK-RV32C-NEXT: lbu a7, 4(a1)
2509 ; CHECK-RV32C-NEXT: lbu t0, 8(a1)
2510 ; CHECK-RV32C-NEXT: lbu t1, 12(a1)
2511 ; CHECK-RV32C-NEXT: lbu t2, 16(a1)
2512 ; CHECK-RV32C-NEXT: lbu t3, 20(a1)
2513 ; CHECK-RV32C-NEXT: lbu t4, 24(a1)
2514 ; CHECK-RV32C-NEXT: lbu t5, 28(a1)
2515 ; CHECK-RV32C-NEXT: lbu t6, 32(a1)
2516 ; CHECK-RV32C-NEXT: lbu a3, 36(a1)
2517 ; CHECK-RV32C-NEXT: lbu a4, 40(a1)
2518 ; CHECK-RV32C-NEXT: lbu a5, 44(a1)
2519 ; CHECK-RV32C-NEXT: lbu a2, 60(a1)
2520 ; CHECK-RV32C-NEXT: lbu s0, 56(a1)
2521 ; CHECK-RV32C-NEXT: lbu s1, 52(a1)
2522 ; CHECK-RV32C-NEXT: lbu a1, 48(a1)
2523 ; CHECK-RV32C-NEXT: c.ntl.p1
2524 ; CHECK-RV32C-NEXT: sb a2, 15(a0)
2525 ; CHECK-RV32C-NEXT: c.ntl.p1
2526 ; CHECK-RV32C-NEXT: sb s0, 14(a0)
2527 ; CHECK-RV32C-NEXT: c.ntl.p1
2528 ; CHECK-RV32C-NEXT: sb s1, 13(a0)
2529 ; CHECK-RV32C-NEXT: c.ntl.p1
2530 ; CHECK-RV32C-NEXT: sb a1, 12(a0)
2531 ; CHECK-RV32C-NEXT: c.ntl.p1
2532 ; CHECK-RV32C-NEXT: sb a5, 11(a0)
2533 ; CHECK-RV32C-NEXT: c.ntl.p1
2534 ; CHECK-RV32C-NEXT: sb a4, 10(a0)
2535 ; CHECK-RV32C-NEXT: c.ntl.p1
2536 ; CHECK-RV32C-NEXT: sb a3, 9(a0)
2537 ; CHECK-RV32C-NEXT: c.ntl.p1
2538 ; CHECK-RV32C-NEXT: sb t6, 8(a0)
2539 ; CHECK-RV32C-NEXT: c.ntl.p1
2540 ; CHECK-RV32C-NEXT: sb t5, 7(a0)
2541 ; CHECK-RV32C-NEXT: c.ntl.p1
2542 ; CHECK-RV32C-NEXT: sb t4, 6(a0)
2543 ; CHECK-RV32C-NEXT: c.ntl.p1
2544 ; CHECK-RV32C-NEXT: sb t3, 5(a0)
2545 ; CHECK-RV32C-NEXT: c.ntl.p1
2546 ; CHECK-RV32C-NEXT: sb t2, 4(a0)
2547 ; CHECK-RV32C-NEXT: c.ntl.p1
2548 ; CHECK-RV32C-NEXT: sb t1, 3(a0)
2549 ; CHECK-RV32C-NEXT: c.ntl.p1
2550 ; CHECK-RV32C-NEXT: sb t0, 2(a0)
2551 ; CHECK-RV32C-NEXT: c.ntl.p1
2552 ; CHECK-RV32C-NEXT: sb a7, 1(a0)
2553 ; CHECK-RV32C-NEXT: c.ntl.p1
2554 ; CHECK-RV32C-NEXT: sb a6, 0(a0)
2555 ; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
2556 ; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
2557 ; CHECK-RV32C-NEXT: addi sp, sp, 16
2558 ; CHECK-RV32C-NEXT: ret
2559 ;
2560 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_v16i8:
2561 ; CHECK-RV64V: # %bb.0:
2562 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
2563 ; CHECK-RV64V-NEXT: ntl.p1
2564 ; CHECK-RV64V-NEXT: vse8.v v8, (a0)
2565 ; CHECK-RV64V-NEXT: ret
2566 ;
2567 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_v16i8:
2568 ; CHECK-RV32V: # %bb.0:
2569 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
2570 ; CHECK-RV32V-NEXT: ntl.p1
2571 ; CHECK-RV32V-NEXT: vse8.v v8, (a0)
2572 ; CHECK-RV32V-NEXT: ret
2573 store <16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2574 ret void
2575 }
2577 define void @test_nontemporal_P1_store_v8i16(ptr %p, <8 x i16> %v) {
2578 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_v8i16:
2579 ; CHECK-RV64: # %bb.0:
2580 ; CHECK-RV64-NEXT: lh a2, 0(a1)
2581 ; CHECK-RV64-NEXT: lh a3, 8(a1)
2582 ; CHECK-RV64-NEXT: lh a4, 16(a1)
2583 ; CHECK-RV64-NEXT: lh a5, 24(a1)
2584 ; CHECK-RV64-NEXT: lh a6, 56(a1)
2585 ; CHECK-RV64-NEXT: lh a7, 48(a1)
2586 ; CHECK-RV64-NEXT: lh t0, 40(a1)
2587 ; CHECK-RV64-NEXT: lh a1, 32(a1)
2588 ; CHECK-RV64-NEXT: ntl.p1
2589 ; CHECK-RV64-NEXT: sh a6, 14(a0)
2590 ; CHECK-RV64-NEXT: ntl.p1
2591 ; CHECK-RV64-NEXT: sh a7, 12(a0)
2592 ; CHECK-RV64-NEXT: ntl.p1
2593 ; CHECK-RV64-NEXT: sh t0, 10(a0)
2594 ; CHECK-RV64-NEXT: ntl.p1
2595 ; CHECK-RV64-NEXT: sh a1, 8(a0)
2596 ; CHECK-RV64-NEXT: ntl.p1
2597 ; CHECK-RV64-NEXT: sh a5, 6(a0)
2598 ; CHECK-RV64-NEXT: ntl.p1
2599 ; CHECK-RV64-NEXT: sh a4, 4(a0)
2600 ; CHECK-RV64-NEXT: ntl.p1
2601 ; CHECK-RV64-NEXT: sh a3, 2(a0)
2602 ; CHECK-RV64-NEXT: ntl.p1
2603 ; CHECK-RV64-NEXT: sh a2, 0(a0)
2604 ; CHECK-RV64-NEXT: ret
2605 ;
2606 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_v8i16:
2607 ; CHECK-RV32: # %bb.0:
2608 ; CHECK-RV32-NEXT: lh a2, 0(a1)
2609 ; CHECK-RV32-NEXT: lh a3, 4(a1)
2610 ; CHECK-RV32-NEXT: lh a4, 8(a1)
2611 ; CHECK-RV32-NEXT: lh a5, 12(a1)
2612 ; CHECK-RV32-NEXT: lh a6, 28(a1)
2613 ; CHECK-RV32-NEXT: lh a7, 24(a1)
2614 ; CHECK-RV32-NEXT: lh t0, 20(a1)
2615 ; CHECK-RV32-NEXT: lh a1, 16(a1)
2616 ; CHECK-RV32-NEXT: ntl.p1
2617 ; CHECK-RV32-NEXT: sh a6, 14(a0)
2618 ; CHECK-RV32-NEXT: ntl.p1
2619 ; CHECK-RV32-NEXT: sh a7, 12(a0)
2620 ; CHECK-RV32-NEXT: ntl.p1
2621 ; CHECK-RV32-NEXT: sh t0, 10(a0)
2622 ; CHECK-RV32-NEXT: ntl.p1
2623 ; CHECK-RV32-NEXT: sh a1, 8(a0)
2624 ; CHECK-RV32-NEXT: ntl.p1
2625 ; CHECK-RV32-NEXT: sh a5, 6(a0)
2626 ; CHECK-RV32-NEXT: ntl.p1
2627 ; CHECK-RV32-NEXT: sh a4, 4(a0)
2628 ; CHECK-RV32-NEXT: ntl.p1
2629 ; CHECK-RV32-NEXT: sh a3, 2(a0)
2630 ; CHECK-RV32-NEXT: ntl.p1
2631 ; CHECK-RV32-NEXT: sh a2, 0(a0)
2632 ; CHECK-RV32-NEXT: ret
2633 ;
2634 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_v8i16:
2635 ; CHECK-RV64C: # %bb.0:
2636 ; CHECK-RV64C-NEXT: lh a6, 0(a1)
2637 ; CHECK-RV64C-NEXT: lh a7, 8(a1)
2638 ; CHECK-RV64C-NEXT: lh t0, 16(a1)
2639 ; CHECK-RV64C-NEXT: lh a5, 24(a1)
2640 ; CHECK-RV64C-NEXT: lh a2, 56(a1)
2641 ; CHECK-RV64C-NEXT: lh a3, 48(a1)
2642 ; CHECK-RV64C-NEXT: lh a4, 40(a1)
2643 ; CHECK-RV64C-NEXT: lh a1, 32(a1)
2644 ; CHECK-RV64C-NEXT: c.ntl.p1
2645 ; CHECK-RV64C-NEXT: sh a2, 14(a0)
2646 ; CHECK-RV64C-NEXT: c.ntl.p1
2647 ; CHECK-RV64C-NEXT: sh a3, 12(a0)
2648 ; CHECK-RV64C-NEXT: c.ntl.p1
2649 ; CHECK-RV64C-NEXT: sh a4, 10(a0)
2650 ; CHECK-RV64C-NEXT: c.ntl.p1
2651 ; CHECK-RV64C-NEXT: sh a1, 8(a0)
2652 ; CHECK-RV64C-NEXT: c.ntl.p1
2653 ; CHECK-RV64C-NEXT: sh a5, 6(a0)
2654 ; CHECK-RV64C-NEXT: c.ntl.p1
2655 ; CHECK-RV64C-NEXT: sh t0, 4(a0)
2656 ; CHECK-RV64C-NEXT: c.ntl.p1
2657 ; CHECK-RV64C-NEXT: sh a7, 2(a0)
2658 ; CHECK-RV64C-NEXT: c.ntl.p1
2659 ; CHECK-RV64C-NEXT: sh a6, 0(a0)
2660 ; CHECK-RV64C-NEXT: ret
2661 ;
2662 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_v8i16:
2663 ; CHECK-RV32C: # %bb.0:
2664 ; CHECK-RV32C-NEXT: lh a6, 0(a1)
2665 ; CHECK-RV32C-NEXT: lh a7, 4(a1)
2666 ; CHECK-RV32C-NEXT: lh t0, 8(a1)
2667 ; CHECK-RV32C-NEXT: lh a5, 12(a1)
2668 ; CHECK-RV32C-NEXT: lh a2, 28(a1)
2669 ; CHECK-RV32C-NEXT: lh a3, 24(a1)
2670 ; CHECK-RV32C-NEXT: lh a4, 20(a1)
2671 ; CHECK-RV32C-NEXT: lh a1, 16(a1)
2672 ; CHECK-RV32C-NEXT: c.ntl.p1
2673 ; CHECK-RV32C-NEXT: sh a2, 14(a0)
2674 ; CHECK-RV32C-NEXT: c.ntl.p1
2675 ; CHECK-RV32C-NEXT: sh a3, 12(a0)
2676 ; CHECK-RV32C-NEXT: c.ntl.p1
2677 ; CHECK-RV32C-NEXT: sh a4, 10(a0)
2678 ; CHECK-RV32C-NEXT: c.ntl.p1
2679 ; CHECK-RV32C-NEXT: sh a1, 8(a0)
2680 ; CHECK-RV32C-NEXT: c.ntl.p1
2681 ; CHECK-RV32C-NEXT: sh a5, 6(a0)
2682 ; CHECK-RV32C-NEXT: c.ntl.p1
2683 ; CHECK-RV32C-NEXT: sh t0, 4(a0)
2684 ; CHECK-RV32C-NEXT: c.ntl.p1
2685 ; CHECK-RV32C-NEXT: sh a7, 2(a0)
2686 ; CHECK-RV32C-NEXT: c.ntl.p1
2687 ; CHECK-RV32C-NEXT: sh a6, 0(a0)
2688 ; CHECK-RV32C-NEXT: ret
2689 ;
2690 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_v8i16:
2691 ; CHECK-RV64V: # %bb.0:
2692 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
2693 ; CHECK-RV64V-NEXT: ntl.p1
2694 ; CHECK-RV64V-NEXT: vse16.v v8, (a0)
2695 ; CHECK-RV64V-NEXT: ret
2696 ;
2697 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_v8i16:
2698 ; CHECK-RV32V: # %bb.0:
2699 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
2700 ; CHECK-RV32V-NEXT: ntl.p1
2701 ; CHECK-RV32V-NEXT: vse16.v v8, (a0)
2702 ; CHECK-RV32V-NEXT: ret
2703 store <8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2704 ret void
2705 }
2707 define void @test_nontemporal_P1_store_v4i32(ptr %p, <4 x i32> %v) {
2708 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_v4i32:
2709 ; CHECK-RV64: # %bb.0:
2710 ; CHECK-RV64-NEXT: lw a2, 24(a1)
2711 ; CHECK-RV64-NEXT: lw a3, 16(a1)
2712 ; CHECK-RV64-NEXT: lw a4, 8(a1)
2713 ; CHECK-RV64-NEXT: lw a1, 0(a1)
2714 ; CHECK-RV64-NEXT: ntl.p1
2715 ; CHECK-RV64-NEXT: sw a2, 12(a0)
2716 ; CHECK-RV64-NEXT: ntl.p1
2717 ; CHECK-RV64-NEXT: sw a3, 8(a0)
2718 ; CHECK-RV64-NEXT: ntl.p1
2719 ; CHECK-RV64-NEXT: sw a4, 4(a0)
2720 ; CHECK-RV64-NEXT: ntl.p1
2721 ; CHECK-RV64-NEXT: sw a1, 0(a0)
2722 ; CHECK-RV64-NEXT: ret
2723 ;
2724 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_v4i32:
2725 ; CHECK-RV32: # %bb.0:
2726 ; CHECK-RV32-NEXT: lw a2, 12(a1)
2727 ; CHECK-RV32-NEXT: lw a3, 8(a1)
2728 ; CHECK-RV32-NEXT: lw a4, 4(a1)
2729 ; CHECK-RV32-NEXT: lw a1, 0(a1)
2730 ; CHECK-RV32-NEXT: ntl.p1
2731 ; CHECK-RV32-NEXT: sw a2, 12(a0)
2732 ; CHECK-RV32-NEXT: ntl.p1
2733 ; CHECK-RV32-NEXT: sw a3, 8(a0)
2734 ; CHECK-RV32-NEXT: ntl.p1
2735 ; CHECK-RV32-NEXT: sw a4, 4(a0)
2736 ; CHECK-RV32-NEXT: ntl.p1
2737 ; CHECK-RV32-NEXT: sw a1, 0(a0)
2738 ; CHECK-RV32-NEXT: ret
2739 ;
2740 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_v4i32:
2741 ; CHECK-RV64C: # %bb.0:
2742 ; CHECK-RV64C-NEXT: lw a2, 24(a1)
2743 ; CHECK-RV64C-NEXT: lw a3, 16(a1)
2744 ; CHECK-RV64C-NEXT: lw a4, 8(a1)
2745 ; CHECK-RV64C-NEXT: lw a1, 0(a1)
2746 ; CHECK-RV64C-NEXT: c.ntl.p1
2747 ; CHECK-RV64C-NEXT: sw a2, 12(a0)
2748 ; CHECK-RV64C-NEXT: c.ntl.p1
2749 ; CHECK-RV64C-NEXT: sw a3, 8(a0)
2750 ; CHECK-RV64C-NEXT: c.ntl.p1
2751 ; CHECK-RV64C-NEXT: sw a4, 4(a0)
2752 ; CHECK-RV64C-NEXT: c.ntl.p1
2753 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
2754 ; CHECK-RV64C-NEXT: ret
2755 ;
2756 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_v4i32:
2757 ; CHECK-RV32C: # %bb.0:
2758 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
2759 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
2760 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
2761 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
2762 ; CHECK-RV32C-NEXT: c.ntl.p1
2763 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
2764 ; CHECK-RV32C-NEXT: c.ntl.p1
2765 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
2766 ; CHECK-RV32C-NEXT: c.ntl.p1
2767 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
2768 ; CHECK-RV32C-NEXT: c.ntl.p1
2769 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
2770 ; CHECK-RV32C-NEXT: ret
2771 ;
2772 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_v4i32:
2773 ; CHECK-RV64V: # %bb.0:
2774 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
2775 ; CHECK-RV64V-NEXT: ntl.p1
2776 ; CHECK-RV64V-NEXT: vse32.v v8, (a0)
2777 ; CHECK-RV64V-NEXT: ret
2778 ;
2779 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_v4i32:
2780 ; CHECK-RV32V: # %bb.0:
2781 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
2782 ; CHECK-RV32V-NEXT: ntl.p1
2783 ; CHECK-RV32V-NEXT: vse32.v v8, (a0)
2784 ; CHECK-RV32V-NEXT: ret
2785 store <4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2786 ret void
2787 }
2789 define void @test_nontemporal_P1_store_v2i64(ptr %p, <2 x i64> %v) {
2790 ; CHECK-RV64-LABEL: test_nontemporal_P1_store_v2i64:
2791 ; CHECK-RV64: # %bb.0:
2792 ; CHECK-RV64-NEXT: ntl.p1
2793 ; CHECK-RV64-NEXT: sd a2, 8(a0)
2794 ; CHECK-RV64-NEXT: ntl.p1
2795 ; CHECK-RV64-NEXT: sd a1, 0(a0)
2796 ; CHECK-RV64-NEXT: ret
2797 ;
2798 ; CHECK-RV32-LABEL: test_nontemporal_P1_store_v2i64:
2799 ; CHECK-RV32: # %bb.0:
2800 ; CHECK-RV32-NEXT: lw a2, 12(a1)
2801 ; CHECK-RV32-NEXT: lw a3, 8(a1)
2802 ; CHECK-RV32-NEXT: lw a4, 4(a1)
2803 ; CHECK-RV32-NEXT: lw a1, 0(a1)
2804 ; CHECK-RV32-NEXT: ntl.p1
2805 ; CHECK-RV32-NEXT: sw a2, 12(a0)
2806 ; CHECK-RV32-NEXT: ntl.p1
2807 ; CHECK-RV32-NEXT: sw a3, 8(a0)
2808 ; CHECK-RV32-NEXT: ntl.p1
2809 ; CHECK-RV32-NEXT: sw a4, 4(a0)
2810 ; CHECK-RV32-NEXT: ntl.p1
2811 ; CHECK-RV32-NEXT: sw a1, 0(a0)
2812 ; CHECK-RV32-NEXT: ret
2813 ;
2814 ; CHECK-RV64C-LABEL: test_nontemporal_P1_store_v2i64:
2815 ; CHECK-RV64C: # %bb.0:
2816 ; CHECK-RV64C-NEXT: c.ntl.p1
2817 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
2818 ; CHECK-RV64C-NEXT: c.ntl.p1
2819 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
2820 ; CHECK-RV64C-NEXT: ret
2821 ;
2822 ; CHECK-RV32C-LABEL: test_nontemporal_P1_store_v2i64:
2823 ; CHECK-RV32C: # %bb.0:
2824 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
2825 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
2826 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
2827 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
2828 ; CHECK-RV32C-NEXT: c.ntl.p1
2829 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
2830 ; CHECK-RV32C-NEXT: c.ntl.p1
2831 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
2832 ; CHECK-RV32C-NEXT: c.ntl.p1
2833 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
2834 ; CHECK-RV32C-NEXT: c.ntl.p1
2835 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
2836 ; CHECK-RV32C-NEXT: ret
2837 ;
2838 ; CHECK-RV64V-LABEL: test_nontemporal_P1_store_v2i64:
2839 ; CHECK-RV64V: # %bb.0:
2840 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
2841 ; CHECK-RV64V-NEXT: ntl.p1
2842 ; CHECK-RV64V-NEXT: vse64.v v8, (a0)
2843 ; CHECK-RV64V-NEXT: ret
2844 ;
2845 ; CHECK-RV32V-LABEL: test_nontemporal_P1_store_v2i64:
2846 ; CHECK-RV32V: # %bb.0:
2847 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
2848 ; CHECK-RV32V-NEXT: ntl.p1
2849 ; CHECK-RV32V-NEXT: vse64.v v8, (a0)
2850 ; CHECK-RV32V-NEXT: ret
2851 store <2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !1
2852 ret void
2853 }
2855 define i64 @test_nontemporal_PALL_load_i64(ptr %p) {
2856 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_i64:
2857 ; CHECK-RV64: # %bb.0:
2858 ; CHECK-RV64-NEXT: ntl.pall
2859 ; CHECK-RV64-NEXT: ld a0, 0(a0)
2860 ; CHECK-RV64-NEXT: ret
2861 ;
2862 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_i64:
2863 ; CHECK-RV32: # %bb.0:
2864 ; CHECK-RV32-NEXT: ntl.pall
2865 ; CHECK-RV32-NEXT: lw a2, 0(a0)
2866 ; CHECK-RV32-NEXT: ntl.pall
2867 ; CHECK-RV32-NEXT: lw a1, 4(a0)
2868 ; CHECK-RV32-NEXT: mv a0, a2
2869 ; CHECK-RV32-NEXT: ret
2870 ;
2871 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_i64:
2872 ; CHECK-RV64C: # %bb.0:
2873 ; CHECK-RV64C-NEXT: c.ntl.pall
2874 ; CHECK-RV64C-NEXT: ld a0, 0(a0)
2875 ; CHECK-RV64C-NEXT: ret
2876 ;
2877 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_i64:
2878 ; CHECK-RV32C: # %bb.0:
2879 ; CHECK-RV32C-NEXT: c.ntl.pall
2880 ; CHECK-RV32C-NEXT: lw a2, 0(a0)
2881 ; CHECK-RV32C-NEXT: c.ntl.pall
2882 ; CHECK-RV32C-NEXT: lw a1, 4(a0)
2883 ; CHECK-RV32C-NEXT: mv a0, a2
2884 ; CHECK-RV32C-NEXT: ret
2885 ;
2886 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_i64:
2887 ; CHECK-RV64V: # %bb.0:
2888 ; CHECK-RV64V-NEXT: ntl.pall
2889 ; CHECK-RV64V-NEXT: ld a0, 0(a0)
2890 ; CHECK-RV64V-NEXT: ret
2891 ;
2892 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_i64:
2893 ; CHECK-RV32V: # %bb.0:
2894 ; CHECK-RV32V-NEXT: ntl.pall
2895 ; CHECK-RV32V-NEXT: lw a2, 0(a0)
2896 ; CHECK-RV32V-NEXT: ntl.pall
2897 ; CHECK-RV32V-NEXT: lw a1, 4(a0)
2898 ; CHECK-RV32V-NEXT: mv a0, a2
2899 ; CHECK-RV32V-NEXT: ret
2900 %1 = load i64, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
2901 ret i64 %1
2902 }
2904 define i32 @test_nontemporal_PALL_load_i32(ptr %p) {
2905 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_i32:
2906 ; CHECK-RV64: # %bb.0:
2907 ; CHECK-RV64-NEXT: ntl.pall
2908 ; CHECK-RV64-NEXT: lw a0, 0(a0)
2909 ; CHECK-RV64-NEXT: ret
2910 ;
2911 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_i32:
2912 ; CHECK-RV32: # %bb.0:
2913 ; CHECK-RV32-NEXT: ntl.pall
2914 ; CHECK-RV32-NEXT: lw a0, 0(a0)
2915 ; CHECK-RV32-NEXT: ret
2916 ;
2917 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_i32:
2918 ; CHECK-RV64C: # %bb.0:
2919 ; CHECK-RV64C-NEXT: c.ntl.pall
2920 ; CHECK-RV64C-NEXT: lw a0, 0(a0)
2921 ; CHECK-RV64C-NEXT: ret
2922 ;
2923 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_i32:
2924 ; CHECK-RV32C: # %bb.0:
2925 ; CHECK-RV32C-NEXT: c.ntl.pall
2926 ; CHECK-RV32C-NEXT: lw a0, 0(a0)
2927 ; CHECK-RV32C-NEXT: ret
2928 ;
2929 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_i32:
2930 ; CHECK-RV64V: # %bb.0:
2931 ; CHECK-RV64V-NEXT: ntl.pall
2932 ; CHECK-RV64V-NEXT: lw a0, 0(a0)
2933 ; CHECK-RV64V-NEXT: ret
2934 ;
2935 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_i32:
2936 ; CHECK-RV32V: # %bb.0:
2937 ; CHECK-RV32V-NEXT: ntl.pall
2938 ; CHECK-RV32V-NEXT: lw a0, 0(a0)
2939 ; CHECK-RV32V-NEXT: ret
2940 %1 = load i32, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
2941 ret i32 %1
2942 }
2944 define i16 @test_nontemporal_PALL_load_i16(ptr %p) {
2945 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_i16:
2946 ; CHECK-RV64: # %bb.0:
2947 ; CHECK-RV64-NEXT: ntl.pall
2948 ; CHECK-RV64-NEXT: lh a0, 0(a0)
2949 ; CHECK-RV64-NEXT: ret
2950 ;
2951 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_i16:
2952 ; CHECK-RV32: # %bb.0:
2953 ; CHECK-RV32-NEXT: ntl.pall
2954 ; CHECK-RV32-NEXT: lh a0, 0(a0)
2955 ; CHECK-RV32-NEXT: ret
2956 ;
2957 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_i16:
2958 ; CHECK-RV64C: # %bb.0:
2959 ; CHECK-RV64C-NEXT: c.ntl.pall
2960 ; CHECK-RV64C-NEXT: lh a0, 0(a0)
2961 ; CHECK-RV64C-NEXT: ret
2962 ;
2963 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_i16:
2964 ; CHECK-RV32C: # %bb.0:
2965 ; CHECK-RV32C-NEXT: c.ntl.pall
2966 ; CHECK-RV32C-NEXT: lh a0, 0(a0)
2967 ; CHECK-RV32C-NEXT: ret
2968 ;
2969 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_i16:
2970 ; CHECK-RV64V: # %bb.0:
2971 ; CHECK-RV64V-NEXT: ntl.pall
2972 ; CHECK-RV64V-NEXT: lh a0, 0(a0)
2973 ; CHECK-RV64V-NEXT: ret
2974 ;
2975 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_i16:
2976 ; CHECK-RV32V: # %bb.0:
2977 ; CHECK-RV32V-NEXT: ntl.pall
2978 ; CHECK-RV32V-NEXT: lh a0, 0(a0)
2979 ; CHECK-RV32V-NEXT: ret
2980 %1 = load i16, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
2981 ret i16 %1
2982 }
2984 define i8 @test_nontemporal_PALL_load_i8(ptr %p) {
2985 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_i8:
2986 ; CHECK-RV64: # %bb.0:
2987 ; CHECK-RV64-NEXT: ntl.pall
2988 ; CHECK-RV64-NEXT: lbu a0, 0(a0)
2989 ; CHECK-RV64-NEXT: ret
2990 ;
2991 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_i8:
2992 ; CHECK-RV32: # %bb.0:
2993 ; CHECK-RV32-NEXT: ntl.pall
2994 ; CHECK-RV32-NEXT: lbu a0, 0(a0)
2995 ; CHECK-RV32-NEXT: ret
2996 ;
2997 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_i8:
2998 ; CHECK-RV64C: # %bb.0:
2999 ; CHECK-RV64C-NEXT: c.ntl.pall
3000 ; CHECK-RV64C-NEXT: lbu a0, 0(a0)
3001 ; CHECK-RV64C-NEXT: ret
3002 ;
3003 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_i8:
3004 ; CHECK-RV32C: # %bb.0:
3005 ; CHECK-RV32C-NEXT: c.ntl.pall
3006 ; CHECK-RV32C-NEXT: lbu a0, 0(a0)
3007 ; CHECK-RV32C-NEXT: ret
3008 ;
3009 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_i8:
3010 ; CHECK-RV64V: # %bb.0:
3011 ; CHECK-RV64V-NEXT: ntl.pall
3012 ; CHECK-RV64V-NEXT: lbu a0, 0(a0)
3013 ; CHECK-RV64V-NEXT: ret
3014 ;
3015 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_i8:
3016 ; CHECK-RV32V: # %bb.0:
3017 ; CHECK-RV32V-NEXT: ntl.pall
3018 ; CHECK-RV32V-NEXT: lbu a0, 0(a0)
3019 ; CHECK-RV32V-NEXT: ret
3020 %1 = load i8, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3021 ret i8 %1
3022 }
3024 define half @test_nontemporal_PALL_load_half(ptr %p) nounwind {
3025 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_half:
3026 ; CHECK-RV64: # %bb.0:
3027 ; CHECK-RV64-NEXT: ntl.pall
3028 ; CHECK-RV64-NEXT: flh fa5, 0(a0)
3029 ; CHECK-RV64-NEXT: ntl.pall
3030 ; CHECK-RV64-NEXT: flh fa4, 6(a0)
3031 ; CHECK-RV64-NEXT: fadd.h fa0, fa5, fa4
3032 ; CHECK-RV64-NEXT: ret
3033 ;
3034 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_half:
3035 ; CHECK-RV32: # %bb.0:
3036 ; CHECK-RV32-NEXT: ntl.pall
3037 ; CHECK-RV32-NEXT: flh fa5, 0(a0)
3038 ; CHECK-RV32-NEXT: ntl.pall
3039 ; CHECK-RV32-NEXT: flh fa4, 6(a0)
3040 ; CHECK-RV32-NEXT: fadd.h fa0, fa5, fa4
3041 ; CHECK-RV32-NEXT: ret
3042 ;
3043 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_half:
3044 ; CHECK-RV64C: # %bb.0:
3045 ; CHECK-RV64C-NEXT: c.ntl.pall
3046 ; CHECK-RV64C-NEXT: flh fa5, 0(a0)
3047 ; CHECK-RV64C-NEXT: c.ntl.pall
3048 ; CHECK-RV64C-NEXT: flh fa4, 6(a0)
3049 ; CHECK-RV64C-NEXT: fadd.h fa0, fa5, fa4
3050 ; CHECK-RV64C-NEXT: ret
3051 ;
3052 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_half:
3053 ; CHECK-RV32C: # %bb.0:
3054 ; CHECK-RV32C-NEXT: c.ntl.pall
3055 ; CHECK-RV32C-NEXT: flh fa5, 0(a0)
3056 ; CHECK-RV32C-NEXT: c.ntl.pall
3057 ; CHECK-RV32C-NEXT: flh fa4, 6(a0)
3058 ; CHECK-RV32C-NEXT: fadd.h fa0, fa5, fa4
3059 ; CHECK-RV32C-NEXT: ret
3060 ;
3061 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_half:
3062 ; CHECK-RV64V: # %bb.0:
3063 ; CHECK-RV64V-NEXT: ntl.pall
3064 ; CHECK-RV64V-NEXT: flh fa5, 0(a0)
3065 ; CHECK-RV64V-NEXT: ntl.pall
3066 ; CHECK-RV64V-NEXT: flh fa4, 6(a0)
3067 ; CHECK-RV64V-NEXT: fadd.h fa0, fa5, fa4
3068 ; CHECK-RV64V-NEXT: ret
3069 ;
3070 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_half:
3071 ; CHECK-RV32V: # %bb.0:
3072 ; CHECK-RV32V-NEXT: ntl.pall
3073 ; CHECK-RV32V-NEXT: flh fa5, 0(a0)
3074 ; CHECK-RV32V-NEXT: ntl.pall
3075 ; CHECK-RV32V-NEXT: flh fa4, 6(a0)
3076 ; CHECK-RV32V-NEXT: fadd.h fa0, fa5, fa4
3077 ; CHECK-RV32V-NEXT: ret
3078 %1 = load half, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3079 %2 = getelementptr half, ptr %p, i32 3
3080 %3 = load half, ptr %2, !nontemporal !0, !riscv-nontemporal-domain !2
3081 %4 = fadd half %1, %3
3082 ret half %4
3083 }
3085 define float @test_nontemporal_PALL_load_float(ptr %p) {
3086 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_float:
3087 ; CHECK-RV64: # %bb.0:
3088 ; CHECK-RV64-NEXT: ntl.pall
3089 ; CHECK-RV64-NEXT: flw fa0, 0(a0)
3090 ; CHECK-RV64-NEXT: ret
3091 ;
3092 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_float:
3093 ; CHECK-RV32: # %bb.0:
3094 ; CHECK-RV32-NEXT: ntl.pall
3095 ; CHECK-RV32-NEXT: flw fa0, 0(a0)
3096 ; CHECK-RV32-NEXT: ret
3097 ;
3098 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_float:
3099 ; CHECK-RV64C: # %bb.0:
3100 ; CHECK-RV64C-NEXT: c.ntl.pall
3101 ; CHECK-RV64C-NEXT: flw fa0, 0(a0)
3102 ; CHECK-RV64C-NEXT: ret
3103 ;
3104 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_float:
3105 ; CHECK-RV32C: # %bb.0:
3106 ; CHECK-RV32C-NEXT: c.ntl.pall
3107 ; CHECK-RV32C-NEXT: flw fa0, 0(a0)
3108 ; CHECK-RV32C-NEXT: ret
3109 ;
3110 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_float:
3111 ; CHECK-RV64V: # %bb.0:
3112 ; CHECK-RV64V-NEXT: ntl.pall
3113 ; CHECK-RV64V-NEXT: flw fa0, 0(a0)
3114 ; CHECK-RV64V-NEXT: ret
3115 ;
3116 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_float:
3117 ; CHECK-RV32V: # %bb.0:
3118 ; CHECK-RV32V-NEXT: ntl.pall
3119 ; CHECK-RV32V-NEXT: flw fa0, 0(a0)
3120 ; CHECK-RV32V-NEXT: ret
3121 %1 = load float, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3122 ret float %1
3123 }
3125 define double @test_nontemporal_PALL_load_double(ptr %p) {
3126 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_double:
3127 ; CHECK-RV64: # %bb.0:
3128 ; CHECK-RV64-NEXT: ntl.pall
3129 ; CHECK-RV64-NEXT: fld fa0, 0(a0)
3130 ; CHECK-RV64-NEXT: ret
3131 ;
3132 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_double:
3133 ; CHECK-RV32: # %bb.0:
3134 ; CHECK-RV32-NEXT: ntl.pall
3135 ; CHECK-RV32-NEXT: fld fa0, 0(a0)
3136 ; CHECK-RV32-NEXT: ret
3137 ;
3138 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_double:
3139 ; CHECK-RV64C: # %bb.0:
3140 ; CHECK-RV64C-NEXT: c.ntl.pall
3141 ; CHECK-RV64C-NEXT: fld fa0, 0(a0)
3142 ; CHECK-RV64C-NEXT: ret
3143 ;
3144 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_double:
3145 ; CHECK-RV32C: # %bb.0:
3146 ; CHECK-RV32C-NEXT: c.ntl.pall
3147 ; CHECK-RV32C-NEXT: fld fa0, 0(a0)
3148 ; CHECK-RV32C-NEXT: ret
3149 ;
3150 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_double:
3151 ; CHECK-RV64V: # %bb.0:
3152 ; CHECK-RV64V-NEXT: ntl.pall
3153 ; CHECK-RV64V-NEXT: fld fa0, 0(a0)
3154 ; CHECK-RV64V-NEXT: ret
3155 ;
3156 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_double:
3157 ; CHECK-RV32V: # %bb.0:
3158 ; CHECK-RV32V-NEXT: ntl.pall
3159 ; CHECK-RV32V-NEXT: fld fa0, 0(a0)
3160 ; CHECK-RV32V-NEXT: ret
3161 %1 = load double, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3162 ret double %1
3163 }
3165 define <16 x i8> @test_nontemporal_PALL_load_v16i8(ptr %p) {
3166 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_v16i8:
3167 ; CHECK-RV64: # %bb.0:
3168 ; CHECK-RV64-NEXT: ntl.pall
3169 ; CHECK-RV64-NEXT: ld a2, 8(a1)
3170 ; CHECK-RV64-NEXT: ntl.pall
3171 ; CHECK-RV64-NEXT: ld a1, 0(a1)
3172 ; CHECK-RV64-NEXT: sd a2, 8(a0)
3173 ; CHECK-RV64-NEXT: sd a1, 0(a0)
3174 ; CHECK-RV64-NEXT: ret
3175 ;
3176 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_v16i8:
3177 ; CHECK-RV32: # %bb.0:
3178 ; CHECK-RV32-NEXT: ntl.pall
3179 ; CHECK-RV32-NEXT: lw a2, 12(a1)
3180 ; CHECK-RV32-NEXT: ntl.pall
3181 ; CHECK-RV32-NEXT: lw a3, 8(a1)
3182 ; CHECK-RV32-NEXT: ntl.pall
3183 ; CHECK-RV32-NEXT: lw a4, 4(a1)
3184 ; CHECK-RV32-NEXT: ntl.pall
3185 ; CHECK-RV32-NEXT: lw a1, 0(a1)
3186 ; CHECK-RV32-NEXT: sw a2, 12(a0)
3187 ; CHECK-RV32-NEXT: sw a3, 8(a0)
3188 ; CHECK-RV32-NEXT: sw a4, 4(a0)
3189 ; CHECK-RV32-NEXT: sw a1, 0(a0)
3190 ; CHECK-RV32-NEXT: ret
3191 ;
3192 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_v16i8:
3193 ; CHECK-RV64C: # %bb.0:
3194 ; CHECK-RV64C-NEXT: c.ntl.pall
3195 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
3196 ; CHECK-RV64C-NEXT: c.ntl.pall
3197 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
3198 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
3199 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
3200 ; CHECK-RV64C-NEXT: ret
3201 ;
3202 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_v16i8:
3203 ; CHECK-RV32C: # %bb.0:
3204 ; CHECK-RV32C-NEXT: c.ntl.pall
3205 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
3206 ; CHECK-RV32C-NEXT: c.ntl.pall
3207 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
3208 ; CHECK-RV32C-NEXT: c.ntl.pall
3209 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
3210 ; CHECK-RV32C-NEXT: c.ntl.pall
3211 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
3212 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
3213 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
3214 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
3215 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
3216 ; CHECK-RV32C-NEXT: ret
3217 ;
3218 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_v16i8:
3219 ; CHECK-RV64V: # %bb.0:
3220 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
3221 ; CHECK-RV64V-NEXT: ntl.pall
3222 ; CHECK-RV64V-NEXT: vle8.v v8, (a0)
3223 ; CHECK-RV64V-NEXT: ret
3224 ;
3225 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_v16i8:
3226 ; CHECK-RV32V: # %bb.0:
3227 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
3228 ; CHECK-RV32V-NEXT: ntl.pall
3229 ; CHECK-RV32V-NEXT: vle8.v v8, (a0)
3230 ; CHECK-RV32V-NEXT: ret
3231 %1 = load <16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3232 ret <16 x i8> %1
3233 }
3235 define <8 x i16> @test_nontemporal_PALL_load_v8i16(ptr %p) {
3236 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_v8i16:
3237 ; CHECK-RV64: # %bb.0:
3238 ; CHECK-RV64-NEXT: ntl.pall
3239 ; CHECK-RV64-NEXT: ld a2, 8(a1)
3240 ; CHECK-RV64-NEXT: ntl.pall
3241 ; CHECK-RV64-NEXT: ld a1, 0(a1)
3242 ; CHECK-RV64-NEXT: sd a2, 8(a0)
3243 ; CHECK-RV64-NEXT: sd a1, 0(a0)
3244 ; CHECK-RV64-NEXT: ret
3245 ;
3246 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_v8i16:
3247 ; CHECK-RV32: # %bb.0:
3248 ; CHECK-RV32-NEXT: ntl.pall
3249 ; CHECK-RV32-NEXT: lw a2, 12(a1)
3250 ; CHECK-RV32-NEXT: ntl.pall
3251 ; CHECK-RV32-NEXT: lw a3, 8(a1)
3252 ; CHECK-RV32-NEXT: ntl.pall
3253 ; CHECK-RV32-NEXT: lw a4, 4(a1)
3254 ; CHECK-RV32-NEXT: ntl.pall
3255 ; CHECK-RV32-NEXT: lw a1, 0(a1)
3256 ; CHECK-RV32-NEXT: sw a2, 12(a0)
3257 ; CHECK-RV32-NEXT: sw a3, 8(a0)
3258 ; CHECK-RV32-NEXT: sw a4, 4(a0)
3259 ; CHECK-RV32-NEXT: sw a1, 0(a0)
3260 ; CHECK-RV32-NEXT: ret
3261 ;
3262 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_v8i16:
3263 ; CHECK-RV64C: # %bb.0:
3264 ; CHECK-RV64C-NEXT: c.ntl.pall
3265 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
3266 ; CHECK-RV64C-NEXT: c.ntl.pall
3267 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
3268 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
3269 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
3270 ; CHECK-RV64C-NEXT: ret
3271 ;
3272 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_v8i16:
3273 ; CHECK-RV32C: # %bb.0:
3274 ; CHECK-RV32C-NEXT: c.ntl.pall
3275 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
3276 ; CHECK-RV32C-NEXT: c.ntl.pall
3277 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
3278 ; CHECK-RV32C-NEXT: c.ntl.pall
3279 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
3280 ; CHECK-RV32C-NEXT: c.ntl.pall
3281 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
3282 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
3283 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
3284 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
3285 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
3286 ; CHECK-RV32C-NEXT: ret
3287 ;
3288 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_v8i16:
3289 ; CHECK-RV64V: # %bb.0:
3290 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
3291 ; CHECK-RV64V-NEXT: ntl.pall
3292 ; CHECK-RV64V-NEXT: vle16.v v8, (a0)
3293 ; CHECK-RV64V-NEXT: ret
3294 ;
3295 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_v8i16:
3296 ; CHECK-RV32V: # %bb.0:
3297 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
3298 ; CHECK-RV32V-NEXT: ntl.pall
3299 ; CHECK-RV32V-NEXT: vle16.v v8, (a0)
3300 ; CHECK-RV32V-NEXT: ret
3301 %1 = load <8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3302 ret <8 x i16> %1
3303 }
3305 define <4 x i32> @test_nontemporal_PALL_load_v4i32(ptr %p) {
3306 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_v4i32:
3307 ; CHECK-RV64: # %bb.0:
3308 ; CHECK-RV64-NEXT: ntl.pall
3309 ; CHECK-RV64-NEXT: ld a2, 8(a1)
3310 ; CHECK-RV64-NEXT: ntl.pall
3311 ; CHECK-RV64-NEXT: ld a1, 0(a1)
3312 ; CHECK-RV64-NEXT: sd a2, 8(a0)
3313 ; CHECK-RV64-NEXT: sd a1, 0(a0)
3314 ; CHECK-RV64-NEXT: ret
3315 ;
3316 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_v4i32:
3317 ; CHECK-RV32: # %bb.0:
3318 ; CHECK-RV32-NEXT: ntl.pall
3319 ; CHECK-RV32-NEXT: lw a2, 12(a1)
3320 ; CHECK-RV32-NEXT: ntl.pall
3321 ; CHECK-RV32-NEXT: lw a3, 8(a1)
3322 ; CHECK-RV32-NEXT: ntl.pall
3323 ; CHECK-RV32-NEXT: lw a4, 4(a1)
3324 ; CHECK-RV32-NEXT: ntl.pall
3325 ; CHECK-RV32-NEXT: lw a1, 0(a1)
3326 ; CHECK-RV32-NEXT: sw a2, 12(a0)
3327 ; CHECK-RV32-NEXT: sw a3, 8(a0)
3328 ; CHECK-RV32-NEXT: sw a4, 4(a0)
3329 ; CHECK-RV32-NEXT: sw a1, 0(a0)
3330 ; CHECK-RV32-NEXT: ret
3331 ;
3332 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_v4i32:
3333 ; CHECK-RV64C: # %bb.0:
3334 ; CHECK-RV64C-NEXT: c.ntl.pall
3335 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
3336 ; CHECK-RV64C-NEXT: c.ntl.pall
3337 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
3338 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
3339 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
3340 ; CHECK-RV64C-NEXT: ret
3341 ;
3342 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_v4i32:
3343 ; CHECK-RV32C: # %bb.0:
3344 ; CHECK-RV32C-NEXT: c.ntl.pall
3345 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
3346 ; CHECK-RV32C-NEXT: c.ntl.pall
3347 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
3348 ; CHECK-RV32C-NEXT: c.ntl.pall
3349 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
3350 ; CHECK-RV32C-NEXT: c.ntl.pall
3351 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
3352 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
3353 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
3354 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
3355 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
3356 ; CHECK-RV32C-NEXT: ret
3357 ;
3358 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_v4i32:
3359 ; CHECK-RV64V: # %bb.0:
3360 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
3361 ; CHECK-RV64V-NEXT: ntl.pall
3362 ; CHECK-RV64V-NEXT: vle32.v v8, (a0)
3363 ; CHECK-RV64V-NEXT: ret
3364 ;
3365 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_v4i32:
3366 ; CHECK-RV32V: # %bb.0:
3367 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
3368 ; CHECK-RV32V-NEXT: ntl.pall
3369 ; CHECK-RV32V-NEXT: vle32.v v8, (a0)
3370 ; CHECK-RV32V-NEXT: ret
3371 %1 = load <4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3372 ret <4 x i32> %1
3373 }
3375 define <2 x i64> @test_nontemporal_PALL_load_v2i64(ptr %p) {
3376 ; CHECK-RV64-LABEL: test_nontemporal_PALL_load_v2i64:
3377 ; CHECK-RV64: # %bb.0:
3378 ; CHECK-RV64-NEXT: ntl.pall
3379 ; CHECK-RV64-NEXT: ld a2, 0(a0)
3380 ; CHECK-RV64-NEXT: ntl.pall
3381 ; CHECK-RV64-NEXT: ld a1, 8(a0)
3382 ; CHECK-RV64-NEXT: mv a0, a2
3383 ; CHECK-RV64-NEXT: ret
3384 ;
3385 ; CHECK-RV32-LABEL: test_nontemporal_PALL_load_v2i64:
3386 ; CHECK-RV32: # %bb.0:
3387 ; CHECK-RV32-NEXT: ntl.pall
3388 ; CHECK-RV32-NEXT: lw a2, 12(a1)
3389 ; CHECK-RV32-NEXT: ntl.pall
3390 ; CHECK-RV32-NEXT: lw a3, 8(a1)
3391 ; CHECK-RV32-NEXT: ntl.pall
3392 ; CHECK-RV32-NEXT: lw a4, 4(a1)
3393 ; CHECK-RV32-NEXT: ntl.pall
3394 ; CHECK-RV32-NEXT: lw a1, 0(a1)
3395 ; CHECK-RV32-NEXT: sw a2, 12(a0)
3396 ; CHECK-RV32-NEXT: sw a3, 8(a0)
3397 ; CHECK-RV32-NEXT: sw a4, 4(a0)
3398 ; CHECK-RV32-NEXT: sw a1, 0(a0)
3399 ; CHECK-RV32-NEXT: ret
3400 ;
3401 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_load_v2i64:
3402 ; CHECK-RV64C: # %bb.0:
3403 ; CHECK-RV64C-NEXT: c.ntl.pall
3404 ; CHECK-RV64C-NEXT: ld a2, 0(a0)
3405 ; CHECK-RV64C-NEXT: c.ntl.pall
3406 ; CHECK-RV64C-NEXT: ld a1, 8(a0)
3407 ; CHECK-RV64C-NEXT: mv a0, a2
3408 ; CHECK-RV64C-NEXT: ret
3409 ;
3410 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_load_v2i64:
3411 ; CHECK-RV32C: # %bb.0:
3412 ; CHECK-RV32C-NEXT: c.ntl.pall
3413 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
3414 ; CHECK-RV32C-NEXT: c.ntl.pall
3415 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
3416 ; CHECK-RV32C-NEXT: c.ntl.pall
3417 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
3418 ; CHECK-RV32C-NEXT: c.ntl.pall
3419 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
3420 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
3421 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
3422 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
3423 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
3424 ; CHECK-RV32C-NEXT: ret
3425 ;
3426 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_load_v2i64:
3427 ; CHECK-RV64V: # %bb.0:
3428 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
3429 ; CHECK-RV64V-NEXT: ntl.pall
3430 ; CHECK-RV64V-NEXT: vle64.v v8, (a0)
3431 ; CHECK-RV64V-NEXT: ret
3432 ;
3433 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_load_v2i64:
3434 ; CHECK-RV32V: # %bb.0:
3435 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
3436 ; CHECK-RV32V-NEXT: ntl.pall
3437 ; CHECK-RV32V-NEXT: vle64.v v8, (a0)
3438 ; CHECK-RV32V-NEXT: ret
3439 %1 = load <2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3440 ret <2 x i64> %1
3441 }
3443 define void @test_nontemporal_PALL_store_i64(ptr %p, i64 %v) {
3444 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_i64:
3445 ; CHECK-RV64: # %bb.0:
3446 ; CHECK-RV64-NEXT: ntl.pall
3447 ; CHECK-RV64-NEXT: sd a1, 0(a0)
3448 ; CHECK-RV64-NEXT: ret
3449 ;
3450 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_i64:
3451 ; CHECK-RV32: # %bb.0:
3452 ; CHECK-RV32-NEXT: ntl.pall
3453 ; CHECK-RV32-NEXT: sw a2, 4(a0)
3454 ; CHECK-RV32-NEXT: ntl.pall
3455 ; CHECK-RV32-NEXT: sw a1, 0(a0)
3456 ; CHECK-RV32-NEXT: ret
3457 ;
3458 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_i64:
3459 ; CHECK-RV64C: # %bb.0:
3460 ; CHECK-RV64C-NEXT: c.ntl.pall
3461 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
3462 ; CHECK-RV64C-NEXT: ret
3463 ;
3464 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_i64:
3465 ; CHECK-RV32C: # %bb.0:
3466 ; CHECK-RV32C-NEXT: c.ntl.pall
3467 ; CHECK-RV32C-NEXT: sw a2, 4(a0)
3468 ; CHECK-RV32C-NEXT: c.ntl.pall
3469 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
3470 ; CHECK-RV32C-NEXT: ret
3471 ;
3472 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_i64:
3473 ; CHECK-RV64V: # %bb.0:
3474 ; CHECK-RV64V-NEXT: ntl.pall
3475 ; CHECK-RV64V-NEXT: sd a1, 0(a0)
3476 ; CHECK-RV64V-NEXT: ret
3477 ;
3478 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_i64:
3479 ; CHECK-RV32V: # %bb.0:
3480 ; CHECK-RV32V-NEXT: ntl.pall
3481 ; CHECK-RV32V-NEXT: sw a2, 4(a0)
3482 ; CHECK-RV32V-NEXT: ntl.pall
3483 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
3484 ; CHECK-RV32V-NEXT: ret
3485 store i64 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3486 ret void
3487 }
3489 define void @test_nontemporal_PALL_store_i32(ptr %p, i32 %v) {
3490 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_i32:
3491 ; CHECK-RV64: # %bb.0:
3492 ; CHECK-RV64-NEXT: ntl.pall
3493 ; CHECK-RV64-NEXT: sw a1, 0(a0)
3494 ; CHECK-RV64-NEXT: ret
3495 ;
3496 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_i32:
3497 ; CHECK-RV32: # %bb.0:
3498 ; CHECK-RV32-NEXT: ntl.pall
3499 ; CHECK-RV32-NEXT: sw a1, 0(a0)
3500 ; CHECK-RV32-NEXT: ret
3501 ;
3502 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_i32:
3503 ; CHECK-RV64C: # %bb.0:
3504 ; CHECK-RV64C-NEXT: c.ntl.pall
3505 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
3506 ; CHECK-RV64C-NEXT: ret
3507 ;
3508 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_i32:
3509 ; CHECK-RV32C: # %bb.0:
3510 ; CHECK-RV32C-NEXT: c.ntl.pall
3511 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
3512 ; CHECK-RV32C-NEXT: ret
3513 ;
3514 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_i32:
3515 ; CHECK-RV64V: # %bb.0:
3516 ; CHECK-RV64V-NEXT: ntl.pall
3517 ; CHECK-RV64V-NEXT: sw a1, 0(a0)
3518 ; CHECK-RV64V-NEXT: ret
3519 ;
3520 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_i32:
3521 ; CHECK-RV32V: # %bb.0:
3522 ; CHECK-RV32V-NEXT: ntl.pall
3523 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
3524 ; CHECK-RV32V-NEXT: ret
3525 store i32 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3526 ret void
3527 }
3529 define void @test_nontemporal_PALL_store_i16(ptr %p, i16 %v) {
3530 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_i16:
3531 ; CHECK-RV64: # %bb.0:
3532 ; CHECK-RV64-NEXT: ntl.pall
3533 ; CHECK-RV64-NEXT: sh a1, 0(a0)
3534 ; CHECK-RV64-NEXT: ret
3535 ;
3536 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_i16:
3537 ; CHECK-RV32: # %bb.0:
3538 ; CHECK-RV32-NEXT: ntl.pall
3539 ; CHECK-RV32-NEXT: sh a1, 0(a0)
3540 ; CHECK-RV32-NEXT: ret
3541 ;
3542 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_i16:
3543 ; CHECK-RV64C: # %bb.0:
3544 ; CHECK-RV64C-NEXT: c.ntl.pall
3545 ; CHECK-RV64C-NEXT: sh a1, 0(a0)
3546 ; CHECK-RV64C-NEXT: ret
3547 ;
3548 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_i16:
3549 ; CHECK-RV32C: # %bb.0:
3550 ; CHECK-RV32C-NEXT: c.ntl.pall
3551 ; CHECK-RV32C-NEXT: sh a1, 0(a0)
3552 ; CHECK-RV32C-NEXT: ret
3553 ;
3554 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_i16:
3555 ; CHECK-RV64V: # %bb.0:
3556 ; CHECK-RV64V-NEXT: ntl.pall
3557 ; CHECK-RV64V-NEXT: sh a1, 0(a0)
3558 ; CHECK-RV64V-NEXT: ret
3559 ;
3560 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_i16:
3561 ; CHECK-RV32V: # %bb.0:
3562 ; CHECK-RV32V-NEXT: ntl.pall
3563 ; CHECK-RV32V-NEXT: sh a1, 0(a0)
3564 ; CHECK-RV32V-NEXT: ret
3565 store i16 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3566 ret void
3567 }
3569 define void @test_nontemporal_PALL_store_i8(ptr %p, i8 %v) {
3570 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_i8:
3571 ; CHECK-RV64: # %bb.0:
3572 ; CHECK-RV64-NEXT: ntl.pall
3573 ; CHECK-RV64-NEXT: sb a1, 0(a0)
3574 ; CHECK-RV64-NEXT: ret
3575 ;
3576 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_i8:
3577 ; CHECK-RV32: # %bb.0:
3578 ; CHECK-RV32-NEXT: ntl.pall
3579 ; CHECK-RV32-NEXT: sb a1, 0(a0)
3580 ; CHECK-RV32-NEXT: ret
3581 ;
3582 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_i8:
3583 ; CHECK-RV64C: # %bb.0:
3584 ; CHECK-RV64C-NEXT: c.ntl.pall
3585 ; CHECK-RV64C-NEXT: sb a1, 0(a0)
3586 ; CHECK-RV64C-NEXT: ret
3587 ;
3588 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_i8:
3589 ; CHECK-RV32C: # %bb.0:
3590 ; CHECK-RV32C-NEXT: c.ntl.pall
3591 ; CHECK-RV32C-NEXT: sb a1, 0(a0)
3592 ; CHECK-RV32C-NEXT: ret
3593 ;
3594 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_i8:
3595 ; CHECK-RV64V: # %bb.0:
3596 ; CHECK-RV64V-NEXT: ntl.pall
3597 ; CHECK-RV64V-NEXT: sb a1, 0(a0)
3598 ; CHECK-RV64V-NEXT: ret
3599 ;
3600 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_i8:
3601 ; CHECK-RV32V: # %bb.0:
3602 ; CHECK-RV32V-NEXT: ntl.pall
3603 ; CHECK-RV32V-NEXT: sb a1, 0(a0)
3604 ; CHECK-RV32V-NEXT: ret
3605 store i8 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3606 ret void
3607 }
3609 define void @test_nontemporal_PALL_store_half(ptr %p, half %v) {
3610 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_half:
3611 ; CHECK-RV64: # %bb.0:
3612 ; CHECK-RV64-NEXT: ntl.pall
3613 ; CHECK-RV64-NEXT: fsh fa0, 0(a0)
3614 ; CHECK-RV64-NEXT: ret
3615 ;
3616 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_half:
3617 ; CHECK-RV32: # %bb.0:
3618 ; CHECK-RV32-NEXT: ntl.pall
3619 ; CHECK-RV32-NEXT: fsh fa0, 0(a0)
3620 ; CHECK-RV32-NEXT: ret
3621 ;
3622 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_half:
3623 ; CHECK-RV64C: # %bb.0:
3624 ; CHECK-RV64C-NEXT: c.ntl.pall
3625 ; CHECK-RV64C-NEXT: fsh fa0, 0(a0)
3626 ; CHECK-RV64C-NEXT: ret
3627 ;
3628 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_half:
3629 ; CHECK-RV32C: # %bb.0:
3630 ; CHECK-RV32C-NEXT: c.ntl.pall
3631 ; CHECK-RV32C-NEXT: fsh fa0, 0(a0)
3632 ; CHECK-RV32C-NEXT: ret
3633 ;
3634 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_half:
3635 ; CHECK-RV64V: # %bb.0:
3636 ; CHECK-RV64V-NEXT: ntl.pall
3637 ; CHECK-RV64V-NEXT: fsh fa0, 0(a0)
3638 ; CHECK-RV64V-NEXT: ret
3639 ;
3640 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_half:
3641 ; CHECK-RV32V: # %bb.0:
3642 ; CHECK-RV32V-NEXT: ntl.pall
3643 ; CHECK-RV32V-NEXT: fsh fa0, 0(a0)
3644 ; CHECK-RV32V-NEXT: ret
3645 store half %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3646 ret void
3647 }
3649 define void @test_nontemporal_PALL_store_float(ptr %p, float %v) {
3650 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_float:
3651 ; CHECK-RV64: # %bb.0:
3652 ; CHECK-RV64-NEXT: ntl.pall
3653 ; CHECK-RV64-NEXT: fsw fa0, 0(a0)
3654 ; CHECK-RV64-NEXT: ret
3655 ;
3656 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_float:
3657 ; CHECK-RV32: # %bb.0:
3658 ; CHECK-RV32-NEXT: ntl.pall
3659 ; CHECK-RV32-NEXT: fsw fa0, 0(a0)
3660 ; CHECK-RV32-NEXT: ret
3661 ;
3662 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_float:
3663 ; CHECK-RV64C: # %bb.0:
3664 ; CHECK-RV64C-NEXT: c.ntl.pall
3665 ; CHECK-RV64C-NEXT: fsw fa0, 0(a0)
3666 ; CHECK-RV64C-NEXT: ret
3667 ;
3668 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_float:
3669 ; CHECK-RV32C: # %bb.0:
3670 ; CHECK-RV32C-NEXT: c.ntl.pall
3671 ; CHECK-RV32C-NEXT: fsw fa0, 0(a0)
3672 ; CHECK-RV32C-NEXT: ret
3673 ;
3674 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_float:
3675 ; CHECK-RV64V: # %bb.0:
3676 ; CHECK-RV64V-NEXT: ntl.pall
3677 ; CHECK-RV64V-NEXT: fsw fa0, 0(a0)
3678 ; CHECK-RV64V-NEXT: ret
3679 ;
3680 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_float:
3681 ; CHECK-RV32V: # %bb.0:
3682 ; CHECK-RV32V-NEXT: ntl.pall
3683 ; CHECK-RV32V-NEXT: fsw fa0, 0(a0)
3684 ; CHECK-RV32V-NEXT: ret
3685 store float %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3686 ret void
3687 }
3689 define void @test_nontemporal_PALL_store_double(ptr %p, double %v) {
3690 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_double:
3691 ; CHECK-RV64: # %bb.0:
3692 ; CHECK-RV64-NEXT: ntl.pall
3693 ; CHECK-RV64-NEXT: fsd fa0, 0(a0)
3694 ; CHECK-RV64-NEXT: ret
3695 ;
3696 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_double:
3697 ; CHECK-RV32: # %bb.0:
3698 ; CHECK-RV32-NEXT: ntl.pall
3699 ; CHECK-RV32-NEXT: fsd fa0, 0(a0)
3700 ; CHECK-RV32-NEXT: ret
3701 ;
3702 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_double:
3703 ; CHECK-RV64C: # %bb.0:
3704 ; CHECK-RV64C-NEXT: c.ntl.pall
3705 ; CHECK-RV64C-NEXT: fsd fa0, 0(a0)
3706 ; CHECK-RV64C-NEXT: ret
3707 ;
3708 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_double:
3709 ; CHECK-RV32C: # %bb.0:
3710 ; CHECK-RV32C-NEXT: c.ntl.pall
3711 ; CHECK-RV32C-NEXT: fsd fa0, 0(a0)
3712 ; CHECK-RV32C-NEXT: ret
3713 ;
3714 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_double:
3715 ; CHECK-RV64V: # %bb.0:
3716 ; CHECK-RV64V-NEXT: ntl.pall
3717 ; CHECK-RV64V-NEXT: fsd fa0, 0(a0)
3718 ; CHECK-RV64V-NEXT: ret
3719 ;
3720 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_double:
3721 ; CHECK-RV32V: # %bb.0:
3722 ; CHECK-RV32V-NEXT: ntl.pall
3723 ; CHECK-RV32V-NEXT: fsd fa0, 0(a0)
3724 ; CHECK-RV32V-NEXT: ret
3725 store double %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3726 ret void
3727 }
3729 define void @test_nontemporal_PALL_store_v16i8(ptr %p, <16 x i8> %v) {
3730 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_v16i8:
3731 ; CHECK-RV64: # %bb.0:
3732 ; CHECK-RV64-NEXT: addi sp, sp, -16
3733 ; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
3734 ; CHECK-RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
3735 ; CHECK-RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
3736 ; CHECK-RV64-NEXT: .cfi_offset s0, -8
3737 ; CHECK-RV64-NEXT: .cfi_offset s1, -16
3738 ; CHECK-RV64-NEXT: lbu a2, 0(a1)
3739 ; CHECK-RV64-NEXT: lbu a3, 8(a1)
3740 ; CHECK-RV64-NEXT: lbu a4, 16(a1)
3741 ; CHECK-RV64-NEXT: lbu a5, 24(a1)
3742 ; CHECK-RV64-NEXT: lbu a6, 32(a1)
3743 ; CHECK-RV64-NEXT: lbu a7, 40(a1)
3744 ; CHECK-RV64-NEXT: lbu t0, 48(a1)
3745 ; CHECK-RV64-NEXT: lbu t1, 56(a1)
3746 ; CHECK-RV64-NEXT: lbu t2, 64(a1)
3747 ; CHECK-RV64-NEXT: lbu t3, 72(a1)
3748 ; CHECK-RV64-NEXT: lbu t4, 80(a1)
3749 ; CHECK-RV64-NEXT: lbu t5, 88(a1)
3750 ; CHECK-RV64-NEXT: lbu t6, 120(a1)
3751 ; CHECK-RV64-NEXT: lbu s0, 112(a1)
3752 ; CHECK-RV64-NEXT: lbu s1, 104(a1)
3753 ; CHECK-RV64-NEXT: lbu a1, 96(a1)
3754 ; CHECK-RV64-NEXT: ntl.pall
3755 ; CHECK-RV64-NEXT: sb t6, 15(a0)
3756 ; CHECK-RV64-NEXT: ntl.pall
3757 ; CHECK-RV64-NEXT: sb s0, 14(a0)
3758 ; CHECK-RV64-NEXT: ntl.pall
3759 ; CHECK-RV64-NEXT: sb s1, 13(a0)
3760 ; CHECK-RV64-NEXT: ntl.pall
3761 ; CHECK-RV64-NEXT: sb a1, 12(a0)
3762 ; CHECK-RV64-NEXT: ntl.pall
3763 ; CHECK-RV64-NEXT: sb t5, 11(a0)
3764 ; CHECK-RV64-NEXT: ntl.pall
3765 ; CHECK-RV64-NEXT: sb t4, 10(a0)
3766 ; CHECK-RV64-NEXT: ntl.pall
3767 ; CHECK-RV64-NEXT: sb t3, 9(a0)
3768 ; CHECK-RV64-NEXT: ntl.pall
3769 ; CHECK-RV64-NEXT: sb t2, 8(a0)
3770 ; CHECK-RV64-NEXT: ntl.pall
3771 ; CHECK-RV64-NEXT: sb t1, 7(a0)
3772 ; CHECK-RV64-NEXT: ntl.pall
3773 ; CHECK-RV64-NEXT: sb t0, 6(a0)
3774 ; CHECK-RV64-NEXT: ntl.pall
3775 ; CHECK-RV64-NEXT: sb a7, 5(a0)
3776 ; CHECK-RV64-NEXT: ntl.pall
3777 ; CHECK-RV64-NEXT: sb a6, 4(a0)
3778 ; CHECK-RV64-NEXT: ntl.pall
3779 ; CHECK-RV64-NEXT: sb a5, 3(a0)
3780 ; CHECK-RV64-NEXT: ntl.pall
3781 ; CHECK-RV64-NEXT: sb a4, 2(a0)
3782 ; CHECK-RV64-NEXT: ntl.pall
3783 ; CHECK-RV64-NEXT: sb a3, 1(a0)
3784 ; CHECK-RV64-NEXT: ntl.pall
3785 ; CHECK-RV64-NEXT: sb a2, 0(a0)
3786 ; CHECK-RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
3787 ; CHECK-RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
3788 ; CHECK-RV64-NEXT: addi sp, sp, 16
3789 ; CHECK-RV64-NEXT: ret
3790 ;
3791 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_v16i8:
3792 ; CHECK-RV32: # %bb.0:
3793 ; CHECK-RV32-NEXT: addi sp, sp, -16
3794 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
3795 ; CHECK-RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3796 ; CHECK-RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
3797 ; CHECK-RV32-NEXT: .cfi_offset s0, -4
3798 ; CHECK-RV32-NEXT: .cfi_offset s1, -8
3799 ; CHECK-RV32-NEXT: lbu a2, 0(a1)
3800 ; CHECK-RV32-NEXT: lbu a3, 4(a1)
3801 ; CHECK-RV32-NEXT: lbu a4, 8(a1)
3802 ; CHECK-RV32-NEXT: lbu a5, 12(a1)
3803 ; CHECK-RV32-NEXT: lbu a6, 16(a1)
3804 ; CHECK-RV32-NEXT: lbu a7, 20(a1)
3805 ; CHECK-RV32-NEXT: lbu t0, 24(a1)
3806 ; CHECK-RV32-NEXT: lbu t1, 28(a1)
3807 ; CHECK-RV32-NEXT: lbu t2, 32(a1)
3808 ; CHECK-RV32-NEXT: lbu t3, 36(a1)
3809 ; CHECK-RV32-NEXT: lbu t4, 40(a1)
3810 ; CHECK-RV32-NEXT: lbu t5, 44(a1)
3811 ; CHECK-RV32-NEXT: lbu t6, 60(a1)
3812 ; CHECK-RV32-NEXT: lbu s0, 56(a1)
3813 ; CHECK-RV32-NEXT: lbu s1, 52(a1)
3814 ; CHECK-RV32-NEXT: lbu a1, 48(a1)
3815 ; CHECK-RV32-NEXT: ntl.pall
3816 ; CHECK-RV32-NEXT: sb t6, 15(a0)
3817 ; CHECK-RV32-NEXT: ntl.pall
3818 ; CHECK-RV32-NEXT: sb s0, 14(a0)
3819 ; CHECK-RV32-NEXT: ntl.pall
3820 ; CHECK-RV32-NEXT: sb s1, 13(a0)
3821 ; CHECK-RV32-NEXT: ntl.pall
3822 ; CHECK-RV32-NEXT: sb a1, 12(a0)
3823 ; CHECK-RV32-NEXT: ntl.pall
3824 ; CHECK-RV32-NEXT: sb t5, 11(a0)
3825 ; CHECK-RV32-NEXT: ntl.pall
3826 ; CHECK-RV32-NEXT: sb t4, 10(a0)
3827 ; CHECK-RV32-NEXT: ntl.pall
3828 ; CHECK-RV32-NEXT: sb t3, 9(a0)
3829 ; CHECK-RV32-NEXT: ntl.pall
3830 ; CHECK-RV32-NEXT: sb t2, 8(a0)
3831 ; CHECK-RV32-NEXT: ntl.pall
3832 ; CHECK-RV32-NEXT: sb t1, 7(a0)
3833 ; CHECK-RV32-NEXT: ntl.pall
3834 ; CHECK-RV32-NEXT: sb t0, 6(a0)
3835 ; CHECK-RV32-NEXT: ntl.pall
3836 ; CHECK-RV32-NEXT: sb a7, 5(a0)
3837 ; CHECK-RV32-NEXT: ntl.pall
3838 ; CHECK-RV32-NEXT: sb a6, 4(a0)
3839 ; CHECK-RV32-NEXT: ntl.pall
3840 ; CHECK-RV32-NEXT: sb a5, 3(a0)
3841 ; CHECK-RV32-NEXT: ntl.pall
3842 ; CHECK-RV32-NEXT: sb a4, 2(a0)
3843 ; CHECK-RV32-NEXT: ntl.pall
3844 ; CHECK-RV32-NEXT: sb a3, 1(a0)
3845 ; CHECK-RV32-NEXT: ntl.pall
3846 ; CHECK-RV32-NEXT: sb a2, 0(a0)
3847 ; CHECK-RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3848 ; CHECK-RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
3849 ; CHECK-RV32-NEXT: addi sp, sp, 16
3850 ; CHECK-RV32-NEXT: ret
3851 ;
3852 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_v16i8:
3853 ; CHECK-RV64C: # %bb.0:
3854 ; CHECK-RV64C-NEXT: addi sp, sp, -16
3855 ; CHECK-RV64C-NEXT: .cfi_def_cfa_offset 16
3856 ; CHECK-RV64C-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
3857 ; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
3858 ; CHECK-RV64C-NEXT: .cfi_offset s0, -8
3859 ; CHECK-RV64C-NEXT: .cfi_offset s1, -16
3860 ; CHECK-RV64C-NEXT: lbu a6, 0(a1)
3861 ; CHECK-RV64C-NEXT: lbu a7, 8(a1)
3862 ; CHECK-RV64C-NEXT: lbu t0, 16(a1)
3863 ; CHECK-RV64C-NEXT: lbu t1, 24(a1)
3864 ; CHECK-RV64C-NEXT: lbu t2, 32(a1)
3865 ; CHECK-RV64C-NEXT: lbu t3, 40(a1)
3866 ; CHECK-RV64C-NEXT: lbu t4, 48(a1)
3867 ; CHECK-RV64C-NEXT: lbu t5, 56(a1)
3868 ; CHECK-RV64C-NEXT: lbu t6, 64(a1)
3869 ; CHECK-RV64C-NEXT: lbu a3, 72(a1)
3870 ; CHECK-RV64C-NEXT: lbu a4, 80(a1)
3871 ; CHECK-RV64C-NEXT: lbu a5, 88(a1)
3872 ; CHECK-RV64C-NEXT: lbu a2, 120(a1)
3873 ; CHECK-RV64C-NEXT: lbu s0, 112(a1)
3874 ; CHECK-RV64C-NEXT: lbu s1, 104(a1)
3875 ; CHECK-RV64C-NEXT: lbu a1, 96(a1)
3876 ; CHECK-RV64C-NEXT: c.ntl.pall
3877 ; CHECK-RV64C-NEXT: sb a2, 15(a0)
3878 ; CHECK-RV64C-NEXT: c.ntl.pall
3879 ; CHECK-RV64C-NEXT: sb s0, 14(a0)
3880 ; CHECK-RV64C-NEXT: c.ntl.pall
3881 ; CHECK-RV64C-NEXT: sb s1, 13(a0)
3882 ; CHECK-RV64C-NEXT: c.ntl.pall
3883 ; CHECK-RV64C-NEXT: sb a1, 12(a0)
3884 ; CHECK-RV64C-NEXT: c.ntl.pall
3885 ; CHECK-RV64C-NEXT: sb a5, 11(a0)
3886 ; CHECK-RV64C-NEXT: c.ntl.pall
3887 ; CHECK-RV64C-NEXT: sb a4, 10(a0)
3888 ; CHECK-RV64C-NEXT: c.ntl.pall
3889 ; CHECK-RV64C-NEXT: sb a3, 9(a0)
3890 ; CHECK-RV64C-NEXT: c.ntl.pall
3891 ; CHECK-RV64C-NEXT: sb t6, 8(a0)
3892 ; CHECK-RV64C-NEXT: c.ntl.pall
3893 ; CHECK-RV64C-NEXT: sb t5, 7(a0)
3894 ; CHECK-RV64C-NEXT: c.ntl.pall
3895 ; CHECK-RV64C-NEXT: sb t4, 6(a0)
3896 ; CHECK-RV64C-NEXT: c.ntl.pall
3897 ; CHECK-RV64C-NEXT: sb t3, 5(a0)
3898 ; CHECK-RV64C-NEXT: c.ntl.pall
3899 ; CHECK-RV64C-NEXT: sb t2, 4(a0)
3900 ; CHECK-RV64C-NEXT: c.ntl.pall
3901 ; CHECK-RV64C-NEXT: sb t1, 3(a0)
3902 ; CHECK-RV64C-NEXT: c.ntl.pall
3903 ; CHECK-RV64C-NEXT: sb t0, 2(a0)
3904 ; CHECK-RV64C-NEXT: c.ntl.pall
3905 ; CHECK-RV64C-NEXT: sb a7, 1(a0)
3906 ; CHECK-RV64C-NEXT: c.ntl.pall
3907 ; CHECK-RV64C-NEXT: sb a6, 0(a0)
3908 ; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
3909 ; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
3910 ; CHECK-RV64C-NEXT: addi sp, sp, 16
3911 ; CHECK-RV64C-NEXT: ret
3912 ;
3913 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_v16i8:
3914 ; CHECK-RV32C: # %bb.0:
3915 ; CHECK-RV32C-NEXT: addi sp, sp, -16
3916 ; CHECK-RV32C-NEXT: .cfi_def_cfa_offset 16
3917 ; CHECK-RV32C-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
3918 ; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
3919 ; CHECK-RV32C-NEXT: .cfi_offset s0, -4
3920 ; CHECK-RV32C-NEXT: .cfi_offset s1, -8
3921 ; CHECK-RV32C-NEXT: lbu a6, 0(a1)
3922 ; CHECK-RV32C-NEXT: lbu a7, 4(a1)
3923 ; CHECK-RV32C-NEXT: lbu t0, 8(a1)
3924 ; CHECK-RV32C-NEXT: lbu t1, 12(a1)
3925 ; CHECK-RV32C-NEXT: lbu t2, 16(a1)
3926 ; CHECK-RV32C-NEXT: lbu t3, 20(a1)
3927 ; CHECK-RV32C-NEXT: lbu t4, 24(a1)
3928 ; CHECK-RV32C-NEXT: lbu t5, 28(a1)
3929 ; CHECK-RV32C-NEXT: lbu t6, 32(a1)
3930 ; CHECK-RV32C-NEXT: lbu a3, 36(a1)
3931 ; CHECK-RV32C-NEXT: lbu a4, 40(a1)
3932 ; CHECK-RV32C-NEXT: lbu a5, 44(a1)
3933 ; CHECK-RV32C-NEXT: lbu a2, 60(a1)
3934 ; CHECK-RV32C-NEXT: lbu s0, 56(a1)
3935 ; CHECK-RV32C-NEXT: lbu s1, 52(a1)
3936 ; CHECK-RV32C-NEXT: lbu a1, 48(a1)
3937 ; CHECK-RV32C-NEXT: c.ntl.pall
3938 ; CHECK-RV32C-NEXT: sb a2, 15(a0)
3939 ; CHECK-RV32C-NEXT: c.ntl.pall
3940 ; CHECK-RV32C-NEXT: sb s0, 14(a0)
3941 ; CHECK-RV32C-NEXT: c.ntl.pall
3942 ; CHECK-RV32C-NEXT: sb s1, 13(a0)
3943 ; CHECK-RV32C-NEXT: c.ntl.pall
3944 ; CHECK-RV32C-NEXT: sb a1, 12(a0)
3945 ; CHECK-RV32C-NEXT: c.ntl.pall
3946 ; CHECK-RV32C-NEXT: sb a5, 11(a0)
3947 ; CHECK-RV32C-NEXT: c.ntl.pall
3948 ; CHECK-RV32C-NEXT: sb a4, 10(a0)
3949 ; CHECK-RV32C-NEXT: c.ntl.pall
3950 ; CHECK-RV32C-NEXT: sb a3, 9(a0)
3951 ; CHECK-RV32C-NEXT: c.ntl.pall
3952 ; CHECK-RV32C-NEXT: sb t6, 8(a0)
3953 ; CHECK-RV32C-NEXT: c.ntl.pall
3954 ; CHECK-RV32C-NEXT: sb t5, 7(a0)
3955 ; CHECK-RV32C-NEXT: c.ntl.pall
3956 ; CHECK-RV32C-NEXT: sb t4, 6(a0)
3957 ; CHECK-RV32C-NEXT: c.ntl.pall
3958 ; CHECK-RV32C-NEXT: sb t3, 5(a0)
3959 ; CHECK-RV32C-NEXT: c.ntl.pall
3960 ; CHECK-RV32C-NEXT: sb t2, 4(a0)
3961 ; CHECK-RV32C-NEXT: c.ntl.pall
3962 ; CHECK-RV32C-NEXT: sb t1, 3(a0)
3963 ; CHECK-RV32C-NEXT: c.ntl.pall
3964 ; CHECK-RV32C-NEXT: sb t0, 2(a0)
3965 ; CHECK-RV32C-NEXT: c.ntl.pall
3966 ; CHECK-RV32C-NEXT: sb a7, 1(a0)
3967 ; CHECK-RV32C-NEXT: c.ntl.pall
3968 ; CHECK-RV32C-NEXT: sb a6, 0(a0)
3969 ; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
3970 ; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
3971 ; CHECK-RV32C-NEXT: addi sp, sp, 16
3972 ; CHECK-RV32C-NEXT: ret
3973 ;
3974 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_v16i8:
3975 ; CHECK-RV64V: # %bb.0:
3976 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
3977 ; CHECK-RV64V-NEXT: ntl.pall
3978 ; CHECK-RV64V-NEXT: vse8.v v8, (a0)
3979 ; CHECK-RV64V-NEXT: ret
3980 ;
3981 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_v16i8:
3982 ; CHECK-RV32V: # %bb.0:
3983 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
3984 ; CHECK-RV32V-NEXT: ntl.pall
3985 ; CHECK-RV32V-NEXT: vse8.v v8, (a0)
3986 ; CHECK-RV32V-NEXT: ret
3987 store <16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
3988 ret void
3989 }
3991 define void @test_nontemporal_PALL_store_v8i16(ptr %p, <8 x i16> %v) {
3992 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_v8i16:
3993 ; CHECK-RV64: # %bb.0:
3994 ; CHECK-RV64-NEXT: lh a2, 0(a1)
3995 ; CHECK-RV64-NEXT: lh a3, 8(a1)
3996 ; CHECK-RV64-NEXT: lh a4, 16(a1)
3997 ; CHECK-RV64-NEXT: lh a5, 24(a1)
3998 ; CHECK-RV64-NEXT: lh a6, 56(a1)
3999 ; CHECK-RV64-NEXT: lh a7, 48(a1)
4000 ; CHECK-RV64-NEXT: lh t0, 40(a1)
4001 ; CHECK-RV64-NEXT: lh a1, 32(a1)
4002 ; CHECK-RV64-NEXT: ntl.pall
4003 ; CHECK-RV64-NEXT: sh a6, 14(a0)
4004 ; CHECK-RV64-NEXT: ntl.pall
4005 ; CHECK-RV64-NEXT: sh a7, 12(a0)
4006 ; CHECK-RV64-NEXT: ntl.pall
4007 ; CHECK-RV64-NEXT: sh t0, 10(a0)
4008 ; CHECK-RV64-NEXT: ntl.pall
4009 ; CHECK-RV64-NEXT: sh a1, 8(a0)
4010 ; CHECK-RV64-NEXT: ntl.pall
4011 ; CHECK-RV64-NEXT: sh a5, 6(a0)
4012 ; CHECK-RV64-NEXT: ntl.pall
4013 ; CHECK-RV64-NEXT: sh a4, 4(a0)
4014 ; CHECK-RV64-NEXT: ntl.pall
4015 ; CHECK-RV64-NEXT: sh a3, 2(a0)
4016 ; CHECK-RV64-NEXT: ntl.pall
4017 ; CHECK-RV64-NEXT: sh a2, 0(a0)
4018 ; CHECK-RV64-NEXT: ret
4019 ;
4020 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_v8i16:
4021 ; CHECK-RV32: # %bb.0:
4022 ; CHECK-RV32-NEXT: lh a2, 0(a1)
4023 ; CHECK-RV32-NEXT: lh a3, 4(a1)
4024 ; CHECK-RV32-NEXT: lh a4, 8(a1)
4025 ; CHECK-RV32-NEXT: lh a5, 12(a1)
4026 ; CHECK-RV32-NEXT: lh a6, 28(a1)
4027 ; CHECK-RV32-NEXT: lh a7, 24(a1)
4028 ; CHECK-RV32-NEXT: lh t0, 20(a1)
4029 ; CHECK-RV32-NEXT: lh a1, 16(a1)
4030 ; CHECK-RV32-NEXT: ntl.pall
4031 ; CHECK-RV32-NEXT: sh a6, 14(a0)
4032 ; CHECK-RV32-NEXT: ntl.pall
4033 ; CHECK-RV32-NEXT: sh a7, 12(a0)
4034 ; CHECK-RV32-NEXT: ntl.pall
4035 ; CHECK-RV32-NEXT: sh t0, 10(a0)
4036 ; CHECK-RV32-NEXT: ntl.pall
4037 ; CHECK-RV32-NEXT: sh a1, 8(a0)
4038 ; CHECK-RV32-NEXT: ntl.pall
4039 ; CHECK-RV32-NEXT: sh a5, 6(a0)
4040 ; CHECK-RV32-NEXT: ntl.pall
4041 ; CHECK-RV32-NEXT: sh a4, 4(a0)
4042 ; CHECK-RV32-NEXT: ntl.pall
4043 ; CHECK-RV32-NEXT: sh a3, 2(a0)
4044 ; CHECK-RV32-NEXT: ntl.pall
4045 ; CHECK-RV32-NEXT: sh a2, 0(a0)
4046 ; CHECK-RV32-NEXT: ret
4047 ;
4048 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_v8i16:
4049 ; CHECK-RV64C: # %bb.0:
4050 ; CHECK-RV64C-NEXT: lh a6, 0(a1)
4051 ; CHECK-RV64C-NEXT: lh a7, 8(a1)
4052 ; CHECK-RV64C-NEXT: lh t0, 16(a1)
4053 ; CHECK-RV64C-NEXT: lh a5, 24(a1)
4054 ; CHECK-RV64C-NEXT: lh a2, 56(a1)
4055 ; CHECK-RV64C-NEXT: lh a3, 48(a1)
4056 ; CHECK-RV64C-NEXT: lh a4, 40(a1)
4057 ; CHECK-RV64C-NEXT: lh a1, 32(a1)
4058 ; CHECK-RV64C-NEXT: c.ntl.pall
4059 ; CHECK-RV64C-NEXT: sh a2, 14(a0)
4060 ; CHECK-RV64C-NEXT: c.ntl.pall
4061 ; CHECK-RV64C-NEXT: sh a3, 12(a0)
4062 ; CHECK-RV64C-NEXT: c.ntl.pall
4063 ; CHECK-RV64C-NEXT: sh a4, 10(a0)
4064 ; CHECK-RV64C-NEXT: c.ntl.pall
4065 ; CHECK-RV64C-NEXT: sh a1, 8(a0)
4066 ; CHECK-RV64C-NEXT: c.ntl.pall
4067 ; CHECK-RV64C-NEXT: sh a5, 6(a0)
4068 ; CHECK-RV64C-NEXT: c.ntl.pall
4069 ; CHECK-RV64C-NEXT: sh t0, 4(a0)
4070 ; CHECK-RV64C-NEXT: c.ntl.pall
4071 ; CHECK-RV64C-NEXT: sh a7, 2(a0)
4072 ; CHECK-RV64C-NEXT: c.ntl.pall
4073 ; CHECK-RV64C-NEXT: sh a6, 0(a0)
4074 ; CHECK-RV64C-NEXT: ret
4075 ;
4076 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_v8i16:
4077 ; CHECK-RV32C: # %bb.0:
4078 ; CHECK-RV32C-NEXT: lh a6, 0(a1)
4079 ; CHECK-RV32C-NEXT: lh a7, 4(a1)
4080 ; CHECK-RV32C-NEXT: lh t0, 8(a1)
4081 ; CHECK-RV32C-NEXT: lh a5, 12(a1)
4082 ; CHECK-RV32C-NEXT: lh a2, 28(a1)
4083 ; CHECK-RV32C-NEXT: lh a3, 24(a1)
4084 ; CHECK-RV32C-NEXT: lh a4, 20(a1)
4085 ; CHECK-RV32C-NEXT: lh a1, 16(a1)
4086 ; CHECK-RV32C-NEXT: c.ntl.pall
4087 ; CHECK-RV32C-NEXT: sh a2, 14(a0)
4088 ; CHECK-RV32C-NEXT: c.ntl.pall
4089 ; CHECK-RV32C-NEXT: sh a3, 12(a0)
4090 ; CHECK-RV32C-NEXT: c.ntl.pall
4091 ; CHECK-RV32C-NEXT: sh a4, 10(a0)
4092 ; CHECK-RV32C-NEXT: c.ntl.pall
4093 ; CHECK-RV32C-NEXT: sh a1, 8(a0)
4094 ; CHECK-RV32C-NEXT: c.ntl.pall
4095 ; CHECK-RV32C-NEXT: sh a5, 6(a0)
4096 ; CHECK-RV32C-NEXT: c.ntl.pall
4097 ; CHECK-RV32C-NEXT: sh t0, 4(a0)
4098 ; CHECK-RV32C-NEXT: c.ntl.pall
4099 ; CHECK-RV32C-NEXT: sh a7, 2(a0)
4100 ; CHECK-RV32C-NEXT: c.ntl.pall
4101 ; CHECK-RV32C-NEXT: sh a6, 0(a0)
4102 ; CHECK-RV32C-NEXT: ret
4103 ;
4104 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_v8i16:
4105 ; CHECK-RV64V: # %bb.0:
4106 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4107 ; CHECK-RV64V-NEXT: ntl.pall
4108 ; CHECK-RV64V-NEXT: vse16.v v8, (a0)
4109 ; CHECK-RV64V-NEXT: ret
4110 ;
4111 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_v8i16:
4112 ; CHECK-RV32V: # %bb.0:
4113 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4114 ; CHECK-RV32V-NEXT: ntl.pall
4115 ; CHECK-RV32V-NEXT: vse16.v v8, (a0)
4116 ; CHECK-RV32V-NEXT: ret
4117 store <8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
4118 ret void
4119 }
4121 define void @test_nontemporal_PALL_store_v4i32(ptr %p, <4 x i32> %v) {
4122 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_v4i32:
4123 ; CHECK-RV64: # %bb.0:
4124 ; CHECK-RV64-NEXT: lw a2, 24(a1)
4125 ; CHECK-RV64-NEXT: lw a3, 16(a1)
4126 ; CHECK-RV64-NEXT: lw a4, 8(a1)
4127 ; CHECK-RV64-NEXT: lw a1, 0(a1)
4128 ; CHECK-RV64-NEXT: ntl.pall
4129 ; CHECK-RV64-NEXT: sw a2, 12(a0)
4130 ; CHECK-RV64-NEXT: ntl.pall
4131 ; CHECK-RV64-NEXT: sw a3, 8(a0)
4132 ; CHECK-RV64-NEXT: ntl.pall
4133 ; CHECK-RV64-NEXT: sw a4, 4(a0)
4134 ; CHECK-RV64-NEXT: ntl.pall
4135 ; CHECK-RV64-NEXT: sw a1, 0(a0)
4136 ; CHECK-RV64-NEXT: ret
4137 ;
4138 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_v4i32:
4139 ; CHECK-RV32: # %bb.0:
4140 ; CHECK-RV32-NEXT: lw a2, 12(a1)
4141 ; CHECK-RV32-NEXT: lw a3, 8(a1)
4142 ; CHECK-RV32-NEXT: lw a4, 4(a1)
4143 ; CHECK-RV32-NEXT: lw a1, 0(a1)
4144 ; CHECK-RV32-NEXT: ntl.pall
4145 ; CHECK-RV32-NEXT: sw a2, 12(a0)
4146 ; CHECK-RV32-NEXT: ntl.pall
4147 ; CHECK-RV32-NEXT: sw a3, 8(a0)
4148 ; CHECK-RV32-NEXT: ntl.pall
4149 ; CHECK-RV32-NEXT: sw a4, 4(a0)
4150 ; CHECK-RV32-NEXT: ntl.pall
4151 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4152 ; CHECK-RV32-NEXT: ret
4153 ;
4154 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_v4i32:
4155 ; CHECK-RV64C: # %bb.0:
4156 ; CHECK-RV64C-NEXT: lw a2, 24(a1)
4157 ; CHECK-RV64C-NEXT: lw a3, 16(a1)
4158 ; CHECK-RV64C-NEXT: lw a4, 8(a1)
4159 ; CHECK-RV64C-NEXT: lw a1, 0(a1)
4160 ; CHECK-RV64C-NEXT: c.ntl.pall
4161 ; CHECK-RV64C-NEXT: sw a2, 12(a0)
4162 ; CHECK-RV64C-NEXT: c.ntl.pall
4163 ; CHECK-RV64C-NEXT: sw a3, 8(a0)
4164 ; CHECK-RV64C-NEXT: c.ntl.pall
4165 ; CHECK-RV64C-NEXT: sw a4, 4(a0)
4166 ; CHECK-RV64C-NEXT: c.ntl.pall
4167 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
4168 ; CHECK-RV64C-NEXT: ret
4169 ;
4170 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_v4i32:
4171 ; CHECK-RV32C: # %bb.0:
4172 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
4173 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
4174 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
4175 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
4176 ; CHECK-RV32C-NEXT: c.ntl.pall
4177 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
4178 ; CHECK-RV32C-NEXT: c.ntl.pall
4179 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
4180 ; CHECK-RV32C-NEXT: c.ntl.pall
4181 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
4182 ; CHECK-RV32C-NEXT: c.ntl.pall
4183 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4184 ; CHECK-RV32C-NEXT: ret
4185 ;
4186 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_v4i32:
4187 ; CHECK-RV64V: # %bb.0:
4188 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
4189 ; CHECK-RV64V-NEXT: ntl.pall
4190 ; CHECK-RV64V-NEXT: vse32.v v8, (a0)
4191 ; CHECK-RV64V-NEXT: ret
4192 ;
4193 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_v4i32:
4194 ; CHECK-RV32V: # %bb.0:
4195 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
4196 ; CHECK-RV32V-NEXT: ntl.pall
4197 ; CHECK-RV32V-NEXT: vse32.v v8, (a0)
4198 ; CHECK-RV32V-NEXT: ret
4199 store <4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
4200 ret void
4201 }
4203 define void @test_nontemporal_PALL_store_v2i64(ptr %p, <2 x i64> %v) {
4204 ; CHECK-RV64-LABEL: test_nontemporal_PALL_store_v2i64:
4205 ; CHECK-RV64: # %bb.0:
4206 ; CHECK-RV64-NEXT: ntl.pall
4207 ; CHECK-RV64-NEXT: sd a2, 8(a0)
4208 ; CHECK-RV64-NEXT: ntl.pall
4209 ; CHECK-RV64-NEXT: sd a1, 0(a0)
4210 ; CHECK-RV64-NEXT: ret
4211 ;
4212 ; CHECK-RV32-LABEL: test_nontemporal_PALL_store_v2i64:
4213 ; CHECK-RV32: # %bb.0:
4214 ; CHECK-RV32-NEXT: lw a2, 12(a1)
4215 ; CHECK-RV32-NEXT: lw a3, 8(a1)
4216 ; CHECK-RV32-NEXT: lw a4, 4(a1)
4217 ; CHECK-RV32-NEXT: lw a1, 0(a1)
4218 ; CHECK-RV32-NEXT: ntl.pall
4219 ; CHECK-RV32-NEXT: sw a2, 12(a0)
4220 ; CHECK-RV32-NEXT: ntl.pall
4221 ; CHECK-RV32-NEXT: sw a3, 8(a0)
4222 ; CHECK-RV32-NEXT: ntl.pall
4223 ; CHECK-RV32-NEXT: sw a4, 4(a0)
4224 ; CHECK-RV32-NEXT: ntl.pall
4225 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4226 ; CHECK-RV32-NEXT: ret
4227 ;
4228 ; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_v2i64:
4229 ; CHECK-RV64C: # %bb.0:
4230 ; CHECK-RV64C-NEXT: c.ntl.pall
4231 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
4232 ; CHECK-RV64C-NEXT: c.ntl.pall
4233 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
4234 ; CHECK-RV64C-NEXT: ret
4235 ;
4236 ; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_v2i64:
4237 ; CHECK-RV32C: # %bb.0:
4238 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
4239 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
4240 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
4241 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
4242 ; CHECK-RV32C-NEXT: c.ntl.pall
4243 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
4244 ; CHECK-RV32C-NEXT: c.ntl.pall
4245 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
4246 ; CHECK-RV32C-NEXT: c.ntl.pall
4247 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
4248 ; CHECK-RV32C-NEXT: c.ntl.pall
4249 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4250 ; CHECK-RV32C-NEXT: ret
4251 ;
4252 ; CHECK-RV64V-LABEL: test_nontemporal_PALL_store_v2i64:
4253 ; CHECK-RV64V: # %bb.0:
4254 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
4255 ; CHECK-RV64V-NEXT: ntl.pall
4256 ; CHECK-RV64V-NEXT: vse64.v v8, (a0)
4257 ; CHECK-RV64V-NEXT: ret
4258 ;
4259 ; CHECK-RV32V-LABEL: test_nontemporal_PALL_store_v2i64:
4260 ; CHECK-RV32V: # %bb.0:
4261 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
4262 ; CHECK-RV32V-NEXT: ntl.pall
4263 ; CHECK-RV32V-NEXT: vse64.v v8, (a0)
4264 ; CHECK-RV32V-NEXT: ret
4265 store <2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !2
4266 ret void
4267 }
4269 define i64 @test_nontemporal_S1_load_i64(ptr %p) {
4270 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_i64:
4271 ; CHECK-RV64: # %bb.0:
4272 ; CHECK-RV64-NEXT: ntl.s1
4273 ; CHECK-RV64-NEXT: ld a0, 0(a0)
4274 ; CHECK-RV64-NEXT: ret
4275 ;
4276 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_i64:
4277 ; CHECK-RV32: # %bb.0:
4278 ; CHECK-RV32-NEXT: ntl.s1
4279 ; CHECK-RV32-NEXT: lw a2, 0(a0)
4280 ; CHECK-RV32-NEXT: ntl.s1
4281 ; CHECK-RV32-NEXT: lw a1, 4(a0)
4282 ; CHECK-RV32-NEXT: mv a0, a2
4283 ; CHECK-RV32-NEXT: ret
4284 ;
4285 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_i64:
4286 ; CHECK-RV64C: # %bb.0:
4287 ; CHECK-RV64C-NEXT: c.ntl.s1
4288 ; CHECK-RV64C-NEXT: ld a0, 0(a0)
4289 ; CHECK-RV64C-NEXT: ret
4290 ;
4291 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_i64:
4292 ; CHECK-RV32C: # %bb.0:
4293 ; CHECK-RV32C-NEXT: c.ntl.s1
4294 ; CHECK-RV32C-NEXT: lw a2, 0(a0)
4295 ; CHECK-RV32C-NEXT: c.ntl.s1
4296 ; CHECK-RV32C-NEXT: lw a1, 4(a0)
4297 ; CHECK-RV32C-NEXT: mv a0, a2
4298 ; CHECK-RV32C-NEXT: ret
4299 ;
4300 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_i64:
4301 ; CHECK-RV64V: # %bb.0:
4302 ; CHECK-RV64V-NEXT: ntl.s1
4303 ; CHECK-RV64V-NEXT: ld a0, 0(a0)
4304 ; CHECK-RV64V-NEXT: ret
4305 ;
4306 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_i64:
4307 ; CHECK-RV32V: # %bb.0:
4308 ; CHECK-RV32V-NEXT: ntl.s1
4309 ; CHECK-RV32V-NEXT: lw a2, 0(a0)
4310 ; CHECK-RV32V-NEXT: ntl.s1
4311 ; CHECK-RV32V-NEXT: lw a1, 4(a0)
4312 ; CHECK-RV32V-NEXT: mv a0, a2
4313 ; CHECK-RV32V-NEXT: ret
4314 %1 = load i64, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4315 ret i64 %1
4316 }
4318 define i32 @test_nontemporal_S1_load_i32(ptr %p) {
4319 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_i32:
4320 ; CHECK-RV64: # %bb.0:
4321 ; CHECK-RV64-NEXT: ntl.s1
4322 ; CHECK-RV64-NEXT: lw a0, 0(a0)
4323 ; CHECK-RV64-NEXT: ret
4324 ;
4325 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_i32:
4326 ; CHECK-RV32: # %bb.0:
4327 ; CHECK-RV32-NEXT: ntl.s1
4328 ; CHECK-RV32-NEXT: lw a0, 0(a0)
4329 ; CHECK-RV32-NEXT: ret
4330 ;
4331 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_i32:
4332 ; CHECK-RV64C: # %bb.0:
4333 ; CHECK-RV64C-NEXT: c.ntl.s1
4334 ; CHECK-RV64C-NEXT: lw a0, 0(a0)
4335 ; CHECK-RV64C-NEXT: ret
4336 ;
4337 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_i32:
4338 ; CHECK-RV32C: # %bb.0:
4339 ; CHECK-RV32C-NEXT: c.ntl.s1
4340 ; CHECK-RV32C-NEXT: lw a0, 0(a0)
4341 ; CHECK-RV32C-NEXT: ret
4342 ;
4343 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_i32:
4344 ; CHECK-RV64V: # %bb.0:
4345 ; CHECK-RV64V-NEXT: ntl.s1
4346 ; CHECK-RV64V-NEXT: lw a0, 0(a0)
4347 ; CHECK-RV64V-NEXT: ret
4348 ;
4349 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_i32:
4350 ; CHECK-RV32V: # %bb.0:
4351 ; CHECK-RV32V-NEXT: ntl.s1
4352 ; CHECK-RV32V-NEXT: lw a0, 0(a0)
4353 ; CHECK-RV32V-NEXT: ret
4354 %1 = load i32, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4355 ret i32 %1
4356 }
4358 define i16 @test_nontemporal_S1_load_i16(ptr %p) {
4359 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_i16:
4360 ; CHECK-RV64: # %bb.0:
4361 ; CHECK-RV64-NEXT: ntl.s1
4362 ; CHECK-RV64-NEXT: lh a0, 0(a0)
4363 ; CHECK-RV64-NEXT: ret
4364 ;
4365 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_i16:
4366 ; CHECK-RV32: # %bb.0:
4367 ; CHECK-RV32-NEXT: ntl.s1
4368 ; CHECK-RV32-NEXT: lh a0, 0(a0)
4369 ; CHECK-RV32-NEXT: ret
4370 ;
4371 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_i16:
4372 ; CHECK-RV64C: # %bb.0:
4373 ; CHECK-RV64C-NEXT: c.ntl.s1
4374 ; CHECK-RV64C-NEXT: lh a0, 0(a0)
4375 ; CHECK-RV64C-NEXT: ret
4376 ;
4377 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_i16:
4378 ; CHECK-RV32C: # %bb.0:
4379 ; CHECK-RV32C-NEXT: c.ntl.s1
4380 ; CHECK-RV32C-NEXT: lh a0, 0(a0)
4381 ; CHECK-RV32C-NEXT: ret
4382 ;
4383 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_i16:
4384 ; CHECK-RV64V: # %bb.0:
4385 ; CHECK-RV64V-NEXT: ntl.s1
4386 ; CHECK-RV64V-NEXT: lh a0, 0(a0)
4387 ; CHECK-RV64V-NEXT: ret
4388 ;
4389 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_i16:
4390 ; CHECK-RV32V: # %bb.0:
4391 ; CHECK-RV32V-NEXT: ntl.s1
4392 ; CHECK-RV32V-NEXT: lh a0, 0(a0)
4393 ; CHECK-RV32V-NEXT: ret
4394 %1 = load i16, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4395 ret i16 %1
4396 }
4398 define i8 @test_nontemporal_S1_load_i8(ptr %p) {
4399 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_i8:
4400 ; CHECK-RV64: # %bb.0:
4401 ; CHECK-RV64-NEXT: ntl.s1
4402 ; CHECK-RV64-NEXT: lbu a0, 0(a0)
4403 ; CHECK-RV64-NEXT: ret
4404 ;
4405 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_i8:
4406 ; CHECK-RV32: # %bb.0:
4407 ; CHECK-RV32-NEXT: ntl.s1
4408 ; CHECK-RV32-NEXT: lbu a0, 0(a0)
4409 ; CHECK-RV32-NEXT: ret
4410 ;
4411 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_i8:
4412 ; CHECK-RV64C: # %bb.0:
4413 ; CHECK-RV64C-NEXT: c.ntl.s1
4414 ; CHECK-RV64C-NEXT: lbu a0, 0(a0)
4415 ; CHECK-RV64C-NEXT: ret
4416 ;
4417 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_i8:
4418 ; CHECK-RV32C: # %bb.0:
4419 ; CHECK-RV32C-NEXT: c.ntl.s1
4420 ; CHECK-RV32C-NEXT: lbu a0, 0(a0)
4421 ; CHECK-RV32C-NEXT: ret
4422 ;
4423 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_i8:
4424 ; CHECK-RV64V: # %bb.0:
4425 ; CHECK-RV64V-NEXT: ntl.s1
4426 ; CHECK-RV64V-NEXT: lbu a0, 0(a0)
4427 ; CHECK-RV64V-NEXT: ret
4428 ;
4429 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_i8:
4430 ; CHECK-RV32V: # %bb.0:
4431 ; CHECK-RV32V-NEXT: ntl.s1
4432 ; CHECK-RV32V-NEXT: lbu a0, 0(a0)
4433 ; CHECK-RV32V-NEXT: ret
4434 %1 = load i8, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4435 ret i8 %1
4436 }
4438 define half @test_nontemporal_S1_load_half(ptr %p) nounwind {
4439 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_half:
4440 ; CHECK-RV64: # %bb.0:
4441 ; CHECK-RV64-NEXT: ntl.s1
4442 ; CHECK-RV64-NEXT: flh fa5, 0(a0)
4443 ; CHECK-RV64-NEXT: ntl.s1
4444 ; CHECK-RV64-NEXT: flh fa4, 6(a0)
4445 ; CHECK-RV64-NEXT: fadd.h fa0, fa5, fa4
4446 ; CHECK-RV64-NEXT: ret
4447 ;
4448 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_half:
4449 ; CHECK-RV32: # %bb.0:
4450 ; CHECK-RV32-NEXT: ntl.s1
4451 ; CHECK-RV32-NEXT: flh fa5, 0(a0)
4452 ; CHECK-RV32-NEXT: ntl.s1
4453 ; CHECK-RV32-NEXT: flh fa4, 6(a0)
4454 ; CHECK-RV32-NEXT: fadd.h fa0, fa5, fa4
4455 ; CHECK-RV32-NEXT: ret
4456 ;
4457 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_half:
4458 ; CHECK-RV64C: # %bb.0:
4459 ; CHECK-RV64C-NEXT: c.ntl.s1
4460 ; CHECK-RV64C-NEXT: flh fa5, 0(a0)
4461 ; CHECK-RV64C-NEXT: c.ntl.s1
4462 ; CHECK-RV64C-NEXT: flh fa4, 6(a0)
4463 ; CHECK-RV64C-NEXT: fadd.h fa0, fa5, fa4
4464 ; CHECK-RV64C-NEXT: ret
4465 ;
4466 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_half:
4467 ; CHECK-RV32C: # %bb.0:
4468 ; CHECK-RV32C-NEXT: c.ntl.s1
4469 ; CHECK-RV32C-NEXT: flh fa5, 0(a0)
4470 ; CHECK-RV32C-NEXT: c.ntl.s1
4471 ; CHECK-RV32C-NEXT: flh fa4, 6(a0)
4472 ; CHECK-RV32C-NEXT: fadd.h fa0, fa5, fa4
4473 ; CHECK-RV32C-NEXT: ret
4474 ;
4475 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_half:
4476 ; CHECK-RV64V: # %bb.0:
4477 ; CHECK-RV64V-NEXT: ntl.s1
4478 ; CHECK-RV64V-NEXT: flh fa5, 0(a0)
4479 ; CHECK-RV64V-NEXT: ntl.s1
4480 ; CHECK-RV64V-NEXT: flh fa4, 6(a0)
4481 ; CHECK-RV64V-NEXT: fadd.h fa0, fa5, fa4
4482 ; CHECK-RV64V-NEXT: ret
4483 ;
4484 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_half:
4485 ; CHECK-RV32V: # %bb.0:
4486 ; CHECK-RV32V-NEXT: ntl.s1
4487 ; CHECK-RV32V-NEXT: flh fa5, 0(a0)
4488 ; CHECK-RV32V-NEXT: ntl.s1
4489 ; CHECK-RV32V-NEXT: flh fa4, 6(a0)
4490 ; CHECK-RV32V-NEXT: fadd.h fa0, fa5, fa4
4491 ; CHECK-RV32V-NEXT: ret
4492 %1 = load half, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4493 %2 = getelementptr half, ptr %p, i32 3
4494 %3 = load half, ptr %2, !nontemporal !0, !riscv-nontemporal-domain !3
4495 %4 = fadd half %1, %3
4496 ret half %4
4497 }
4499 define float @test_nontemporal_S1_load_float(ptr %p) {
4500 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_float:
4501 ; CHECK-RV64: # %bb.0:
4502 ; CHECK-RV64-NEXT: ntl.s1
4503 ; CHECK-RV64-NEXT: flw fa0, 0(a0)
4504 ; CHECK-RV64-NEXT: ret
4505 ;
4506 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_float:
4507 ; CHECK-RV32: # %bb.0:
4508 ; CHECK-RV32-NEXT: ntl.s1
4509 ; CHECK-RV32-NEXT: flw fa0, 0(a0)
4510 ; CHECK-RV32-NEXT: ret
4511 ;
4512 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_float:
4513 ; CHECK-RV64C: # %bb.0:
4514 ; CHECK-RV64C-NEXT: c.ntl.s1
4515 ; CHECK-RV64C-NEXT: flw fa0, 0(a0)
4516 ; CHECK-RV64C-NEXT: ret
4517 ;
4518 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_float:
4519 ; CHECK-RV32C: # %bb.0:
4520 ; CHECK-RV32C-NEXT: c.ntl.s1
4521 ; CHECK-RV32C-NEXT: flw fa0, 0(a0)
4522 ; CHECK-RV32C-NEXT: ret
4523 ;
4524 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_float:
4525 ; CHECK-RV64V: # %bb.0:
4526 ; CHECK-RV64V-NEXT: ntl.s1
4527 ; CHECK-RV64V-NEXT: flw fa0, 0(a0)
4528 ; CHECK-RV64V-NEXT: ret
4529 ;
4530 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_float:
4531 ; CHECK-RV32V: # %bb.0:
4532 ; CHECK-RV32V-NEXT: ntl.s1
4533 ; CHECK-RV32V-NEXT: flw fa0, 0(a0)
4534 ; CHECK-RV32V-NEXT: ret
4535 %1 = load float, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4536 ret float %1
4537 }
4539 define double @test_nontemporal_S1_load_double(ptr %p) {
4540 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_double:
4541 ; CHECK-RV64: # %bb.0:
4542 ; CHECK-RV64-NEXT: ntl.s1
4543 ; CHECK-RV64-NEXT: fld fa0, 0(a0)
4544 ; CHECK-RV64-NEXT: ret
4545 ;
4546 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_double:
4547 ; CHECK-RV32: # %bb.0:
4548 ; CHECK-RV32-NEXT: ntl.s1
4549 ; CHECK-RV32-NEXT: fld fa0, 0(a0)
4550 ; CHECK-RV32-NEXT: ret
4551 ;
4552 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_double:
4553 ; CHECK-RV64C: # %bb.0:
4554 ; CHECK-RV64C-NEXT: c.ntl.s1
4555 ; CHECK-RV64C-NEXT: fld fa0, 0(a0)
4556 ; CHECK-RV64C-NEXT: ret
4557 ;
4558 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_double:
4559 ; CHECK-RV32C: # %bb.0:
4560 ; CHECK-RV32C-NEXT: c.ntl.s1
4561 ; CHECK-RV32C-NEXT: fld fa0, 0(a0)
4562 ; CHECK-RV32C-NEXT: ret
4563 ;
4564 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_double:
4565 ; CHECK-RV64V: # %bb.0:
4566 ; CHECK-RV64V-NEXT: ntl.s1
4567 ; CHECK-RV64V-NEXT: fld fa0, 0(a0)
4568 ; CHECK-RV64V-NEXT: ret
4569 ;
4570 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_double:
4571 ; CHECK-RV32V: # %bb.0:
4572 ; CHECK-RV32V-NEXT: ntl.s1
4573 ; CHECK-RV32V-NEXT: fld fa0, 0(a0)
4574 ; CHECK-RV32V-NEXT: ret
4575 %1 = load double, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4576 ret double %1
4577 }
4579 define <16 x i8> @test_nontemporal_S1_load_v16i8(ptr %p) {
4580 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_v16i8:
4581 ; CHECK-RV64: # %bb.0:
4582 ; CHECK-RV64-NEXT: ntl.s1
4583 ; CHECK-RV64-NEXT: ld a2, 8(a1)
4584 ; CHECK-RV64-NEXT: ntl.s1
4585 ; CHECK-RV64-NEXT: ld a1, 0(a1)
4586 ; CHECK-RV64-NEXT: sd a2, 8(a0)
4587 ; CHECK-RV64-NEXT: sd a1, 0(a0)
4588 ; CHECK-RV64-NEXT: ret
4589 ;
4590 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_v16i8:
4591 ; CHECK-RV32: # %bb.0:
4592 ; CHECK-RV32-NEXT: ntl.s1
4593 ; CHECK-RV32-NEXT: lw a2, 12(a1)
4594 ; CHECK-RV32-NEXT: ntl.s1
4595 ; CHECK-RV32-NEXT: lw a3, 8(a1)
4596 ; CHECK-RV32-NEXT: ntl.s1
4597 ; CHECK-RV32-NEXT: lw a4, 4(a1)
4598 ; CHECK-RV32-NEXT: ntl.s1
4599 ; CHECK-RV32-NEXT: lw a1, 0(a1)
4600 ; CHECK-RV32-NEXT: sw a2, 12(a0)
4601 ; CHECK-RV32-NEXT: sw a3, 8(a0)
4602 ; CHECK-RV32-NEXT: sw a4, 4(a0)
4603 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4604 ; CHECK-RV32-NEXT: ret
4605 ;
4606 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_v16i8:
4607 ; CHECK-RV64C: # %bb.0:
4608 ; CHECK-RV64C-NEXT: c.ntl.s1
4609 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
4610 ; CHECK-RV64C-NEXT: c.ntl.s1
4611 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
4612 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
4613 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
4614 ; CHECK-RV64C-NEXT: ret
4615 ;
4616 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_v16i8:
4617 ; CHECK-RV32C: # %bb.0:
4618 ; CHECK-RV32C-NEXT: c.ntl.s1
4619 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
4620 ; CHECK-RV32C-NEXT: c.ntl.s1
4621 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
4622 ; CHECK-RV32C-NEXT: c.ntl.s1
4623 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
4624 ; CHECK-RV32C-NEXT: c.ntl.s1
4625 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
4626 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
4627 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
4628 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
4629 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4630 ; CHECK-RV32C-NEXT: ret
4631 ;
4632 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_v16i8:
4633 ; CHECK-RV64V: # %bb.0:
4634 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
4635 ; CHECK-RV64V-NEXT: ntl.s1
4636 ; CHECK-RV64V-NEXT: vle8.v v8, (a0)
4637 ; CHECK-RV64V-NEXT: ret
4638 ;
4639 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_v16i8:
4640 ; CHECK-RV32V: # %bb.0:
4641 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
4642 ; CHECK-RV32V-NEXT: ntl.s1
4643 ; CHECK-RV32V-NEXT: vle8.v v8, (a0)
4644 ; CHECK-RV32V-NEXT: ret
4645 %1 = load <16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4646 ret <16 x i8> %1
4647 }
4649 define <8 x i16> @test_nontemporal_S1_load_v8i16(ptr %p) {
4650 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_v8i16:
4651 ; CHECK-RV64: # %bb.0:
4652 ; CHECK-RV64-NEXT: ntl.s1
4653 ; CHECK-RV64-NEXT: ld a2, 8(a1)
4654 ; CHECK-RV64-NEXT: ntl.s1
4655 ; CHECK-RV64-NEXT: ld a1, 0(a1)
4656 ; CHECK-RV64-NEXT: sd a2, 8(a0)
4657 ; CHECK-RV64-NEXT: sd a1, 0(a0)
4658 ; CHECK-RV64-NEXT: ret
4659 ;
4660 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_v8i16:
4661 ; CHECK-RV32: # %bb.0:
4662 ; CHECK-RV32-NEXT: ntl.s1
4663 ; CHECK-RV32-NEXT: lw a2, 12(a1)
4664 ; CHECK-RV32-NEXT: ntl.s1
4665 ; CHECK-RV32-NEXT: lw a3, 8(a1)
4666 ; CHECK-RV32-NEXT: ntl.s1
4667 ; CHECK-RV32-NEXT: lw a4, 4(a1)
4668 ; CHECK-RV32-NEXT: ntl.s1
4669 ; CHECK-RV32-NEXT: lw a1, 0(a1)
4670 ; CHECK-RV32-NEXT: sw a2, 12(a0)
4671 ; CHECK-RV32-NEXT: sw a3, 8(a0)
4672 ; CHECK-RV32-NEXT: sw a4, 4(a0)
4673 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4674 ; CHECK-RV32-NEXT: ret
4675 ;
4676 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_v8i16:
4677 ; CHECK-RV64C: # %bb.0:
4678 ; CHECK-RV64C-NEXT: c.ntl.s1
4679 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
4680 ; CHECK-RV64C-NEXT: c.ntl.s1
4681 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
4682 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
4683 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
4684 ; CHECK-RV64C-NEXT: ret
4685 ;
4686 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_v8i16:
4687 ; CHECK-RV32C: # %bb.0:
4688 ; CHECK-RV32C-NEXT: c.ntl.s1
4689 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
4690 ; CHECK-RV32C-NEXT: c.ntl.s1
4691 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
4692 ; CHECK-RV32C-NEXT: c.ntl.s1
4693 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
4694 ; CHECK-RV32C-NEXT: c.ntl.s1
4695 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
4696 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
4697 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
4698 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
4699 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4700 ; CHECK-RV32C-NEXT: ret
4701 ;
4702 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_v8i16:
4703 ; CHECK-RV64V: # %bb.0:
4704 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4705 ; CHECK-RV64V-NEXT: ntl.s1
4706 ; CHECK-RV64V-NEXT: vle16.v v8, (a0)
4707 ; CHECK-RV64V-NEXT: ret
4708 ;
4709 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_v8i16:
4710 ; CHECK-RV32V: # %bb.0:
4711 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
4712 ; CHECK-RV32V-NEXT: ntl.s1
4713 ; CHECK-RV32V-NEXT: vle16.v v8, (a0)
4714 ; CHECK-RV32V-NEXT: ret
4715 %1 = load <8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4716 ret <8 x i16> %1
4717 }
4719 define <4 x i32> @test_nontemporal_S1_load_v4i32(ptr %p) {
4720 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_v4i32:
4721 ; CHECK-RV64: # %bb.0:
4722 ; CHECK-RV64-NEXT: ntl.s1
4723 ; CHECK-RV64-NEXT: ld a2, 8(a1)
4724 ; CHECK-RV64-NEXT: ntl.s1
4725 ; CHECK-RV64-NEXT: ld a1, 0(a1)
4726 ; CHECK-RV64-NEXT: sd a2, 8(a0)
4727 ; CHECK-RV64-NEXT: sd a1, 0(a0)
4728 ; CHECK-RV64-NEXT: ret
4729 ;
4730 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_v4i32:
4731 ; CHECK-RV32: # %bb.0:
4732 ; CHECK-RV32-NEXT: ntl.s1
4733 ; CHECK-RV32-NEXT: lw a2, 12(a1)
4734 ; CHECK-RV32-NEXT: ntl.s1
4735 ; CHECK-RV32-NEXT: lw a3, 8(a1)
4736 ; CHECK-RV32-NEXT: ntl.s1
4737 ; CHECK-RV32-NEXT: lw a4, 4(a1)
4738 ; CHECK-RV32-NEXT: ntl.s1
4739 ; CHECK-RV32-NEXT: lw a1, 0(a1)
4740 ; CHECK-RV32-NEXT: sw a2, 12(a0)
4741 ; CHECK-RV32-NEXT: sw a3, 8(a0)
4742 ; CHECK-RV32-NEXT: sw a4, 4(a0)
4743 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4744 ; CHECK-RV32-NEXT: ret
4745 ;
4746 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_v4i32:
4747 ; CHECK-RV64C: # %bb.0:
4748 ; CHECK-RV64C-NEXT: c.ntl.s1
4749 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
4750 ; CHECK-RV64C-NEXT: c.ntl.s1
4751 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
4752 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
4753 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
4754 ; CHECK-RV64C-NEXT: ret
4755 ;
4756 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_v4i32:
4757 ; CHECK-RV32C: # %bb.0:
4758 ; CHECK-RV32C-NEXT: c.ntl.s1
4759 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
4760 ; CHECK-RV32C-NEXT: c.ntl.s1
4761 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
4762 ; CHECK-RV32C-NEXT: c.ntl.s1
4763 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
4764 ; CHECK-RV32C-NEXT: c.ntl.s1
4765 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
4766 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
4767 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
4768 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
4769 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4770 ; CHECK-RV32C-NEXT: ret
4771 ;
4772 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_v4i32:
4773 ; CHECK-RV64V: # %bb.0:
4774 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
4775 ; CHECK-RV64V-NEXT: ntl.s1
4776 ; CHECK-RV64V-NEXT: vle32.v v8, (a0)
4777 ; CHECK-RV64V-NEXT: ret
4778 ;
4779 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_v4i32:
4780 ; CHECK-RV32V: # %bb.0:
4781 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
4782 ; CHECK-RV32V-NEXT: ntl.s1
4783 ; CHECK-RV32V-NEXT: vle32.v v8, (a0)
4784 ; CHECK-RV32V-NEXT: ret
4785 %1 = load <4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4786 ret <4 x i32> %1
4787 }
4789 define <2 x i64> @test_nontemporal_S1_load_v2i64(ptr %p) {
4790 ; CHECK-RV64-LABEL: test_nontemporal_S1_load_v2i64:
4791 ; CHECK-RV64: # %bb.0:
4792 ; CHECK-RV64-NEXT: ntl.s1
4793 ; CHECK-RV64-NEXT: ld a2, 0(a0)
4794 ; CHECK-RV64-NEXT: ntl.s1
4795 ; CHECK-RV64-NEXT: ld a1, 8(a0)
4796 ; CHECK-RV64-NEXT: mv a0, a2
4797 ; CHECK-RV64-NEXT: ret
4798 ;
4799 ; CHECK-RV32-LABEL: test_nontemporal_S1_load_v2i64:
4800 ; CHECK-RV32: # %bb.0:
4801 ; CHECK-RV32-NEXT: ntl.s1
4802 ; CHECK-RV32-NEXT: lw a2, 12(a1)
4803 ; CHECK-RV32-NEXT: ntl.s1
4804 ; CHECK-RV32-NEXT: lw a3, 8(a1)
4805 ; CHECK-RV32-NEXT: ntl.s1
4806 ; CHECK-RV32-NEXT: lw a4, 4(a1)
4807 ; CHECK-RV32-NEXT: ntl.s1
4808 ; CHECK-RV32-NEXT: lw a1, 0(a1)
4809 ; CHECK-RV32-NEXT: sw a2, 12(a0)
4810 ; CHECK-RV32-NEXT: sw a3, 8(a0)
4811 ; CHECK-RV32-NEXT: sw a4, 4(a0)
4812 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4813 ; CHECK-RV32-NEXT: ret
4814 ;
4815 ; CHECK-RV64C-LABEL: test_nontemporal_S1_load_v2i64:
4816 ; CHECK-RV64C: # %bb.0:
4817 ; CHECK-RV64C-NEXT: c.ntl.s1
4818 ; CHECK-RV64C-NEXT: ld a2, 0(a0)
4819 ; CHECK-RV64C-NEXT: c.ntl.s1
4820 ; CHECK-RV64C-NEXT: ld a1, 8(a0)
4821 ; CHECK-RV64C-NEXT: mv a0, a2
4822 ; CHECK-RV64C-NEXT: ret
4823 ;
4824 ; CHECK-RV32C-LABEL: test_nontemporal_S1_load_v2i64:
4825 ; CHECK-RV32C: # %bb.0:
4826 ; CHECK-RV32C-NEXT: c.ntl.s1
4827 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
4828 ; CHECK-RV32C-NEXT: c.ntl.s1
4829 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
4830 ; CHECK-RV32C-NEXT: c.ntl.s1
4831 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
4832 ; CHECK-RV32C-NEXT: c.ntl.s1
4833 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
4834 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
4835 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
4836 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
4837 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4838 ; CHECK-RV32C-NEXT: ret
4839 ;
4840 ; CHECK-RV64V-LABEL: test_nontemporal_S1_load_v2i64:
4841 ; CHECK-RV64V: # %bb.0:
4842 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
4843 ; CHECK-RV64V-NEXT: ntl.s1
4844 ; CHECK-RV64V-NEXT: vle64.v v8, (a0)
4845 ; CHECK-RV64V-NEXT: ret
4846 ;
4847 ; CHECK-RV32V-LABEL: test_nontemporal_S1_load_v2i64:
4848 ; CHECK-RV32V: # %bb.0:
4849 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
4850 ; CHECK-RV32V-NEXT: ntl.s1
4851 ; CHECK-RV32V-NEXT: vle64.v v8, (a0)
4852 ; CHECK-RV32V-NEXT: ret
4853 %1 = load <2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4854 ret <2 x i64> %1
4855 }
4857 define void @test_nontemporal_S1_store_i64(ptr %p, i64 %v) {
4858 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_i64:
4859 ; CHECK-RV64: # %bb.0:
4860 ; CHECK-RV64-NEXT: ntl.s1
4861 ; CHECK-RV64-NEXT: sd a1, 0(a0)
4862 ; CHECK-RV64-NEXT: ret
4863 ;
4864 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_i64:
4865 ; CHECK-RV32: # %bb.0:
4866 ; CHECK-RV32-NEXT: ntl.s1
4867 ; CHECK-RV32-NEXT: sw a2, 4(a0)
4868 ; CHECK-RV32-NEXT: ntl.s1
4869 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4870 ; CHECK-RV32-NEXT: ret
4871 ;
4872 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_i64:
4873 ; CHECK-RV64C: # %bb.0:
4874 ; CHECK-RV64C-NEXT: c.ntl.s1
4875 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
4876 ; CHECK-RV64C-NEXT: ret
4877 ;
4878 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_i64:
4879 ; CHECK-RV32C: # %bb.0:
4880 ; CHECK-RV32C-NEXT: c.ntl.s1
4881 ; CHECK-RV32C-NEXT: sw a2, 4(a0)
4882 ; CHECK-RV32C-NEXT: c.ntl.s1
4883 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4884 ; CHECK-RV32C-NEXT: ret
4885 ;
4886 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_i64:
4887 ; CHECK-RV64V: # %bb.0:
4888 ; CHECK-RV64V-NEXT: ntl.s1
4889 ; CHECK-RV64V-NEXT: sd a1, 0(a0)
4890 ; CHECK-RV64V-NEXT: ret
4891 ;
4892 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_i64:
4893 ; CHECK-RV32V: # %bb.0:
4894 ; CHECK-RV32V-NEXT: ntl.s1
4895 ; CHECK-RV32V-NEXT: sw a2, 4(a0)
4896 ; CHECK-RV32V-NEXT: ntl.s1
4897 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
4898 ; CHECK-RV32V-NEXT: ret
4899 store i64 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4900 ret void
4901 }
4903 define void @test_nontemporal_S1_store_i32(ptr %p, i32 %v) {
4904 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_i32:
4905 ; CHECK-RV64: # %bb.0:
4906 ; CHECK-RV64-NEXT: ntl.s1
4907 ; CHECK-RV64-NEXT: sw a1, 0(a0)
4908 ; CHECK-RV64-NEXT: ret
4909 ;
4910 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_i32:
4911 ; CHECK-RV32: # %bb.0:
4912 ; CHECK-RV32-NEXT: ntl.s1
4913 ; CHECK-RV32-NEXT: sw a1, 0(a0)
4914 ; CHECK-RV32-NEXT: ret
4915 ;
4916 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_i32:
4917 ; CHECK-RV64C: # %bb.0:
4918 ; CHECK-RV64C-NEXT: c.ntl.s1
4919 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
4920 ; CHECK-RV64C-NEXT: ret
4921 ;
4922 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_i32:
4923 ; CHECK-RV32C: # %bb.0:
4924 ; CHECK-RV32C-NEXT: c.ntl.s1
4925 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
4926 ; CHECK-RV32C-NEXT: ret
4927 ;
4928 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_i32:
4929 ; CHECK-RV64V: # %bb.0:
4930 ; CHECK-RV64V-NEXT: ntl.s1
4931 ; CHECK-RV64V-NEXT: sw a1, 0(a0)
4932 ; CHECK-RV64V-NEXT: ret
4933 ;
4934 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_i32:
4935 ; CHECK-RV32V: # %bb.0:
4936 ; CHECK-RV32V-NEXT: ntl.s1
4937 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
4938 ; CHECK-RV32V-NEXT: ret
4939 store i32 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4940 ret void
4941 }
4943 define void @test_nontemporal_S1_store_i16(ptr %p, i16 %v) {
4944 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_i16:
4945 ; CHECK-RV64: # %bb.0:
4946 ; CHECK-RV64-NEXT: ntl.s1
4947 ; CHECK-RV64-NEXT: sh a1, 0(a0)
4948 ; CHECK-RV64-NEXT: ret
4949 ;
4950 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_i16:
4951 ; CHECK-RV32: # %bb.0:
4952 ; CHECK-RV32-NEXT: ntl.s1
4953 ; CHECK-RV32-NEXT: sh a1, 0(a0)
4954 ; CHECK-RV32-NEXT: ret
4955 ;
4956 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_i16:
4957 ; CHECK-RV64C: # %bb.0:
4958 ; CHECK-RV64C-NEXT: c.ntl.s1
4959 ; CHECK-RV64C-NEXT: sh a1, 0(a0)
4960 ; CHECK-RV64C-NEXT: ret
4961 ;
4962 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_i16:
4963 ; CHECK-RV32C: # %bb.0:
4964 ; CHECK-RV32C-NEXT: c.ntl.s1
4965 ; CHECK-RV32C-NEXT: sh a1, 0(a0)
4966 ; CHECK-RV32C-NEXT: ret
4967 ;
4968 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_i16:
4969 ; CHECK-RV64V: # %bb.0:
4970 ; CHECK-RV64V-NEXT: ntl.s1
4971 ; CHECK-RV64V-NEXT: sh a1, 0(a0)
4972 ; CHECK-RV64V-NEXT: ret
4973 ;
4974 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_i16:
4975 ; CHECK-RV32V: # %bb.0:
4976 ; CHECK-RV32V-NEXT: ntl.s1
4977 ; CHECK-RV32V-NEXT: sh a1, 0(a0)
4978 ; CHECK-RV32V-NEXT: ret
4979 store i16 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
4980 ret void
4981 }
4983 define void @test_nontemporal_S1_store_i8(ptr %p, i8 %v) {
4984 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_i8:
4985 ; CHECK-RV64: # %bb.0:
4986 ; CHECK-RV64-NEXT: ntl.s1
4987 ; CHECK-RV64-NEXT: sb a1, 0(a0)
4988 ; CHECK-RV64-NEXT: ret
4989 ;
4990 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_i8:
4991 ; CHECK-RV32: # %bb.0:
4992 ; CHECK-RV32-NEXT: ntl.s1
4993 ; CHECK-RV32-NEXT: sb a1, 0(a0)
4994 ; CHECK-RV32-NEXT: ret
4995 ;
4996 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_i8:
4997 ; CHECK-RV64C: # %bb.0:
4998 ; CHECK-RV64C-NEXT: c.ntl.s1
4999 ; CHECK-RV64C-NEXT: sb a1, 0(a0)
5000 ; CHECK-RV64C-NEXT: ret
5001 ;
5002 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_i8:
5003 ; CHECK-RV32C: # %bb.0:
5004 ; CHECK-RV32C-NEXT: c.ntl.s1
5005 ; CHECK-RV32C-NEXT: sb a1, 0(a0)
5006 ; CHECK-RV32C-NEXT: ret
5007 ;
5008 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_i8:
5009 ; CHECK-RV64V: # %bb.0:
5010 ; CHECK-RV64V-NEXT: ntl.s1
5011 ; CHECK-RV64V-NEXT: sb a1, 0(a0)
5012 ; CHECK-RV64V-NEXT: ret
5013 ;
5014 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_i8:
5015 ; CHECK-RV32V: # %bb.0:
5016 ; CHECK-RV32V-NEXT: ntl.s1
5017 ; CHECK-RV32V-NEXT: sb a1, 0(a0)
5018 ; CHECK-RV32V-NEXT: ret
5019 store i8 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5020 ret void
5021 }
5023 define void @test_nontemporal_S1_store_half(ptr %p, half %v) {
5024 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_half:
5025 ; CHECK-RV64: # %bb.0:
5026 ; CHECK-RV64-NEXT: ntl.s1
5027 ; CHECK-RV64-NEXT: fsh fa0, 0(a0)
5028 ; CHECK-RV64-NEXT: ret
5029 ;
5030 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_half:
5031 ; CHECK-RV32: # %bb.0:
5032 ; CHECK-RV32-NEXT: ntl.s1
5033 ; CHECK-RV32-NEXT: fsh fa0, 0(a0)
5034 ; CHECK-RV32-NEXT: ret
5035 ;
5036 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_half:
5037 ; CHECK-RV64C: # %bb.0:
5038 ; CHECK-RV64C-NEXT: c.ntl.s1
5039 ; CHECK-RV64C-NEXT: fsh fa0, 0(a0)
5040 ; CHECK-RV64C-NEXT: ret
5041 ;
5042 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_half:
5043 ; CHECK-RV32C: # %bb.0:
5044 ; CHECK-RV32C-NEXT: c.ntl.s1
5045 ; CHECK-RV32C-NEXT: fsh fa0, 0(a0)
5046 ; CHECK-RV32C-NEXT: ret
5047 ;
5048 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_half:
5049 ; CHECK-RV64V: # %bb.0:
5050 ; CHECK-RV64V-NEXT: ntl.s1
5051 ; CHECK-RV64V-NEXT: fsh fa0, 0(a0)
5052 ; CHECK-RV64V-NEXT: ret
5053 ;
5054 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_half:
5055 ; CHECK-RV32V: # %bb.0:
5056 ; CHECK-RV32V-NEXT: ntl.s1
5057 ; CHECK-RV32V-NEXT: fsh fa0, 0(a0)
5058 ; CHECK-RV32V-NEXT: ret
5059 store half %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5060 ret void
5061 }
5063 define void @test_nontemporal_S1_store_float(ptr %p, float %v) {
5064 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_float:
5065 ; CHECK-RV64: # %bb.0:
5066 ; CHECK-RV64-NEXT: ntl.s1
5067 ; CHECK-RV64-NEXT: fsw fa0, 0(a0)
5068 ; CHECK-RV64-NEXT: ret
5069 ;
5070 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_float:
5071 ; CHECK-RV32: # %bb.0:
5072 ; CHECK-RV32-NEXT: ntl.s1
5073 ; CHECK-RV32-NEXT: fsw fa0, 0(a0)
5074 ; CHECK-RV32-NEXT: ret
5075 ;
5076 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_float:
5077 ; CHECK-RV64C: # %bb.0:
5078 ; CHECK-RV64C-NEXT: c.ntl.s1
5079 ; CHECK-RV64C-NEXT: fsw fa0, 0(a0)
5080 ; CHECK-RV64C-NEXT: ret
5081 ;
5082 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_float:
5083 ; CHECK-RV32C: # %bb.0:
5084 ; CHECK-RV32C-NEXT: c.ntl.s1
5085 ; CHECK-RV32C-NEXT: fsw fa0, 0(a0)
5086 ; CHECK-RV32C-NEXT: ret
5087 ;
5088 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_float:
5089 ; CHECK-RV64V: # %bb.0:
5090 ; CHECK-RV64V-NEXT: ntl.s1
5091 ; CHECK-RV64V-NEXT: fsw fa0, 0(a0)
5092 ; CHECK-RV64V-NEXT: ret
5093 ;
5094 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_float:
5095 ; CHECK-RV32V: # %bb.0:
5096 ; CHECK-RV32V-NEXT: ntl.s1
5097 ; CHECK-RV32V-NEXT: fsw fa0, 0(a0)
5098 ; CHECK-RV32V-NEXT: ret
5099 store float %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5100 ret void
5101 }
5103 define void @test_nontemporal_S1_store_double(ptr %p, double %v) {
5104 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_double:
5105 ; CHECK-RV64: # %bb.0:
5106 ; CHECK-RV64-NEXT: ntl.s1
5107 ; CHECK-RV64-NEXT: fsd fa0, 0(a0)
5108 ; CHECK-RV64-NEXT: ret
5109 ;
5110 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_double:
5111 ; CHECK-RV32: # %bb.0:
5112 ; CHECK-RV32-NEXT: ntl.s1
5113 ; CHECK-RV32-NEXT: fsd fa0, 0(a0)
5114 ; CHECK-RV32-NEXT: ret
5115 ;
5116 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_double:
5117 ; CHECK-RV64C: # %bb.0:
5118 ; CHECK-RV64C-NEXT: c.ntl.s1
5119 ; CHECK-RV64C-NEXT: fsd fa0, 0(a0)
5120 ; CHECK-RV64C-NEXT: ret
5121 ;
5122 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_double:
5123 ; CHECK-RV32C: # %bb.0:
5124 ; CHECK-RV32C-NEXT: c.ntl.s1
5125 ; CHECK-RV32C-NEXT: fsd fa0, 0(a0)
5126 ; CHECK-RV32C-NEXT: ret
5127 ;
5128 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_double:
5129 ; CHECK-RV64V: # %bb.0:
5130 ; CHECK-RV64V-NEXT: ntl.s1
5131 ; CHECK-RV64V-NEXT: fsd fa0, 0(a0)
5132 ; CHECK-RV64V-NEXT: ret
5133 ;
5134 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_double:
5135 ; CHECK-RV32V: # %bb.0:
5136 ; CHECK-RV32V-NEXT: ntl.s1
5137 ; CHECK-RV32V-NEXT: fsd fa0, 0(a0)
5138 ; CHECK-RV32V-NEXT: ret
5139 store double %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5140 ret void
5141 }
5143 define void @test_nontemporal_S1_store_v16i8(ptr %p, <16 x i8> %v) {
5144 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_v16i8:
5145 ; CHECK-RV64: # %bb.0:
5146 ; CHECK-RV64-NEXT: addi sp, sp, -16
5147 ; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
5148 ; CHECK-RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
5149 ; CHECK-RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
5150 ; CHECK-RV64-NEXT: .cfi_offset s0, -8
5151 ; CHECK-RV64-NEXT: .cfi_offset s1, -16
5152 ; CHECK-RV64-NEXT: lbu a2, 0(a1)
5153 ; CHECK-RV64-NEXT: lbu a3, 8(a1)
5154 ; CHECK-RV64-NEXT: lbu a4, 16(a1)
5155 ; CHECK-RV64-NEXT: lbu a5, 24(a1)
5156 ; CHECK-RV64-NEXT: lbu a6, 32(a1)
5157 ; CHECK-RV64-NEXT: lbu a7, 40(a1)
5158 ; CHECK-RV64-NEXT: lbu t0, 48(a1)
5159 ; CHECK-RV64-NEXT: lbu t1, 56(a1)
5160 ; CHECK-RV64-NEXT: lbu t2, 64(a1)
5161 ; CHECK-RV64-NEXT: lbu t3, 72(a1)
5162 ; CHECK-RV64-NEXT: lbu t4, 80(a1)
5163 ; CHECK-RV64-NEXT: lbu t5, 88(a1)
5164 ; CHECK-RV64-NEXT: lbu t6, 120(a1)
5165 ; CHECK-RV64-NEXT: lbu s0, 112(a1)
5166 ; CHECK-RV64-NEXT: lbu s1, 104(a1)
5167 ; CHECK-RV64-NEXT: lbu a1, 96(a1)
5168 ; CHECK-RV64-NEXT: ntl.s1
5169 ; CHECK-RV64-NEXT: sb t6, 15(a0)
5170 ; CHECK-RV64-NEXT: ntl.s1
5171 ; CHECK-RV64-NEXT: sb s0, 14(a0)
5172 ; CHECK-RV64-NEXT: ntl.s1
5173 ; CHECK-RV64-NEXT: sb s1, 13(a0)
5174 ; CHECK-RV64-NEXT: ntl.s1
5175 ; CHECK-RV64-NEXT: sb a1, 12(a0)
5176 ; CHECK-RV64-NEXT: ntl.s1
5177 ; CHECK-RV64-NEXT: sb t5, 11(a0)
5178 ; CHECK-RV64-NEXT: ntl.s1
5179 ; CHECK-RV64-NEXT: sb t4, 10(a0)
5180 ; CHECK-RV64-NEXT: ntl.s1
5181 ; CHECK-RV64-NEXT: sb t3, 9(a0)
5182 ; CHECK-RV64-NEXT: ntl.s1
5183 ; CHECK-RV64-NEXT: sb t2, 8(a0)
5184 ; CHECK-RV64-NEXT: ntl.s1
5185 ; CHECK-RV64-NEXT: sb t1, 7(a0)
5186 ; CHECK-RV64-NEXT: ntl.s1
5187 ; CHECK-RV64-NEXT: sb t0, 6(a0)
5188 ; CHECK-RV64-NEXT: ntl.s1
5189 ; CHECK-RV64-NEXT: sb a7, 5(a0)
5190 ; CHECK-RV64-NEXT: ntl.s1
5191 ; CHECK-RV64-NEXT: sb a6, 4(a0)
5192 ; CHECK-RV64-NEXT: ntl.s1
5193 ; CHECK-RV64-NEXT: sb a5, 3(a0)
5194 ; CHECK-RV64-NEXT: ntl.s1
5195 ; CHECK-RV64-NEXT: sb a4, 2(a0)
5196 ; CHECK-RV64-NEXT: ntl.s1
5197 ; CHECK-RV64-NEXT: sb a3, 1(a0)
5198 ; CHECK-RV64-NEXT: ntl.s1
5199 ; CHECK-RV64-NEXT: sb a2, 0(a0)
5200 ; CHECK-RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
5201 ; CHECK-RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
5202 ; CHECK-RV64-NEXT: addi sp, sp, 16
5203 ; CHECK-RV64-NEXT: ret
5204 ;
5205 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_v16i8:
5206 ; CHECK-RV32: # %bb.0:
5207 ; CHECK-RV32-NEXT: addi sp, sp, -16
5208 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
5209 ; CHECK-RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
5210 ; CHECK-RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
5211 ; CHECK-RV32-NEXT: .cfi_offset s0, -4
5212 ; CHECK-RV32-NEXT: .cfi_offset s1, -8
5213 ; CHECK-RV32-NEXT: lbu a2, 0(a1)
5214 ; CHECK-RV32-NEXT: lbu a3, 4(a1)
5215 ; CHECK-RV32-NEXT: lbu a4, 8(a1)
5216 ; CHECK-RV32-NEXT: lbu a5, 12(a1)
5217 ; CHECK-RV32-NEXT: lbu a6, 16(a1)
5218 ; CHECK-RV32-NEXT: lbu a7, 20(a1)
5219 ; CHECK-RV32-NEXT: lbu t0, 24(a1)
5220 ; CHECK-RV32-NEXT: lbu t1, 28(a1)
5221 ; CHECK-RV32-NEXT: lbu t2, 32(a1)
5222 ; CHECK-RV32-NEXT: lbu t3, 36(a1)
5223 ; CHECK-RV32-NEXT: lbu t4, 40(a1)
5224 ; CHECK-RV32-NEXT: lbu t5, 44(a1)
5225 ; CHECK-RV32-NEXT: lbu t6, 60(a1)
5226 ; CHECK-RV32-NEXT: lbu s0, 56(a1)
5227 ; CHECK-RV32-NEXT: lbu s1, 52(a1)
5228 ; CHECK-RV32-NEXT: lbu a1, 48(a1)
5229 ; CHECK-RV32-NEXT: ntl.s1
5230 ; CHECK-RV32-NEXT: sb t6, 15(a0)
5231 ; CHECK-RV32-NEXT: ntl.s1
5232 ; CHECK-RV32-NEXT: sb s0, 14(a0)
5233 ; CHECK-RV32-NEXT: ntl.s1
5234 ; CHECK-RV32-NEXT: sb s1, 13(a0)
5235 ; CHECK-RV32-NEXT: ntl.s1
5236 ; CHECK-RV32-NEXT: sb a1, 12(a0)
5237 ; CHECK-RV32-NEXT: ntl.s1
5238 ; CHECK-RV32-NEXT: sb t5, 11(a0)
5239 ; CHECK-RV32-NEXT: ntl.s1
5240 ; CHECK-RV32-NEXT: sb t4, 10(a0)
5241 ; CHECK-RV32-NEXT: ntl.s1
5242 ; CHECK-RV32-NEXT: sb t3, 9(a0)
5243 ; CHECK-RV32-NEXT: ntl.s1
5244 ; CHECK-RV32-NEXT: sb t2, 8(a0)
5245 ; CHECK-RV32-NEXT: ntl.s1
5246 ; CHECK-RV32-NEXT: sb t1, 7(a0)
5247 ; CHECK-RV32-NEXT: ntl.s1
5248 ; CHECK-RV32-NEXT: sb t0, 6(a0)
5249 ; CHECK-RV32-NEXT: ntl.s1
5250 ; CHECK-RV32-NEXT: sb a7, 5(a0)
5251 ; CHECK-RV32-NEXT: ntl.s1
5252 ; CHECK-RV32-NEXT: sb a6, 4(a0)
5253 ; CHECK-RV32-NEXT: ntl.s1
5254 ; CHECK-RV32-NEXT: sb a5, 3(a0)
5255 ; CHECK-RV32-NEXT: ntl.s1
5256 ; CHECK-RV32-NEXT: sb a4, 2(a0)
5257 ; CHECK-RV32-NEXT: ntl.s1
5258 ; CHECK-RV32-NEXT: sb a3, 1(a0)
5259 ; CHECK-RV32-NEXT: ntl.s1
5260 ; CHECK-RV32-NEXT: sb a2, 0(a0)
5261 ; CHECK-RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
5262 ; CHECK-RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
5263 ; CHECK-RV32-NEXT: addi sp, sp, 16
5264 ; CHECK-RV32-NEXT: ret
5265 ;
5266 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_v16i8:
5267 ; CHECK-RV64C: # %bb.0:
5268 ; CHECK-RV64C-NEXT: addi sp, sp, -16
5269 ; CHECK-RV64C-NEXT: .cfi_def_cfa_offset 16
5270 ; CHECK-RV64C-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
5271 ; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
5272 ; CHECK-RV64C-NEXT: .cfi_offset s0, -8
5273 ; CHECK-RV64C-NEXT: .cfi_offset s1, -16
5274 ; CHECK-RV64C-NEXT: lbu a6, 0(a1)
5275 ; CHECK-RV64C-NEXT: lbu a7, 8(a1)
5276 ; CHECK-RV64C-NEXT: lbu t0, 16(a1)
5277 ; CHECK-RV64C-NEXT: lbu t1, 24(a1)
5278 ; CHECK-RV64C-NEXT: lbu t2, 32(a1)
5279 ; CHECK-RV64C-NEXT: lbu t3, 40(a1)
5280 ; CHECK-RV64C-NEXT: lbu t4, 48(a1)
5281 ; CHECK-RV64C-NEXT: lbu t5, 56(a1)
5282 ; CHECK-RV64C-NEXT: lbu t6, 64(a1)
5283 ; CHECK-RV64C-NEXT: lbu a3, 72(a1)
5284 ; CHECK-RV64C-NEXT: lbu a4, 80(a1)
5285 ; CHECK-RV64C-NEXT: lbu a5, 88(a1)
5286 ; CHECK-RV64C-NEXT: lbu a2, 120(a1)
5287 ; CHECK-RV64C-NEXT: lbu s0, 112(a1)
5288 ; CHECK-RV64C-NEXT: lbu s1, 104(a1)
5289 ; CHECK-RV64C-NEXT: lbu a1, 96(a1)
5290 ; CHECK-RV64C-NEXT: c.ntl.s1
5291 ; CHECK-RV64C-NEXT: sb a2, 15(a0)
5292 ; CHECK-RV64C-NEXT: c.ntl.s1
5293 ; CHECK-RV64C-NEXT: sb s0, 14(a0)
5294 ; CHECK-RV64C-NEXT: c.ntl.s1
5295 ; CHECK-RV64C-NEXT: sb s1, 13(a0)
5296 ; CHECK-RV64C-NEXT: c.ntl.s1
5297 ; CHECK-RV64C-NEXT: sb a1, 12(a0)
5298 ; CHECK-RV64C-NEXT: c.ntl.s1
5299 ; CHECK-RV64C-NEXT: sb a5, 11(a0)
5300 ; CHECK-RV64C-NEXT: c.ntl.s1
5301 ; CHECK-RV64C-NEXT: sb a4, 10(a0)
5302 ; CHECK-RV64C-NEXT: c.ntl.s1
5303 ; CHECK-RV64C-NEXT: sb a3, 9(a0)
5304 ; CHECK-RV64C-NEXT: c.ntl.s1
5305 ; CHECK-RV64C-NEXT: sb t6, 8(a0)
5306 ; CHECK-RV64C-NEXT: c.ntl.s1
5307 ; CHECK-RV64C-NEXT: sb t5, 7(a0)
5308 ; CHECK-RV64C-NEXT: c.ntl.s1
5309 ; CHECK-RV64C-NEXT: sb t4, 6(a0)
5310 ; CHECK-RV64C-NEXT: c.ntl.s1
5311 ; CHECK-RV64C-NEXT: sb t3, 5(a0)
5312 ; CHECK-RV64C-NEXT: c.ntl.s1
5313 ; CHECK-RV64C-NEXT: sb t2, 4(a0)
5314 ; CHECK-RV64C-NEXT: c.ntl.s1
5315 ; CHECK-RV64C-NEXT: sb t1, 3(a0)
5316 ; CHECK-RV64C-NEXT: c.ntl.s1
5317 ; CHECK-RV64C-NEXT: sb t0, 2(a0)
5318 ; CHECK-RV64C-NEXT: c.ntl.s1
5319 ; CHECK-RV64C-NEXT: sb a7, 1(a0)
5320 ; CHECK-RV64C-NEXT: c.ntl.s1
5321 ; CHECK-RV64C-NEXT: sb a6, 0(a0)
5322 ; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
5323 ; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
5324 ; CHECK-RV64C-NEXT: addi sp, sp, 16
5325 ; CHECK-RV64C-NEXT: ret
5326 ;
5327 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_v16i8:
5328 ; CHECK-RV32C: # %bb.0:
5329 ; CHECK-RV32C-NEXT: addi sp, sp, -16
5330 ; CHECK-RV32C-NEXT: .cfi_def_cfa_offset 16
5331 ; CHECK-RV32C-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
5332 ; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
5333 ; CHECK-RV32C-NEXT: .cfi_offset s0, -4
5334 ; CHECK-RV32C-NEXT: .cfi_offset s1, -8
5335 ; CHECK-RV32C-NEXT: lbu a6, 0(a1)
5336 ; CHECK-RV32C-NEXT: lbu a7, 4(a1)
5337 ; CHECK-RV32C-NEXT: lbu t0, 8(a1)
5338 ; CHECK-RV32C-NEXT: lbu t1, 12(a1)
5339 ; CHECK-RV32C-NEXT: lbu t2, 16(a1)
5340 ; CHECK-RV32C-NEXT: lbu t3, 20(a1)
5341 ; CHECK-RV32C-NEXT: lbu t4, 24(a1)
5342 ; CHECK-RV32C-NEXT: lbu t5, 28(a1)
5343 ; CHECK-RV32C-NEXT: lbu t6, 32(a1)
5344 ; CHECK-RV32C-NEXT: lbu a3, 36(a1)
5345 ; CHECK-RV32C-NEXT: lbu a4, 40(a1)
5346 ; CHECK-RV32C-NEXT: lbu a5, 44(a1)
5347 ; CHECK-RV32C-NEXT: lbu a2, 60(a1)
5348 ; CHECK-RV32C-NEXT: lbu s0, 56(a1)
5349 ; CHECK-RV32C-NEXT: lbu s1, 52(a1)
5350 ; CHECK-RV32C-NEXT: lbu a1, 48(a1)
5351 ; CHECK-RV32C-NEXT: c.ntl.s1
5352 ; CHECK-RV32C-NEXT: sb a2, 15(a0)
5353 ; CHECK-RV32C-NEXT: c.ntl.s1
5354 ; CHECK-RV32C-NEXT: sb s0, 14(a0)
5355 ; CHECK-RV32C-NEXT: c.ntl.s1
5356 ; CHECK-RV32C-NEXT: sb s1, 13(a0)
5357 ; CHECK-RV32C-NEXT: c.ntl.s1
5358 ; CHECK-RV32C-NEXT: sb a1, 12(a0)
5359 ; CHECK-RV32C-NEXT: c.ntl.s1
5360 ; CHECK-RV32C-NEXT: sb a5, 11(a0)
5361 ; CHECK-RV32C-NEXT: c.ntl.s1
5362 ; CHECK-RV32C-NEXT: sb a4, 10(a0)
5363 ; CHECK-RV32C-NEXT: c.ntl.s1
5364 ; CHECK-RV32C-NEXT: sb a3, 9(a0)
5365 ; CHECK-RV32C-NEXT: c.ntl.s1
5366 ; CHECK-RV32C-NEXT: sb t6, 8(a0)
5367 ; CHECK-RV32C-NEXT: c.ntl.s1
5368 ; CHECK-RV32C-NEXT: sb t5, 7(a0)
5369 ; CHECK-RV32C-NEXT: c.ntl.s1
5370 ; CHECK-RV32C-NEXT: sb t4, 6(a0)
5371 ; CHECK-RV32C-NEXT: c.ntl.s1
5372 ; CHECK-RV32C-NEXT: sb t3, 5(a0)
5373 ; CHECK-RV32C-NEXT: c.ntl.s1
5374 ; CHECK-RV32C-NEXT: sb t2, 4(a0)
5375 ; CHECK-RV32C-NEXT: c.ntl.s1
5376 ; CHECK-RV32C-NEXT: sb t1, 3(a0)
5377 ; CHECK-RV32C-NEXT: c.ntl.s1
5378 ; CHECK-RV32C-NEXT: sb t0, 2(a0)
5379 ; CHECK-RV32C-NEXT: c.ntl.s1
5380 ; CHECK-RV32C-NEXT: sb a7, 1(a0)
5381 ; CHECK-RV32C-NEXT: c.ntl.s1
5382 ; CHECK-RV32C-NEXT: sb a6, 0(a0)
5383 ; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
5384 ; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
5385 ; CHECK-RV32C-NEXT: addi sp, sp, 16
5386 ; CHECK-RV32C-NEXT: ret
5387 ;
5388 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_v16i8:
5389 ; CHECK-RV64V: # %bb.0:
5390 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
5391 ; CHECK-RV64V-NEXT: ntl.s1
5392 ; CHECK-RV64V-NEXT: vse8.v v8, (a0)
5393 ; CHECK-RV64V-NEXT: ret
5394 ;
5395 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_v16i8:
5396 ; CHECK-RV32V: # %bb.0:
5397 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
5398 ; CHECK-RV32V-NEXT: ntl.s1
5399 ; CHECK-RV32V-NEXT: vse8.v v8, (a0)
5400 ; CHECK-RV32V-NEXT: ret
5401 store <16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5402 ret void
5403 }
5405 define void @test_nontemporal_S1_store_v8i16(ptr %p, <8 x i16> %v) {
5406 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_v8i16:
5407 ; CHECK-RV64: # %bb.0:
5408 ; CHECK-RV64-NEXT: lh a2, 0(a1)
5409 ; CHECK-RV64-NEXT: lh a3, 8(a1)
5410 ; CHECK-RV64-NEXT: lh a4, 16(a1)
5411 ; CHECK-RV64-NEXT: lh a5, 24(a1)
5412 ; CHECK-RV64-NEXT: lh a6, 56(a1)
5413 ; CHECK-RV64-NEXT: lh a7, 48(a1)
5414 ; CHECK-RV64-NEXT: lh t0, 40(a1)
5415 ; CHECK-RV64-NEXT: lh a1, 32(a1)
5416 ; CHECK-RV64-NEXT: ntl.s1
5417 ; CHECK-RV64-NEXT: sh a6, 14(a0)
5418 ; CHECK-RV64-NEXT: ntl.s1
5419 ; CHECK-RV64-NEXT: sh a7, 12(a0)
5420 ; CHECK-RV64-NEXT: ntl.s1
5421 ; CHECK-RV64-NEXT: sh t0, 10(a0)
5422 ; CHECK-RV64-NEXT: ntl.s1
5423 ; CHECK-RV64-NEXT: sh a1, 8(a0)
5424 ; CHECK-RV64-NEXT: ntl.s1
5425 ; CHECK-RV64-NEXT: sh a5, 6(a0)
5426 ; CHECK-RV64-NEXT: ntl.s1
5427 ; CHECK-RV64-NEXT: sh a4, 4(a0)
5428 ; CHECK-RV64-NEXT: ntl.s1
5429 ; CHECK-RV64-NEXT: sh a3, 2(a0)
5430 ; CHECK-RV64-NEXT: ntl.s1
5431 ; CHECK-RV64-NEXT: sh a2, 0(a0)
5432 ; CHECK-RV64-NEXT: ret
5433 ;
5434 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_v8i16:
5435 ; CHECK-RV32: # %bb.0:
5436 ; CHECK-RV32-NEXT: lh a2, 0(a1)
5437 ; CHECK-RV32-NEXT: lh a3, 4(a1)
5438 ; CHECK-RV32-NEXT: lh a4, 8(a1)
5439 ; CHECK-RV32-NEXT: lh a5, 12(a1)
5440 ; CHECK-RV32-NEXT: lh a6, 28(a1)
5441 ; CHECK-RV32-NEXT: lh a7, 24(a1)
5442 ; CHECK-RV32-NEXT: lh t0, 20(a1)
5443 ; CHECK-RV32-NEXT: lh a1, 16(a1)
5444 ; CHECK-RV32-NEXT: ntl.s1
5445 ; CHECK-RV32-NEXT: sh a6, 14(a0)
5446 ; CHECK-RV32-NEXT: ntl.s1
5447 ; CHECK-RV32-NEXT: sh a7, 12(a0)
5448 ; CHECK-RV32-NEXT: ntl.s1
5449 ; CHECK-RV32-NEXT: sh t0, 10(a0)
5450 ; CHECK-RV32-NEXT: ntl.s1
5451 ; CHECK-RV32-NEXT: sh a1, 8(a0)
5452 ; CHECK-RV32-NEXT: ntl.s1
5453 ; CHECK-RV32-NEXT: sh a5, 6(a0)
5454 ; CHECK-RV32-NEXT: ntl.s1
5455 ; CHECK-RV32-NEXT: sh a4, 4(a0)
5456 ; CHECK-RV32-NEXT: ntl.s1
5457 ; CHECK-RV32-NEXT: sh a3, 2(a0)
5458 ; CHECK-RV32-NEXT: ntl.s1
5459 ; CHECK-RV32-NEXT: sh a2, 0(a0)
5460 ; CHECK-RV32-NEXT: ret
5461 ;
5462 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_v8i16:
5463 ; CHECK-RV64C: # %bb.0:
5464 ; CHECK-RV64C-NEXT: lh a6, 0(a1)
5465 ; CHECK-RV64C-NEXT: lh a7, 8(a1)
5466 ; CHECK-RV64C-NEXT: lh t0, 16(a1)
5467 ; CHECK-RV64C-NEXT: lh a5, 24(a1)
5468 ; CHECK-RV64C-NEXT: lh a2, 56(a1)
5469 ; CHECK-RV64C-NEXT: lh a3, 48(a1)
5470 ; CHECK-RV64C-NEXT: lh a4, 40(a1)
5471 ; CHECK-RV64C-NEXT: lh a1, 32(a1)
5472 ; CHECK-RV64C-NEXT: c.ntl.s1
5473 ; CHECK-RV64C-NEXT: sh a2, 14(a0)
5474 ; CHECK-RV64C-NEXT: c.ntl.s1
5475 ; CHECK-RV64C-NEXT: sh a3, 12(a0)
5476 ; CHECK-RV64C-NEXT: c.ntl.s1
5477 ; CHECK-RV64C-NEXT: sh a4, 10(a0)
5478 ; CHECK-RV64C-NEXT: c.ntl.s1
5479 ; CHECK-RV64C-NEXT: sh a1, 8(a0)
5480 ; CHECK-RV64C-NEXT: c.ntl.s1
5481 ; CHECK-RV64C-NEXT: sh a5, 6(a0)
5482 ; CHECK-RV64C-NEXT: c.ntl.s1
5483 ; CHECK-RV64C-NEXT: sh t0, 4(a0)
5484 ; CHECK-RV64C-NEXT: c.ntl.s1
5485 ; CHECK-RV64C-NEXT: sh a7, 2(a0)
5486 ; CHECK-RV64C-NEXT: c.ntl.s1
5487 ; CHECK-RV64C-NEXT: sh a6, 0(a0)
5488 ; CHECK-RV64C-NEXT: ret
5489 ;
5490 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_v8i16:
5491 ; CHECK-RV32C: # %bb.0:
5492 ; CHECK-RV32C-NEXT: lh a6, 0(a1)
5493 ; CHECK-RV32C-NEXT: lh a7, 4(a1)
5494 ; CHECK-RV32C-NEXT: lh t0, 8(a1)
5495 ; CHECK-RV32C-NEXT: lh a5, 12(a1)
5496 ; CHECK-RV32C-NEXT: lh a2, 28(a1)
5497 ; CHECK-RV32C-NEXT: lh a3, 24(a1)
5498 ; CHECK-RV32C-NEXT: lh a4, 20(a1)
5499 ; CHECK-RV32C-NEXT: lh a1, 16(a1)
5500 ; CHECK-RV32C-NEXT: c.ntl.s1
5501 ; CHECK-RV32C-NEXT: sh a2, 14(a0)
5502 ; CHECK-RV32C-NEXT: c.ntl.s1
5503 ; CHECK-RV32C-NEXT: sh a3, 12(a0)
5504 ; CHECK-RV32C-NEXT: c.ntl.s1
5505 ; CHECK-RV32C-NEXT: sh a4, 10(a0)
5506 ; CHECK-RV32C-NEXT: c.ntl.s1
5507 ; CHECK-RV32C-NEXT: sh a1, 8(a0)
5508 ; CHECK-RV32C-NEXT: c.ntl.s1
5509 ; CHECK-RV32C-NEXT: sh a5, 6(a0)
5510 ; CHECK-RV32C-NEXT: c.ntl.s1
5511 ; CHECK-RV32C-NEXT: sh t0, 4(a0)
5512 ; CHECK-RV32C-NEXT: c.ntl.s1
5513 ; CHECK-RV32C-NEXT: sh a7, 2(a0)
5514 ; CHECK-RV32C-NEXT: c.ntl.s1
5515 ; CHECK-RV32C-NEXT: sh a6, 0(a0)
5516 ; CHECK-RV32C-NEXT: ret
5517 ;
5518 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_v8i16:
5519 ; CHECK-RV64V: # %bb.0:
5520 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5521 ; CHECK-RV64V-NEXT: ntl.s1
5522 ; CHECK-RV64V-NEXT: vse16.v v8, (a0)
5523 ; CHECK-RV64V-NEXT: ret
5524 ;
5525 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_v8i16:
5526 ; CHECK-RV32V: # %bb.0:
5527 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5528 ; CHECK-RV32V-NEXT: ntl.s1
5529 ; CHECK-RV32V-NEXT: vse16.v v8, (a0)
5530 ; CHECK-RV32V-NEXT: ret
5531 store <8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5532 ret void
5533 }
5535 define void @test_nontemporal_S1_store_v4i32(ptr %p, <4 x i32> %v) {
5536 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_v4i32:
5537 ; CHECK-RV64: # %bb.0:
5538 ; CHECK-RV64-NEXT: lw a2, 24(a1)
5539 ; CHECK-RV64-NEXT: lw a3, 16(a1)
5540 ; CHECK-RV64-NEXT: lw a4, 8(a1)
5541 ; CHECK-RV64-NEXT: lw a1, 0(a1)
5542 ; CHECK-RV64-NEXT: ntl.s1
5543 ; CHECK-RV64-NEXT: sw a2, 12(a0)
5544 ; CHECK-RV64-NEXT: ntl.s1
5545 ; CHECK-RV64-NEXT: sw a3, 8(a0)
5546 ; CHECK-RV64-NEXT: ntl.s1
5547 ; CHECK-RV64-NEXT: sw a4, 4(a0)
5548 ; CHECK-RV64-NEXT: ntl.s1
5549 ; CHECK-RV64-NEXT: sw a1, 0(a0)
5550 ; CHECK-RV64-NEXT: ret
5551 ;
5552 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_v4i32:
5553 ; CHECK-RV32: # %bb.0:
5554 ; CHECK-RV32-NEXT: lw a2, 12(a1)
5555 ; CHECK-RV32-NEXT: lw a3, 8(a1)
5556 ; CHECK-RV32-NEXT: lw a4, 4(a1)
5557 ; CHECK-RV32-NEXT: lw a1, 0(a1)
5558 ; CHECK-RV32-NEXT: ntl.s1
5559 ; CHECK-RV32-NEXT: sw a2, 12(a0)
5560 ; CHECK-RV32-NEXT: ntl.s1
5561 ; CHECK-RV32-NEXT: sw a3, 8(a0)
5562 ; CHECK-RV32-NEXT: ntl.s1
5563 ; CHECK-RV32-NEXT: sw a4, 4(a0)
5564 ; CHECK-RV32-NEXT: ntl.s1
5565 ; CHECK-RV32-NEXT: sw a1, 0(a0)
5566 ; CHECK-RV32-NEXT: ret
5567 ;
5568 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_v4i32:
5569 ; CHECK-RV64C: # %bb.0:
5570 ; CHECK-RV64C-NEXT: lw a2, 24(a1)
5571 ; CHECK-RV64C-NEXT: lw a3, 16(a1)
5572 ; CHECK-RV64C-NEXT: lw a4, 8(a1)
5573 ; CHECK-RV64C-NEXT: lw a1, 0(a1)
5574 ; CHECK-RV64C-NEXT: c.ntl.s1
5575 ; CHECK-RV64C-NEXT: sw a2, 12(a0)
5576 ; CHECK-RV64C-NEXT: c.ntl.s1
5577 ; CHECK-RV64C-NEXT: sw a3, 8(a0)
5578 ; CHECK-RV64C-NEXT: c.ntl.s1
5579 ; CHECK-RV64C-NEXT: sw a4, 4(a0)
5580 ; CHECK-RV64C-NEXT: c.ntl.s1
5581 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
5582 ; CHECK-RV64C-NEXT: ret
5583 ;
5584 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_v4i32:
5585 ; CHECK-RV32C: # %bb.0:
5586 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
5587 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
5588 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
5589 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
5590 ; CHECK-RV32C-NEXT: c.ntl.s1
5591 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
5592 ; CHECK-RV32C-NEXT: c.ntl.s1
5593 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
5594 ; CHECK-RV32C-NEXT: c.ntl.s1
5595 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
5596 ; CHECK-RV32C-NEXT: c.ntl.s1
5597 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
5598 ; CHECK-RV32C-NEXT: ret
5599 ;
5600 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_v4i32:
5601 ; CHECK-RV64V: # %bb.0:
5602 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5603 ; CHECK-RV64V-NEXT: ntl.s1
5604 ; CHECK-RV64V-NEXT: vse32.v v8, (a0)
5605 ; CHECK-RV64V-NEXT: ret
5606 ;
5607 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_v4i32:
5608 ; CHECK-RV32V: # %bb.0:
5609 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5610 ; CHECK-RV32V-NEXT: ntl.s1
5611 ; CHECK-RV32V-NEXT: vse32.v v8, (a0)
5612 ; CHECK-RV32V-NEXT: ret
5613 store <4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5614 ret void
5615 }
5617 define void @test_nontemporal_S1_store_v2i64(ptr %p, <2 x i64> %v) {
5618 ; CHECK-RV64-LABEL: test_nontemporal_S1_store_v2i64:
5619 ; CHECK-RV64: # %bb.0:
5620 ; CHECK-RV64-NEXT: ntl.s1
5621 ; CHECK-RV64-NEXT: sd a2, 8(a0)
5622 ; CHECK-RV64-NEXT: ntl.s1
5623 ; CHECK-RV64-NEXT: sd a1, 0(a0)
5624 ; CHECK-RV64-NEXT: ret
5625 ;
5626 ; CHECK-RV32-LABEL: test_nontemporal_S1_store_v2i64:
5627 ; CHECK-RV32: # %bb.0:
5628 ; CHECK-RV32-NEXT: lw a2, 12(a1)
5629 ; CHECK-RV32-NEXT: lw a3, 8(a1)
5630 ; CHECK-RV32-NEXT: lw a4, 4(a1)
5631 ; CHECK-RV32-NEXT: lw a1, 0(a1)
5632 ; CHECK-RV32-NEXT: ntl.s1
5633 ; CHECK-RV32-NEXT: sw a2, 12(a0)
5634 ; CHECK-RV32-NEXT: ntl.s1
5635 ; CHECK-RV32-NEXT: sw a3, 8(a0)
5636 ; CHECK-RV32-NEXT: ntl.s1
5637 ; CHECK-RV32-NEXT: sw a4, 4(a0)
5638 ; CHECK-RV32-NEXT: ntl.s1
5639 ; CHECK-RV32-NEXT: sw a1, 0(a0)
5640 ; CHECK-RV32-NEXT: ret
5641 ;
5642 ; CHECK-RV64C-LABEL: test_nontemporal_S1_store_v2i64:
5643 ; CHECK-RV64C: # %bb.0:
5644 ; CHECK-RV64C-NEXT: c.ntl.s1
5645 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
5646 ; CHECK-RV64C-NEXT: c.ntl.s1
5647 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
5648 ; CHECK-RV64C-NEXT: ret
5649 ;
5650 ; CHECK-RV32C-LABEL: test_nontemporal_S1_store_v2i64:
5651 ; CHECK-RV32C: # %bb.0:
5652 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
5653 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
5654 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
5655 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
5656 ; CHECK-RV32C-NEXT: c.ntl.s1
5657 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
5658 ; CHECK-RV32C-NEXT: c.ntl.s1
5659 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
5660 ; CHECK-RV32C-NEXT: c.ntl.s1
5661 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
5662 ; CHECK-RV32C-NEXT: c.ntl.s1
5663 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
5664 ; CHECK-RV32C-NEXT: ret
5665 ;
5666 ; CHECK-RV64V-LABEL: test_nontemporal_S1_store_v2i64:
5667 ; CHECK-RV64V: # %bb.0:
5668 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5669 ; CHECK-RV64V-NEXT: ntl.s1
5670 ; CHECK-RV64V-NEXT: vse64.v v8, (a0)
5671 ; CHECK-RV64V-NEXT: ret
5672 ;
5673 ; CHECK-RV32V-LABEL: test_nontemporal_S1_store_v2i64:
5674 ; CHECK-RV32V: # %bb.0:
5675 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5676 ; CHECK-RV32V-NEXT: ntl.s1
5677 ; CHECK-RV32V-NEXT: vse64.v v8, (a0)
5678 ; CHECK-RV32V-NEXT: ret
5679 store <2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !3
5680 ret void
5681 }
5683 define i64 @test_nontemporal_ALL_load_i64(ptr %p) {
5684 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_i64:
5685 ; CHECK-RV64: # %bb.0:
5686 ; CHECK-RV64-NEXT: ntl.all
5687 ; CHECK-RV64-NEXT: ld a0, 0(a0)
5688 ; CHECK-RV64-NEXT: ret
5689 ;
5690 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_i64:
5691 ; CHECK-RV32: # %bb.0:
5692 ; CHECK-RV32-NEXT: ntl.all
5693 ; CHECK-RV32-NEXT: lw a2, 0(a0)
5694 ; CHECK-RV32-NEXT: ntl.all
5695 ; CHECK-RV32-NEXT: lw a1, 4(a0)
5696 ; CHECK-RV32-NEXT: mv a0, a2
5697 ; CHECK-RV32-NEXT: ret
5698 ;
5699 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_i64:
5700 ; CHECK-RV64C: # %bb.0:
5701 ; CHECK-RV64C-NEXT: c.ntl.all
5702 ; CHECK-RV64C-NEXT: ld a0, 0(a0)
5703 ; CHECK-RV64C-NEXT: ret
5704 ;
5705 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_i64:
5706 ; CHECK-RV32C: # %bb.0:
5707 ; CHECK-RV32C-NEXT: c.ntl.all
5708 ; CHECK-RV32C-NEXT: lw a2, 0(a0)
5709 ; CHECK-RV32C-NEXT: c.ntl.all
5710 ; CHECK-RV32C-NEXT: lw a1, 4(a0)
5711 ; CHECK-RV32C-NEXT: mv a0, a2
5712 ; CHECK-RV32C-NEXT: ret
5713 ;
5714 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_i64:
5715 ; CHECK-RV64V: # %bb.0:
5716 ; CHECK-RV64V-NEXT: ntl.all
5717 ; CHECK-RV64V-NEXT: ld a0, 0(a0)
5718 ; CHECK-RV64V-NEXT: ret
5719 ;
5720 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_i64:
5721 ; CHECK-RV32V: # %bb.0:
5722 ; CHECK-RV32V-NEXT: ntl.all
5723 ; CHECK-RV32V-NEXT: lw a2, 0(a0)
5724 ; CHECK-RV32V-NEXT: ntl.all
5725 ; CHECK-RV32V-NEXT: lw a1, 4(a0)
5726 ; CHECK-RV32V-NEXT: mv a0, a2
5727 ; CHECK-RV32V-NEXT: ret
5728 %1 = load i64, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
5729 ret i64 %1
5730 }
5732 define i32 @test_nontemporal_ALL_load_i32(ptr %p) {
5733 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_i32:
5734 ; CHECK-RV64: # %bb.0:
5735 ; CHECK-RV64-NEXT: ntl.all
5736 ; CHECK-RV64-NEXT: lw a0, 0(a0)
5737 ; CHECK-RV64-NEXT: ret
5738 ;
5739 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_i32:
5740 ; CHECK-RV32: # %bb.0:
5741 ; CHECK-RV32-NEXT: ntl.all
5742 ; CHECK-RV32-NEXT: lw a0, 0(a0)
5743 ; CHECK-RV32-NEXT: ret
5744 ;
5745 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_i32:
5746 ; CHECK-RV64C: # %bb.0:
5747 ; CHECK-RV64C-NEXT: c.ntl.all
5748 ; CHECK-RV64C-NEXT: lw a0, 0(a0)
5749 ; CHECK-RV64C-NEXT: ret
5750 ;
5751 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_i32:
5752 ; CHECK-RV32C: # %bb.0:
5753 ; CHECK-RV32C-NEXT: c.ntl.all
5754 ; CHECK-RV32C-NEXT: lw a0, 0(a0)
5755 ; CHECK-RV32C-NEXT: ret
5756 ;
5757 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_i32:
5758 ; CHECK-RV64V: # %bb.0:
5759 ; CHECK-RV64V-NEXT: ntl.all
5760 ; CHECK-RV64V-NEXT: lw a0, 0(a0)
5761 ; CHECK-RV64V-NEXT: ret
5762 ;
5763 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_i32:
5764 ; CHECK-RV32V: # %bb.0:
5765 ; CHECK-RV32V-NEXT: ntl.all
5766 ; CHECK-RV32V-NEXT: lw a0, 0(a0)
5767 ; CHECK-RV32V-NEXT: ret
5768 %1 = load i32, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
5769 ret i32 %1
5770 }
5772 define i16 @test_nontemporal_ALL_load_i16(ptr %p) {
5773 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_i16:
5774 ; CHECK-RV64: # %bb.0:
5775 ; CHECK-RV64-NEXT: ntl.all
5776 ; CHECK-RV64-NEXT: lh a0, 0(a0)
5777 ; CHECK-RV64-NEXT: ret
5778 ;
5779 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_i16:
5780 ; CHECK-RV32: # %bb.0:
5781 ; CHECK-RV32-NEXT: ntl.all
5782 ; CHECK-RV32-NEXT: lh a0, 0(a0)
5783 ; CHECK-RV32-NEXT: ret
5784 ;
5785 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_i16:
5786 ; CHECK-RV64C: # %bb.0:
5787 ; CHECK-RV64C-NEXT: c.ntl.all
5788 ; CHECK-RV64C-NEXT: lh a0, 0(a0)
5789 ; CHECK-RV64C-NEXT: ret
5790 ;
5791 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_i16:
5792 ; CHECK-RV32C: # %bb.0:
5793 ; CHECK-RV32C-NEXT: c.ntl.all
5794 ; CHECK-RV32C-NEXT: lh a0, 0(a0)
5795 ; CHECK-RV32C-NEXT: ret
5796 ;
5797 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_i16:
5798 ; CHECK-RV64V: # %bb.0:
5799 ; CHECK-RV64V-NEXT: ntl.all
5800 ; CHECK-RV64V-NEXT: lh a0, 0(a0)
5801 ; CHECK-RV64V-NEXT: ret
5802 ;
5803 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_i16:
5804 ; CHECK-RV32V: # %bb.0:
5805 ; CHECK-RV32V-NEXT: ntl.all
5806 ; CHECK-RV32V-NEXT: lh a0, 0(a0)
5807 ; CHECK-RV32V-NEXT: ret
5808 %1 = load i16, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
5809 ret i16 %1
5810 }
5812 define i8 @test_nontemporal_ALL_load_i8(ptr %p) {
5813 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_i8:
5814 ; CHECK-RV64: # %bb.0:
5815 ; CHECK-RV64-NEXT: ntl.all
5816 ; CHECK-RV64-NEXT: lbu a0, 0(a0)
5817 ; CHECK-RV64-NEXT: ret
5818 ;
5819 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_i8:
5820 ; CHECK-RV32: # %bb.0:
5821 ; CHECK-RV32-NEXT: ntl.all
5822 ; CHECK-RV32-NEXT: lbu a0, 0(a0)
5823 ; CHECK-RV32-NEXT: ret
5824 ;
5825 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_i8:
5826 ; CHECK-RV64C: # %bb.0:
5827 ; CHECK-RV64C-NEXT: c.ntl.all
5828 ; CHECK-RV64C-NEXT: lbu a0, 0(a0)
5829 ; CHECK-RV64C-NEXT: ret
5830 ;
5831 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_i8:
5832 ; CHECK-RV32C: # %bb.0:
5833 ; CHECK-RV32C-NEXT: c.ntl.all
5834 ; CHECK-RV32C-NEXT: lbu a0, 0(a0)
5835 ; CHECK-RV32C-NEXT: ret
5836 ;
5837 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_i8:
5838 ; CHECK-RV64V: # %bb.0:
5839 ; CHECK-RV64V-NEXT: ntl.all
5840 ; CHECK-RV64V-NEXT: lbu a0, 0(a0)
5841 ; CHECK-RV64V-NEXT: ret
5842 ;
5843 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_i8:
5844 ; CHECK-RV32V: # %bb.0:
5845 ; CHECK-RV32V-NEXT: ntl.all
5846 ; CHECK-RV32V-NEXT: lbu a0, 0(a0)
5847 ; CHECK-RV32V-NEXT: ret
5848 %1 = load i8, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
5849 ret i8 %1
5850 }
5852 define half @test_nontemporal_ALL_load_half(ptr %p) nounwind {
5853 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_half:
5854 ; CHECK-RV64: # %bb.0:
5855 ; CHECK-RV64-NEXT: ntl.all
5856 ; CHECK-RV64-NEXT: flh fa5, 0(a0)
5857 ; CHECK-RV64-NEXT: ntl.all
5858 ; CHECK-RV64-NEXT: flh fa4, 6(a0)
5859 ; CHECK-RV64-NEXT: fadd.h fa0, fa5, fa4
5860 ; CHECK-RV64-NEXT: ret
5861 ;
5862 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_half:
5863 ; CHECK-RV32: # %bb.0:
5864 ; CHECK-RV32-NEXT: ntl.all
5865 ; CHECK-RV32-NEXT: flh fa5, 0(a0)
5866 ; CHECK-RV32-NEXT: ntl.all
5867 ; CHECK-RV32-NEXT: flh fa4, 6(a0)
5868 ; CHECK-RV32-NEXT: fadd.h fa0, fa5, fa4
5869 ; CHECK-RV32-NEXT: ret
5870 ;
5871 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_half:
5872 ; CHECK-RV64C: # %bb.0:
5873 ; CHECK-RV64C-NEXT: c.ntl.all
5874 ; CHECK-RV64C-NEXT: flh fa5, 0(a0)
5875 ; CHECK-RV64C-NEXT: c.ntl.all
5876 ; CHECK-RV64C-NEXT: flh fa4, 6(a0)
5877 ; CHECK-RV64C-NEXT: fadd.h fa0, fa5, fa4
5878 ; CHECK-RV64C-NEXT: ret
5879 ;
5880 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_half:
5881 ; CHECK-RV32C: # %bb.0:
5882 ; CHECK-RV32C-NEXT: c.ntl.all
5883 ; CHECK-RV32C-NEXT: flh fa5, 0(a0)
5884 ; CHECK-RV32C-NEXT: c.ntl.all
5885 ; CHECK-RV32C-NEXT: flh fa4, 6(a0)
5886 ; CHECK-RV32C-NEXT: fadd.h fa0, fa5, fa4
5887 ; CHECK-RV32C-NEXT: ret
5888 ;
5889 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_half:
5890 ; CHECK-RV64V: # %bb.0:
5891 ; CHECK-RV64V-NEXT: ntl.all
5892 ; CHECK-RV64V-NEXT: flh fa5, 0(a0)
5893 ; CHECK-RV64V-NEXT: ntl.all
5894 ; CHECK-RV64V-NEXT: flh fa4, 6(a0)
5895 ; CHECK-RV64V-NEXT: fadd.h fa0, fa5, fa4
5896 ; CHECK-RV64V-NEXT: ret
5897 ;
5898 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_half:
5899 ; CHECK-RV32V: # %bb.0:
5900 ; CHECK-RV32V-NEXT: ntl.all
5901 ; CHECK-RV32V-NEXT: flh fa5, 0(a0)
5902 ; CHECK-RV32V-NEXT: ntl.all
5903 ; CHECK-RV32V-NEXT: flh fa4, 6(a0)
5904 ; CHECK-RV32V-NEXT: fadd.h fa0, fa5, fa4
5905 ; CHECK-RV32V-NEXT: ret
5906 %1 = load half, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
5907 %2 = getelementptr half, ptr %p, i32 3
5908 %3 = load half, ptr %2, !nontemporal !0, !riscv-nontemporal-domain !4
5909 %4 = fadd half %1, %3
5910 ret half %4
5911 }
5913 define float @test_nontemporal_ALL_load_float(ptr %p) {
5914 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_float:
5915 ; CHECK-RV64: # %bb.0:
5916 ; CHECK-RV64-NEXT: ntl.all
5917 ; CHECK-RV64-NEXT: flw fa0, 0(a0)
5918 ; CHECK-RV64-NEXT: ret
5919 ;
5920 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_float:
5921 ; CHECK-RV32: # %bb.0:
5922 ; CHECK-RV32-NEXT: ntl.all
5923 ; CHECK-RV32-NEXT: flw fa0, 0(a0)
5924 ; CHECK-RV32-NEXT: ret
5925 ;
5926 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_float:
5927 ; CHECK-RV64C: # %bb.0:
5928 ; CHECK-RV64C-NEXT: c.ntl.all
5929 ; CHECK-RV64C-NEXT: flw fa0, 0(a0)
5930 ; CHECK-RV64C-NEXT: ret
5931 ;
5932 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_float:
5933 ; CHECK-RV32C: # %bb.0:
5934 ; CHECK-RV32C-NEXT: c.ntl.all
5935 ; CHECK-RV32C-NEXT: flw fa0, 0(a0)
5936 ; CHECK-RV32C-NEXT: ret
5937 ;
5938 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_float:
5939 ; CHECK-RV64V: # %bb.0:
5940 ; CHECK-RV64V-NEXT: ntl.all
5941 ; CHECK-RV64V-NEXT: flw fa0, 0(a0)
5942 ; CHECK-RV64V-NEXT: ret
5943 ;
5944 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_float:
5945 ; CHECK-RV32V: # %bb.0:
5946 ; CHECK-RV32V-NEXT: ntl.all
5947 ; CHECK-RV32V-NEXT: flw fa0, 0(a0)
5948 ; CHECK-RV32V-NEXT: ret
5949 %1 = load float, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
5950 ret float %1
5951 }
5953 define double @test_nontemporal_ALL_load_double(ptr %p) {
5954 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_double:
5955 ; CHECK-RV64: # %bb.0:
5956 ; CHECK-RV64-NEXT: ntl.all
5957 ; CHECK-RV64-NEXT: fld fa0, 0(a0)
5958 ; CHECK-RV64-NEXT: ret
5959 ;
5960 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_double:
5961 ; CHECK-RV32: # %bb.0:
5962 ; CHECK-RV32-NEXT: ntl.all
5963 ; CHECK-RV32-NEXT: fld fa0, 0(a0)
5964 ; CHECK-RV32-NEXT: ret
5965 ;
5966 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_double:
5967 ; CHECK-RV64C: # %bb.0:
5968 ; CHECK-RV64C-NEXT: c.ntl.all
5969 ; CHECK-RV64C-NEXT: fld fa0, 0(a0)
5970 ; CHECK-RV64C-NEXT: ret
5971 ;
5972 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_double:
5973 ; CHECK-RV32C: # %bb.0:
5974 ; CHECK-RV32C-NEXT: c.ntl.all
5975 ; CHECK-RV32C-NEXT: fld fa0, 0(a0)
5976 ; CHECK-RV32C-NEXT: ret
5977 ;
5978 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_double:
5979 ; CHECK-RV64V: # %bb.0:
5980 ; CHECK-RV64V-NEXT: ntl.all
5981 ; CHECK-RV64V-NEXT: fld fa0, 0(a0)
5982 ; CHECK-RV64V-NEXT: ret
5983 ;
5984 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_double:
5985 ; CHECK-RV32V: # %bb.0:
5986 ; CHECK-RV32V-NEXT: ntl.all
5987 ; CHECK-RV32V-NEXT: fld fa0, 0(a0)
5988 ; CHECK-RV32V-NEXT: ret
5989 %1 = load double, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
5990 ret double %1
5991 }
5993 define <16 x i8> @test_nontemporal_ALL_load_v16i8(ptr %p) {
5994 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_v16i8:
5995 ; CHECK-RV64: # %bb.0:
5996 ; CHECK-RV64-NEXT: ntl.all
5997 ; CHECK-RV64-NEXT: ld a2, 8(a1)
5998 ; CHECK-RV64-NEXT: ntl.all
5999 ; CHECK-RV64-NEXT: ld a1, 0(a1)
6000 ; CHECK-RV64-NEXT: sd a2, 8(a0)
6001 ; CHECK-RV64-NEXT: sd a1, 0(a0)
6002 ; CHECK-RV64-NEXT: ret
6003 ;
6004 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_v16i8:
6005 ; CHECK-RV32: # %bb.0:
6006 ; CHECK-RV32-NEXT: ntl.all
6007 ; CHECK-RV32-NEXT: lw a2, 12(a1)
6008 ; CHECK-RV32-NEXT: ntl.all
6009 ; CHECK-RV32-NEXT: lw a3, 8(a1)
6010 ; CHECK-RV32-NEXT: ntl.all
6011 ; CHECK-RV32-NEXT: lw a4, 4(a1)
6012 ; CHECK-RV32-NEXT: ntl.all
6013 ; CHECK-RV32-NEXT: lw a1, 0(a1)
6014 ; CHECK-RV32-NEXT: sw a2, 12(a0)
6015 ; CHECK-RV32-NEXT: sw a3, 8(a0)
6016 ; CHECK-RV32-NEXT: sw a4, 4(a0)
6017 ; CHECK-RV32-NEXT: sw a1, 0(a0)
6018 ; CHECK-RV32-NEXT: ret
6019 ;
6020 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_v16i8:
6021 ; CHECK-RV64C: # %bb.0:
6022 ; CHECK-RV64C-NEXT: c.ntl.all
6023 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
6024 ; CHECK-RV64C-NEXT: c.ntl.all
6025 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
6026 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
6027 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
6028 ; CHECK-RV64C-NEXT: ret
6029 ;
6030 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_v16i8:
6031 ; CHECK-RV32C: # %bb.0:
6032 ; CHECK-RV32C-NEXT: c.ntl.all
6033 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
6034 ; CHECK-RV32C-NEXT: c.ntl.all
6035 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
6036 ; CHECK-RV32C-NEXT: c.ntl.all
6037 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
6038 ; CHECK-RV32C-NEXT: c.ntl.all
6039 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
6040 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
6041 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
6042 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
6043 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
6044 ; CHECK-RV32C-NEXT: ret
6045 ;
6046 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_v16i8:
6047 ; CHECK-RV64V: # %bb.0:
6048 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
6049 ; CHECK-RV64V-NEXT: ntl.all
6050 ; CHECK-RV64V-NEXT: vle8.v v8, (a0)
6051 ; CHECK-RV64V-NEXT: ret
6052 ;
6053 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_v16i8:
6054 ; CHECK-RV32V: # %bb.0:
6055 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
6056 ; CHECK-RV32V-NEXT: ntl.all
6057 ; CHECK-RV32V-NEXT: vle8.v v8, (a0)
6058 ; CHECK-RV32V-NEXT: ret
6059 %1 = load <16 x i8>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6060 ret <16 x i8> %1
6061 }
6063 define <8 x i16> @test_nontemporal_ALL_load_v8i16(ptr %p) {
6064 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_v8i16:
6065 ; CHECK-RV64: # %bb.0:
6066 ; CHECK-RV64-NEXT: ntl.all
6067 ; CHECK-RV64-NEXT: ld a2, 8(a1)
6068 ; CHECK-RV64-NEXT: ntl.all
6069 ; CHECK-RV64-NEXT: ld a1, 0(a1)
6070 ; CHECK-RV64-NEXT: sd a2, 8(a0)
6071 ; CHECK-RV64-NEXT: sd a1, 0(a0)
6072 ; CHECK-RV64-NEXT: ret
6073 ;
6074 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_v8i16:
6075 ; CHECK-RV32: # %bb.0:
6076 ; CHECK-RV32-NEXT: ntl.all
6077 ; CHECK-RV32-NEXT: lw a2, 12(a1)
6078 ; CHECK-RV32-NEXT: ntl.all
6079 ; CHECK-RV32-NEXT: lw a3, 8(a1)
6080 ; CHECK-RV32-NEXT: ntl.all
6081 ; CHECK-RV32-NEXT: lw a4, 4(a1)
6082 ; CHECK-RV32-NEXT: ntl.all
6083 ; CHECK-RV32-NEXT: lw a1, 0(a1)
6084 ; CHECK-RV32-NEXT: sw a2, 12(a0)
6085 ; CHECK-RV32-NEXT: sw a3, 8(a0)
6086 ; CHECK-RV32-NEXT: sw a4, 4(a0)
6087 ; CHECK-RV32-NEXT: sw a1, 0(a0)
6088 ; CHECK-RV32-NEXT: ret
6089 ;
6090 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_v8i16:
6091 ; CHECK-RV64C: # %bb.0:
6092 ; CHECK-RV64C-NEXT: c.ntl.all
6093 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
6094 ; CHECK-RV64C-NEXT: c.ntl.all
6095 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
6096 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
6097 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
6098 ; CHECK-RV64C-NEXT: ret
6099 ;
6100 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_v8i16:
6101 ; CHECK-RV32C: # %bb.0:
6102 ; CHECK-RV32C-NEXT: c.ntl.all
6103 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
6104 ; CHECK-RV32C-NEXT: c.ntl.all
6105 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
6106 ; CHECK-RV32C-NEXT: c.ntl.all
6107 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
6108 ; CHECK-RV32C-NEXT: c.ntl.all
6109 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
6110 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
6111 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
6112 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
6113 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
6114 ; CHECK-RV32C-NEXT: ret
6115 ;
6116 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_v8i16:
6117 ; CHECK-RV64V: # %bb.0:
6118 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
6119 ; CHECK-RV64V-NEXT: ntl.all
6120 ; CHECK-RV64V-NEXT: vle16.v v8, (a0)
6121 ; CHECK-RV64V-NEXT: ret
6122 ;
6123 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_v8i16:
6124 ; CHECK-RV32V: # %bb.0:
6125 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
6126 ; CHECK-RV32V-NEXT: ntl.all
6127 ; CHECK-RV32V-NEXT: vle16.v v8, (a0)
6128 ; CHECK-RV32V-NEXT: ret
6129 %1 = load <8 x i16>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6130 ret <8 x i16> %1
6131 }
6133 define <4 x i32> @test_nontemporal_ALL_load_v4i32(ptr %p) {
6134 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_v4i32:
6135 ; CHECK-RV64: # %bb.0:
6136 ; CHECK-RV64-NEXT: ntl.all
6137 ; CHECK-RV64-NEXT: ld a2, 8(a1)
6138 ; CHECK-RV64-NEXT: ntl.all
6139 ; CHECK-RV64-NEXT: ld a1, 0(a1)
6140 ; CHECK-RV64-NEXT: sd a2, 8(a0)
6141 ; CHECK-RV64-NEXT: sd a1, 0(a0)
6142 ; CHECK-RV64-NEXT: ret
6143 ;
6144 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_v4i32:
6145 ; CHECK-RV32: # %bb.0:
6146 ; CHECK-RV32-NEXT: ntl.all
6147 ; CHECK-RV32-NEXT: lw a2, 12(a1)
6148 ; CHECK-RV32-NEXT: ntl.all
6149 ; CHECK-RV32-NEXT: lw a3, 8(a1)
6150 ; CHECK-RV32-NEXT: ntl.all
6151 ; CHECK-RV32-NEXT: lw a4, 4(a1)
6152 ; CHECK-RV32-NEXT: ntl.all
6153 ; CHECK-RV32-NEXT: lw a1, 0(a1)
6154 ; CHECK-RV32-NEXT: sw a2, 12(a0)
6155 ; CHECK-RV32-NEXT: sw a3, 8(a0)
6156 ; CHECK-RV32-NEXT: sw a4, 4(a0)
6157 ; CHECK-RV32-NEXT: sw a1, 0(a0)
6158 ; CHECK-RV32-NEXT: ret
6159 ;
6160 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_v4i32:
6161 ; CHECK-RV64C: # %bb.0:
6162 ; CHECK-RV64C-NEXT: c.ntl.all
6163 ; CHECK-RV64C-NEXT: ld a2, 8(a1)
6164 ; CHECK-RV64C-NEXT: c.ntl.all
6165 ; CHECK-RV64C-NEXT: ld a1, 0(a1)
6166 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
6167 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
6168 ; CHECK-RV64C-NEXT: ret
6169 ;
6170 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_v4i32:
6171 ; CHECK-RV32C: # %bb.0:
6172 ; CHECK-RV32C-NEXT: c.ntl.all
6173 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
6174 ; CHECK-RV32C-NEXT: c.ntl.all
6175 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
6176 ; CHECK-RV32C-NEXT: c.ntl.all
6177 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
6178 ; CHECK-RV32C-NEXT: c.ntl.all
6179 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
6180 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
6181 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
6182 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
6183 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
6184 ; CHECK-RV32C-NEXT: ret
6185 ;
6186 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_v4i32:
6187 ; CHECK-RV64V: # %bb.0:
6188 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
6189 ; CHECK-RV64V-NEXT: ntl.all
6190 ; CHECK-RV64V-NEXT: vle32.v v8, (a0)
6191 ; CHECK-RV64V-NEXT: ret
6192 ;
6193 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_v4i32:
6194 ; CHECK-RV32V: # %bb.0:
6195 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
6196 ; CHECK-RV32V-NEXT: ntl.all
6197 ; CHECK-RV32V-NEXT: vle32.v v8, (a0)
6198 ; CHECK-RV32V-NEXT: ret
6199 %1 = load <4 x i32>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6200 ret <4 x i32> %1
6201 }
6203 define <2 x i64> @test_nontemporal_ALL_load_v2i64(ptr %p) {
6204 ; CHECK-RV64-LABEL: test_nontemporal_ALL_load_v2i64:
6205 ; CHECK-RV64: # %bb.0:
6206 ; CHECK-RV64-NEXT: ntl.all
6207 ; CHECK-RV64-NEXT: ld a2, 0(a0)
6208 ; CHECK-RV64-NEXT: ntl.all
6209 ; CHECK-RV64-NEXT: ld a1, 8(a0)
6210 ; CHECK-RV64-NEXT: mv a0, a2
6211 ; CHECK-RV64-NEXT: ret
6212 ;
6213 ; CHECK-RV32-LABEL: test_nontemporal_ALL_load_v2i64:
6214 ; CHECK-RV32: # %bb.0:
6215 ; CHECK-RV32-NEXT: ntl.all
6216 ; CHECK-RV32-NEXT: lw a2, 12(a1)
6217 ; CHECK-RV32-NEXT: ntl.all
6218 ; CHECK-RV32-NEXT: lw a3, 8(a1)
6219 ; CHECK-RV32-NEXT: ntl.all
6220 ; CHECK-RV32-NEXT: lw a4, 4(a1)
6221 ; CHECK-RV32-NEXT: ntl.all
6222 ; CHECK-RV32-NEXT: lw a1, 0(a1)
6223 ; CHECK-RV32-NEXT: sw a2, 12(a0)
6224 ; CHECK-RV32-NEXT: sw a3, 8(a0)
6225 ; CHECK-RV32-NEXT: sw a4, 4(a0)
6226 ; CHECK-RV32-NEXT: sw a1, 0(a0)
6227 ; CHECK-RV32-NEXT: ret
6228 ;
6229 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_load_v2i64:
6230 ; CHECK-RV64C: # %bb.0:
6231 ; CHECK-RV64C-NEXT: c.ntl.all
6232 ; CHECK-RV64C-NEXT: ld a2, 0(a0)
6233 ; CHECK-RV64C-NEXT: c.ntl.all
6234 ; CHECK-RV64C-NEXT: ld a1, 8(a0)
6235 ; CHECK-RV64C-NEXT: mv a0, a2
6236 ; CHECK-RV64C-NEXT: ret
6237 ;
6238 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_load_v2i64:
6239 ; CHECK-RV32C: # %bb.0:
6240 ; CHECK-RV32C-NEXT: c.ntl.all
6241 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
6242 ; CHECK-RV32C-NEXT: c.ntl.all
6243 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
6244 ; CHECK-RV32C-NEXT: c.ntl.all
6245 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
6246 ; CHECK-RV32C-NEXT: c.ntl.all
6247 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
6248 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
6249 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
6250 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
6251 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
6252 ; CHECK-RV32C-NEXT: ret
6253 ;
6254 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_load_v2i64:
6255 ; CHECK-RV64V: # %bb.0:
6256 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
6257 ; CHECK-RV64V-NEXT: ntl.all
6258 ; CHECK-RV64V-NEXT: vle64.v v8, (a0)
6259 ; CHECK-RV64V-NEXT: ret
6260 ;
6261 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_load_v2i64:
6262 ; CHECK-RV32V: # %bb.0:
6263 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
6264 ; CHECK-RV32V-NEXT: ntl.all
6265 ; CHECK-RV32V-NEXT: vle64.v v8, (a0)
6266 ; CHECK-RV32V-NEXT: ret
6267 %1 = load <2 x i64>, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6268 ret <2 x i64> %1
6269 }
6271 define void @test_nontemporal_ALL_store_i64(ptr %p, i64 %v) {
6272 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_i64:
6273 ; CHECK-RV64: # %bb.0:
6274 ; CHECK-RV64-NEXT: ntl.all
6275 ; CHECK-RV64-NEXT: sd a1, 0(a0)
6276 ; CHECK-RV64-NEXT: ret
6277 ;
6278 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_i64:
6279 ; CHECK-RV32: # %bb.0:
6280 ; CHECK-RV32-NEXT: ntl.all
6281 ; CHECK-RV32-NEXT: sw a2, 4(a0)
6282 ; CHECK-RV32-NEXT: ntl.all
6283 ; CHECK-RV32-NEXT: sw a1, 0(a0)
6284 ; CHECK-RV32-NEXT: ret
6285 ;
6286 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_i64:
6287 ; CHECK-RV64C: # %bb.0:
6288 ; CHECK-RV64C-NEXT: c.ntl.all
6289 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
6290 ; CHECK-RV64C-NEXT: ret
6291 ;
6292 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_i64:
6293 ; CHECK-RV32C: # %bb.0:
6294 ; CHECK-RV32C-NEXT: c.ntl.all
6295 ; CHECK-RV32C-NEXT: sw a2, 4(a0)
6296 ; CHECK-RV32C-NEXT: c.ntl.all
6297 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
6298 ; CHECK-RV32C-NEXT: ret
6299 ;
6300 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_i64:
6301 ; CHECK-RV64V: # %bb.0:
6302 ; CHECK-RV64V-NEXT: ntl.all
6303 ; CHECK-RV64V-NEXT: sd a1, 0(a0)
6304 ; CHECK-RV64V-NEXT: ret
6305 ;
6306 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_i64:
6307 ; CHECK-RV32V: # %bb.0:
6308 ; CHECK-RV32V-NEXT: ntl.all
6309 ; CHECK-RV32V-NEXT: sw a2, 4(a0)
6310 ; CHECK-RV32V-NEXT: ntl.all
6311 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
6312 ; CHECK-RV32V-NEXT: ret
6313 store i64 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6314 ret void
6315 }
6317 define void @test_nontemporal_ALL_store_i32(ptr %p, i32 %v) {
6318 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_i32:
6319 ; CHECK-RV64: # %bb.0:
6320 ; CHECK-RV64-NEXT: ntl.all
6321 ; CHECK-RV64-NEXT: sw a1, 0(a0)
6322 ; CHECK-RV64-NEXT: ret
6323 ;
6324 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_i32:
6325 ; CHECK-RV32: # %bb.0:
6326 ; CHECK-RV32-NEXT: ntl.all
6327 ; CHECK-RV32-NEXT: sw a1, 0(a0)
6328 ; CHECK-RV32-NEXT: ret
6329 ;
6330 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_i32:
6331 ; CHECK-RV64C: # %bb.0:
6332 ; CHECK-RV64C-NEXT: c.ntl.all
6333 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
6334 ; CHECK-RV64C-NEXT: ret
6335 ;
6336 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_i32:
6337 ; CHECK-RV32C: # %bb.0:
6338 ; CHECK-RV32C-NEXT: c.ntl.all
6339 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
6340 ; CHECK-RV32C-NEXT: ret
6341 ;
6342 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_i32:
6343 ; CHECK-RV64V: # %bb.0:
6344 ; CHECK-RV64V-NEXT: ntl.all
6345 ; CHECK-RV64V-NEXT: sw a1, 0(a0)
6346 ; CHECK-RV64V-NEXT: ret
6347 ;
6348 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_i32:
6349 ; CHECK-RV32V: # %bb.0:
6350 ; CHECK-RV32V-NEXT: ntl.all
6351 ; CHECK-RV32V-NEXT: sw a1, 0(a0)
6352 ; CHECK-RV32V-NEXT: ret
6353 store i32 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6354 ret void
6355 }
6357 define void @test_nontemporal_ALL_store_i16(ptr %p, i16 %v) {
6358 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_i16:
6359 ; CHECK-RV64: # %bb.0:
6360 ; CHECK-RV64-NEXT: ntl.all
6361 ; CHECK-RV64-NEXT: sh a1, 0(a0)
6362 ; CHECK-RV64-NEXT: ret
6363 ;
6364 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_i16:
6365 ; CHECK-RV32: # %bb.0:
6366 ; CHECK-RV32-NEXT: ntl.all
6367 ; CHECK-RV32-NEXT: sh a1, 0(a0)
6368 ; CHECK-RV32-NEXT: ret
6369 ;
6370 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_i16:
6371 ; CHECK-RV64C: # %bb.0:
6372 ; CHECK-RV64C-NEXT: c.ntl.all
6373 ; CHECK-RV64C-NEXT: sh a1, 0(a0)
6374 ; CHECK-RV64C-NEXT: ret
6375 ;
6376 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_i16:
6377 ; CHECK-RV32C: # %bb.0:
6378 ; CHECK-RV32C-NEXT: c.ntl.all
6379 ; CHECK-RV32C-NEXT: sh a1, 0(a0)
6380 ; CHECK-RV32C-NEXT: ret
6381 ;
6382 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_i16:
6383 ; CHECK-RV64V: # %bb.0:
6384 ; CHECK-RV64V-NEXT: ntl.all
6385 ; CHECK-RV64V-NEXT: sh a1, 0(a0)
6386 ; CHECK-RV64V-NEXT: ret
6387 ;
6388 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_i16:
6389 ; CHECK-RV32V: # %bb.0:
6390 ; CHECK-RV32V-NEXT: ntl.all
6391 ; CHECK-RV32V-NEXT: sh a1, 0(a0)
6392 ; CHECK-RV32V-NEXT: ret
6393 store i16 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6394 ret void
6395 }
6397 define void @test_nontemporal_ALL_store_i8(ptr %p, i8 %v) {
6398 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_i8:
6399 ; CHECK-RV64: # %bb.0:
6400 ; CHECK-RV64-NEXT: ntl.all
6401 ; CHECK-RV64-NEXT: sb a1, 0(a0)
6402 ; CHECK-RV64-NEXT: ret
6403 ;
6404 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_i8:
6405 ; CHECK-RV32: # %bb.0:
6406 ; CHECK-RV32-NEXT: ntl.all
6407 ; CHECK-RV32-NEXT: sb a1, 0(a0)
6408 ; CHECK-RV32-NEXT: ret
6409 ;
6410 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_i8:
6411 ; CHECK-RV64C: # %bb.0:
6412 ; CHECK-RV64C-NEXT: c.ntl.all
6413 ; CHECK-RV64C-NEXT: sb a1, 0(a0)
6414 ; CHECK-RV64C-NEXT: ret
6415 ;
6416 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_i8:
6417 ; CHECK-RV32C: # %bb.0:
6418 ; CHECK-RV32C-NEXT: c.ntl.all
6419 ; CHECK-RV32C-NEXT: sb a1, 0(a0)
6420 ; CHECK-RV32C-NEXT: ret
6421 ;
6422 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_i8:
6423 ; CHECK-RV64V: # %bb.0:
6424 ; CHECK-RV64V-NEXT: ntl.all
6425 ; CHECK-RV64V-NEXT: sb a1, 0(a0)
6426 ; CHECK-RV64V-NEXT: ret
6427 ;
6428 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_i8:
6429 ; CHECK-RV32V: # %bb.0:
6430 ; CHECK-RV32V-NEXT: ntl.all
6431 ; CHECK-RV32V-NEXT: sb a1, 0(a0)
6432 ; CHECK-RV32V-NEXT: ret
6433 store i8 %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6434 ret void
6435 }
6437 define void @test_nontemporal_ALL_store_half(ptr %p, half %v) {
6438 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_half:
6439 ; CHECK-RV64: # %bb.0:
6440 ; CHECK-RV64-NEXT: ntl.all
6441 ; CHECK-RV64-NEXT: fsh fa0, 0(a0)
6442 ; CHECK-RV64-NEXT: ret
6443 ;
6444 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_half:
6445 ; CHECK-RV32: # %bb.0:
6446 ; CHECK-RV32-NEXT: ntl.all
6447 ; CHECK-RV32-NEXT: fsh fa0, 0(a0)
6448 ; CHECK-RV32-NEXT: ret
6449 ;
6450 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_half:
6451 ; CHECK-RV64C: # %bb.0:
6452 ; CHECK-RV64C-NEXT: c.ntl.all
6453 ; CHECK-RV64C-NEXT: fsh fa0, 0(a0)
6454 ; CHECK-RV64C-NEXT: ret
6455 ;
6456 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_half:
6457 ; CHECK-RV32C: # %bb.0:
6458 ; CHECK-RV32C-NEXT: c.ntl.all
6459 ; CHECK-RV32C-NEXT: fsh fa0, 0(a0)
6460 ; CHECK-RV32C-NEXT: ret
6461 ;
6462 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_half:
6463 ; CHECK-RV64V: # %bb.0:
6464 ; CHECK-RV64V-NEXT: ntl.all
6465 ; CHECK-RV64V-NEXT: fsh fa0, 0(a0)
6466 ; CHECK-RV64V-NEXT: ret
6467 ;
6468 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_half:
6469 ; CHECK-RV32V: # %bb.0:
6470 ; CHECK-RV32V-NEXT: ntl.all
6471 ; CHECK-RV32V-NEXT: fsh fa0, 0(a0)
6472 ; CHECK-RV32V-NEXT: ret
6473 store half %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6474 ret void
6475 }
6477 define void @test_nontemporal_ALL_store_float(ptr %p, float %v) {
6478 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_float:
6479 ; CHECK-RV64: # %bb.0:
6480 ; CHECK-RV64-NEXT: ntl.all
6481 ; CHECK-RV64-NEXT: fsw fa0, 0(a0)
6482 ; CHECK-RV64-NEXT: ret
6483 ;
6484 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_float:
6485 ; CHECK-RV32: # %bb.0:
6486 ; CHECK-RV32-NEXT: ntl.all
6487 ; CHECK-RV32-NEXT: fsw fa0, 0(a0)
6488 ; CHECK-RV32-NEXT: ret
6489 ;
6490 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_float:
6491 ; CHECK-RV64C: # %bb.0:
6492 ; CHECK-RV64C-NEXT: c.ntl.all
6493 ; CHECK-RV64C-NEXT: fsw fa0, 0(a0)
6494 ; CHECK-RV64C-NEXT: ret
6495 ;
6496 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_float:
6497 ; CHECK-RV32C: # %bb.0:
6498 ; CHECK-RV32C-NEXT: c.ntl.all
6499 ; CHECK-RV32C-NEXT: fsw fa0, 0(a0)
6500 ; CHECK-RV32C-NEXT: ret
6501 ;
6502 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_float:
6503 ; CHECK-RV64V: # %bb.0:
6504 ; CHECK-RV64V-NEXT: ntl.all
6505 ; CHECK-RV64V-NEXT: fsw fa0, 0(a0)
6506 ; CHECK-RV64V-NEXT: ret
6507 ;
6508 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_float:
6509 ; CHECK-RV32V: # %bb.0:
6510 ; CHECK-RV32V-NEXT: ntl.all
6511 ; CHECK-RV32V-NEXT: fsw fa0, 0(a0)
6512 ; CHECK-RV32V-NEXT: ret
6513 store float %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6514 ret void
6515 }
6517 define void @test_nontemporal_ALL_store_double(ptr %p, double %v) {
6518 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_double:
6519 ; CHECK-RV64: # %bb.0:
6520 ; CHECK-RV64-NEXT: ntl.all
6521 ; CHECK-RV64-NEXT: fsd fa0, 0(a0)
6522 ; CHECK-RV64-NEXT: ret
6523 ;
6524 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_double:
6525 ; CHECK-RV32: # %bb.0:
6526 ; CHECK-RV32-NEXT: ntl.all
6527 ; CHECK-RV32-NEXT: fsd fa0, 0(a0)
6528 ; CHECK-RV32-NEXT: ret
6529 ;
6530 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_double:
6531 ; CHECK-RV64C: # %bb.0:
6532 ; CHECK-RV64C-NEXT: c.ntl.all
6533 ; CHECK-RV64C-NEXT: fsd fa0, 0(a0)
6534 ; CHECK-RV64C-NEXT: ret
6535 ;
6536 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_double:
6537 ; CHECK-RV32C: # %bb.0:
6538 ; CHECK-RV32C-NEXT: c.ntl.all
6539 ; CHECK-RV32C-NEXT: fsd fa0, 0(a0)
6540 ; CHECK-RV32C-NEXT: ret
6541 ;
6542 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_double:
6543 ; CHECK-RV64V: # %bb.0:
6544 ; CHECK-RV64V-NEXT: ntl.all
6545 ; CHECK-RV64V-NEXT: fsd fa0, 0(a0)
6546 ; CHECK-RV64V-NEXT: ret
6547 ;
6548 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_double:
6549 ; CHECK-RV32V: # %bb.0:
6550 ; CHECK-RV32V-NEXT: ntl.all
6551 ; CHECK-RV32V-NEXT: fsd fa0, 0(a0)
6552 ; CHECK-RV32V-NEXT: ret
6553 store double %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6554 ret void
6555 }
6557 define void @test_nontemporal_ALL_store_v16i8(ptr %p, <16 x i8> %v) {
6558 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_v16i8:
6559 ; CHECK-RV64: # %bb.0:
6560 ; CHECK-RV64-NEXT: addi sp, sp, -16
6561 ; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
6562 ; CHECK-RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
6563 ; CHECK-RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
6564 ; CHECK-RV64-NEXT: .cfi_offset s0, -8
6565 ; CHECK-RV64-NEXT: .cfi_offset s1, -16
6566 ; CHECK-RV64-NEXT: lbu a2, 0(a1)
6567 ; CHECK-RV64-NEXT: lbu a3, 8(a1)
6568 ; CHECK-RV64-NEXT: lbu a4, 16(a1)
6569 ; CHECK-RV64-NEXT: lbu a5, 24(a1)
6570 ; CHECK-RV64-NEXT: lbu a6, 32(a1)
6571 ; CHECK-RV64-NEXT: lbu a7, 40(a1)
6572 ; CHECK-RV64-NEXT: lbu t0, 48(a1)
6573 ; CHECK-RV64-NEXT: lbu t1, 56(a1)
6574 ; CHECK-RV64-NEXT: lbu t2, 64(a1)
6575 ; CHECK-RV64-NEXT: lbu t3, 72(a1)
6576 ; CHECK-RV64-NEXT: lbu t4, 80(a1)
6577 ; CHECK-RV64-NEXT: lbu t5, 88(a1)
6578 ; CHECK-RV64-NEXT: lbu t6, 120(a1)
6579 ; CHECK-RV64-NEXT: lbu s0, 112(a1)
6580 ; CHECK-RV64-NEXT: lbu s1, 104(a1)
6581 ; CHECK-RV64-NEXT: lbu a1, 96(a1)
6582 ; CHECK-RV64-NEXT: ntl.all
6583 ; CHECK-RV64-NEXT: sb t6, 15(a0)
6584 ; CHECK-RV64-NEXT: ntl.all
6585 ; CHECK-RV64-NEXT: sb s0, 14(a0)
6586 ; CHECK-RV64-NEXT: ntl.all
6587 ; CHECK-RV64-NEXT: sb s1, 13(a0)
6588 ; CHECK-RV64-NEXT: ntl.all
6589 ; CHECK-RV64-NEXT: sb a1, 12(a0)
6590 ; CHECK-RV64-NEXT: ntl.all
6591 ; CHECK-RV64-NEXT: sb t5, 11(a0)
6592 ; CHECK-RV64-NEXT: ntl.all
6593 ; CHECK-RV64-NEXT: sb t4, 10(a0)
6594 ; CHECK-RV64-NEXT: ntl.all
6595 ; CHECK-RV64-NEXT: sb t3, 9(a0)
6596 ; CHECK-RV64-NEXT: ntl.all
6597 ; CHECK-RV64-NEXT: sb t2, 8(a0)
6598 ; CHECK-RV64-NEXT: ntl.all
6599 ; CHECK-RV64-NEXT: sb t1, 7(a0)
6600 ; CHECK-RV64-NEXT: ntl.all
6601 ; CHECK-RV64-NEXT: sb t0, 6(a0)
6602 ; CHECK-RV64-NEXT: ntl.all
6603 ; CHECK-RV64-NEXT: sb a7, 5(a0)
6604 ; CHECK-RV64-NEXT: ntl.all
6605 ; CHECK-RV64-NEXT: sb a6, 4(a0)
6606 ; CHECK-RV64-NEXT: ntl.all
6607 ; CHECK-RV64-NEXT: sb a5, 3(a0)
6608 ; CHECK-RV64-NEXT: ntl.all
6609 ; CHECK-RV64-NEXT: sb a4, 2(a0)
6610 ; CHECK-RV64-NEXT: ntl.all
6611 ; CHECK-RV64-NEXT: sb a3, 1(a0)
6612 ; CHECK-RV64-NEXT: ntl.all
6613 ; CHECK-RV64-NEXT: sb a2, 0(a0)
6614 ; CHECK-RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
6615 ; CHECK-RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
6616 ; CHECK-RV64-NEXT: addi sp, sp, 16
6617 ; CHECK-RV64-NEXT: ret
6618 ;
6619 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_v16i8:
6620 ; CHECK-RV32: # %bb.0:
6621 ; CHECK-RV32-NEXT: addi sp, sp, -16
6622 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
6623 ; CHECK-RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
6624 ; CHECK-RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
6625 ; CHECK-RV32-NEXT: .cfi_offset s0, -4
6626 ; CHECK-RV32-NEXT: .cfi_offset s1, -8
6627 ; CHECK-RV32-NEXT: lbu a2, 0(a1)
6628 ; CHECK-RV32-NEXT: lbu a3, 4(a1)
6629 ; CHECK-RV32-NEXT: lbu a4, 8(a1)
6630 ; CHECK-RV32-NEXT: lbu a5, 12(a1)
6631 ; CHECK-RV32-NEXT: lbu a6, 16(a1)
6632 ; CHECK-RV32-NEXT: lbu a7, 20(a1)
6633 ; CHECK-RV32-NEXT: lbu t0, 24(a1)
6634 ; CHECK-RV32-NEXT: lbu t1, 28(a1)
6635 ; CHECK-RV32-NEXT: lbu t2, 32(a1)
6636 ; CHECK-RV32-NEXT: lbu t3, 36(a1)
6637 ; CHECK-RV32-NEXT: lbu t4, 40(a1)
6638 ; CHECK-RV32-NEXT: lbu t5, 44(a1)
6639 ; CHECK-RV32-NEXT: lbu t6, 60(a1)
6640 ; CHECK-RV32-NEXT: lbu s0, 56(a1)
6641 ; CHECK-RV32-NEXT: lbu s1, 52(a1)
6642 ; CHECK-RV32-NEXT: lbu a1, 48(a1)
6643 ; CHECK-RV32-NEXT: ntl.all
6644 ; CHECK-RV32-NEXT: sb t6, 15(a0)
6645 ; CHECK-RV32-NEXT: ntl.all
6646 ; CHECK-RV32-NEXT: sb s0, 14(a0)
6647 ; CHECK-RV32-NEXT: ntl.all
6648 ; CHECK-RV32-NEXT: sb s1, 13(a0)
6649 ; CHECK-RV32-NEXT: ntl.all
6650 ; CHECK-RV32-NEXT: sb a1, 12(a0)
6651 ; CHECK-RV32-NEXT: ntl.all
6652 ; CHECK-RV32-NEXT: sb t5, 11(a0)
6653 ; CHECK-RV32-NEXT: ntl.all
6654 ; CHECK-RV32-NEXT: sb t4, 10(a0)
6655 ; CHECK-RV32-NEXT: ntl.all
6656 ; CHECK-RV32-NEXT: sb t3, 9(a0)
6657 ; CHECK-RV32-NEXT: ntl.all
6658 ; CHECK-RV32-NEXT: sb t2, 8(a0)
6659 ; CHECK-RV32-NEXT: ntl.all
6660 ; CHECK-RV32-NEXT: sb t1, 7(a0)
6661 ; CHECK-RV32-NEXT: ntl.all
6662 ; CHECK-RV32-NEXT: sb t0, 6(a0)
6663 ; CHECK-RV32-NEXT: ntl.all
6664 ; CHECK-RV32-NEXT: sb a7, 5(a0)
6665 ; CHECK-RV32-NEXT: ntl.all
6666 ; CHECK-RV32-NEXT: sb a6, 4(a0)
6667 ; CHECK-RV32-NEXT: ntl.all
6668 ; CHECK-RV32-NEXT: sb a5, 3(a0)
6669 ; CHECK-RV32-NEXT: ntl.all
6670 ; CHECK-RV32-NEXT: sb a4, 2(a0)
6671 ; CHECK-RV32-NEXT: ntl.all
6672 ; CHECK-RV32-NEXT: sb a3, 1(a0)
6673 ; CHECK-RV32-NEXT: ntl.all
6674 ; CHECK-RV32-NEXT: sb a2, 0(a0)
6675 ; CHECK-RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
6676 ; CHECK-RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
6677 ; CHECK-RV32-NEXT: addi sp, sp, 16
6678 ; CHECK-RV32-NEXT: ret
6679 ;
6680 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_v16i8:
6681 ; CHECK-RV64C: # %bb.0:
6682 ; CHECK-RV64C-NEXT: addi sp, sp, -16
6683 ; CHECK-RV64C-NEXT: .cfi_def_cfa_offset 16
6684 ; CHECK-RV64C-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
6685 ; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
6686 ; CHECK-RV64C-NEXT: .cfi_offset s0, -8
6687 ; CHECK-RV64C-NEXT: .cfi_offset s1, -16
6688 ; CHECK-RV64C-NEXT: lbu a6, 0(a1)
6689 ; CHECK-RV64C-NEXT: lbu a7, 8(a1)
6690 ; CHECK-RV64C-NEXT: lbu t0, 16(a1)
6691 ; CHECK-RV64C-NEXT: lbu t1, 24(a1)
6692 ; CHECK-RV64C-NEXT: lbu t2, 32(a1)
6693 ; CHECK-RV64C-NEXT: lbu t3, 40(a1)
6694 ; CHECK-RV64C-NEXT: lbu t4, 48(a1)
6695 ; CHECK-RV64C-NEXT: lbu t5, 56(a1)
6696 ; CHECK-RV64C-NEXT: lbu t6, 64(a1)
6697 ; CHECK-RV64C-NEXT: lbu a3, 72(a1)
6698 ; CHECK-RV64C-NEXT: lbu a4, 80(a1)
6699 ; CHECK-RV64C-NEXT: lbu a5, 88(a1)
6700 ; CHECK-RV64C-NEXT: lbu a2, 120(a1)
6701 ; CHECK-RV64C-NEXT: lbu s0, 112(a1)
6702 ; CHECK-RV64C-NEXT: lbu s1, 104(a1)
6703 ; CHECK-RV64C-NEXT: lbu a1, 96(a1)
6704 ; CHECK-RV64C-NEXT: c.ntl.all
6705 ; CHECK-RV64C-NEXT: sb a2, 15(a0)
6706 ; CHECK-RV64C-NEXT: c.ntl.all
6707 ; CHECK-RV64C-NEXT: sb s0, 14(a0)
6708 ; CHECK-RV64C-NEXT: c.ntl.all
6709 ; CHECK-RV64C-NEXT: sb s1, 13(a0)
6710 ; CHECK-RV64C-NEXT: c.ntl.all
6711 ; CHECK-RV64C-NEXT: sb a1, 12(a0)
6712 ; CHECK-RV64C-NEXT: c.ntl.all
6713 ; CHECK-RV64C-NEXT: sb a5, 11(a0)
6714 ; CHECK-RV64C-NEXT: c.ntl.all
6715 ; CHECK-RV64C-NEXT: sb a4, 10(a0)
6716 ; CHECK-RV64C-NEXT: c.ntl.all
6717 ; CHECK-RV64C-NEXT: sb a3, 9(a0)
6718 ; CHECK-RV64C-NEXT: c.ntl.all
6719 ; CHECK-RV64C-NEXT: sb t6, 8(a0)
6720 ; CHECK-RV64C-NEXT: c.ntl.all
6721 ; CHECK-RV64C-NEXT: sb t5, 7(a0)
6722 ; CHECK-RV64C-NEXT: c.ntl.all
6723 ; CHECK-RV64C-NEXT: sb t4, 6(a0)
6724 ; CHECK-RV64C-NEXT: c.ntl.all
6725 ; CHECK-RV64C-NEXT: sb t3, 5(a0)
6726 ; CHECK-RV64C-NEXT: c.ntl.all
6727 ; CHECK-RV64C-NEXT: sb t2, 4(a0)
6728 ; CHECK-RV64C-NEXT: c.ntl.all
6729 ; CHECK-RV64C-NEXT: sb t1, 3(a0)
6730 ; CHECK-RV64C-NEXT: c.ntl.all
6731 ; CHECK-RV64C-NEXT: sb t0, 2(a0)
6732 ; CHECK-RV64C-NEXT: c.ntl.all
6733 ; CHECK-RV64C-NEXT: sb a7, 1(a0)
6734 ; CHECK-RV64C-NEXT: c.ntl.all
6735 ; CHECK-RV64C-NEXT: sb a6, 0(a0)
6736 ; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
6737 ; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
6738 ; CHECK-RV64C-NEXT: addi sp, sp, 16
6739 ; CHECK-RV64C-NEXT: ret
6740 ;
6741 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_v16i8:
6742 ; CHECK-RV32C: # %bb.0:
6743 ; CHECK-RV32C-NEXT: addi sp, sp, -16
6744 ; CHECK-RV32C-NEXT: .cfi_def_cfa_offset 16
6745 ; CHECK-RV32C-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
6746 ; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
6747 ; CHECK-RV32C-NEXT: .cfi_offset s0, -4
6748 ; CHECK-RV32C-NEXT: .cfi_offset s1, -8
6749 ; CHECK-RV32C-NEXT: lbu a6, 0(a1)
6750 ; CHECK-RV32C-NEXT: lbu a7, 4(a1)
6751 ; CHECK-RV32C-NEXT: lbu t0, 8(a1)
6752 ; CHECK-RV32C-NEXT: lbu t1, 12(a1)
6753 ; CHECK-RV32C-NEXT: lbu t2, 16(a1)
6754 ; CHECK-RV32C-NEXT: lbu t3, 20(a1)
6755 ; CHECK-RV32C-NEXT: lbu t4, 24(a1)
6756 ; CHECK-RV32C-NEXT: lbu t5, 28(a1)
6757 ; CHECK-RV32C-NEXT: lbu t6, 32(a1)
6758 ; CHECK-RV32C-NEXT: lbu a3, 36(a1)
6759 ; CHECK-RV32C-NEXT: lbu a4, 40(a1)
6760 ; CHECK-RV32C-NEXT: lbu a5, 44(a1)
6761 ; CHECK-RV32C-NEXT: lbu a2, 60(a1)
6762 ; CHECK-RV32C-NEXT: lbu s0, 56(a1)
6763 ; CHECK-RV32C-NEXT: lbu s1, 52(a1)
6764 ; CHECK-RV32C-NEXT: lbu a1, 48(a1)
6765 ; CHECK-RV32C-NEXT: c.ntl.all
6766 ; CHECK-RV32C-NEXT: sb a2, 15(a0)
6767 ; CHECK-RV32C-NEXT: c.ntl.all
6768 ; CHECK-RV32C-NEXT: sb s0, 14(a0)
6769 ; CHECK-RV32C-NEXT: c.ntl.all
6770 ; CHECK-RV32C-NEXT: sb s1, 13(a0)
6771 ; CHECK-RV32C-NEXT: c.ntl.all
6772 ; CHECK-RV32C-NEXT: sb a1, 12(a0)
6773 ; CHECK-RV32C-NEXT: c.ntl.all
6774 ; CHECK-RV32C-NEXT: sb a5, 11(a0)
6775 ; CHECK-RV32C-NEXT: c.ntl.all
6776 ; CHECK-RV32C-NEXT: sb a4, 10(a0)
6777 ; CHECK-RV32C-NEXT: c.ntl.all
6778 ; CHECK-RV32C-NEXT: sb a3, 9(a0)
6779 ; CHECK-RV32C-NEXT: c.ntl.all
6780 ; CHECK-RV32C-NEXT: sb t6, 8(a0)
6781 ; CHECK-RV32C-NEXT: c.ntl.all
6782 ; CHECK-RV32C-NEXT: sb t5, 7(a0)
6783 ; CHECK-RV32C-NEXT: c.ntl.all
6784 ; CHECK-RV32C-NEXT: sb t4, 6(a0)
6785 ; CHECK-RV32C-NEXT: c.ntl.all
6786 ; CHECK-RV32C-NEXT: sb t3, 5(a0)
6787 ; CHECK-RV32C-NEXT: c.ntl.all
6788 ; CHECK-RV32C-NEXT: sb t2, 4(a0)
6789 ; CHECK-RV32C-NEXT: c.ntl.all
6790 ; CHECK-RV32C-NEXT: sb t1, 3(a0)
6791 ; CHECK-RV32C-NEXT: c.ntl.all
6792 ; CHECK-RV32C-NEXT: sb t0, 2(a0)
6793 ; CHECK-RV32C-NEXT: c.ntl.all
6794 ; CHECK-RV32C-NEXT: sb a7, 1(a0)
6795 ; CHECK-RV32C-NEXT: c.ntl.all
6796 ; CHECK-RV32C-NEXT: sb a6, 0(a0)
6797 ; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
6798 ; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
6799 ; CHECK-RV32C-NEXT: addi sp, sp, 16
6800 ; CHECK-RV32C-NEXT: ret
6801 ;
6802 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_v16i8:
6803 ; CHECK-RV64V: # %bb.0:
6804 ; CHECK-RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
6805 ; CHECK-RV64V-NEXT: ntl.all
6806 ; CHECK-RV64V-NEXT: vse8.v v8, (a0)
6807 ; CHECK-RV64V-NEXT: ret
6808 ;
6809 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_v16i8:
6810 ; CHECK-RV32V: # %bb.0:
6811 ; CHECK-RV32V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
6812 ; CHECK-RV32V-NEXT: ntl.all
6813 ; CHECK-RV32V-NEXT: vse8.v v8, (a0)
6814 ; CHECK-RV32V-NEXT: ret
6815 store <16 x i8> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6816 ret void
6817 }
6819 define void @test_nontemporal_ALL_store_v8i16(ptr %p, <8 x i16> %v) {
6820 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_v8i16:
6821 ; CHECK-RV64: # %bb.0:
6822 ; CHECK-RV64-NEXT: lh a2, 0(a1)
6823 ; CHECK-RV64-NEXT: lh a3, 8(a1)
6824 ; CHECK-RV64-NEXT: lh a4, 16(a1)
6825 ; CHECK-RV64-NEXT: lh a5, 24(a1)
6826 ; CHECK-RV64-NEXT: lh a6, 56(a1)
6827 ; CHECK-RV64-NEXT: lh a7, 48(a1)
6828 ; CHECK-RV64-NEXT: lh t0, 40(a1)
6829 ; CHECK-RV64-NEXT: lh a1, 32(a1)
6830 ; CHECK-RV64-NEXT: ntl.all
6831 ; CHECK-RV64-NEXT: sh a6, 14(a0)
6832 ; CHECK-RV64-NEXT: ntl.all
6833 ; CHECK-RV64-NEXT: sh a7, 12(a0)
6834 ; CHECK-RV64-NEXT: ntl.all
6835 ; CHECK-RV64-NEXT: sh t0, 10(a0)
6836 ; CHECK-RV64-NEXT: ntl.all
6837 ; CHECK-RV64-NEXT: sh a1, 8(a0)
6838 ; CHECK-RV64-NEXT: ntl.all
6839 ; CHECK-RV64-NEXT: sh a5, 6(a0)
6840 ; CHECK-RV64-NEXT: ntl.all
6841 ; CHECK-RV64-NEXT: sh a4, 4(a0)
6842 ; CHECK-RV64-NEXT: ntl.all
6843 ; CHECK-RV64-NEXT: sh a3, 2(a0)
6844 ; CHECK-RV64-NEXT: ntl.all
6845 ; CHECK-RV64-NEXT: sh a2, 0(a0)
6846 ; CHECK-RV64-NEXT: ret
6847 ;
6848 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_v8i16:
6849 ; CHECK-RV32: # %bb.0:
6850 ; CHECK-RV32-NEXT: lh a2, 0(a1)
6851 ; CHECK-RV32-NEXT: lh a3, 4(a1)
6852 ; CHECK-RV32-NEXT: lh a4, 8(a1)
6853 ; CHECK-RV32-NEXT: lh a5, 12(a1)
6854 ; CHECK-RV32-NEXT: lh a6, 28(a1)
6855 ; CHECK-RV32-NEXT: lh a7, 24(a1)
6856 ; CHECK-RV32-NEXT: lh t0, 20(a1)
6857 ; CHECK-RV32-NEXT: lh a1, 16(a1)
6858 ; CHECK-RV32-NEXT: ntl.all
6859 ; CHECK-RV32-NEXT: sh a6, 14(a0)
6860 ; CHECK-RV32-NEXT: ntl.all
6861 ; CHECK-RV32-NEXT: sh a7, 12(a0)
6862 ; CHECK-RV32-NEXT: ntl.all
6863 ; CHECK-RV32-NEXT: sh t0, 10(a0)
6864 ; CHECK-RV32-NEXT: ntl.all
6865 ; CHECK-RV32-NEXT: sh a1, 8(a0)
6866 ; CHECK-RV32-NEXT: ntl.all
6867 ; CHECK-RV32-NEXT: sh a5, 6(a0)
6868 ; CHECK-RV32-NEXT: ntl.all
6869 ; CHECK-RV32-NEXT: sh a4, 4(a0)
6870 ; CHECK-RV32-NEXT: ntl.all
6871 ; CHECK-RV32-NEXT: sh a3, 2(a0)
6872 ; CHECK-RV32-NEXT: ntl.all
6873 ; CHECK-RV32-NEXT: sh a2, 0(a0)
6874 ; CHECK-RV32-NEXT: ret
6875 ;
6876 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_v8i16:
6877 ; CHECK-RV64C: # %bb.0:
6878 ; CHECK-RV64C-NEXT: lh a6, 0(a1)
6879 ; CHECK-RV64C-NEXT: lh a7, 8(a1)
6880 ; CHECK-RV64C-NEXT: lh t0, 16(a1)
6881 ; CHECK-RV64C-NEXT: lh a5, 24(a1)
6882 ; CHECK-RV64C-NEXT: lh a2, 56(a1)
6883 ; CHECK-RV64C-NEXT: lh a3, 48(a1)
6884 ; CHECK-RV64C-NEXT: lh a4, 40(a1)
6885 ; CHECK-RV64C-NEXT: lh a1, 32(a1)
6886 ; CHECK-RV64C-NEXT: c.ntl.all
6887 ; CHECK-RV64C-NEXT: sh a2, 14(a0)
6888 ; CHECK-RV64C-NEXT: c.ntl.all
6889 ; CHECK-RV64C-NEXT: sh a3, 12(a0)
6890 ; CHECK-RV64C-NEXT: c.ntl.all
6891 ; CHECK-RV64C-NEXT: sh a4, 10(a0)
6892 ; CHECK-RV64C-NEXT: c.ntl.all
6893 ; CHECK-RV64C-NEXT: sh a1, 8(a0)
6894 ; CHECK-RV64C-NEXT: c.ntl.all
6895 ; CHECK-RV64C-NEXT: sh a5, 6(a0)
6896 ; CHECK-RV64C-NEXT: c.ntl.all
6897 ; CHECK-RV64C-NEXT: sh t0, 4(a0)
6898 ; CHECK-RV64C-NEXT: c.ntl.all
6899 ; CHECK-RV64C-NEXT: sh a7, 2(a0)
6900 ; CHECK-RV64C-NEXT: c.ntl.all
6901 ; CHECK-RV64C-NEXT: sh a6, 0(a0)
6902 ; CHECK-RV64C-NEXT: ret
6903 ;
6904 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_v8i16:
6905 ; CHECK-RV32C: # %bb.0:
6906 ; CHECK-RV32C-NEXT: lh a6, 0(a1)
6907 ; CHECK-RV32C-NEXT: lh a7, 4(a1)
6908 ; CHECK-RV32C-NEXT: lh t0, 8(a1)
6909 ; CHECK-RV32C-NEXT: lh a5, 12(a1)
6910 ; CHECK-RV32C-NEXT: lh a2, 28(a1)
6911 ; CHECK-RV32C-NEXT: lh a3, 24(a1)
6912 ; CHECK-RV32C-NEXT: lh a4, 20(a1)
6913 ; CHECK-RV32C-NEXT: lh a1, 16(a1)
6914 ; CHECK-RV32C-NEXT: c.ntl.all
6915 ; CHECK-RV32C-NEXT: sh a2, 14(a0)
6916 ; CHECK-RV32C-NEXT: c.ntl.all
6917 ; CHECK-RV32C-NEXT: sh a3, 12(a0)
6918 ; CHECK-RV32C-NEXT: c.ntl.all
6919 ; CHECK-RV32C-NEXT: sh a4, 10(a0)
6920 ; CHECK-RV32C-NEXT: c.ntl.all
6921 ; CHECK-RV32C-NEXT: sh a1, 8(a0)
6922 ; CHECK-RV32C-NEXT: c.ntl.all
6923 ; CHECK-RV32C-NEXT: sh a5, 6(a0)
6924 ; CHECK-RV32C-NEXT: c.ntl.all
6925 ; CHECK-RV32C-NEXT: sh t0, 4(a0)
6926 ; CHECK-RV32C-NEXT: c.ntl.all
6927 ; CHECK-RV32C-NEXT: sh a7, 2(a0)
6928 ; CHECK-RV32C-NEXT: c.ntl.all
6929 ; CHECK-RV32C-NEXT: sh a6, 0(a0)
6930 ; CHECK-RV32C-NEXT: ret
6931 ;
6932 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_v8i16:
6933 ; CHECK-RV64V: # %bb.0:
6934 ; CHECK-RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
6935 ; CHECK-RV64V-NEXT: ntl.all
6936 ; CHECK-RV64V-NEXT: vse16.v v8, (a0)
6937 ; CHECK-RV64V-NEXT: ret
6938 ;
6939 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_v8i16:
6940 ; CHECK-RV32V: # %bb.0:
6941 ; CHECK-RV32V-NEXT: vsetivli zero, 8, e16, m1, ta, ma
6942 ; CHECK-RV32V-NEXT: ntl.all
6943 ; CHECK-RV32V-NEXT: vse16.v v8, (a0)
6944 ; CHECK-RV32V-NEXT: ret
6945 store <8 x i16> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
6946 ret void
6947 }
6949 define void @test_nontemporal_ALL_store_v4i32(ptr %p, <4 x i32> %v) {
6950 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_v4i32:
6951 ; CHECK-RV64: # %bb.0:
6952 ; CHECK-RV64-NEXT: lw a2, 24(a1)
6953 ; CHECK-RV64-NEXT: lw a3, 16(a1)
6954 ; CHECK-RV64-NEXT: lw a4, 8(a1)
6955 ; CHECK-RV64-NEXT: lw a1, 0(a1)
6956 ; CHECK-RV64-NEXT: ntl.all
6957 ; CHECK-RV64-NEXT: sw a2, 12(a0)
6958 ; CHECK-RV64-NEXT: ntl.all
6959 ; CHECK-RV64-NEXT: sw a3, 8(a0)
6960 ; CHECK-RV64-NEXT: ntl.all
6961 ; CHECK-RV64-NEXT: sw a4, 4(a0)
6962 ; CHECK-RV64-NEXT: ntl.all
6963 ; CHECK-RV64-NEXT: sw a1, 0(a0)
6964 ; CHECK-RV64-NEXT: ret
6965 ;
6966 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_v4i32:
6967 ; CHECK-RV32: # %bb.0:
6968 ; CHECK-RV32-NEXT: lw a2, 12(a1)
6969 ; CHECK-RV32-NEXT: lw a3, 8(a1)
6970 ; CHECK-RV32-NEXT: lw a4, 4(a1)
6971 ; CHECK-RV32-NEXT: lw a1, 0(a1)
6972 ; CHECK-RV32-NEXT: ntl.all
6973 ; CHECK-RV32-NEXT: sw a2, 12(a0)
6974 ; CHECK-RV32-NEXT: ntl.all
6975 ; CHECK-RV32-NEXT: sw a3, 8(a0)
6976 ; CHECK-RV32-NEXT: ntl.all
6977 ; CHECK-RV32-NEXT: sw a4, 4(a0)
6978 ; CHECK-RV32-NEXT: ntl.all
6979 ; CHECK-RV32-NEXT: sw a1, 0(a0)
6980 ; CHECK-RV32-NEXT: ret
6981 ;
6982 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_v4i32:
6983 ; CHECK-RV64C: # %bb.0:
6984 ; CHECK-RV64C-NEXT: lw a2, 24(a1)
6985 ; CHECK-RV64C-NEXT: lw a3, 16(a1)
6986 ; CHECK-RV64C-NEXT: lw a4, 8(a1)
6987 ; CHECK-RV64C-NEXT: lw a1, 0(a1)
6988 ; CHECK-RV64C-NEXT: c.ntl.all
6989 ; CHECK-RV64C-NEXT: sw a2, 12(a0)
6990 ; CHECK-RV64C-NEXT: c.ntl.all
6991 ; CHECK-RV64C-NEXT: sw a3, 8(a0)
6992 ; CHECK-RV64C-NEXT: c.ntl.all
6993 ; CHECK-RV64C-NEXT: sw a4, 4(a0)
6994 ; CHECK-RV64C-NEXT: c.ntl.all
6995 ; CHECK-RV64C-NEXT: sw a1, 0(a0)
6996 ; CHECK-RV64C-NEXT: ret
6997 ;
6998 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_v4i32:
6999 ; CHECK-RV32C: # %bb.0:
7000 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
7001 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
7002 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
7003 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
7004 ; CHECK-RV32C-NEXT: c.ntl.all
7005 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
7006 ; CHECK-RV32C-NEXT: c.ntl.all
7007 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
7008 ; CHECK-RV32C-NEXT: c.ntl.all
7009 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
7010 ; CHECK-RV32C-NEXT: c.ntl.all
7011 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
7012 ; CHECK-RV32C-NEXT: ret
7013 ;
7014 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_v4i32:
7015 ; CHECK-RV64V: # %bb.0:
7016 ; CHECK-RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
7017 ; CHECK-RV64V-NEXT: ntl.all
7018 ; CHECK-RV64V-NEXT: vse32.v v8, (a0)
7019 ; CHECK-RV64V-NEXT: ret
7020 ;
7021 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_v4i32:
7022 ; CHECK-RV32V: # %bb.0:
7023 ; CHECK-RV32V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
7024 ; CHECK-RV32V-NEXT: ntl.all
7025 ; CHECK-RV32V-NEXT: vse32.v v8, (a0)
7026 ; CHECK-RV32V-NEXT: ret
7027 store <4 x i32> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
7028 ret void
7029 }
7031 define void @test_nontemporal_ALL_store_v2i64(ptr %p, <2 x i64> %v) {
7032 ; CHECK-RV64-LABEL: test_nontemporal_ALL_store_v2i64:
7033 ; CHECK-RV64: # %bb.0:
7034 ; CHECK-RV64-NEXT: ntl.all
7035 ; CHECK-RV64-NEXT: sd a2, 8(a0)
7036 ; CHECK-RV64-NEXT: ntl.all
7037 ; CHECK-RV64-NEXT: sd a1, 0(a0)
7038 ; CHECK-RV64-NEXT: ret
7039 ;
7040 ; CHECK-RV32-LABEL: test_nontemporal_ALL_store_v2i64:
7041 ; CHECK-RV32: # %bb.0:
7042 ; CHECK-RV32-NEXT: lw a2, 12(a1)
7043 ; CHECK-RV32-NEXT: lw a3, 8(a1)
7044 ; CHECK-RV32-NEXT: lw a4, 4(a1)
7045 ; CHECK-RV32-NEXT: lw a1, 0(a1)
7046 ; CHECK-RV32-NEXT: ntl.all
7047 ; CHECK-RV32-NEXT: sw a2, 12(a0)
7048 ; CHECK-RV32-NEXT: ntl.all
7049 ; CHECK-RV32-NEXT: sw a3, 8(a0)
7050 ; CHECK-RV32-NEXT: ntl.all
7051 ; CHECK-RV32-NEXT: sw a4, 4(a0)
7052 ; CHECK-RV32-NEXT: ntl.all
7053 ; CHECK-RV32-NEXT: sw a1, 0(a0)
7054 ; CHECK-RV32-NEXT: ret
7055 ;
7056 ; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_v2i64:
7057 ; CHECK-RV64C: # %bb.0:
7058 ; CHECK-RV64C-NEXT: c.ntl.all
7059 ; CHECK-RV64C-NEXT: sd a2, 8(a0)
7060 ; CHECK-RV64C-NEXT: c.ntl.all
7061 ; CHECK-RV64C-NEXT: sd a1, 0(a0)
7062 ; CHECK-RV64C-NEXT: ret
7063 ;
7064 ; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_v2i64:
7065 ; CHECK-RV32C: # %bb.0:
7066 ; CHECK-RV32C-NEXT: lw a2, 12(a1)
7067 ; CHECK-RV32C-NEXT: lw a3, 8(a1)
7068 ; CHECK-RV32C-NEXT: lw a4, 4(a1)
7069 ; CHECK-RV32C-NEXT: lw a1, 0(a1)
7070 ; CHECK-RV32C-NEXT: c.ntl.all
7071 ; CHECK-RV32C-NEXT: sw a2, 12(a0)
7072 ; CHECK-RV32C-NEXT: c.ntl.all
7073 ; CHECK-RV32C-NEXT: sw a3, 8(a0)
7074 ; CHECK-RV32C-NEXT: c.ntl.all
7075 ; CHECK-RV32C-NEXT: sw a4, 4(a0)
7076 ; CHECK-RV32C-NEXT: c.ntl.all
7077 ; CHECK-RV32C-NEXT: sw a1, 0(a0)
7078 ; CHECK-RV32C-NEXT: ret
7079 ;
7080 ; CHECK-RV64V-LABEL: test_nontemporal_ALL_store_v2i64:
7081 ; CHECK-RV64V: # %bb.0:
7082 ; CHECK-RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
7083 ; CHECK-RV64V-NEXT: ntl.all
7084 ; CHECK-RV64V-NEXT: vse64.v v8, (a0)
7085 ; CHECK-RV64V-NEXT: ret
7086 ;
7087 ; CHECK-RV32V-LABEL: test_nontemporal_ALL_store_v2i64:
7088 ; CHECK-RV32V: # %bb.0:
7089 ; CHECK-RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
7090 ; CHECK-RV32V-NEXT: ntl.all
7091 ; CHECK-RV32V-NEXT: vse64.v v8, (a0)
7092 ; CHECK-RV32V-NEXT: ret
7093 store <2 x i64> %v, ptr %p, !nontemporal !0, !riscv-nontemporal-domain !4
7094 ret void
7095 }
7098 !0 = !{i32 1}
7099 !1 = !{i32 2}
7100 !2 = !{i32 3}
7101 !3 = !{i32 4}
7102 !4 = !{i32 5}