| blob | 3bddcf798f66bf5c271b2d45ea3fa5188f37cda8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV32,RV32I
3 ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV64,RV64I
4 ; RUN: llc -mtriple=riscv32 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV32,RV32F
5 ; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64,RV64F
6 ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32,RV32D
7 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64,RV64D
8 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
9 ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
11 define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
12 ; CHECK-ZVE64X-LABEL: cttz_nxv1i8:
13 ; CHECK-ZVE64X: # %bb.0:
14 ; CHECK-ZVE64X-NEXT: li a0, 1
15 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
16 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
17 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
18 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
19 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
20 ; CHECK-ZVE64X-NEXT: li a0, 85
21 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
22 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
23 ; CHECK-ZVE64X-NEXT: li a0, 51
24 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
25 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
26 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
27 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
28 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
29 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
30 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
31 ; CHECK-ZVE64X-NEXT: ret
32 ;
33 ; CHECK-F-LABEL: cttz_nxv1i8:
34 ; CHECK-F: # %bb.0:
35 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
36 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
37 ; CHECK-F-NEXT: vand.vv v9, v8, v9
38 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
39 ; CHECK-F-NEXT: vzext.vf2 v10, v9
40 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v10
41 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
42 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
43 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
44 ; CHECK-F-NEXT: li a0, 127
45 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
46 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
47 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
48 ; CHECK-F-NEXT: ret
49 ;
50 ; CHECK-D-LABEL: cttz_nxv1i8:
51 ; CHECK-D: # %bb.0:
52 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
53 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
54 ; CHECK-D-NEXT: vand.vv v9, v8, v9
55 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
56 ; CHECK-D-NEXT: vzext.vf2 v10, v9
57 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v10
58 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
59 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
60 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
61 ; CHECK-D-NEXT: li a0, 127
62 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
63 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
64 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
65 ; CHECK-D-NEXT: ret
66 ;
67 ; CHECK-ZVBB-LABEL: cttz_nxv1i8:
68 ; CHECK-ZVBB: # %bb.0:
69 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
70 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
71 ; CHECK-ZVBB-NEXT: ret
72 %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
73 ret <vscale x 1 x i8> %a
74 }
75 declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
77 define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
78 ; CHECK-ZVE64X-LABEL: cttz_nxv2i8:
79 ; CHECK-ZVE64X: # %bb.0:
80 ; CHECK-ZVE64X-NEXT: li a0, 1
81 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
82 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
83 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
84 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
85 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
86 ; CHECK-ZVE64X-NEXT: li a0, 85
87 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
88 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
89 ; CHECK-ZVE64X-NEXT: li a0, 51
90 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
91 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
92 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
93 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
94 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
95 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
96 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
97 ; CHECK-ZVE64X-NEXT: ret
98 ;
99 ; CHECK-F-LABEL: cttz_nxv2i8:
100 ; CHECK-F: # %bb.0:
101 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
102 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
103 ; CHECK-F-NEXT: vand.vv v9, v8, v9
104 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
105 ; CHECK-F-NEXT: vzext.vf2 v10, v9
106 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v10
107 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
108 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
109 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
110 ; CHECK-F-NEXT: li a0, 127
111 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
112 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
113 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
114 ; CHECK-F-NEXT: ret
115 ;
116 ; CHECK-D-LABEL: cttz_nxv2i8:
117 ; CHECK-D: # %bb.0:
118 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
119 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
120 ; CHECK-D-NEXT: vand.vv v9, v8, v9
121 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
122 ; CHECK-D-NEXT: vzext.vf2 v10, v9
123 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v10
124 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
125 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
126 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
127 ; CHECK-D-NEXT: li a0, 127
128 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
129 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
130 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
131 ; CHECK-D-NEXT: ret
132 ;
133 ; CHECK-ZVBB-LABEL: cttz_nxv2i8:
134 ; CHECK-ZVBB: # %bb.0:
135 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
136 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
137 ; CHECK-ZVBB-NEXT: ret
138 %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
139 ret <vscale x 2 x i8> %a
140 }
141 declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
143 define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
144 ; CHECK-ZVE64X-LABEL: cttz_nxv4i8:
145 ; CHECK-ZVE64X: # %bb.0:
146 ; CHECK-ZVE64X-NEXT: li a0, 1
147 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
148 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
149 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
150 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
151 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
152 ; CHECK-ZVE64X-NEXT: li a0, 85
153 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
154 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
155 ; CHECK-ZVE64X-NEXT: li a0, 51
156 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
157 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
158 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
159 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
160 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
161 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
162 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
163 ; CHECK-ZVE64X-NEXT: ret
164 ;
165 ; CHECK-F-LABEL: cttz_nxv4i8:
166 ; CHECK-F: # %bb.0:
167 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
168 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
169 ; CHECK-F-NEXT: vand.vv v9, v8, v9
170 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
171 ; CHECK-F-NEXT: vzext.vf2 v10, v9
172 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
173 ; CHECK-F-NEXT: vnsrl.wi v9, v12, 23
174 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
175 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
176 ; CHECK-F-NEXT: li a0, 127
177 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
178 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
179 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
180 ; CHECK-F-NEXT: ret
181 ;
182 ; CHECK-D-LABEL: cttz_nxv4i8:
183 ; CHECK-D: # %bb.0:
184 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
185 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
186 ; CHECK-D-NEXT: vand.vv v9, v8, v9
187 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m1, ta, ma
188 ; CHECK-D-NEXT: vzext.vf2 v10, v9
189 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
190 ; CHECK-D-NEXT: vnsrl.wi v9, v12, 23
191 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
192 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
193 ; CHECK-D-NEXT: li a0, 127
194 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
195 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
196 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
197 ; CHECK-D-NEXT: ret
198 ;
199 ; CHECK-ZVBB-LABEL: cttz_nxv4i8:
200 ; CHECK-ZVBB: # %bb.0:
201 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
202 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
203 ; CHECK-ZVBB-NEXT: ret
204 %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
205 ret <vscale x 4 x i8> %a
206 }
207 declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
209 define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
210 ; CHECK-ZVE64X-LABEL: cttz_nxv8i8:
211 ; CHECK-ZVE64X: # %bb.0:
212 ; CHECK-ZVE64X-NEXT: li a0, 1
213 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m1, ta, ma
214 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
215 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
216 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
217 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
218 ; CHECK-ZVE64X-NEXT: li a0, 85
219 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
220 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
221 ; CHECK-ZVE64X-NEXT: li a0, 51
222 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
223 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
224 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
225 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
226 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
227 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
228 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
229 ; CHECK-ZVE64X-NEXT: ret
230 ;
231 ; CHECK-F-LABEL: cttz_nxv8i8:
232 ; CHECK-F: # %bb.0:
233 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m1, ta, ma
234 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
235 ; CHECK-F-NEXT: vand.vv v9, v8, v9
236 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
237 ; CHECK-F-NEXT: vzext.vf2 v10, v9
238 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
239 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 23
240 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
241 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 0
242 ; CHECK-F-NEXT: li a0, 127
243 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
244 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
245 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
246 ; CHECK-F-NEXT: ret
247 ;
248 ; CHECK-D-LABEL: cttz_nxv8i8:
249 ; CHECK-D: # %bb.0:
250 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m1, ta, ma
251 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
252 ; CHECK-D-NEXT: vand.vv v9, v8, v9
253 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m2, ta, ma
254 ; CHECK-D-NEXT: vzext.vf2 v10, v9
255 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
256 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 23
257 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m1, ta, ma
258 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 0
259 ; CHECK-D-NEXT: li a0, 127
260 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
261 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
262 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
263 ; CHECK-D-NEXT: ret
264 ;
265 ; CHECK-ZVBB-LABEL: cttz_nxv8i8:
266 ; CHECK-ZVBB: # %bb.0:
267 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
268 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
269 ; CHECK-ZVBB-NEXT: ret
270 %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
271 ret <vscale x 8 x i8> %a
272 }
273 declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
275 define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
276 ; CHECK-ZVE64X-LABEL: cttz_nxv16i8:
277 ; CHECK-ZVE64X: # %bb.0:
278 ; CHECK-ZVE64X-NEXT: li a0, 1
279 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
280 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
281 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
282 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
283 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
284 ; CHECK-ZVE64X-NEXT: li a0, 85
285 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
286 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
287 ; CHECK-ZVE64X-NEXT: li a0, 51
288 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
289 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
290 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
291 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
292 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
293 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
294 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
295 ; CHECK-ZVE64X-NEXT: ret
296 ;
297 ; CHECK-F-LABEL: cttz_nxv16i8:
298 ; CHECK-F: # %bb.0:
299 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m2, ta, ma
300 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
301 ; CHECK-F-NEXT: vand.vv v10, v8, v10
302 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m4, ta, ma
303 ; CHECK-F-NEXT: vzext.vf2 v12, v10
304 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
305 ; CHECK-F-NEXT: vnsrl.wi v12, v16, 23
306 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m2, ta, ma
307 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 0
308 ; CHECK-F-NEXT: li a0, 127
309 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
310 ; CHECK-F-NEXT: vsub.vx v8, v10, a0
311 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
312 ; CHECK-F-NEXT: ret
313 ;
314 ; CHECK-D-LABEL: cttz_nxv16i8:
315 ; CHECK-D: # %bb.0:
316 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m2, ta, ma
317 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
318 ; CHECK-D-NEXT: vand.vv v10, v8, v10
319 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m4, ta, ma
320 ; CHECK-D-NEXT: vzext.vf2 v12, v10
321 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
322 ; CHECK-D-NEXT: vnsrl.wi v12, v16, 23
323 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m2, ta, ma
324 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 0
325 ; CHECK-D-NEXT: li a0, 127
326 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
327 ; CHECK-D-NEXT: vsub.vx v8, v10, a0
328 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
329 ; CHECK-D-NEXT: ret
330 ;
331 ; CHECK-ZVBB-LABEL: cttz_nxv16i8:
332 ; CHECK-ZVBB: # %bb.0:
333 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
334 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
335 ; CHECK-ZVBB-NEXT: ret
336 %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
337 ret <vscale x 16 x i8> %a
338 }
339 declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
341 define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
342 ; CHECK-LABEL: cttz_nxv32i8:
343 ; CHECK: # %bb.0:
344 ; CHECK-NEXT: li a0, 1
345 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
346 ; CHECK-NEXT: vsub.vx v12, v8, a0
347 ; CHECK-NEXT: vnot.v v8, v8
348 ; CHECK-NEXT: vand.vv v8, v8, v12
349 ; CHECK-NEXT: vsrl.vi v12, v8, 1
350 ; CHECK-NEXT: li a0, 85
351 ; CHECK-NEXT: vand.vx v12, v12, a0
352 ; CHECK-NEXT: vsub.vv v8, v8, v12
353 ; CHECK-NEXT: li a0, 51
354 ; CHECK-NEXT: vand.vx v12, v8, a0
355 ; CHECK-NEXT: vsrl.vi v8, v8, 2
356 ; CHECK-NEXT: vand.vx v8, v8, a0
357 ; CHECK-NEXT: vadd.vv v8, v12, v8
358 ; CHECK-NEXT: vsrl.vi v12, v8, 4
359 ; CHECK-NEXT: vadd.vv v8, v8, v12
360 ; CHECK-NEXT: vand.vi v8, v8, 15
361 ; CHECK-NEXT: ret
362 ;
363 ; CHECK-ZVBB-LABEL: cttz_nxv32i8:
364 ; CHECK-ZVBB: # %bb.0:
365 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
366 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
367 ; CHECK-ZVBB-NEXT: ret
368 %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false)
369 ret <vscale x 32 x i8> %a
370 }
371 declare <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8>, i1)
373 define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
374 ; CHECK-LABEL: cttz_nxv64i8:
375 ; CHECK: # %bb.0:
376 ; CHECK-NEXT: li a0, 1
377 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
378 ; CHECK-NEXT: vsub.vx v16, v8, a0
379 ; CHECK-NEXT: vnot.v v8, v8
380 ; CHECK-NEXT: vand.vv v8, v8, v16
381 ; CHECK-NEXT: vsrl.vi v16, v8, 1
382 ; CHECK-NEXT: li a0, 85
383 ; CHECK-NEXT: vand.vx v16, v16, a0
384 ; CHECK-NEXT: vsub.vv v8, v8, v16
385 ; CHECK-NEXT: li a0, 51
386 ; CHECK-NEXT: vand.vx v16, v8, a0
387 ; CHECK-NEXT: vsrl.vi v8, v8, 2
388 ; CHECK-NEXT: vand.vx v8, v8, a0
389 ; CHECK-NEXT: vadd.vv v8, v16, v8
390 ; CHECK-NEXT: vsrl.vi v16, v8, 4
391 ; CHECK-NEXT: vadd.vv v8, v8, v16
392 ; CHECK-NEXT: vand.vi v8, v8, 15
393 ; CHECK-NEXT: ret
394 ;
395 ; CHECK-ZVBB-LABEL: cttz_nxv64i8:
396 ; CHECK-ZVBB: # %bb.0:
397 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
398 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
399 ; CHECK-ZVBB-NEXT: ret
400 %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false)
401 ret <vscale x 64 x i8> %a
402 }
403 declare <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8>, i1)
405 define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
406 ; CHECK-ZVE64X-LABEL: cttz_nxv1i16:
407 ; CHECK-ZVE64X: # %bb.0:
408 ; CHECK-ZVE64X-NEXT: li a0, 1
409 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
410 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
411 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
412 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
413 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
414 ; CHECK-ZVE64X-NEXT: lui a0, 5
415 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
416 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
417 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
418 ; CHECK-ZVE64X-NEXT: lui a0, 3
419 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
420 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
421 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
422 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
423 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
424 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
425 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
426 ; CHECK-ZVE64X-NEXT: lui a0, 1
427 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
428 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
429 ; CHECK-ZVE64X-NEXT: li a0, 257
430 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
431 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
432 ; CHECK-ZVE64X-NEXT: ret
433 ;
434 ; CHECK-F-LABEL: cttz_nxv1i16:
435 ; CHECK-F: # %bb.0:
436 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
437 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
438 ; CHECK-F-NEXT: vand.vv v9, v8, v9
439 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
440 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
441 ; CHECK-F-NEXT: li a0, 127
442 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
443 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
444 ; CHECK-F-NEXT: li a0, 16
445 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
446 ; CHECK-F-NEXT: ret
447 ;
448 ; CHECK-D-LABEL: cttz_nxv1i16:
449 ; CHECK-D: # %bb.0:
450 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
451 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
452 ; CHECK-D-NEXT: vand.vv v9, v8, v9
453 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
454 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
455 ; CHECK-D-NEXT: li a0, 127
456 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
457 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
458 ; CHECK-D-NEXT: li a0, 16
459 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
460 ; CHECK-D-NEXT: ret
461 ;
462 ; CHECK-ZVBB-LABEL: cttz_nxv1i16:
463 ; CHECK-ZVBB: # %bb.0:
464 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
465 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
466 ; CHECK-ZVBB-NEXT: ret
467 %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
468 ret <vscale x 1 x i16> %a
469 }
470 declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
472 define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
473 ; CHECK-ZVE64X-LABEL: cttz_nxv2i16:
474 ; CHECK-ZVE64X: # %bb.0:
475 ; CHECK-ZVE64X-NEXT: li a0, 1
476 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
477 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
478 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
479 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
480 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
481 ; CHECK-ZVE64X-NEXT: lui a0, 5
482 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
483 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
484 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
485 ; CHECK-ZVE64X-NEXT: lui a0, 3
486 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
487 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
488 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
489 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
490 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
491 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
492 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
493 ; CHECK-ZVE64X-NEXT: lui a0, 1
494 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
495 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
496 ; CHECK-ZVE64X-NEXT: li a0, 257
497 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
498 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
499 ; CHECK-ZVE64X-NEXT: ret
500 ;
501 ; CHECK-F-LABEL: cttz_nxv2i16:
502 ; CHECK-F: # %bb.0:
503 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
504 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
505 ; CHECK-F-NEXT: vand.vv v9, v8, v9
506 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
507 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
508 ; CHECK-F-NEXT: li a0, 127
509 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
510 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
511 ; CHECK-F-NEXT: li a0, 16
512 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
513 ; CHECK-F-NEXT: ret
514 ;
515 ; CHECK-D-LABEL: cttz_nxv2i16:
516 ; CHECK-D: # %bb.0:
517 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
518 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
519 ; CHECK-D-NEXT: vand.vv v9, v8, v9
520 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
521 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
522 ; CHECK-D-NEXT: li a0, 127
523 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
524 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
525 ; CHECK-D-NEXT: li a0, 16
526 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
527 ; CHECK-D-NEXT: ret
528 ;
529 ; CHECK-ZVBB-LABEL: cttz_nxv2i16:
530 ; CHECK-ZVBB: # %bb.0:
531 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
532 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
533 ; CHECK-ZVBB-NEXT: ret
534 %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
535 ret <vscale x 2 x i16> %a
536 }
537 declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
539 define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
540 ; CHECK-ZVE64X-LABEL: cttz_nxv4i16:
541 ; CHECK-ZVE64X: # %bb.0:
542 ; CHECK-ZVE64X-NEXT: li a0, 1
543 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m1, ta, ma
544 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
545 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
546 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
547 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
548 ; CHECK-ZVE64X-NEXT: lui a0, 5
549 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
550 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
551 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
552 ; CHECK-ZVE64X-NEXT: lui a0, 3
553 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
554 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
555 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
556 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
557 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
558 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
559 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
560 ; CHECK-ZVE64X-NEXT: lui a0, 1
561 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
562 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
563 ; CHECK-ZVE64X-NEXT: li a0, 257
564 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
565 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
566 ; CHECK-ZVE64X-NEXT: ret
567 ;
568 ; CHECK-F-LABEL: cttz_nxv4i16:
569 ; CHECK-F: # %bb.0:
570 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
571 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
572 ; CHECK-F-NEXT: vand.vv v9, v8, v9
573 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
574 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
575 ; CHECK-F-NEXT: li a0, 127
576 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
577 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
578 ; CHECK-F-NEXT: li a0, 16
579 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
580 ; CHECK-F-NEXT: ret
581 ;
582 ; CHECK-D-LABEL: cttz_nxv4i16:
583 ; CHECK-D: # %bb.0:
584 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
585 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
586 ; CHECK-D-NEXT: vand.vv v9, v8, v9
587 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
588 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
589 ; CHECK-D-NEXT: li a0, 127
590 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
591 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
592 ; CHECK-D-NEXT: li a0, 16
593 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
594 ; CHECK-D-NEXT: ret
595 ;
596 ; CHECK-ZVBB-LABEL: cttz_nxv4i16:
597 ; CHECK-ZVBB: # %bb.0:
598 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
599 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
600 ; CHECK-ZVBB-NEXT: ret
601 %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
602 ret <vscale x 4 x i16> %a
603 }
604 declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
606 define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
607 ; CHECK-ZVE64X-LABEL: cttz_nxv8i16:
608 ; CHECK-ZVE64X: # %bb.0:
609 ; CHECK-ZVE64X-NEXT: li a0, 1
610 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
611 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
612 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
613 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
614 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
615 ; CHECK-ZVE64X-NEXT: lui a0, 5
616 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
617 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
618 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
619 ; CHECK-ZVE64X-NEXT: lui a0, 3
620 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
621 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
622 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
623 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
624 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
625 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
626 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
627 ; CHECK-ZVE64X-NEXT: lui a0, 1
628 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
629 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
630 ; CHECK-ZVE64X-NEXT: li a0, 257
631 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
632 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
633 ; CHECK-ZVE64X-NEXT: ret
634 ;
635 ; CHECK-F-LABEL: cttz_nxv8i16:
636 ; CHECK-F: # %bb.0:
637 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
638 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
639 ; CHECK-F-NEXT: vand.vv v10, v8, v10
640 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
641 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 23
642 ; CHECK-F-NEXT: li a0, 127
643 ; CHECK-F-NEXT: vsub.vx v10, v10, a0
644 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
645 ; CHECK-F-NEXT: li a0, 16
646 ; CHECK-F-NEXT: vmerge.vxm v8, v10, a0, v0
647 ; CHECK-F-NEXT: ret
648 ;
649 ; CHECK-D-LABEL: cttz_nxv8i16:
650 ; CHECK-D: # %bb.0:
651 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
652 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
653 ; CHECK-D-NEXT: vand.vv v10, v8, v10
654 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
655 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 23
656 ; CHECK-D-NEXT: li a0, 127
657 ; CHECK-D-NEXT: vsub.vx v10, v10, a0
658 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
659 ; CHECK-D-NEXT: li a0, 16
660 ; CHECK-D-NEXT: vmerge.vxm v8, v10, a0, v0
661 ; CHECK-D-NEXT: ret
662 ;
663 ; CHECK-ZVBB-LABEL: cttz_nxv8i16:
664 ; CHECK-ZVBB: # %bb.0:
665 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
666 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
667 ; CHECK-ZVBB-NEXT: ret
668 %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
669 ret <vscale x 8 x i16> %a
670 }
671 declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
673 define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
674 ; CHECK-ZVE64X-LABEL: cttz_nxv16i16:
675 ; CHECK-ZVE64X: # %bb.0:
676 ; CHECK-ZVE64X-NEXT: li a0, 1
677 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
678 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
679 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
680 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
681 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
682 ; CHECK-ZVE64X-NEXT: lui a0, 5
683 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
684 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
685 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
686 ; CHECK-ZVE64X-NEXT: lui a0, 3
687 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
688 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
689 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
690 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
691 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
692 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
693 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
694 ; CHECK-ZVE64X-NEXT: lui a0, 1
695 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
696 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
697 ; CHECK-ZVE64X-NEXT: li a0, 257
698 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
699 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
700 ; CHECK-ZVE64X-NEXT: ret
701 ;
702 ; CHECK-F-LABEL: cttz_nxv16i16:
703 ; CHECK-F: # %bb.0:
704 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
705 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
706 ; CHECK-F-NEXT: vand.vv v12, v8, v12
707 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
708 ; CHECK-F-NEXT: vnsrl.wi v12, v16, 23
709 ; CHECK-F-NEXT: li a0, 127
710 ; CHECK-F-NEXT: vsub.vx v12, v12, a0
711 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
712 ; CHECK-F-NEXT: li a0, 16
713 ; CHECK-F-NEXT: vmerge.vxm v8, v12, a0, v0
714 ; CHECK-F-NEXT: ret
715 ;
716 ; CHECK-D-LABEL: cttz_nxv16i16:
717 ; CHECK-D: # %bb.0:
718 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
719 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
720 ; CHECK-D-NEXT: vand.vv v12, v8, v12
721 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
722 ; CHECK-D-NEXT: vnsrl.wi v12, v16, 23
723 ; CHECK-D-NEXT: li a0, 127
724 ; CHECK-D-NEXT: vsub.vx v12, v12, a0
725 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
726 ; CHECK-D-NEXT: li a0, 16
727 ; CHECK-D-NEXT: vmerge.vxm v8, v12, a0, v0
728 ; CHECK-D-NEXT: ret
729 ;
730 ; CHECK-ZVBB-LABEL: cttz_nxv16i16:
731 ; CHECK-ZVBB: # %bb.0:
732 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
733 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
734 ; CHECK-ZVBB-NEXT: ret
735 %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
736 ret <vscale x 16 x i16> %a
737 }
738 declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
740 define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
741 ; CHECK-LABEL: cttz_nxv32i16:
742 ; CHECK: # %bb.0:
743 ; CHECK-NEXT: li a0, 1
744 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
745 ; CHECK-NEXT: vsub.vx v16, v8, a0
746 ; CHECK-NEXT: vnot.v v8, v8
747 ; CHECK-NEXT: vand.vv v8, v8, v16
748 ; CHECK-NEXT: vsrl.vi v16, v8, 1
749 ; CHECK-NEXT: lui a0, 5
750 ; CHECK-NEXT: addi a0, a0, 1365
751 ; CHECK-NEXT: vand.vx v16, v16, a0
752 ; CHECK-NEXT: vsub.vv v8, v8, v16
753 ; CHECK-NEXT: lui a0, 3
754 ; CHECK-NEXT: addi a0, a0, 819
755 ; CHECK-NEXT: vand.vx v16, v8, a0
756 ; CHECK-NEXT: vsrl.vi v8, v8, 2
757 ; CHECK-NEXT: vand.vx v8, v8, a0
758 ; CHECK-NEXT: vadd.vv v8, v16, v8
759 ; CHECK-NEXT: vsrl.vi v16, v8, 4
760 ; CHECK-NEXT: vadd.vv v8, v8, v16
761 ; CHECK-NEXT: lui a0, 1
762 ; CHECK-NEXT: addi a0, a0, -241
763 ; CHECK-NEXT: vand.vx v8, v8, a0
764 ; CHECK-NEXT: li a0, 257
765 ; CHECK-NEXT: vmul.vx v8, v8, a0
766 ; CHECK-NEXT: vsrl.vi v8, v8, 8
767 ; CHECK-NEXT: ret
768 ;
769 ; CHECK-ZVBB-LABEL: cttz_nxv32i16:
770 ; CHECK-ZVBB: # %bb.0:
771 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
772 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
773 ; CHECK-ZVBB-NEXT: ret
774 %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false)
775 ret <vscale x 32 x i16> %a
776 }
777 declare <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16>, i1)
779 define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
780 ; CHECK-ZVE64X-LABEL: cttz_nxv1i32:
781 ; CHECK-ZVE64X: # %bb.0:
782 ; CHECK-ZVE64X-NEXT: li a0, 1
783 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
784 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
785 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
786 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
787 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
788 ; CHECK-ZVE64X-NEXT: lui a0, 349525
789 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
790 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
791 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
792 ; CHECK-ZVE64X-NEXT: lui a0, 209715
793 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
794 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
795 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
796 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
797 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
798 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
799 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
800 ; CHECK-ZVE64X-NEXT: lui a0, 61681
801 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
802 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
803 ; CHECK-ZVE64X-NEXT: lui a0, 4112
804 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
805 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
806 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
807 ; CHECK-ZVE64X-NEXT: ret
808 ;
809 ; CHECK-F-LABEL: cttz_nxv1i32:
810 ; CHECK-F: # %bb.0:
811 ; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
812 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
813 ; CHECK-F-NEXT: vand.vv v9, v8, v9
814 ; CHECK-F-NEXT: fsrmi a0, 1
815 ; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
816 ; CHECK-F-NEXT: vsrl.vi v9, v9, 23
817 ; CHECK-F-NEXT: li a1, 127
818 ; CHECK-F-NEXT: vsub.vx v9, v9, a1
819 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
820 ; CHECK-F-NEXT: li a1, 32
821 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a1, v0
822 ; CHECK-F-NEXT: fsrm a0
823 ; CHECK-F-NEXT: ret
824 ;
825 ; CHECK-D-LABEL: cttz_nxv1i32:
826 ; CHECK-D: # %bb.0:
827 ; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
828 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
829 ; CHECK-D-NEXT: vand.vv v9, v8, v9
830 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
831 ; CHECK-D-NEXT: li a0, 52
832 ; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
833 ; CHECK-D-NEXT: li a0, 1023
834 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
835 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
836 ; CHECK-D-NEXT: li a0, 32
837 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
838 ; CHECK-D-NEXT: ret
839 ;
840 ; CHECK-ZVBB-LABEL: cttz_nxv1i32:
841 ; CHECK-ZVBB: # %bb.0:
842 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
843 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
844 ; CHECK-ZVBB-NEXT: ret
845 %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
846 ret <vscale x 1 x i32> %a
847 }
848 declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
850 define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
851 ; CHECK-ZVE64X-LABEL: cttz_nxv2i32:
852 ; CHECK-ZVE64X: # %bb.0:
853 ; CHECK-ZVE64X-NEXT: li a0, 1
854 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m1, ta, ma
855 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
856 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
857 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
858 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
859 ; CHECK-ZVE64X-NEXT: lui a0, 349525
860 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
861 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
862 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
863 ; CHECK-ZVE64X-NEXT: lui a0, 209715
864 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
865 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
866 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
867 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
868 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
869 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
870 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
871 ; CHECK-ZVE64X-NEXT: lui a0, 61681
872 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
873 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
874 ; CHECK-ZVE64X-NEXT: lui a0, 4112
875 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
876 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
877 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
878 ; CHECK-ZVE64X-NEXT: ret
879 ;
880 ; CHECK-F-LABEL: cttz_nxv2i32:
881 ; CHECK-F: # %bb.0:
882 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
883 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
884 ; CHECK-F-NEXT: vand.vv v9, v8, v9
885 ; CHECK-F-NEXT: fsrmi a0, 1
886 ; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
887 ; CHECK-F-NEXT: vsrl.vi v9, v9, 23
888 ; CHECK-F-NEXT: li a1, 127
889 ; CHECK-F-NEXT: vsub.vx v9, v9, a1
890 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
891 ; CHECK-F-NEXT: li a1, 32
892 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a1, v0
893 ; CHECK-F-NEXT: fsrm a0
894 ; CHECK-F-NEXT: ret
895 ;
896 ; CHECK-D-LABEL: cttz_nxv2i32:
897 ; CHECK-D: # %bb.0:
898 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
899 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
900 ; CHECK-D-NEXT: vand.vv v9, v8, v9
901 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
902 ; CHECK-D-NEXT: li a0, 52
903 ; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
904 ; CHECK-D-NEXT: li a0, 1023
905 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
906 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
907 ; CHECK-D-NEXT: li a0, 32
908 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
909 ; CHECK-D-NEXT: ret
910 ;
911 ; CHECK-ZVBB-LABEL: cttz_nxv2i32:
912 ; CHECK-ZVBB: # %bb.0:
913 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
914 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
915 ; CHECK-ZVBB-NEXT: ret
916 %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
917 ret <vscale x 2 x i32> %a
918 }
919 declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
921 define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
922 ; CHECK-ZVE64X-LABEL: cttz_nxv4i32:
923 ; CHECK-ZVE64X: # %bb.0:
924 ; CHECK-ZVE64X-NEXT: li a0, 1
925 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
926 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
927 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
928 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
929 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
930 ; CHECK-ZVE64X-NEXT: lui a0, 349525
931 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
932 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
933 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
934 ; CHECK-ZVE64X-NEXT: lui a0, 209715
935 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
936 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
937 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
938 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
939 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
940 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
941 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
942 ; CHECK-ZVE64X-NEXT: lui a0, 61681
943 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
944 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
945 ; CHECK-ZVE64X-NEXT: lui a0, 4112
946 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
947 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
948 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
949 ; CHECK-ZVE64X-NEXT: ret
950 ;
951 ; CHECK-F-LABEL: cttz_nxv4i32:
952 ; CHECK-F: # %bb.0:
953 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
954 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
955 ; CHECK-F-NEXT: vand.vv v10, v8, v10
956 ; CHECK-F-NEXT: fsrmi a0, 1
957 ; CHECK-F-NEXT: vfcvt.f.xu.v v10, v10
958 ; CHECK-F-NEXT: vsrl.vi v10, v10, 23
959 ; CHECK-F-NEXT: li a1, 127
960 ; CHECK-F-NEXT: vsub.vx v10, v10, a1
961 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
962 ; CHECK-F-NEXT: li a1, 32
963 ; CHECK-F-NEXT: vmerge.vxm v8, v10, a1, v0
964 ; CHECK-F-NEXT: fsrm a0
965 ; CHECK-F-NEXT: ret
966 ;
967 ; CHECK-D-LABEL: cttz_nxv4i32:
968 ; CHECK-D: # %bb.0:
969 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
970 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
971 ; CHECK-D-NEXT: vand.vv v10, v8, v10
972 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
973 ; CHECK-D-NEXT: li a0, 52
974 ; CHECK-D-NEXT: vnsrl.wx v10, v12, a0
975 ; CHECK-D-NEXT: li a0, 1023
976 ; CHECK-D-NEXT: vsub.vx v10, v10, a0
977 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
978 ; CHECK-D-NEXT: li a0, 32
979 ; CHECK-D-NEXT: vmerge.vxm v8, v10, a0, v0
980 ; CHECK-D-NEXT: ret
981 ;
982 ; CHECK-ZVBB-LABEL: cttz_nxv4i32:
983 ; CHECK-ZVBB: # %bb.0:
984 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
985 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
986 ; CHECK-ZVBB-NEXT: ret
987 %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
988 ret <vscale x 4 x i32> %a
989 }
990 declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
992 define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
993 ; CHECK-ZVE64X-LABEL: cttz_nxv8i32:
994 ; CHECK-ZVE64X: # %bb.0:
995 ; CHECK-ZVE64X-NEXT: li a0, 1
996 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
997 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
998 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
999 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
1000 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
1001 ; CHECK-ZVE64X-NEXT: lui a0, 349525
1002 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
1003 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
1004 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
1005 ; CHECK-ZVE64X-NEXT: lui a0, 209715
1006 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
1007 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
1008 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1009 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1010 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
1011 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
1012 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
1013 ; CHECK-ZVE64X-NEXT: lui a0, 61681
1014 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
1015 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1016 ; CHECK-ZVE64X-NEXT: lui a0, 4112
1017 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
1018 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
1019 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
1020 ; CHECK-ZVE64X-NEXT: ret
1021 ;
1022 ; CHECK-F-LABEL: cttz_nxv8i32:
1023 ; CHECK-F: # %bb.0:
1024 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1025 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
1026 ; CHECK-F-NEXT: vand.vv v12, v8, v12
1027 ; CHECK-F-NEXT: fsrmi a0, 1
1028 ; CHECK-F-NEXT: vfcvt.f.xu.v v12, v12
1029 ; CHECK-F-NEXT: vsrl.vi v12, v12, 23
1030 ; CHECK-F-NEXT: li a1, 127
1031 ; CHECK-F-NEXT: vsub.vx v12, v12, a1
1032 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1033 ; CHECK-F-NEXT: li a1, 32
1034 ; CHECK-F-NEXT: vmerge.vxm v8, v12, a1, v0
1035 ; CHECK-F-NEXT: fsrm a0
1036 ; CHECK-F-NEXT: ret
1037 ;
1038 ; CHECK-D-LABEL: cttz_nxv8i32:
1039 ; CHECK-D: # %bb.0:
1040 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1041 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
1042 ; CHECK-D-NEXT: vand.vv v12, v8, v12
1043 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
1044 ; CHECK-D-NEXT: li a0, 52
1045 ; CHECK-D-NEXT: vnsrl.wx v12, v16, a0
1046 ; CHECK-D-NEXT: li a0, 1023
1047 ; CHECK-D-NEXT: vsub.vx v12, v12, a0
1048 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1049 ; CHECK-D-NEXT: li a0, 32
1050 ; CHECK-D-NEXT: vmerge.vxm v8, v12, a0, v0
1051 ; CHECK-D-NEXT: ret
1052 ;
1053 ; CHECK-ZVBB-LABEL: cttz_nxv8i32:
1054 ; CHECK-ZVBB: # %bb.0:
1055 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1056 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1057 ; CHECK-ZVBB-NEXT: ret
1058 %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
1059 ret <vscale x 8 x i32> %a
1060 }
1061 declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
1063 define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
1064 ; CHECK-ZVE64X-LABEL: cttz_nxv16i32:
1065 ; CHECK-ZVE64X: # %bb.0:
1066 ; CHECK-ZVE64X-NEXT: li a0, 1
1067 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1068 ; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
1069 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1070 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
1071 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
1072 ; CHECK-ZVE64X-NEXT: lui a0, 349525
1073 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
1074 ; CHECK-ZVE64X-NEXT: vand.vx v16, v16, a0
1075 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v16
1076 ; CHECK-ZVE64X-NEXT: lui a0, 209715
1077 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
1078 ; CHECK-ZVE64X-NEXT: vand.vx v16, v8, a0
1079 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1080 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1081 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v16, v8
1082 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 4
1083 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v16
1084 ; CHECK-ZVE64X-NEXT: lui a0, 61681
1085 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
1086 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1087 ; CHECK-ZVE64X-NEXT: lui a0, 4112
1088 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
1089 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
1090 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
1091 ; CHECK-ZVE64X-NEXT: ret
1092 ;
1093 ; CHECK-F-LABEL: cttz_nxv16i32:
1094 ; CHECK-F: # %bb.0:
1095 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1096 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
1097 ; CHECK-F-NEXT: vand.vv v16, v8, v16
1098 ; CHECK-F-NEXT: fsrmi a0, 1
1099 ; CHECK-F-NEXT: vfcvt.f.xu.v v16, v16
1100 ; CHECK-F-NEXT: vsrl.vi v16, v16, 23
1101 ; CHECK-F-NEXT: li a1, 127
1102 ; CHECK-F-NEXT: vsub.vx v16, v16, a1
1103 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1104 ; CHECK-F-NEXT: li a1, 32
1105 ; CHECK-F-NEXT: vmerge.vxm v8, v16, a1, v0
1106 ; CHECK-F-NEXT: fsrm a0
1107 ; CHECK-F-NEXT: ret
1108 ;
1109 ; CHECK-D-LABEL: cttz_nxv16i32:
1110 ; CHECK-D: # %bb.0:
1111 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1112 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
1113 ; CHECK-D-NEXT: vand.vv v16, v8, v16
1114 ; CHECK-D-NEXT: fsrmi a0, 1
1115 ; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16
1116 ; CHECK-D-NEXT: vsrl.vi v16, v16, 23
1117 ; CHECK-D-NEXT: li a1, 127
1118 ; CHECK-D-NEXT: vsub.vx v16, v16, a1
1119 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1120 ; CHECK-D-NEXT: li a1, 32
1121 ; CHECK-D-NEXT: vmerge.vxm v8, v16, a1, v0
1122 ; CHECK-D-NEXT: fsrm a0
1123 ; CHECK-D-NEXT: ret
1124 ;
1125 ; CHECK-ZVBB-LABEL: cttz_nxv16i32:
1126 ; CHECK-ZVBB: # %bb.0:
1127 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1128 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1129 ; CHECK-ZVBB-NEXT: ret
1130 %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false)
1131 ret <vscale x 16 x i32> %a
1132 }
1133 declare <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32>, i1)
1135 define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
1136 ; RV32I-LABEL: cttz_nxv1i64:
1137 ; RV32I: # %bb.0:
1138 ; RV32I-NEXT: li a0, 1
1139 ; RV32I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1140 ; RV32I-NEXT: vsub.vx v9, v8, a0
1141 ; RV32I-NEXT: vnot.v v8, v8
1142 ; RV32I-NEXT: vand.vv v8, v8, v9
1143 ; RV32I-NEXT: vsrl.vi v9, v8, 1
1144 ; RV32I-NEXT: lui a0, 349525
1145 ; RV32I-NEXT: addi a0, a0, 1365
1146 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1147 ; RV32I-NEXT: vmv.v.x v10, a0
1148 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1149 ; RV32I-NEXT: vand.vv v9, v9, v10
1150 ; RV32I-NEXT: vsub.vv v8, v8, v9
1151 ; RV32I-NEXT: lui a0, 209715
1152 ; RV32I-NEXT: addi a0, a0, 819
1153 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1154 ; RV32I-NEXT: vmv.v.x v9, a0
1155 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1156 ; RV32I-NEXT: vand.vv v10, v8, v9
1157 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1158 ; RV32I-NEXT: vand.vv v8, v8, v9
1159 ; RV32I-NEXT: vadd.vv v8, v10, v8
1160 ; RV32I-NEXT: vsrl.vi v9, v8, 4
1161 ; RV32I-NEXT: vadd.vv v8, v8, v9
1162 ; RV32I-NEXT: lui a0, 61681
1163 ; RV32I-NEXT: addi a0, a0, -241
1164 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1165 ; RV32I-NEXT: vmv.v.x v9, a0
1166 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1167 ; RV32I-NEXT: vand.vv v8, v8, v9
1168 ; RV32I-NEXT: lui a0, 4112
1169 ; RV32I-NEXT: addi a0, a0, 257
1170 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1171 ; RV32I-NEXT: vmv.v.x v9, a0
1172 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1173 ; RV32I-NEXT: vmul.vv v8, v8, v9
1174 ; RV32I-NEXT: li a0, 56
1175 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1176 ; RV32I-NEXT: ret
1177 ;
1178 ; RV64I-LABEL: cttz_nxv1i64:
1179 ; RV64I: # %bb.0:
1180 ; RV64I-NEXT: li a0, 1
1181 ; RV64I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1182 ; RV64I-NEXT: vsub.vx v9, v8, a0
1183 ; RV64I-NEXT: vnot.v v8, v8
1184 ; RV64I-NEXT: vand.vv v8, v8, v9
1185 ; RV64I-NEXT: vsrl.vi v9, v8, 1
1186 ; RV64I-NEXT: lui a0, 349525
1187 ; RV64I-NEXT: addiw a0, a0, 1365
1188 ; RV64I-NEXT: slli a1, a0, 32
1189 ; RV64I-NEXT: add a0, a0, a1
1190 ; RV64I-NEXT: vand.vx v9, v9, a0
1191 ; RV64I-NEXT: vsub.vv v8, v8, v9
1192 ; RV64I-NEXT: lui a0, 209715
1193 ; RV64I-NEXT: addiw a0, a0, 819
1194 ; RV64I-NEXT: slli a1, a0, 32
1195 ; RV64I-NEXT: add a0, a0, a1
1196 ; RV64I-NEXT: vand.vx v9, v8, a0
1197 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1198 ; RV64I-NEXT: vand.vx v8, v8, a0
1199 ; RV64I-NEXT: vadd.vv v8, v9, v8
1200 ; RV64I-NEXT: vsrl.vi v9, v8, 4
1201 ; RV64I-NEXT: vadd.vv v8, v8, v9
1202 ; RV64I-NEXT: lui a0, 61681
1203 ; RV64I-NEXT: addiw a0, a0, -241
1204 ; RV64I-NEXT: slli a1, a0, 32
1205 ; RV64I-NEXT: add a0, a0, a1
1206 ; RV64I-NEXT: vand.vx v8, v8, a0
1207 ; RV64I-NEXT: lui a0, 4112
1208 ; RV64I-NEXT: addiw a0, a0, 257
1209 ; RV64I-NEXT: slli a1, a0, 32
1210 ; RV64I-NEXT: add a0, a0, a1
1211 ; RV64I-NEXT: vmul.vx v8, v8, a0
1212 ; RV64I-NEXT: li a0, 56
1213 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1214 ; RV64I-NEXT: ret
1215 ;
1216 ; CHECK-F-LABEL: cttz_nxv1i64:
1217 ; CHECK-F: # %bb.0:
1218 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1219 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1220 ; CHECK-F-NEXT: vand.vv v9, v8, v9
1221 ; CHECK-F-NEXT: fsrmi a0, 1
1222 ; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1223 ; CHECK-F-NEXT: vfncvt.f.xu.w v10, v9
1224 ; CHECK-F-NEXT: vsrl.vi v9, v10, 23
1225 ; CHECK-F-NEXT: li a1, 127
1226 ; CHECK-F-NEXT: vwsubu.vx v10, v9, a1
1227 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1228 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1229 ; CHECK-F-NEXT: li a1, 64
1230 ; CHECK-F-NEXT: vmerge.vxm v8, v10, a1, v0
1231 ; CHECK-F-NEXT: fsrm a0
1232 ; CHECK-F-NEXT: ret
1233 ;
1234 ; CHECK-D-LABEL: cttz_nxv1i64:
1235 ; CHECK-D: # %bb.0:
1236 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1237 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1238 ; CHECK-D-NEXT: vand.vv v9, v8, v9
1239 ; CHECK-D-NEXT: fsrmi a0, 1
1240 ; CHECK-D-NEXT: vfcvt.f.xu.v v9, v9
1241 ; CHECK-D-NEXT: li a1, 52
1242 ; CHECK-D-NEXT: vsrl.vx v9, v9, a1
1243 ; CHECK-D-NEXT: li a1, 1023
1244 ; CHECK-D-NEXT: vsub.vx v9, v9, a1
1245 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1246 ; CHECK-D-NEXT: li a1, 64
1247 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a1, v0
1248 ; CHECK-D-NEXT: fsrm a0
1249 ; CHECK-D-NEXT: ret
1250 ;
1251 ; CHECK-ZVBB-LABEL: cttz_nxv1i64:
1252 ; CHECK-ZVBB: # %bb.0:
1253 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1254 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1255 ; CHECK-ZVBB-NEXT: ret
1256 %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false)
1257 ret <vscale x 1 x i64> %a
1258 }
1259 declare <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64>, i1)
1261 define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
1262 ; RV32I-LABEL: cttz_nxv2i64:
1263 ; RV32I: # %bb.0:
1264 ; RV32I-NEXT: li a0, 1
1265 ; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1266 ; RV32I-NEXT: vsub.vx v10, v8, a0
1267 ; RV32I-NEXT: vnot.v v8, v8
1268 ; RV32I-NEXT: vand.vv v8, v8, v10
1269 ; RV32I-NEXT: vsrl.vi v10, v8, 1
1270 ; RV32I-NEXT: lui a0, 349525
1271 ; RV32I-NEXT: addi a0, a0, 1365
1272 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1273 ; RV32I-NEXT: vmv.v.x v12, a0
1274 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1275 ; RV32I-NEXT: vand.vv v10, v10, v12
1276 ; RV32I-NEXT: vsub.vv v8, v8, v10
1277 ; RV32I-NEXT: lui a0, 209715
1278 ; RV32I-NEXT: addi a0, a0, 819
1279 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1280 ; RV32I-NEXT: vmv.v.x v10, a0
1281 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1282 ; RV32I-NEXT: vand.vv v12, v8, v10
1283 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1284 ; RV32I-NEXT: vand.vv v8, v8, v10
1285 ; RV32I-NEXT: vadd.vv v8, v12, v8
1286 ; RV32I-NEXT: vsrl.vi v10, v8, 4
1287 ; RV32I-NEXT: vadd.vv v8, v8, v10
1288 ; RV32I-NEXT: lui a0, 61681
1289 ; RV32I-NEXT: addi a0, a0, -241
1290 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1291 ; RV32I-NEXT: vmv.v.x v10, a0
1292 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1293 ; RV32I-NEXT: vand.vv v8, v8, v10
1294 ; RV32I-NEXT: lui a0, 4112
1295 ; RV32I-NEXT: addi a0, a0, 257
1296 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1297 ; RV32I-NEXT: vmv.v.x v10, a0
1298 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1299 ; RV32I-NEXT: vmul.vv v8, v8, v10
1300 ; RV32I-NEXT: li a0, 56
1301 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1302 ; RV32I-NEXT: ret
1303 ;
1304 ; RV64I-LABEL: cttz_nxv2i64:
1305 ; RV64I: # %bb.0:
1306 ; RV64I-NEXT: li a0, 1
1307 ; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1308 ; RV64I-NEXT: vsub.vx v10, v8, a0
1309 ; RV64I-NEXT: vnot.v v8, v8
1310 ; RV64I-NEXT: vand.vv v8, v8, v10
1311 ; RV64I-NEXT: vsrl.vi v10, v8, 1
1312 ; RV64I-NEXT: lui a0, 349525
1313 ; RV64I-NEXT: addiw a0, a0, 1365
1314 ; RV64I-NEXT: slli a1, a0, 32
1315 ; RV64I-NEXT: add a0, a0, a1
1316 ; RV64I-NEXT: vand.vx v10, v10, a0
1317 ; RV64I-NEXT: vsub.vv v8, v8, v10
1318 ; RV64I-NEXT: lui a0, 209715
1319 ; RV64I-NEXT: addiw a0, a0, 819
1320 ; RV64I-NEXT: slli a1, a0, 32
1321 ; RV64I-NEXT: add a0, a0, a1
1322 ; RV64I-NEXT: vand.vx v10, v8, a0
1323 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1324 ; RV64I-NEXT: vand.vx v8, v8, a0
1325 ; RV64I-NEXT: vadd.vv v8, v10, v8
1326 ; RV64I-NEXT: vsrl.vi v10, v8, 4
1327 ; RV64I-NEXT: vadd.vv v8, v8, v10
1328 ; RV64I-NEXT: lui a0, 61681
1329 ; RV64I-NEXT: addiw a0, a0, -241
1330 ; RV64I-NEXT: slli a1, a0, 32
1331 ; RV64I-NEXT: add a0, a0, a1
1332 ; RV64I-NEXT: vand.vx v8, v8, a0
1333 ; RV64I-NEXT: lui a0, 4112
1334 ; RV64I-NEXT: addiw a0, a0, 257
1335 ; RV64I-NEXT: slli a1, a0, 32
1336 ; RV64I-NEXT: add a0, a0, a1
1337 ; RV64I-NEXT: vmul.vx v8, v8, a0
1338 ; RV64I-NEXT: li a0, 56
1339 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1340 ; RV64I-NEXT: ret
1341 ;
1342 ; CHECK-F-LABEL: cttz_nxv2i64:
1343 ; CHECK-F: # %bb.0:
1344 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1345 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
1346 ; CHECK-F-NEXT: vand.vv v10, v8, v10
1347 ; CHECK-F-NEXT: fsrmi a0, 1
1348 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1349 ; CHECK-F-NEXT: vfncvt.f.xu.w v12, v10
1350 ; CHECK-F-NEXT: vsrl.vi v10, v12, 23
1351 ; CHECK-F-NEXT: li a1, 127
1352 ; CHECK-F-NEXT: vwsubu.vx v12, v10, a1
1353 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1354 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1355 ; CHECK-F-NEXT: li a1, 64
1356 ; CHECK-F-NEXT: vmerge.vxm v8, v12, a1, v0
1357 ; CHECK-F-NEXT: fsrm a0
1358 ; CHECK-F-NEXT: ret
1359 ;
1360 ; CHECK-D-LABEL: cttz_nxv2i64:
1361 ; CHECK-D: # %bb.0:
1362 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1363 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
1364 ; CHECK-D-NEXT: vand.vv v10, v8, v10
1365 ; CHECK-D-NEXT: fsrmi a0, 1
1366 ; CHECK-D-NEXT: vfcvt.f.xu.v v10, v10
1367 ; CHECK-D-NEXT: li a1, 52
1368 ; CHECK-D-NEXT: vsrl.vx v10, v10, a1
1369 ; CHECK-D-NEXT: li a1, 1023
1370 ; CHECK-D-NEXT: vsub.vx v10, v10, a1
1371 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1372 ; CHECK-D-NEXT: li a1, 64
1373 ; CHECK-D-NEXT: vmerge.vxm v8, v10, a1, v0
1374 ; CHECK-D-NEXT: fsrm a0
1375 ; CHECK-D-NEXT: ret
1376 ;
1377 ; CHECK-ZVBB-LABEL: cttz_nxv2i64:
1378 ; CHECK-ZVBB: # %bb.0:
1379 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1380 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1381 ; CHECK-ZVBB-NEXT: ret
1382 %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
1383 ret <vscale x 2 x i64> %a
1384 }
1385 declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>, i1)
1387 define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
1388 ; RV32I-LABEL: cttz_nxv4i64:
1389 ; RV32I: # %bb.0:
1390 ; RV32I-NEXT: li a0, 1
1391 ; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1392 ; RV32I-NEXT: vsub.vx v12, v8, a0
1393 ; RV32I-NEXT: vnot.v v8, v8
1394 ; RV32I-NEXT: vand.vv v8, v8, v12
1395 ; RV32I-NEXT: vsrl.vi v12, v8, 1
1396 ; RV32I-NEXT: lui a0, 349525
1397 ; RV32I-NEXT: addi a0, a0, 1365
1398 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1399 ; RV32I-NEXT: vmv.v.x v16, a0
1400 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1401 ; RV32I-NEXT: vand.vv v12, v12, v16
1402 ; RV32I-NEXT: vsub.vv v8, v8, v12
1403 ; RV32I-NEXT: lui a0, 209715
1404 ; RV32I-NEXT: addi a0, a0, 819
1405 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1406 ; RV32I-NEXT: vmv.v.x v12, a0
1407 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1408 ; RV32I-NEXT: vand.vv v16, v8, v12
1409 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1410 ; RV32I-NEXT: vand.vv v8, v8, v12
1411 ; RV32I-NEXT: vadd.vv v8, v16, v8
1412 ; RV32I-NEXT: vsrl.vi v12, v8, 4
1413 ; RV32I-NEXT: vadd.vv v8, v8, v12
1414 ; RV32I-NEXT: lui a0, 61681
1415 ; RV32I-NEXT: addi a0, a0, -241
1416 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1417 ; RV32I-NEXT: vmv.v.x v12, a0
1418 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1419 ; RV32I-NEXT: vand.vv v8, v8, v12
1420 ; RV32I-NEXT: lui a0, 4112
1421 ; RV32I-NEXT: addi a0, a0, 257
1422 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1423 ; RV32I-NEXT: vmv.v.x v12, a0
1424 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1425 ; RV32I-NEXT: vmul.vv v8, v8, v12
1426 ; RV32I-NEXT: li a0, 56
1427 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1428 ; RV32I-NEXT: ret
1429 ;
1430 ; RV64I-LABEL: cttz_nxv4i64:
1431 ; RV64I: # %bb.0:
1432 ; RV64I-NEXT: li a0, 1
1433 ; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1434 ; RV64I-NEXT: vsub.vx v12, v8, a0
1435 ; RV64I-NEXT: vnot.v v8, v8
1436 ; RV64I-NEXT: vand.vv v8, v8, v12
1437 ; RV64I-NEXT: vsrl.vi v12, v8, 1
1438 ; RV64I-NEXT: lui a0, 349525
1439 ; RV64I-NEXT: addiw a0, a0, 1365
1440 ; RV64I-NEXT: slli a1, a0, 32
1441 ; RV64I-NEXT: add a0, a0, a1
1442 ; RV64I-NEXT: vand.vx v12, v12, a0
1443 ; RV64I-NEXT: vsub.vv v8, v8, v12
1444 ; RV64I-NEXT: lui a0, 209715
1445 ; RV64I-NEXT: addiw a0, a0, 819
1446 ; RV64I-NEXT: slli a1, a0, 32
1447 ; RV64I-NEXT: add a0, a0, a1
1448 ; RV64I-NEXT: vand.vx v12, v8, a0
1449 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1450 ; RV64I-NEXT: vand.vx v8, v8, a0
1451 ; RV64I-NEXT: vadd.vv v8, v12, v8
1452 ; RV64I-NEXT: vsrl.vi v12, v8, 4
1453 ; RV64I-NEXT: vadd.vv v8, v8, v12
1454 ; RV64I-NEXT: lui a0, 61681
1455 ; RV64I-NEXT: addiw a0, a0, -241
1456 ; RV64I-NEXT: slli a1, a0, 32
1457 ; RV64I-NEXT: add a0, a0, a1
1458 ; RV64I-NEXT: vand.vx v8, v8, a0
1459 ; RV64I-NEXT: lui a0, 4112
1460 ; RV64I-NEXT: addiw a0, a0, 257
1461 ; RV64I-NEXT: slli a1, a0, 32
1462 ; RV64I-NEXT: add a0, a0, a1
1463 ; RV64I-NEXT: vmul.vx v8, v8, a0
1464 ; RV64I-NEXT: li a0, 56
1465 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1466 ; RV64I-NEXT: ret
1467 ;
1468 ; CHECK-F-LABEL: cttz_nxv4i64:
1469 ; CHECK-F: # %bb.0:
1470 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1471 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
1472 ; CHECK-F-NEXT: vand.vv v12, v8, v12
1473 ; CHECK-F-NEXT: fsrmi a0, 1
1474 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1475 ; CHECK-F-NEXT: vfncvt.f.xu.w v16, v12
1476 ; CHECK-F-NEXT: vsrl.vi v12, v16, 23
1477 ; CHECK-F-NEXT: li a1, 127
1478 ; CHECK-F-NEXT: vwsubu.vx v16, v12, a1
1479 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1480 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1481 ; CHECK-F-NEXT: li a1, 64
1482 ; CHECK-F-NEXT: vmerge.vxm v8, v16, a1, v0
1483 ; CHECK-F-NEXT: fsrm a0
1484 ; CHECK-F-NEXT: ret
1485 ;
1486 ; CHECK-D-LABEL: cttz_nxv4i64:
1487 ; CHECK-D: # %bb.0:
1488 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1489 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
1490 ; CHECK-D-NEXT: vand.vv v12, v8, v12
1491 ; CHECK-D-NEXT: fsrmi a0, 1
1492 ; CHECK-D-NEXT: vfcvt.f.xu.v v12, v12
1493 ; CHECK-D-NEXT: li a1, 52
1494 ; CHECK-D-NEXT: vsrl.vx v12, v12, a1
1495 ; CHECK-D-NEXT: li a1, 1023
1496 ; CHECK-D-NEXT: vsub.vx v12, v12, a1
1497 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1498 ; CHECK-D-NEXT: li a1, 64
1499 ; CHECK-D-NEXT: vmerge.vxm v8, v12, a1, v0
1500 ; CHECK-D-NEXT: fsrm a0
1501 ; CHECK-D-NEXT: ret
1502 ;
1503 ; CHECK-ZVBB-LABEL: cttz_nxv4i64:
1504 ; CHECK-ZVBB: # %bb.0:
1505 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1506 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1507 ; CHECK-ZVBB-NEXT: ret
1508 %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false)
1509 ret <vscale x 4 x i64> %a
1510 }
1511 declare <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64>, i1)
1513 define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
1514 ; RV32I-LABEL: cttz_nxv8i64:
1515 ; RV32I: # %bb.0:
1516 ; RV32I-NEXT: li a0, 1
1517 ; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1518 ; RV32I-NEXT: vsub.vx v16, v8, a0
1519 ; RV32I-NEXT: vnot.v v8, v8
1520 ; RV32I-NEXT: vand.vv v8, v8, v16
1521 ; RV32I-NEXT: vsrl.vi v16, v8, 1
1522 ; RV32I-NEXT: lui a0, 349525
1523 ; RV32I-NEXT: addi a0, a0, 1365
1524 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1525 ; RV32I-NEXT: vmv.v.x v24, a0
1526 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1527 ; RV32I-NEXT: vand.vv v16, v16, v24
1528 ; RV32I-NEXT: vsub.vv v8, v8, v16
1529 ; RV32I-NEXT: lui a0, 209715
1530 ; RV32I-NEXT: addi a0, a0, 819
1531 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1532 ; RV32I-NEXT: vmv.v.x v16, a0
1533 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1534 ; RV32I-NEXT: vand.vv v24, v8, v16
1535 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1536 ; RV32I-NEXT: vand.vv v8, v8, v16
1537 ; RV32I-NEXT: vadd.vv v8, v24, v8
1538 ; RV32I-NEXT: vsrl.vi v16, v8, 4
1539 ; RV32I-NEXT: vadd.vv v8, v8, v16
1540 ; RV32I-NEXT: lui a0, 61681
1541 ; RV32I-NEXT: addi a0, a0, -241
1542 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1543 ; RV32I-NEXT: vmv.v.x v16, a0
1544 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1545 ; RV32I-NEXT: vand.vv v8, v8, v16
1546 ; RV32I-NEXT: lui a0, 4112
1547 ; RV32I-NEXT: addi a0, a0, 257
1548 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1549 ; RV32I-NEXT: vmv.v.x v16, a0
1550 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1551 ; RV32I-NEXT: vmul.vv v8, v8, v16
1552 ; RV32I-NEXT: li a0, 56
1553 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1554 ; RV32I-NEXT: ret
1555 ;
1556 ; RV64I-LABEL: cttz_nxv8i64:
1557 ; RV64I: # %bb.0:
1558 ; RV64I-NEXT: li a0, 1
1559 ; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1560 ; RV64I-NEXT: vsub.vx v16, v8, a0
1561 ; RV64I-NEXT: vnot.v v8, v8
1562 ; RV64I-NEXT: vand.vv v8, v8, v16
1563 ; RV64I-NEXT: vsrl.vi v16, v8, 1
1564 ; RV64I-NEXT: lui a0, 349525
1565 ; RV64I-NEXT: addiw a0, a0, 1365
1566 ; RV64I-NEXT: slli a1, a0, 32
1567 ; RV64I-NEXT: add a0, a0, a1
1568 ; RV64I-NEXT: vand.vx v16, v16, a0
1569 ; RV64I-NEXT: vsub.vv v8, v8, v16
1570 ; RV64I-NEXT: lui a0, 209715
1571 ; RV64I-NEXT: addiw a0, a0, 819
1572 ; RV64I-NEXT: slli a1, a0, 32
1573 ; RV64I-NEXT: add a0, a0, a1
1574 ; RV64I-NEXT: vand.vx v16, v8, a0
1575 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1576 ; RV64I-NEXT: vand.vx v8, v8, a0
1577 ; RV64I-NEXT: vadd.vv v8, v16, v8
1578 ; RV64I-NEXT: vsrl.vi v16, v8, 4
1579 ; RV64I-NEXT: vadd.vv v8, v8, v16
1580 ; RV64I-NEXT: lui a0, 61681
1581 ; RV64I-NEXT: addiw a0, a0, -241
1582 ; RV64I-NEXT: slli a1, a0, 32
1583 ; RV64I-NEXT: add a0, a0, a1
1584 ; RV64I-NEXT: vand.vx v8, v8, a0
1585 ; RV64I-NEXT: lui a0, 4112
1586 ; RV64I-NEXT: addiw a0, a0, 257
1587 ; RV64I-NEXT: slli a1, a0, 32
1588 ; RV64I-NEXT: add a0, a0, a1
1589 ; RV64I-NEXT: vmul.vx v8, v8, a0
1590 ; RV64I-NEXT: li a0, 56
1591 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1592 ; RV64I-NEXT: ret
1593 ;
1594 ; CHECK-F-LABEL: cttz_nxv8i64:
1595 ; CHECK-F: # %bb.0:
1596 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1597 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
1598 ; CHECK-F-NEXT: vand.vv v16, v8, v16
1599 ; CHECK-F-NEXT: fsrmi a0, 1
1600 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1601 ; CHECK-F-NEXT: vfncvt.f.xu.w v24, v16
1602 ; CHECK-F-NEXT: vsrl.vi v16, v24, 23
1603 ; CHECK-F-NEXT: li a1, 127
1604 ; CHECK-F-NEXT: vwsubu.vx v24, v16, a1
1605 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1606 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1607 ; CHECK-F-NEXT: li a1, 64
1608 ; CHECK-F-NEXT: vmerge.vxm v8, v24, a1, v0
1609 ; CHECK-F-NEXT: fsrm a0
1610 ; CHECK-F-NEXT: ret
1611 ;
1612 ; CHECK-D-LABEL: cttz_nxv8i64:
1613 ; CHECK-D: # %bb.0:
1614 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1615 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
1616 ; CHECK-D-NEXT: vand.vv v16, v8, v16
1617 ; CHECK-D-NEXT: fsrmi a0, 1
1618 ; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16
1619 ; CHECK-D-NEXT: li a1, 52
1620 ; CHECK-D-NEXT: vsrl.vx v16, v16, a1
1621 ; CHECK-D-NEXT: li a1, 1023
1622 ; CHECK-D-NEXT: vsub.vx v16, v16, a1
1623 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1624 ; CHECK-D-NEXT: li a1, 64
1625 ; CHECK-D-NEXT: vmerge.vxm v8, v16, a1, v0
1626 ; CHECK-D-NEXT: fsrm a0
1627 ; CHECK-D-NEXT: ret
1628 ;
1629 ; CHECK-ZVBB-LABEL: cttz_nxv8i64:
1630 ; CHECK-ZVBB: # %bb.0:
1631 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1632 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1633 ; CHECK-ZVBB-NEXT: ret
1634 %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false)
1635 ret <vscale x 8 x i64> %a
1636 }
1637 declare <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64>, i1)
1639 define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
1640 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i8:
1641 ; CHECK-ZVE64X: # %bb.0:
1642 ; CHECK-ZVE64X-NEXT: li a0, 1
1643 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
1644 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1645 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1646 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1647 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1648 ; CHECK-ZVE64X-NEXT: li a0, 85
1649 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1650 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1651 ; CHECK-ZVE64X-NEXT: li a0, 51
1652 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1653 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1654 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1655 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1656 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1657 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1658 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1659 ; CHECK-ZVE64X-NEXT: ret
1660 ;
1661 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i8:
1662 ; CHECK-F: # %bb.0:
1663 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1664 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1665 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1666 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1667 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1668 ; CHECK-F-NEXT: vfwcvt.f.xu.v v8, v9
1669 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 23
1670 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1671 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1672 ; CHECK-F-NEXT: li a0, 127
1673 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1674 ; CHECK-F-NEXT: ret
1675 ;
1676 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i8:
1677 ; CHECK-D: # %bb.0:
1678 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1679 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1680 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1681 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1682 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1683 ; CHECK-D-NEXT: vfwcvt.f.xu.v v8, v9
1684 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 23
1685 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1686 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1687 ; CHECK-D-NEXT: li a0, 127
1688 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1689 ; CHECK-D-NEXT: ret
1690 ;
1691 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i8:
1692 ; CHECK-ZVBB: # %bb.0:
1693 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1694 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1695 ; CHECK-ZVBB-NEXT: ret
1696 %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
1697 ret <vscale x 1 x i8> %a
1698 }
1700 define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
1701 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i8:
1702 ; CHECK-ZVE64X: # %bb.0:
1703 ; CHECK-ZVE64X-NEXT: li a0, 1
1704 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
1705 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1706 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1707 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1708 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1709 ; CHECK-ZVE64X-NEXT: li a0, 85
1710 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1711 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1712 ; CHECK-ZVE64X-NEXT: li a0, 51
1713 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1714 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1715 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1716 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1717 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1718 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1719 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1720 ; CHECK-ZVE64X-NEXT: ret
1721 ;
1722 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i8:
1723 ; CHECK-F: # %bb.0:
1724 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1725 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1726 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1727 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1728 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1729 ; CHECK-F-NEXT: vfwcvt.f.xu.v v8, v9
1730 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 23
1731 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1732 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1733 ; CHECK-F-NEXT: li a0, 127
1734 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1735 ; CHECK-F-NEXT: ret
1736 ;
1737 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i8:
1738 ; CHECK-D: # %bb.0:
1739 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1740 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1741 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1742 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1743 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1744 ; CHECK-D-NEXT: vfwcvt.f.xu.v v8, v9
1745 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 23
1746 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1747 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1748 ; CHECK-D-NEXT: li a0, 127
1749 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1750 ; CHECK-D-NEXT: ret
1751 ;
1752 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i8:
1753 ; CHECK-ZVBB: # %bb.0:
1754 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1755 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1756 ; CHECK-ZVBB-NEXT: ret
1757 %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
1758 ret <vscale x 2 x i8> %a
1759 }
1761 define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
1762 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i8:
1763 ; CHECK-ZVE64X: # %bb.0:
1764 ; CHECK-ZVE64X-NEXT: li a0, 1
1765 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
1766 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1767 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1768 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1769 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1770 ; CHECK-ZVE64X-NEXT: li a0, 85
1771 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1772 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1773 ; CHECK-ZVE64X-NEXT: li a0, 51
1774 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1775 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1776 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1777 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1778 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1779 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1780 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1781 ; CHECK-ZVE64X-NEXT: ret
1782 ;
1783 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i8:
1784 ; CHECK-F: # %bb.0:
1785 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1786 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1787 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1788 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1789 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1790 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
1791 ; CHECK-F-NEXT: vnsrl.wi v8, v10, 23
1792 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1793 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1794 ; CHECK-F-NEXT: li a0, 127
1795 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1796 ; CHECK-F-NEXT: ret
1797 ;
1798 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i8:
1799 ; CHECK-D: # %bb.0:
1800 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1801 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1802 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1803 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1804 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1805 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
1806 ; CHECK-D-NEXT: vnsrl.wi v8, v10, 23
1807 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1808 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1809 ; CHECK-D-NEXT: li a0, 127
1810 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1811 ; CHECK-D-NEXT: ret
1812 ;
1813 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i8:
1814 ; CHECK-ZVBB: # %bb.0:
1815 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1816 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1817 ; CHECK-ZVBB-NEXT: ret
1818 %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
1819 ret <vscale x 4 x i8> %a
1820 }
1822 define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
1823 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i8:
1824 ; CHECK-ZVE64X: # %bb.0:
1825 ; CHECK-ZVE64X-NEXT: li a0, 1
1826 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m1, ta, ma
1827 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1828 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1829 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1830 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1831 ; CHECK-ZVE64X-NEXT: li a0, 85
1832 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1833 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1834 ; CHECK-ZVE64X-NEXT: li a0, 51
1835 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1836 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1837 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1838 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1839 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1840 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1841 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1842 ; CHECK-ZVE64X-NEXT: ret
1843 ;
1844 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i8:
1845 ; CHECK-F: # %bb.0:
1846 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m1, ta, ma
1847 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1848 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1849 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
1850 ; CHECK-F-NEXT: vzext.vf2 v10, v8
1851 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
1852 ; CHECK-F-NEXT: vnsrl.wi v8, v12, 23
1853 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
1854 ; CHECK-F-NEXT: vnsrl.wi v10, v8, 0
1855 ; CHECK-F-NEXT: li a0, 127
1856 ; CHECK-F-NEXT: vsub.vx v8, v10, a0
1857 ; CHECK-F-NEXT: ret
1858 ;
1859 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i8:
1860 ; CHECK-D: # %bb.0:
1861 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m1, ta, ma
1862 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1863 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1864 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m2, ta, ma
1865 ; CHECK-D-NEXT: vzext.vf2 v10, v8
1866 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
1867 ; CHECK-D-NEXT: vnsrl.wi v8, v12, 23
1868 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m1, ta, ma
1869 ; CHECK-D-NEXT: vnsrl.wi v10, v8, 0
1870 ; CHECK-D-NEXT: li a0, 127
1871 ; CHECK-D-NEXT: vsub.vx v8, v10, a0
1872 ; CHECK-D-NEXT: ret
1873 ;
1874 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i8:
1875 ; CHECK-ZVBB: # %bb.0:
1876 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
1877 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1878 ; CHECK-ZVBB-NEXT: ret
1879 %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
1880 ret <vscale x 8 x i8> %a
1881 }
1883 define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
1884 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i8:
1885 ; CHECK-ZVE64X: # %bb.0:
1886 ; CHECK-ZVE64X-NEXT: li a0, 1
1887 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
1888 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
1889 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1890 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
1891 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
1892 ; CHECK-ZVE64X-NEXT: li a0, 85
1893 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
1894 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
1895 ; CHECK-ZVE64X-NEXT: li a0, 51
1896 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
1897 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1898 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1899 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
1900 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
1901 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
1902 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1903 ; CHECK-ZVE64X-NEXT: ret
1904 ;
1905 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i8:
1906 ; CHECK-F: # %bb.0:
1907 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m2, ta, ma
1908 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
1909 ; CHECK-F-NEXT: vand.vv v8, v8, v10
1910 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m4, ta, ma
1911 ; CHECK-F-NEXT: vzext.vf2 v12, v8
1912 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
1913 ; CHECK-F-NEXT: vnsrl.wi v8, v16, 23
1914 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m2, ta, ma
1915 ; CHECK-F-NEXT: vnsrl.wi v12, v8, 0
1916 ; CHECK-F-NEXT: li a0, 127
1917 ; CHECK-F-NEXT: vsub.vx v8, v12, a0
1918 ; CHECK-F-NEXT: ret
1919 ;
1920 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i8:
1921 ; CHECK-D: # %bb.0:
1922 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m2, ta, ma
1923 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
1924 ; CHECK-D-NEXT: vand.vv v8, v8, v10
1925 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m4, ta, ma
1926 ; CHECK-D-NEXT: vzext.vf2 v12, v8
1927 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
1928 ; CHECK-D-NEXT: vnsrl.wi v8, v16, 23
1929 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m2, ta, ma
1930 ; CHECK-D-NEXT: vnsrl.wi v12, v8, 0
1931 ; CHECK-D-NEXT: li a0, 127
1932 ; CHECK-D-NEXT: vsub.vx v8, v12, a0
1933 ; CHECK-D-NEXT: ret
1934 ;
1935 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i8:
1936 ; CHECK-ZVBB: # %bb.0:
1937 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
1938 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1939 ; CHECK-ZVBB-NEXT: ret
1940 %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
1941 ret <vscale x 16 x i8> %a
1942 }
1944 define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
1945 ; CHECK-LABEL: cttz_zero_undef_nxv32i8:
1946 ; CHECK: # %bb.0:
1947 ; CHECK-NEXT: li a0, 1
1948 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
1949 ; CHECK-NEXT: vsub.vx v12, v8, a0
1950 ; CHECK-NEXT: vnot.v v8, v8
1951 ; CHECK-NEXT: vand.vv v8, v8, v12
1952 ; CHECK-NEXT: vsrl.vi v12, v8, 1
1953 ; CHECK-NEXT: li a0, 85
1954 ; CHECK-NEXT: vand.vx v12, v12, a0
1955 ; CHECK-NEXT: vsub.vv v8, v8, v12
1956 ; CHECK-NEXT: li a0, 51
1957 ; CHECK-NEXT: vand.vx v12, v8, a0
1958 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1959 ; CHECK-NEXT: vand.vx v8, v8, a0
1960 ; CHECK-NEXT: vadd.vv v8, v12, v8
1961 ; CHECK-NEXT: vsrl.vi v12, v8, 4
1962 ; CHECK-NEXT: vadd.vv v8, v8, v12
1963 ; CHECK-NEXT: vand.vi v8, v8, 15
1964 ; CHECK-NEXT: ret
1965 ;
1966 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i8:
1967 ; CHECK-ZVBB: # %bb.0:
1968 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
1969 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1970 ; CHECK-ZVBB-NEXT: ret
1971 %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true)
1972 ret <vscale x 32 x i8> %a
1973 }
1975 define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
1976 ; CHECK-LABEL: cttz_zero_undef_nxv64i8:
1977 ; CHECK: # %bb.0:
1978 ; CHECK-NEXT: li a0, 1
1979 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
1980 ; CHECK-NEXT: vsub.vx v16, v8, a0
1981 ; CHECK-NEXT: vnot.v v8, v8
1982 ; CHECK-NEXT: vand.vv v8, v8, v16
1983 ; CHECK-NEXT: vsrl.vi v16, v8, 1
1984 ; CHECK-NEXT: li a0, 85
1985 ; CHECK-NEXT: vand.vx v16, v16, a0
1986 ; CHECK-NEXT: vsub.vv v8, v8, v16
1987 ; CHECK-NEXT: li a0, 51
1988 ; CHECK-NEXT: vand.vx v16, v8, a0
1989 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1990 ; CHECK-NEXT: vand.vx v8, v8, a0
1991 ; CHECK-NEXT: vadd.vv v8, v16, v8
1992 ; CHECK-NEXT: vsrl.vi v16, v8, 4
1993 ; CHECK-NEXT: vadd.vv v8, v8, v16
1994 ; CHECK-NEXT: vand.vi v8, v8, 15
1995 ; CHECK-NEXT: ret
1996 ;
1997 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv64i8:
1998 ; CHECK-ZVBB: # %bb.0:
1999 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
2000 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2001 ; CHECK-ZVBB-NEXT: ret
2002 %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true)
2003 ret <vscale x 64 x i8> %a
2004 }
2006 define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
2007 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i16:
2008 ; CHECK-ZVE64X: # %bb.0:
2009 ; CHECK-ZVE64X-NEXT: li a0, 1
2010 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2011 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2012 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2013 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2014 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2015 ; CHECK-ZVE64X-NEXT: lui a0, 5
2016 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2017 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2018 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2019 ; CHECK-ZVE64X-NEXT: lui a0, 3
2020 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2021 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2022 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2023 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2024 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2025 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2026 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2027 ; CHECK-ZVE64X-NEXT: lui a0, 1
2028 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2029 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2030 ; CHECK-ZVE64X-NEXT: li a0, 257
2031 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2032 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2033 ; CHECK-ZVE64X-NEXT: ret
2034 ;
2035 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i16:
2036 ; CHECK-F: # %bb.0:
2037 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2038 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2039 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2040 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
2041 ; CHECK-F-NEXT: vnsrl.wi v8, v9, 23
2042 ; CHECK-F-NEXT: li a0, 127
2043 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2044 ; CHECK-F-NEXT: ret
2045 ;
2046 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i16:
2047 ; CHECK-D: # %bb.0:
2048 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2049 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2050 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2051 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2052 ; CHECK-D-NEXT: vnsrl.wi v8, v9, 23
2053 ; CHECK-D-NEXT: li a0, 127
2054 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2055 ; CHECK-D-NEXT: ret
2056 ;
2057 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i16:
2058 ; CHECK-ZVBB: # %bb.0:
2059 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2060 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2061 ; CHECK-ZVBB-NEXT: ret
2062 %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
2063 ret <vscale x 1 x i16> %a
2064 }
2066 define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
2067 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i16:
2068 ; CHECK-ZVE64X: # %bb.0:
2069 ; CHECK-ZVE64X-NEXT: li a0, 1
2070 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
2071 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2072 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2073 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2074 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2075 ; CHECK-ZVE64X-NEXT: lui a0, 5
2076 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2077 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2078 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2079 ; CHECK-ZVE64X-NEXT: lui a0, 3
2080 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2081 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2082 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2083 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2084 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2085 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2086 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2087 ; CHECK-ZVE64X-NEXT: lui a0, 1
2088 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2089 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2090 ; CHECK-ZVE64X-NEXT: li a0, 257
2091 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2092 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2093 ; CHECK-ZVE64X-NEXT: ret
2094 ;
2095 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i16:
2096 ; CHECK-F: # %bb.0:
2097 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2098 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2099 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2100 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
2101 ; CHECK-F-NEXT: vnsrl.wi v8, v9, 23
2102 ; CHECK-F-NEXT: li a0, 127
2103 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2104 ; CHECK-F-NEXT: ret
2105 ;
2106 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i16:
2107 ; CHECK-D: # %bb.0:
2108 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2109 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2110 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2111 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2112 ; CHECK-D-NEXT: vnsrl.wi v8, v9, 23
2113 ; CHECK-D-NEXT: li a0, 127
2114 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2115 ; CHECK-D-NEXT: ret
2116 ;
2117 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i16:
2118 ; CHECK-ZVBB: # %bb.0:
2119 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2120 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2121 ; CHECK-ZVBB-NEXT: ret
2122 %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
2123 ret <vscale x 2 x i16> %a
2124 }
2126 define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
2127 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i16:
2128 ; CHECK-ZVE64X: # %bb.0:
2129 ; CHECK-ZVE64X-NEXT: li a0, 1
2130 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m1, ta, ma
2131 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2132 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2133 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2134 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2135 ; CHECK-ZVE64X-NEXT: lui a0, 5
2136 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2137 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2138 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2139 ; CHECK-ZVE64X-NEXT: lui a0, 3
2140 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2141 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2142 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2143 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2144 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2145 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2146 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2147 ; CHECK-ZVE64X-NEXT: lui a0, 1
2148 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2149 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2150 ; CHECK-ZVE64X-NEXT: li a0, 257
2151 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2152 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2153 ; CHECK-ZVE64X-NEXT: ret
2154 ;
2155 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i16:
2156 ; CHECK-F: # %bb.0:
2157 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2158 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2159 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2160 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v8
2161 ; CHECK-F-NEXT: vnsrl.wi v8, v10, 23
2162 ; CHECK-F-NEXT: li a0, 127
2163 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2164 ; CHECK-F-NEXT: ret
2165 ;
2166 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i16:
2167 ; CHECK-D: # %bb.0:
2168 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2169 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2170 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2171 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
2172 ; CHECK-D-NEXT: vnsrl.wi v8, v10, 23
2173 ; CHECK-D-NEXT: li a0, 127
2174 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2175 ; CHECK-D-NEXT: ret
2176 ;
2177 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i16:
2178 ; CHECK-ZVBB: # %bb.0:
2179 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2180 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2181 ; CHECK-ZVBB-NEXT: ret
2182 %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
2183 ret <vscale x 4 x i16> %a
2184 }
2186 define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
2187 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i16:
2188 ; CHECK-ZVE64X: # %bb.0:
2189 ; CHECK-ZVE64X-NEXT: li a0, 1
2190 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
2191 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2192 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2193 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2194 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2195 ; CHECK-ZVE64X-NEXT: lui a0, 5
2196 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2197 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2198 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2199 ; CHECK-ZVE64X-NEXT: lui a0, 3
2200 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2201 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2202 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2203 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2204 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2205 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2206 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2207 ; CHECK-ZVE64X-NEXT: lui a0, 1
2208 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2209 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2210 ; CHECK-ZVE64X-NEXT: li a0, 257
2211 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2212 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2213 ; CHECK-ZVE64X-NEXT: ret
2214 ;
2215 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i16:
2216 ; CHECK-F: # %bb.0:
2217 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2218 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2219 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2220 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v8
2221 ; CHECK-F-NEXT: vnsrl.wi v8, v12, 23
2222 ; CHECK-F-NEXT: li a0, 127
2223 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2224 ; CHECK-F-NEXT: ret
2225 ;
2226 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i16:
2227 ; CHECK-D: # %bb.0:
2228 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2229 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2230 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2231 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
2232 ; CHECK-D-NEXT: vnsrl.wi v8, v12, 23
2233 ; CHECK-D-NEXT: li a0, 127
2234 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2235 ; CHECK-D-NEXT: ret
2236 ;
2237 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i16:
2238 ; CHECK-ZVBB: # %bb.0:
2239 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2240 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2241 ; CHECK-ZVBB-NEXT: ret
2242 %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
2243 ret <vscale x 8 x i16> %a
2244 }
2246 define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
2247 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i16:
2248 ; CHECK-ZVE64X: # %bb.0:
2249 ; CHECK-ZVE64X-NEXT: li a0, 1
2250 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
2251 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
2252 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2253 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
2254 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
2255 ; CHECK-ZVE64X-NEXT: lui a0, 5
2256 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2257 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
2258 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
2259 ; CHECK-ZVE64X-NEXT: lui a0, 3
2260 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2261 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
2262 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2263 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2264 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
2265 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
2266 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
2267 ; CHECK-ZVE64X-NEXT: lui a0, 1
2268 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2269 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2270 ; CHECK-ZVE64X-NEXT: li a0, 257
2271 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2272 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2273 ; CHECK-ZVE64X-NEXT: ret
2274 ;
2275 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i16:
2276 ; CHECK-F: # %bb.0:
2277 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2278 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
2279 ; CHECK-F-NEXT: vand.vv v8, v8, v12
2280 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v8
2281 ; CHECK-F-NEXT: vnsrl.wi v8, v16, 23
2282 ; CHECK-F-NEXT: li a0, 127
2283 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2284 ; CHECK-F-NEXT: ret
2285 ;
2286 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i16:
2287 ; CHECK-D: # %bb.0:
2288 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2289 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
2290 ; CHECK-D-NEXT: vand.vv v8, v8, v12
2291 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
2292 ; CHECK-D-NEXT: vnsrl.wi v8, v16, 23
2293 ; CHECK-D-NEXT: li a0, 127
2294 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2295 ; CHECK-D-NEXT: ret
2296 ;
2297 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i16:
2298 ; CHECK-ZVBB: # %bb.0:
2299 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2300 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2301 ; CHECK-ZVBB-NEXT: ret
2302 %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
2303 ret <vscale x 16 x i16> %a
2304 }
2306 define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
2307 ; CHECK-LABEL: cttz_zero_undef_nxv32i16:
2308 ; CHECK: # %bb.0:
2309 ; CHECK-NEXT: li a0, 1
2310 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
2311 ; CHECK-NEXT: vsub.vx v16, v8, a0
2312 ; CHECK-NEXT: vnot.v v8, v8
2313 ; CHECK-NEXT: vand.vv v8, v8, v16
2314 ; CHECK-NEXT: vsrl.vi v16, v8, 1
2315 ; CHECK-NEXT: lui a0, 5
2316 ; CHECK-NEXT: addi a0, a0, 1365
2317 ; CHECK-NEXT: vand.vx v16, v16, a0
2318 ; CHECK-NEXT: vsub.vv v8, v8, v16
2319 ; CHECK-NEXT: lui a0, 3
2320 ; CHECK-NEXT: addi a0, a0, 819
2321 ; CHECK-NEXT: vand.vx v16, v8, a0
2322 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2323 ; CHECK-NEXT: vand.vx v8, v8, a0
2324 ; CHECK-NEXT: vadd.vv v8, v16, v8
2325 ; CHECK-NEXT: vsrl.vi v16, v8, 4
2326 ; CHECK-NEXT: vadd.vv v8, v8, v16
2327 ; CHECK-NEXT: lui a0, 1
2328 ; CHECK-NEXT: addi a0, a0, -241
2329 ; CHECK-NEXT: vand.vx v8, v8, a0
2330 ; CHECK-NEXT: li a0, 257
2331 ; CHECK-NEXT: vmul.vx v8, v8, a0
2332 ; CHECK-NEXT: vsrl.vi v8, v8, 8
2333 ; CHECK-NEXT: ret
2334 ;
2335 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i16:
2336 ; CHECK-ZVBB: # %bb.0:
2337 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
2338 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2339 ; CHECK-ZVBB-NEXT: ret
2340 %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true)
2341 ret <vscale x 32 x i16> %a
2342 }
2344 define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
2345 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i32:
2346 ; CHECK-ZVE64X: # %bb.0:
2347 ; CHECK-ZVE64X-NEXT: li a0, 1
2348 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
2349 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2350 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2351 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2352 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2353 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2354 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2355 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2356 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2357 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2358 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2359 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2360 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2361 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2362 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2363 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2364 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2365 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2366 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2367 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2368 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2369 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2370 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2371 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2372 ; CHECK-ZVE64X-NEXT: ret
2373 ;
2374 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i32:
2375 ; CHECK-F: # %bb.0:
2376 ; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2377 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2378 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2379 ; CHECK-F-NEXT: fsrmi a0, 1
2380 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2381 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2382 ; CHECK-F-NEXT: li a1, 127
2383 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2384 ; CHECK-F-NEXT: fsrm a0
2385 ; CHECK-F-NEXT: ret
2386 ;
2387 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i32:
2388 ; CHECK-D: # %bb.0:
2389 ; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2390 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2391 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2392 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2393 ; CHECK-D-NEXT: li a0, 52
2394 ; CHECK-D-NEXT: vnsrl.wx v8, v9, a0
2395 ; CHECK-D-NEXT: li a0, 1023
2396 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2397 ; CHECK-D-NEXT: ret
2398 ;
2399 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i32:
2400 ; CHECK-ZVBB: # %bb.0:
2401 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2402 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2403 ; CHECK-ZVBB-NEXT: ret
2404 %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
2405 ret <vscale x 1 x i32> %a
2406 }
2408 define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
2409 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i32:
2410 ; CHECK-ZVE64X: # %bb.0:
2411 ; CHECK-ZVE64X-NEXT: li a0, 1
2412 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2413 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2414 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2415 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2416 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2417 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2418 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2419 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2420 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2421 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2422 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2423 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2424 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2425 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2426 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2427 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2428 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2429 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2430 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2431 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2432 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2433 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2434 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2435 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2436 ; CHECK-ZVE64X-NEXT: ret
2437 ;
2438 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i32:
2439 ; CHECK-F: # %bb.0:
2440 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2441 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2442 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2443 ; CHECK-F-NEXT: fsrmi a0, 1
2444 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2445 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2446 ; CHECK-F-NEXT: li a1, 127
2447 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2448 ; CHECK-F-NEXT: fsrm a0
2449 ; CHECK-F-NEXT: ret
2450 ;
2451 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i32:
2452 ; CHECK-D: # %bb.0:
2453 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2454 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2455 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2456 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
2457 ; CHECK-D-NEXT: li a0, 52
2458 ; CHECK-D-NEXT: vnsrl.wx v8, v10, a0
2459 ; CHECK-D-NEXT: li a0, 1023
2460 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2461 ; CHECK-D-NEXT: ret
2462 ;
2463 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i32:
2464 ; CHECK-ZVBB: # %bb.0:
2465 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2466 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2467 ; CHECK-ZVBB-NEXT: ret
2468 %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
2469 ret <vscale x 2 x i32> %a
2470 }
2472 define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
2473 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i32:
2474 ; CHECK-ZVE64X: # %bb.0:
2475 ; CHECK-ZVE64X-NEXT: li a0, 1
2476 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2477 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2478 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2479 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2480 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2481 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2482 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2483 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2484 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2485 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2486 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2487 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2488 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2489 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2490 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2491 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2492 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2493 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2494 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2495 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2496 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2497 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2498 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2499 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2500 ; CHECK-ZVE64X-NEXT: ret
2501 ;
2502 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i32:
2503 ; CHECK-F: # %bb.0:
2504 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2505 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2506 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2507 ; CHECK-F-NEXT: fsrmi a0, 1
2508 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2509 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2510 ; CHECK-F-NEXT: li a1, 127
2511 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2512 ; CHECK-F-NEXT: fsrm a0
2513 ; CHECK-F-NEXT: ret
2514 ;
2515 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i32:
2516 ; CHECK-D: # %bb.0:
2517 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2518 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2519 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2520 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
2521 ; CHECK-D-NEXT: li a0, 52
2522 ; CHECK-D-NEXT: vnsrl.wx v8, v12, a0
2523 ; CHECK-D-NEXT: li a0, 1023
2524 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2525 ; CHECK-D-NEXT: ret
2526 ;
2527 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i32:
2528 ; CHECK-ZVBB: # %bb.0:
2529 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2530 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2531 ; CHECK-ZVBB-NEXT: ret
2532 %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
2533 ret <vscale x 4 x i32> %a
2534 }
2536 define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
2537 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i32:
2538 ; CHECK-ZVE64X: # %bb.0:
2539 ; CHECK-ZVE64X-NEXT: li a0, 1
2540 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
2541 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
2542 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2543 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
2544 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
2545 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2546 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2547 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
2548 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
2549 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2550 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2551 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
2552 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2553 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2554 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
2555 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
2556 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
2557 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2558 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2559 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2560 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2561 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2562 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2563 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2564 ; CHECK-ZVE64X-NEXT: ret
2565 ;
2566 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i32:
2567 ; CHECK-F: # %bb.0:
2568 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2569 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
2570 ; CHECK-F-NEXT: vand.vv v8, v8, v12
2571 ; CHECK-F-NEXT: fsrmi a0, 1
2572 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2573 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2574 ; CHECK-F-NEXT: li a1, 127
2575 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2576 ; CHECK-F-NEXT: fsrm a0
2577 ; CHECK-F-NEXT: ret
2578 ;
2579 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i32:
2580 ; CHECK-D: # %bb.0:
2581 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2582 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
2583 ; CHECK-D-NEXT: vand.vv v8, v8, v12
2584 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
2585 ; CHECK-D-NEXT: li a0, 52
2586 ; CHECK-D-NEXT: vnsrl.wx v8, v16, a0
2587 ; CHECK-D-NEXT: li a0, 1023
2588 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2589 ; CHECK-D-NEXT: ret
2590 ;
2591 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i32:
2592 ; CHECK-ZVBB: # %bb.0:
2593 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2594 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2595 ; CHECK-ZVBB-NEXT: ret
2596 %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
2597 ret <vscale x 8 x i32> %a
2598 }
2600 define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
2601 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i32:
2602 ; CHECK-ZVE64X: # %bb.0:
2603 ; CHECK-ZVE64X-NEXT: li a0, 1
2604 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
2605 ; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
2606 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2607 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
2608 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
2609 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2610 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2611 ; CHECK-ZVE64X-NEXT: vand.vx v16, v16, a0
2612 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v16
2613 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2614 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2615 ; CHECK-ZVE64X-NEXT: vand.vx v16, v8, a0
2616 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2617 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2618 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v16, v8
2619 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 4
2620 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v16
2621 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2622 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2623 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2624 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2625 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2626 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2627 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2628 ; CHECK-ZVE64X-NEXT: ret
2629 ;
2630 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i32:
2631 ; CHECK-F: # %bb.0:
2632 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2633 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
2634 ; CHECK-F-NEXT: vand.vv v8, v8, v16
2635 ; CHECK-F-NEXT: fsrmi a0, 1
2636 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2637 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2638 ; CHECK-F-NEXT: li a1, 127
2639 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2640 ; CHECK-F-NEXT: fsrm a0
2641 ; CHECK-F-NEXT: ret
2642 ;
2643 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i32:
2644 ; CHECK-D: # %bb.0:
2645 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2646 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
2647 ; CHECK-D-NEXT: vand.vv v8, v8, v16
2648 ; CHECK-D-NEXT: fsrmi a0, 1
2649 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
2650 ; CHECK-D-NEXT: vsrl.vi v8, v8, 23
2651 ; CHECK-D-NEXT: li a1, 127
2652 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
2653 ; CHECK-D-NEXT: fsrm a0
2654 ; CHECK-D-NEXT: ret
2655 ;
2656 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i32:
2657 ; CHECK-ZVBB: # %bb.0:
2658 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2659 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2660 ; CHECK-ZVBB-NEXT: ret
2661 %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true)
2662 ret <vscale x 16 x i32> %a
2663 }
2665 define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
2666 ; RV32I-LABEL: cttz_zero_undef_nxv1i64:
2667 ; RV32I: # %bb.0:
2668 ; RV32I-NEXT: li a0, 1
2669 ; RV32I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2670 ; RV32I-NEXT: vsub.vx v9, v8, a0
2671 ; RV32I-NEXT: vnot.v v8, v8
2672 ; RV32I-NEXT: vand.vv v8, v8, v9
2673 ; RV32I-NEXT: vsrl.vi v9, v8, 1
2674 ; RV32I-NEXT: lui a0, 349525
2675 ; RV32I-NEXT: addi a0, a0, 1365
2676 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2677 ; RV32I-NEXT: vmv.v.x v10, a0
2678 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2679 ; RV32I-NEXT: vand.vv v9, v9, v10
2680 ; RV32I-NEXT: vsub.vv v8, v8, v9
2681 ; RV32I-NEXT: lui a0, 209715
2682 ; RV32I-NEXT: addi a0, a0, 819
2683 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2684 ; RV32I-NEXT: vmv.v.x v9, a0
2685 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2686 ; RV32I-NEXT: vand.vv v10, v8, v9
2687 ; RV32I-NEXT: vsrl.vi v8, v8, 2
2688 ; RV32I-NEXT: vand.vv v8, v8, v9
2689 ; RV32I-NEXT: vadd.vv v8, v10, v8
2690 ; RV32I-NEXT: vsrl.vi v9, v8, 4
2691 ; RV32I-NEXT: vadd.vv v8, v8, v9
2692 ; RV32I-NEXT: lui a0, 61681
2693 ; RV32I-NEXT: addi a0, a0, -241
2694 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2695 ; RV32I-NEXT: vmv.v.x v9, a0
2696 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2697 ; RV32I-NEXT: vand.vv v8, v8, v9
2698 ; RV32I-NEXT: lui a0, 4112
2699 ; RV32I-NEXT: addi a0, a0, 257
2700 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2701 ; RV32I-NEXT: vmv.v.x v9, a0
2702 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2703 ; RV32I-NEXT: vmul.vv v8, v8, v9
2704 ; RV32I-NEXT: li a0, 56
2705 ; RV32I-NEXT: vsrl.vx v8, v8, a0
2706 ; RV32I-NEXT: ret
2707 ;
2708 ; RV64I-LABEL: cttz_zero_undef_nxv1i64:
2709 ; RV64I: # %bb.0:
2710 ; RV64I-NEXT: li a0, 1
2711 ; RV64I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2712 ; RV64I-NEXT: vsub.vx v9, v8, a0
2713 ; RV64I-NEXT: vnot.v v8, v8
2714 ; RV64I-NEXT: vand.vv v8, v8, v9
2715 ; RV64I-NEXT: vsrl.vi v9, v8, 1
2716 ; RV64I-NEXT: lui a0, 349525
2717 ; RV64I-NEXT: addiw a0, a0, 1365
2718 ; RV64I-NEXT: slli a1, a0, 32
2719 ; RV64I-NEXT: add a0, a0, a1
2720 ; RV64I-NEXT: vand.vx v9, v9, a0
2721 ; RV64I-NEXT: vsub.vv v8, v8, v9
2722 ; RV64I-NEXT: lui a0, 209715
2723 ; RV64I-NEXT: addiw a0, a0, 819
2724 ; RV64I-NEXT: slli a1, a0, 32
2725 ; RV64I-NEXT: add a0, a0, a1
2726 ; RV64I-NEXT: vand.vx v9, v8, a0
2727 ; RV64I-NEXT: vsrl.vi v8, v8, 2
2728 ; RV64I-NEXT: vand.vx v8, v8, a0
2729 ; RV64I-NEXT: vadd.vv v8, v9, v8
2730 ; RV64I-NEXT: vsrl.vi v9, v8, 4
2731 ; RV64I-NEXT: vadd.vv v8, v8, v9
2732 ; RV64I-NEXT: lui a0, 61681
2733 ; RV64I-NEXT: addiw a0, a0, -241
2734 ; RV64I-NEXT: slli a1, a0, 32
2735 ; RV64I-NEXT: add a0, a0, a1
2736 ; RV64I-NEXT: vand.vx v8, v8, a0
2737 ; RV64I-NEXT: lui a0, 4112
2738 ; RV64I-NEXT: addiw a0, a0, 257
2739 ; RV64I-NEXT: slli a1, a0, 32
2740 ; RV64I-NEXT: add a0, a0, a1
2741 ; RV64I-NEXT: vmul.vx v8, v8, a0
2742 ; RV64I-NEXT: li a0, 56
2743 ; RV64I-NEXT: vsrl.vx v8, v8, a0
2744 ; RV64I-NEXT: ret
2745 ;
2746 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i64:
2747 ; CHECK-F: # %bb.0:
2748 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2749 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2750 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2751 ; CHECK-F-NEXT: fsrmi a0, 1
2752 ; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2753 ; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8
2754 ; CHECK-F-NEXT: vsrl.vi v9, v9, 23
2755 ; CHECK-F-NEXT: li a1, 127
2756 ; CHECK-F-NEXT: vwsubu.vx v8, v9, a1
2757 ; CHECK-F-NEXT: fsrm a0
2758 ; CHECK-F-NEXT: ret
2759 ;
2760 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i64:
2761 ; CHECK-D: # %bb.0:
2762 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2763 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2764 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2765 ; CHECK-D-NEXT: fsrmi a0, 1
2766 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
2767 ; CHECK-D-NEXT: li a1, 52
2768 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
2769 ; CHECK-D-NEXT: li a1, 1023
2770 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
2771 ; CHECK-D-NEXT: fsrm a0
2772 ; CHECK-D-NEXT: ret
2773 ;
2774 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i64:
2775 ; CHECK-ZVBB: # %bb.0:
2776 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2777 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2778 ; CHECK-ZVBB-NEXT: ret
2779 %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true)
2780 ret <vscale x 1 x i64> %a
2781 }
2783 define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
2784 ; RV32I-LABEL: cttz_zero_undef_nxv2i64:
2785 ; RV32I: # %bb.0:
2786 ; RV32I-NEXT: li a0, 1
2787 ; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
2788 ; RV32I-NEXT: vsub.vx v10, v8, a0
2789 ; RV32I-NEXT: vnot.v v8, v8
2790 ; RV32I-NEXT: vand.vv v8, v8, v10
2791 ; RV32I-NEXT: vsrl.vi v10, v8, 1
2792 ; RV32I-NEXT: lui a0, 349525
2793 ; RV32I-NEXT: addi a0, a0, 1365
2794 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2795 ; RV32I-NEXT: vmv.v.x v12, a0
2796 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2797 ; RV32I-NEXT: vand.vv v10, v10, v12
2798 ; RV32I-NEXT: vsub.vv v8, v8, v10
2799 ; RV32I-NEXT: lui a0, 209715
2800 ; RV32I-NEXT: addi a0, a0, 819
2801 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2802 ; RV32I-NEXT: vmv.v.x v10, a0
2803 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2804 ; RV32I-NEXT: vand.vv v12, v8, v10
2805 ; RV32I-NEXT: vsrl.vi v8, v8, 2
2806 ; RV32I-NEXT: vand.vv v8, v8, v10
2807 ; RV32I-NEXT: vadd.vv v8, v12, v8
2808 ; RV32I-NEXT: vsrl.vi v10, v8, 4
2809 ; RV32I-NEXT: vadd.vv v8, v8, v10
2810 ; RV32I-NEXT: lui a0, 61681
2811 ; RV32I-NEXT: addi a0, a0, -241
2812 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2813 ; RV32I-NEXT: vmv.v.x v10, a0
2814 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2815 ; RV32I-NEXT: vand.vv v8, v8, v10
2816 ; RV32I-NEXT: lui a0, 4112
2817 ; RV32I-NEXT: addi a0, a0, 257
2818 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2819 ; RV32I-NEXT: vmv.v.x v10, a0
2820 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2821 ; RV32I-NEXT: vmul.vv v8, v8, v10
2822 ; RV32I-NEXT: li a0, 56
2823 ; RV32I-NEXT: vsrl.vx v8, v8, a0
2824 ; RV32I-NEXT: ret
2825 ;
2826 ; RV64I-LABEL: cttz_zero_undef_nxv2i64:
2827 ; RV64I: # %bb.0:
2828 ; RV64I-NEXT: li a0, 1
2829 ; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
2830 ; RV64I-NEXT: vsub.vx v10, v8, a0
2831 ; RV64I-NEXT: vnot.v v8, v8
2832 ; RV64I-NEXT: vand.vv v8, v8, v10
2833 ; RV64I-NEXT: vsrl.vi v10, v8, 1
2834 ; RV64I-NEXT: lui a0, 349525
2835 ; RV64I-NEXT: addiw a0, a0, 1365
2836 ; RV64I-NEXT: slli a1, a0, 32
2837 ; RV64I-NEXT: add a0, a0, a1
2838 ; RV64I-NEXT: vand.vx v10, v10, a0
2839 ; RV64I-NEXT: vsub.vv v8, v8, v10
2840 ; RV64I-NEXT: lui a0, 209715
2841 ; RV64I-NEXT: addiw a0, a0, 819
2842 ; RV64I-NEXT: slli a1, a0, 32
2843 ; RV64I-NEXT: add a0, a0, a1
2844 ; RV64I-NEXT: vand.vx v10, v8, a0
2845 ; RV64I-NEXT: vsrl.vi v8, v8, 2
2846 ; RV64I-NEXT: vand.vx v8, v8, a0
2847 ; RV64I-NEXT: vadd.vv v8, v10, v8
2848 ; RV64I-NEXT: vsrl.vi v10, v8, 4
2849 ; RV64I-NEXT: vadd.vv v8, v8, v10
2850 ; RV64I-NEXT: lui a0, 61681
2851 ; RV64I-NEXT: addiw a0, a0, -241
2852 ; RV64I-NEXT: slli a1, a0, 32
2853 ; RV64I-NEXT: add a0, a0, a1
2854 ; RV64I-NEXT: vand.vx v8, v8, a0
2855 ; RV64I-NEXT: lui a0, 4112
2856 ; RV64I-NEXT: addiw a0, a0, 257
2857 ; RV64I-NEXT: slli a1, a0, 32
2858 ; RV64I-NEXT: add a0, a0, a1
2859 ; RV64I-NEXT: vmul.vx v8, v8, a0
2860 ; RV64I-NEXT: li a0, 56
2861 ; RV64I-NEXT: vsrl.vx v8, v8, a0
2862 ; RV64I-NEXT: ret
2863 ;
2864 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i64:
2865 ; CHECK-F: # %bb.0:
2866 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2867 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2868 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2869 ; CHECK-F-NEXT: fsrmi a0, 1
2870 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
2871 ; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
2872 ; CHECK-F-NEXT: vsrl.vi v10, v10, 23
2873 ; CHECK-F-NEXT: li a1, 127
2874 ; CHECK-F-NEXT: vwsubu.vx v8, v10, a1
2875 ; CHECK-F-NEXT: fsrm a0
2876 ; CHECK-F-NEXT: ret
2877 ;
2878 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i64:
2879 ; CHECK-D: # %bb.0:
2880 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2881 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2882 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2883 ; CHECK-D-NEXT: fsrmi a0, 1
2884 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
2885 ; CHECK-D-NEXT: li a1, 52
2886 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
2887 ; CHECK-D-NEXT: li a1, 1023
2888 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
2889 ; CHECK-D-NEXT: fsrm a0
2890 ; CHECK-D-NEXT: ret
2891 ;
2892 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i64:
2893 ; CHECK-ZVBB: # %bb.0:
2894 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2895 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2896 ; CHECK-ZVBB-NEXT: ret
2897 %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true)
2898 ret <vscale x 2 x i64> %a
2899 }
2901 define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
2902 ; RV32I-LABEL: cttz_zero_undef_nxv4i64:
2903 ; RV32I: # %bb.0:
2904 ; RV32I-NEXT: li a0, 1
2905 ; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
2906 ; RV32I-NEXT: vsub.vx v12, v8, a0
2907 ; RV32I-NEXT: vnot.v v8, v8
2908 ; RV32I-NEXT: vand.vv v8, v8, v12
2909 ; RV32I-NEXT: vsrl.vi v12, v8, 1
2910 ; RV32I-NEXT: lui a0, 349525
2911 ; RV32I-NEXT: addi a0, a0, 1365
2912 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
2913 ; RV32I-NEXT: vmv.v.x v16, a0
2914 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
2915 ; RV32I-NEXT: vand.vv v12, v12, v16
2916 ; RV32I-NEXT: vsub.vv v8, v8, v12
2917 ; RV32I-NEXT: lui a0, 209715
2918 ; RV32I-NEXT: addi a0, a0, 819
2919 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
2920 ; RV32I-NEXT: vmv.v.x v12, a0
2921 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
2922 ; RV32I-NEXT: vand.vv v16, v8, v12
2923 ; RV32I-NEXT: vsrl.vi v8, v8, 2
2924 ; RV32I-NEXT: vand.vv v8, v8, v12
2925 ; RV32I-NEXT: vadd.vv v8, v16, v8
2926 ; RV32I-NEXT: vsrl.vi v12, v8, 4
2927 ; RV32I-NEXT: vadd.vv v8, v8, v12
2928 ; RV32I-NEXT: lui a0, 61681
2929 ; RV32I-NEXT: addi a0, a0, -241
2930 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
2931 ; RV32I-NEXT: vmv.v.x v12, a0
2932 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
2933 ; RV32I-NEXT: vand.vv v8, v8, v12
2934 ; RV32I-NEXT: lui a0, 4112
2935 ; RV32I-NEXT: addi a0, a0, 257
2936 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
2937 ; RV32I-NEXT: vmv.v.x v12, a0
2938 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
2939 ; RV32I-NEXT: vmul.vv v8, v8, v12
2940 ; RV32I-NEXT: li a0, 56
2941 ; RV32I-NEXT: vsrl.vx v8, v8, a0
2942 ; RV32I-NEXT: ret
2943 ;
2944 ; RV64I-LABEL: cttz_zero_undef_nxv4i64:
2945 ; RV64I: # %bb.0:
2946 ; RV64I-NEXT: li a0, 1
2947 ; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
2948 ; RV64I-NEXT: vsub.vx v12, v8, a0
2949 ; RV64I-NEXT: vnot.v v8, v8
2950 ; RV64I-NEXT: vand.vv v8, v8, v12
2951 ; RV64I-NEXT: vsrl.vi v12, v8, 1
2952 ; RV64I-NEXT: lui a0, 349525
2953 ; RV64I-NEXT: addiw a0, a0, 1365
2954 ; RV64I-NEXT: slli a1, a0, 32
2955 ; RV64I-NEXT: add a0, a0, a1
2956 ; RV64I-NEXT: vand.vx v12, v12, a0
2957 ; RV64I-NEXT: vsub.vv v8, v8, v12
2958 ; RV64I-NEXT: lui a0, 209715
2959 ; RV64I-NEXT: addiw a0, a0, 819
2960 ; RV64I-NEXT: slli a1, a0, 32
2961 ; RV64I-NEXT: add a0, a0, a1
2962 ; RV64I-NEXT: vand.vx v12, v8, a0
2963 ; RV64I-NEXT: vsrl.vi v8, v8, 2
2964 ; RV64I-NEXT: vand.vx v8, v8, a0
2965 ; RV64I-NEXT: vadd.vv v8, v12, v8
2966 ; RV64I-NEXT: vsrl.vi v12, v8, 4
2967 ; RV64I-NEXT: vadd.vv v8, v8, v12
2968 ; RV64I-NEXT: lui a0, 61681
2969 ; RV64I-NEXT: addiw a0, a0, -241
2970 ; RV64I-NEXT: slli a1, a0, 32
2971 ; RV64I-NEXT: add a0, a0, a1
2972 ; RV64I-NEXT: vand.vx v8, v8, a0
2973 ; RV64I-NEXT: lui a0, 4112
2974 ; RV64I-NEXT: addiw a0, a0, 257
2975 ; RV64I-NEXT: slli a1, a0, 32
2976 ; RV64I-NEXT: add a0, a0, a1
2977 ; RV64I-NEXT: vmul.vx v8, v8, a0
2978 ; RV64I-NEXT: li a0, 56
2979 ; RV64I-NEXT: vsrl.vx v8, v8, a0
2980 ; RV64I-NEXT: ret
2981 ;
2982 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i64:
2983 ; CHECK-F: # %bb.0:
2984 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
2985 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
2986 ; CHECK-F-NEXT: vand.vv v8, v8, v12
2987 ; CHECK-F-NEXT: fsrmi a0, 1
2988 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
2989 ; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8
2990 ; CHECK-F-NEXT: vsrl.vi v12, v12, 23
2991 ; CHECK-F-NEXT: li a1, 127
2992 ; CHECK-F-NEXT: vwsubu.vx v8, v12, a1
2993 ; CHECK-F-NEXT: fsrm a0
2994 ; CHECK-F-NEXT: ret
2995 ;
2996 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i64:
2997 ; CHECK-D: # %bb.0:
2998 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
2999 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
3000 ; CHECK-D-NEXT: vand.vv v8, v8, v12
3001 ; CHECK-D-NEXT: fsrmi a0, 1
3002 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3003 ; CHECK-D-NEXT: li a1, 52
3004 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3005 ; CHECK-D-NEXT: li a1, 1023
3006 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3007 ; CHECK-D-NEXT: fsrm a0
3008 ; CHECK-D-NEXT: ret
3009 ;
3010 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i64:
3011 ; CHECK-ZVBB: # %bb.0:
3012 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3013 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3014 ; CHECK-ZVBB-NEXT: ret
3015 %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true)
3016 ret <vscale x 4 x i64> %a
3017 }
3019 define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
3020 ; RV32I-LABEL: cttz_zero_undef_nxv8i64:
3021 ; RV32I: # %bb.0:
3022 ; RV32I-NEXT: li a0, 1
3023 ; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
3024 ; RV32I-NEXT: vsub.vx v16, v8, a0
3025 ; RV32I-NEXT: vnot.v v8, v8
3026 ; RV32I-NEXT: vand.vv v8, v8, v16
3027 ; RV32I-NEXT: vsrl.vi v16, v8, 1
3028 ; RV32I-NEXT: lui a0, 349525
3029 ; RV32I-NEXT: addi a0, a0, 1365
3030 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3031 ; RV32I-NEXT: vmv.v.x v24, a0
3032 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3033 ; RV32I-NEXT: vand.vv v16, v16, v24
3034 ; RV32I-NEXT: vsub.vv v8, v8, v16
3035 ; RV32I-NEXT: lui a0, 209715
3036 ; RV32I-NEXT: addi a0, a0, 819
3037 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3038 ; RV32I-NEXT: vmv.v.x v16, a0
3039 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3040 ; RV32I-NEXT: vand.vv v24, v8, v16
3041 ; RV32I-NEXT: vsrl.vi v8, v8, 2
3042 ; RV32I-NEXT: vand.vv v8, v8, v16
3043 ; RV32I-NEXT: vadd.vv v8, v24, v8
3044 ; RV32I-NEXT: vsrl.vi v16, v8, 4
3045 ; RV32I-NEXT: vadd.vv v8, v8, v16
3046 ; RV32I-NEXT: lui a0, 61681
3047 ; RV32I-NEXT: addi a0, a0, -241
3048 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3049 ; RV32I-NEXT: vmv.v.x v16, a0
3050 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3051 ; RV32I-NEXT: vand.vv v8, v8, v16
3052 ; RV32I-NEXT: lui a0, 4112
3053 ; RV32I-NEXT: addi a0, a0, 257
3054 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3055 ; RV32I-NEXT: vmv.v.x v16, a0
3056 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3057 ; RV32I-NEXT: vmul.vv v8, v8, v16
3058 ; RV32I-NEXT: li a0, 56
3059 ; RV32I-NEXT: vsrl.vx v8, v8, a0
3060 ; RV32I-NEXT: ret
3061 ;
3062 ; RV64I-LABEL: cttz_zero_undef_nxv8i64:
3063 ; RV64I: # %bb.0:
3064 ; RV64I-NEXT: li a0, 1
3065 ; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
3066 ; RV64I-NEXT: vsub.vx v16, v8, a0
3067 ; RV64I-NEXT: vnot.v v8, v8
3068 ; RV64I-NEXT: vand.vv v8, v8, v16
3069 ; RV64I-NEXT: vsrl.vi v16, v8, 1
3070 ; RV64I-NEXT: lui a0, 349525
3071 ; RV64I-NEXT: addiw a0, a0, 1365
3072 ; RV64I-NEXT: slli a1, a0, 32
3073 ; RV64I-NEXT: add a0, a0, a1
3074 ; RV64I-NEXT: vand.vx v16, v16, a0
3075 ; RV64I-NEXT: vsub.vv v8, v8, v16
3076 ; RV64I-NEXT: lui a0, 209715
3077 ; RV64I-NEXT: addiw a0, a0, 819
3078 ; RV64I-NEXT: slli a1, a0, 32
3079 ; RV64I-NEXT: add a0, a0, a1
3080 ; RV64I-NEXT: vand.vx v16, v8, a0
3081 ; RV64I-NEXT: vsrl.vi v8, v8, 2
3082 ; RV64I-NEXT: vand.vx v8, v8, a0
3083 ; RV64I-NEXT: vadd.vv v8, v16, v8
3084 ; RV64I-NEXT: vsrl.vi v16, v8, 4
3085 ; RV64I-NEXT: vadd.vv v8, v8, v16
3086 ; RV64I-NEXT: lui a0, 61681
3087 ; RV64I-NEXT: addiw a0, a0, -241
3088 ; RV64I-NEXT: slli a1, a0, 32
3089 ; RV64I-NEXT: add a0, a0, a1
3090 ; RV64I-NEXT: vand.vx v8, v8, a0
3091 ; RV64I-NEXT: lui a0, 4112
3092 ; RV64I-NEXT: addiw a0, a0, 257
3093 ; RV64I-NEXT: slli a1, a0, 32
3094 ; RV64I-NEXT: add a0, a0, a1
3095 ; RV64I-NEXT: vmul.vx v8, v8, a0
3096 ; RV64I-NEXT: li a0, 56
3097 ; RV64I-NEXT: vsrl.vx v8, v8, a0
3098 ; RV64I-NEXT: ret
3099 ;
3100 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i64:
3101 ; CHECK-F: # %bb.0:
3102 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3103 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
3104 ; CHECK-F-NEXT: vand.vv v8, v8, v16
3105 ; CHECK-F-NEXT: fsrmi a0, 1
3106 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3107 ; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8
3108 ; CHECK-F-NEXT: vsrl.vi v16, v16, 23
3109 ; CHECK-F-NEXT: li a1, 127
3110 ; CHECK-F-NEXT: vwsubu.vx v8, v16, a1
3111 ; CHECK-F-NEXT: fsrm a0
3112 ; CHECK-F-NEXT: ret
3113 ;
3114 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i64:
3115 ; CHECK-D: # %bb.0:
3116 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3117 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
3118 ; CHECK-D-NEXT: vand.vv v8, v8, v16
3119 ; CHECK-D-NEXT: fsrmi a0, 1
3120 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3121 ; CHECK-D-NEXT: li a1, 52
3122 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3123 ; CHECK-D-NEXT: li a1, 1023
3124 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3125 ; CHECK-D-NEXT: fsrm a0
3126 ; CHECK-D-NEXT: ret
3127 ;
3128 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i64:
3129 ; CHECK-ZVBB: # %bb.0:
3130 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3131 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3132 ; CHECK-ZVBB-NEXT: ret
3133 %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true)
3134 ret <vscale x 8 x i64> %a
3135 }
3136 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
3137 ; RV32: {{.*}}
3138 ; RV32D: {{.*}}
3139 ; RV32F: {{.*}}
3140 ; RV64: {{.*}}
3141 ; RV64D: {{.*}}
3142 ; RV64F: {{.*}}