| blob | 26ed4595ca7583661596e5f55ec6c07ace9b3a99 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
3 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH
4 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH
5 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RV64V
6 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RVA22U64
7 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFHMIN
8 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFHMIN
10 ; Tests that a floating-point build_vector doesn't try and generate a VID
11 ; instruction
12 define void @buildvec_no_vid_v4f32(ptr %x) {
13 ; CHECK-LABEL: buildvec_no_vid_v4f32:
14 ; CHECK: # %bb.0:
15 ; CHECK-NEXT: lui a1, %hi(.LCPI0_0)
16 ; CHECK-NEXT: addi a1, a1, %lo(.LCPI0_0)
17 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
18 ; CHECK-NEXT: vle32.v v8, (a1)
19 ; CHECK-NEXT: vse32.v v8, (a0)
20 ; CHECK-NEXT: ret
21 store <4 x float> <float 0.0, float 4.0, float 0.0, float 2.0>, ptr %x
22 ret void
23 }
25 ; Not all BUILD_VECTORs are successfully lowered by the backend: some are
26 ; expanded into scalarized stack stores. However, this may result in an
27 ; infinite loop in the DAGCombiner which tries to recombine those stores into a
28 ; BUILD_VECTOR followed by a vector store. The BUILD_VECTOR is then expanded
29 ; and the loop begins.
30 ; Until all BUILD_VECTORs are lowered, we disable store-combining after
31 ; legalization for fixed-length vectors.
32 ; This test uses a trick with a shufflevector which can't be lowered to a
33 ; SHUFFLE_VECTOR node; the mask is shorter than the source vectors and the
34 ; shuffle indices aren't located within the same 4-element subvector, so is
35 ; expanded to 4 EXTRACT_VECTOR_ELTs and a BUILD_VECTOR. This then triggers the
36 ; loop when expanded.
37 define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, <8 x float> %y) optsize {
38 ; CHECK-LABEL: hang_when_merging_stores_after_legalization:
39 ; CHECK: # %bb.0:
40 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
41 ; CHECK-NEXT: vid.v v12
42 ; CHECK-NEXT: li a0, 7
43 ; CHECK-NEXT: vmul.vx v14, v12, a0
44 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
45 ; CHECK-NEXT: vrgatherei16.vv v12, v8, v14
46 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
47 ; CHECK-NEXT: vmv.v.i v0, 12
48 ; CHECK-NEXT: vadd.vi v8, v14, -14
49 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
50 ; CHECK-NEXT: vrgatherei16.vv v12, v10, v8, v0.t
51 ; CHECK-NEXT: vmv1r.v v8, v12
52 ; CHECK-NEXT: ret
53 %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15>
54 ret <4 x float> %z
55 }
57 define void @buildvec_dominant0_v2f32(ptr %x) {
58 ; CHECK-LABEL: buildvec_dominant0_v2f32:
59 ; CHECK: # %bb.0:
60 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
61 ; CHECK-NEXT: vid.v v8
62 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
63 ; CHECK-NEXT: vse32.v v8, (a0)
64 ; CHECK-NEXT: ret
65 store <2 x float> <float 0.0, float 1.0>, ptr %x
66 ret void
67 }
69 ; We don't want to lower this to the insertion of two scalar elements as above,
70 ; as each would require their own load from the constant pool.
72 define void @buildvec_dominant1_v2f32(ptr %x) {
73 ; CHECK-LABEL: buildvec_dominant1_v2f32:
74 ; CHECK: # %bb.0:
75 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
76 ; CHECK-NEXT: vid.v v8
77 ; CHECK-NEXT: vadd.vi v8, v8, 1
78 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
79 ; CHECK-NEXT: vse32.v v8, (a0)
80 ; CHECK-NEXT: ret
81 store <2 x float> <float 1.0, float 2.0>, ptr %x
82 ret void
83 }
85 define void @buildvec_dominant0_v4f32(ptr %x) {
86 ; CHECK-LABEL: buildvec_dominant0_v4f32:
87 ; CHECK: # %bb.0:
88 ; CHECK-NEXT: lui a1, 262144
89 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
90 ; CHECK-NEXT: vmv.v.x v8, a1
91 ; CHECK-NEXT: vmv.s.x v9, zero
92 ; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
93 ; CHECK-NEXT: vslideup.vi v8, v9, 2
94 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
95 ; CHECK-NEXT: vse32.v v8, (a0)
96 ; CHECK-NEXT: ret
97 store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, ptr %x
98 ret void
99 }
101 define void @buildvec_dominant1_v4f32(ptr %x, float %f) {
102 ; CHECK-LABEL: buildvec_dominant1_v4f32:
103 ; CHECK: # %bb.0:
104 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
105 ; CHECK-NEXT: vfmv.v.f v8, fa0
106 ; CHECK-NEXT: vmv.s.x v9, zero
107 ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
108 ; CHECK-NEXT: vslideup.vi v8, v9, 1
109 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
110 ; CHECK-NEXT: vse32.v v8, (a0)
111 ; CHECK-NEXT: ret
112 %v0 = insertelement <4 x float> poison, float %f, i32 0
113 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1
114 %v2 = insertelement <4 x float> %v1, float %f, i32 2
115 %v3 = insertelement <4 x float> %v2, float %f, i32 3
116 store <4 x float> %v3, ptr %x
117 ret void
118 }
120 define void @buildvec_dominant2_v4f32(ptr %x, float %f) {
121 ; CHECK-LABEL: buildvec_dominant2_v4f32:
122 ; CHECK: # %bb.0:
123 ; CHECK-NEXT: lui a1, 262144
124 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
125 ; CHECK-NEXT: vmv.s.x v8, a1
126 ; CHECK-NEXT: vfmv.v.f v9, fa0
127 ; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
128 ; CHECK-NEXT: vslideup.vi v9, v8, 1
129 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
130 ; CHECK-NEXT: vse32.v v9, (a0)
131 ; CHECK-NEXT: ret
132 %v0 = insertelement <4 x float> poison, float %f, i32 0
133 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1
134 %v2 = insertelement <4 x float> %v1, float %f, i32 2
135 %v3 = insertelement <4 x float> %v2, float %f, i32 3
136 store <4 x float> %v3, ptr %x
137 ret void
138 }
140 define void @buildvec_merge0_v4f32(ptr %x, float %f) {
141 ; CHECK-LABEL: buildvec_merge0_v4f32:
142 ; CHECK: # %bb.0:
143 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
144 ; CHECK-NEXT: vfmv.v.f v8, fa0
145 ; CHECK-NEXT: vmv.v.i v0, 6
146 ; CHECK-NEXT: lui a1, 262144
147 ; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
148 ; CHECK-NEXT: vse32.v v8, (a0)
149 ; CHECK-NEXT: ret
150 %v0 = insertelement <4 x float> poison, float %f, i32 0
151 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1
152 %v2 = insertelement <4 x float> %v1, float 2.0, i32 2
153 %v3 = insertelement <4 x float> %v2, float %f, i32 3
154 store <4 x float> %v3, ptr %x
155 ret void
156 }
158 define <4 x half> @splat_c3_v4f16(<4 x half> %v) {
159 ; CHECK-LABEL: splat_c3_v4f16:
160 ; CHECK: # %bb.0:
161 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
162 ; CHECK-NEXT: vrgather.vi v9, v8, 3
163 ; CHECK-NEXT: vmv1r.v v8, v9
164 ; CHECK-NEXT: ret
165 %x = extractelement <4 x half> %v, i32 3
166 %ins = insertelement <4 x half> poison, half %x, i32 0
167 %splat = shufflevector <4 x half> %ins, <4 x half> poison, <4 x i32> zeroinitializer
168 ret <4 x half> %splat
169 }
171 define <4 x half> @splat_idx_v4f16(<4 x half> %v, i64 %idx) {
172 ; CHECK-LABEL: splat_idx_v4f16:
173 ; CHECK: # %bb.0:
174 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
175 ; CHECK-NEXT: vrgather.vx v9, v8, a0
176 ; CHECK-NEXT: vmv1r.v v8, v9
177 ; CHECK-NEXT: ret
178 %x = extractelement <4 x half> %v, i64 %idx
179 %ins = insertelement <4 x half> poison, half %x, i32 0
180 %splat = shufflevector <4 x half> %ins, <4 x half> poison, <4 x i32> zeroinitializer
181 ret <4 x half> %splat
182 }
184 define <8 x float> @splat_c5_v8f32(<8 x float> %v) {
185 ; CHECK-LABEL: splat_c5_v8f32:
186 ; CHECK: # %bb.0:
187 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
188 ; CHECK-NEXT: vrgather.vi v10, v8, 5
189 ; CHECK-NEXT: vmv.v.v v8, v10
190 ; CHECK-NEXT: ret
191 %x = extractelement <8 x float> %v, i32 5
192 %ins = insertelement <8 x float> poison, float %x, i32 0
193 %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer
194 ret <8 x float> %splat
195 }
197 define <8 x float> @splat_idx_v8f32(<8 x float> %v, i64 %idx) {
198 ;
199 ; CHECK-LABEL: splat_idx_v8f32:
200 ; CHECK: # %bb.0:
201 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
202 ; CHECK-NEXT: vrgather.vx v10, v8, a0
203 ; CHECK-NEXT: vmv.v.v v8, v10
204 ; CHECK-NEXT: ret
205 %x = extractelement <8 x float> %v, i64 %idx
206 %ins = insertelement <8 x float> poison, float %x, i32 0
207 %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer
208 ret <8 x float> %splat
209 }
211 ; Test that we pull the vlse of the constant pool out of the loop.
212 define dso_local void @splat_load_licm(ptr %0) {
213 ; RV32-LABEL: splat_load_licm:
214 ; RV32: # %bb.0:
215 ; RV32-NEXT: lui a1, 1
216 ; RV32-NEXT: add a1, a0, a1
217 ; RV32-NEXT: lui a2, 263168
218 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
219 ; RV32-NEXT: vmv.v.x v8, a2
220 ; RV32-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
221 ; RV32-NEXT: vse32.v v8, (a0)
222 ; RV32-NEXT: addi a0, a0, 16
223 ; RV32-NEXT: bne a0, a1, .LBB12_1
224 ; RV32-NEXT: # %bb.2:
225 ; RV32-NEXT: ret
226 ;
227 ; RV64V-LABEL: splat_load_licm:
228 ; RV64V: # %bb.0:
229 ; RV64V-NEXT: lui a1, 1
230 ; RV64V-NEXT: add a1, a0, a1
231 ; RV64V-NEXT: lui a2, 263168
232 ; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
233 ; RV64V-NEXT: vmv.v.x v8, a2
234 ; RV64V-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
235 ; RV64V-NEXT: vse32.v v8, (a0)
236 ; RV64V-NEXT: addi a0, a0, 16
237 ; RV64V-NEXT: bne a0, a1, .LBB12_1
238 ; RV64V-NEXT: # %bb.2:
239 ; RV64V-NEXT: ret
240 ;
241 ; RVA22U64-LABEL: splat_load_licm:
242 ; RVA22U64: # %bb.0:
243 ; RVA22U64-NEXT: lui a1, 1
244 ; RVA22U64-NEXT: add a1, a1, a0
245 ; RVA22U64-NEXT: lui a2, 263168
246 ; RVA22U64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
247 ; RVA22U64-NEXT: vmv.v.x v8, a2
248 ; RVA22U64-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
249 ; RVA22U64-NEXT: vse32.v v8, (a0)
250 ; RVA22U64-NEXT: addi a0, a0, 16
251 ; RVA22U64-NEXT: bne a0, a1, .LBB12_1
252 ; RVA22U64-NEXT: # %bb.2:
253 ; RVA22U64-NEXT: ret
254 ;
255 ; RV64ZVFHMIN-LABEL: splat_load_licm:
256 ; RV64ZVFHMIN: # %bb.0:
257 ; RV64ZVFHMIN-NEXT: lui a1, 1
258 ; RV64ZVFHMIN-NEXT: add a1, a0, a1
259 ; RV64ZVFHMIN-NEXT: lui a2, 263168
260 ; RV64ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
261 ; RV64ZVFHMIN-NEXT: vmv.v.x v8, a2
262 ; RV64ZVFHMIN-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
263 ; RV64ZVFHMIN-NEXT: vse32.v v8, (a0)
264 ; RV64ZVFHMIN-NEXT: addi a0, a0, 16
265 ; RV64ZVFHMIN-NEXT: bne a0, a1, .LBB12_1
266 ; RV64ZVFHMIN-NEXT: # %bb.2:
267 ; RV64ZVFHMIN-NEXT: ret
268 br label %2
270 2: ; preds = %2, %1
271 %3 = phi i32 [ 0, %1 ], [ %6, %2 ]
272 %4 = getelementptr inbounds float, ptr %0, i32 %3
273 %5 = bitcast ptr %4 to ptr
274 store <4 x float> <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>, ptr %5, align 4
275 %6 = add nuw i32 %3, 4
276 %7 = icmp eq i32 %6, 1024
277 br i1 %7, label %8, label %2
279 8: ; preds = %2
280 ret void
281 }
283 define <2 x half> @buildvec_v2f16(half %a, half %b) {
284 ; RV32ZVFH-LABEL: buildvec_v2f16:
285 ; RV32ZVFH: # %bb.0:
286 ; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
287 ; RV32ZVFH-NEXT: vfmv.v.f v8, fa0
288 ; RV32ZVFH-NEXT: vfslide1down.vf v8, v8, fa1
289 ; RV32ZVFH-NEXT: ret
290 ;
291 ; RV64ZVFH-LABEL: buildvec_v2f16:
292 ; RV64ZVFH: # %bb.0:
293 ; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
294 ; RV64ZVFH-NEXT: vfmv.v.f v8, fa0
295 ; RV64ZVFH-NEXT: vfslide1down.vf v8, v8, fa1
296 ; RV64ZVFH-NEXT: ret
297 ;
298 ; RV32ZVFHMIN-LABEL: buildvec_v2f16:
299 ; RV32ZVFHMIN: # %bb.0:
300 ; RV32ZVFHMIN-NEXT: fmv.x.w a0, fa1
301 ; RV32ZVFHMIN-NEXT: fmv.x.w a1, fa0
302 ; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
303 ; RV32ZVFHMIN-NEXT: vmv.v.x v8, a1
304 ; RV32ZVFHMIN-NEXT: vslide1down.vx v8, v8, a0
305 ; RV32ZVFHMIN-NEXT: ret
306 ;
307 ; RV64ZVFHMIN-LABEL: buildvec_v2f16:
308 ; RV64ZVFHMIN: # %bb.0:
309 ; RV64ZVFHMIN-NEXT: fmv.x.w a0, fa1
310 ; RV64ZVFHMIN-NEXT: fmv.x.w a1, fa0
311 ; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
312 ; RV64ZVFHMIN-NEXT: vmv.v.x v8, a1
313 ; RV64ZVFHMIN-NEXT: vslide1down.vx v8, v8, a0
314 ; RV64ZVFHMIN-NEXT: ret
315 %v1 = insertelement <2 x half> poison, half %a, i64 0
316 %v2 = insertelement <2 x half> %v1, half %b, i64 1
317 ret <2 x half> %v2
318 }
320 define <2 x float> @buildvec_v2f32(float %a, float %b) {
321 ; CHECK-LABEL: buildvec_v2f32:
322 ; CHECK: # %bb.0:
323 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
324 ; CHECK-NEXT: vfmv.v.f v8, fa0
325 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
326 ; CHECK-NEXT: ret
327 %v1 = insertelement <2 x float> poison, float %a, i64 0
328 %v2 = insertelement <2 x float> %v1, float %b, i64 1
329 ret <2 x float> %v2
330 }
332 define <2 x double> @buildvec_v2f64(double %a, double %b) {
333 ; CHECK-LABEL: buildvec_v2f64:
334 ; CHECK: # %bb.0:
335 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
336 ; CHECK-NEXT: vfmv.v.f v8, fa0
337 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
338 ; CHECK-NEXT: ret
339 %v1 = insertelement <2 x double> poison, double %a, i64 0
340 %v2 = insertelement <2 x double> %v1, double %b, i64 1
341 ret <2 x double> %v2
342 }
344 define <2 x double> @buildvec_v2f64_b(double %a, double %b) {
345 ; CHECK-LABEL: buildvec_v2f64_b:
346 ; CHECK: # %bb.0:
347 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
348 ; CHECK-NEXT: vfmv.v.f v8, fa0
349 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
350 ; CHECK-NEXT: ret
351 %v1 = insertelement <2 x double> poison, double %b, i64 1
352 %v2 = insertelement <2 x double> %v1, double %a, i64 0
353 ret <2 x double> %v2
354 }
356 define <4 x float> @buildvec_v4f32(float %a, float %b, float %c, float %d) {
357 ; CHECK-LABEL: buildvec_v4f32:
358 ; CHECK: # %bb.0:
359 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
360 ; CHECK-NEXT: vfmv.v.f v8, fa0
361 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
362 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa2
363 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa3
364 ; CHECK-NEXT: ret
365 %v1 = insertelement <4 x float> poison, float %a, i64 0
366 %v2 = insertelement <4 x float> %v1, float %b, i64 1
367 %v3 = insertelement <4 x float> %v2, float %c, i64 2
368 %v4 = insertelement <4 x float> %v3, float %d, i64 3
369 ret <4 x float> %v4
370 }
372 define <8 x float> @buildvec_v8f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7) {
373 ; CHECK-LABEL: buildvec_v8f32:
374 ; CHECK: # %bb.0:
375 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
376 ; CHECK-NEXT: vfmv.v.f v8, fa0
377 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
378 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa2
379 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa3
380 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa4
381 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
382 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa6
383 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa7
384 ; CHECK-NEXT: ret
385 %v0 = insertelement <8 x float> poison, float %e0, i64 0
386 %v1 = insertelement <8 x float> %v0, float %e1, i64 1
387 %v2 = insertelement <8 x float> %v1, float %e2, i64 2
388 %v3 = insertelement <8 x float> %v2, float %e3, i64 3
389 %v4 = insertelement <8 x float> %v3, float %e4, i64 4
390 %v5 = insertelement <8 x float> %v4, float %e5, i64 5
391 %v6 = insertelement <8 x float> %v5, float %e6, i64 6
392 %v7 = insertelement <8 x float> %v6, float %e7, i64 7
393 ret <8 x float> %v7
394 }
396 define <16 x float> @buildvec_v16f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7, float %e8, float %e9, float %e10, float %e11, float %e12, float %e13, float %e14, float %e15) {
397 ; RV32-LABEL: buildvec_v16f32:
398 ; RV32: # %bb.0:
399 ; RV32-NEXT: addi sp, sp, -128
400 ; RV32-NEXT: .cfi_def_cfa_offset 128
401 ; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
402 ; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
403 ; RV32-NEXT: .cfi_offset ra, -4
404 ; RV32-NEXT: .cfi_offset s0, -8
405 ; RV32-NEXT: addi s0, sp, 128
406 ; RV32-NEXT: .cfi_def_cfa s0, 0
407 ; RV32-NEXT: andi sp, sp, -64
408 ; RV32-NEXT: sw a7, 60(sp)
409 ; RV32-NEXT: sw a6, 56(sp)
410 ; RV32-NEXT: sw a5, 52(sp)
411 ; RV32-NEXT: sw a4, 48(sp)
412 ; RV32-NEXT: sw a3, 44(sp)
413 ; RV32-NEXT: sw a2, 40(sp)
414 ; RV32-NEXT: sw a1, 36(sp)
415 ; RV32-NEXT: sw a0, 32(sp)
416 ; RV32-NEXT: fsw fa7, 28(sp)
417 ; RV32-NEXT: fsw fa6, 24(sp)
418 ; RV32-NEXT: fsw fa5, 20(sp)
419 ; RV32-NEXT: fsw fa4, 16(sp)
420 ; RV32-NEXT: fsw fa3, 12(sp)
421 ; RV32-NEXT: fsw fa2, 8(sp)
422 ; RV32-NEXT: fsw fa1, 4(sp)
423 ; RV32-NEXT: fsw fa0, 0(sp)
424 ; RV32-NEXT: mv a0, sp
425 ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
426 ; RV32-NEXT: vle32.v v8, (a0)
427 ; RV32-NEXT: addi sp, s0, -128
428 ; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
429 ; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
430 ; RV32-NEXT: addi sp, sp, 128
431 ; RV32-NEXT: ret
432 ;
433 ; RV64-LABEL: buildvec_v16f32:
434 ; RV64: # %bb.0:
435 ; RV64-NEXT: addi sp, sp, -128
436 ; RV64-NEXT: .cfi_def_cfa_offset 128
437 ; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
438 ; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
439 ; RV64-NEXT: .cfi_offset ra, -8
440 ; RV64-NEXT: .cfi_offset s0, -16
441 ; RV64-NEXT: addi s0, sp, 128
442 ; RV64-NEXT: .cfi_def_cfa s0, 0
443 ; RV64-NEXT: andi sp, sp, -64
444 ; RV64-NEXT: fmv.w.x ft0, a0
445 ; RV64-NEXT: fmv.w.x ft1, a1
446 ; RV64-NEXT: fmv.w.x ft2, a2
447 ; RV64-NEXT: fmv.w.x ft3, a3
448 ; RV64-NEXT: fmv.w.x ft4, a4
449 ; RV64-NEXT: fmv.w.x ft5, a5
450 ; RV64-NEXT: fmv.w.x ft6, a6
451 ; RV64-NEXT: fmv.w.x ft7, a7
452 ; RV64-NEXT: fsw fa7, 28(sp)
453 ; RV64-NEXT: fsw fa6, 24(sp)
454 ; RV64-NEXT: fsw fa5, 20(sp)
455 ; RV64-NEXT: fsw fa4, 16(sp)
456 ; RV64-NEXT: fsw fa3, 12(sp)
457 ; RV64-NEXT: fsw fa2, 8(sp)
458 ; RV64-NEXT: fsw fa1, 4(sp)
459 ; RV64-NEXT: fsw fa0, 0(sp)
460 ; RV64-NEXT: fsw ft7, 60(sp)
461 ; RV64-NEXT: fsw ft6, 56(sp)
462 ; RV64-NEXT: fsw ft5, 52(sp)
463 ; RV64-NEXT: fsw ft4, 48(sp)
464 ; RV64-NEXT: fsw ft3, 44(sp)
465 ; RV64-NEXT: fsw ft2, 40(sp)
466 ; RV64-NEXT: fsw ft1, 36(sp)
467 ; RV64-NEXT: fsw ft0, 32(sp)
468 ; RV64-NEXT: mv a0, sp
469 ; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
470 ; RV64-NEXT: vle32.v v8, (a0)
471 ; RV64-NEXT: addi sp, s0, -128
472 ; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
473 ; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
474 ; RV64-NEXT: addi sp, sp, 128
475 ; RV64-NEXT: ret
476 %v0 = insertelement <16 x float> poison, float %e0, i64 0
477 %v1 = insertelement <16 x float> %v0, float %e1, i64 1
478 %v2 = insertelement <16 x float> %v1, float %e2, i64 2
479 %v3 = insertelement <16 x float> %v2, float %e3, i64 3
480 %v4 = insertelement <16 x float> %v3, float %e4, i64 4
481 %v5 = insertelement <16 x float> %v4, float %e5, i64 5
482 %v6 = insertelement <16 x float> %v5, float %e6, i64 6
483 %v7 = insertelement <16 x float> %v6, float %e7, i64 7
484 %v8 = insertelement <16 x float> %v7, float %e8, i64 8
485 %v9 = insertelement <16 x float> %v8, float %e9, i64 9
486 %v10 = insertelement <16 x float> %v9, float %e10, i64 10
487 %v11 = insertelement <16 x float> %v10, float %e11, i64 11
488 %v12 = insertelement <16 x float> %v11, float %e12, i64 12
489 %v13 = insertelement <16 x float> %v12, float %e13, i64 13
490 %v14 = insertelement <16 x float> %v13, float %e14, i64 14
491 %v15 = insertelement <16 x float> %v14, float %e15, i64 15
492 ret <16 x float> %v15
493 }
495 define <32 x float> @buildvec_v32f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7, float %e8, float %e9, float %e10, float %e11, float %e12, float %e13, float %e14, float %e15, float %e16, float %e17, float %e18, float %e19, float %e20, float %e21, float %e22, float %e23, float %e24, float %e25, float %e26, float %e27, float %e28, float %e29, float %e30, float %e31) {
496 ; RV32-LABEL: buildvec_v32f32:
497 ; RV32: # %bb.0:
498 ; RV32-NEXT: addi sp, sp, -256
499 ; RV32-NEXT: .cfi_def_cfa_offset 256
500 ; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
501 ; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
502 ; RV32-NEXT: fsd fs0, 240(sp) # 8-byte Folded Spill
503 ; RV32-NEXT: fsd fs1, 232(sp) # 8-byte Folded Spill
504 ; RV32-NEXT: fsd fs2, 224(sp) # 8-byte Folded Spill
505 ; RV32-NEXT: fsd fs3, 216(sp) # 8-byte Folded Spill
506 ; RV32-NEXT: .cfi_offset ra, -4
507 ; RV32-NEXT: .cfi_offset s0, -8
508 ; RV32-NEXT: .cfi_offset fs0, -16
509 ; RV32-NEXT: .cfi_offset fs1, -24
510 ; RV32-NEXT: .cfi_offset fs2, -32
511 ; RV32-NEXT: .cfi_offset fs3, -40
512 ; RV32-NEXT: addi s0, sp, 256
513 ; RV32-NEXT: .cfi_def_cfa s0, 0
514 ; RV32-NEXT: andi sp, sp, -128
515 ; RV32-NEXT: flw ft0, 0(s0)
516 ; RV32-NEXT: flw ft1, 4(s0)
517 ; RV32-NEXT: flw ft2, 8(s0)
518 ; RV32-NEXT: flw ft3, 12(s0)
519 ; RV32-NEXT: flw ft4, 16(s0)
520 ; RV32-NEXT: flw ft5, 20(s0)
521 ; RV32-NEXT: flw ft6, 24(s0)
522 ; RV32-NEXT: flw ft7, 28(s0)
523 ; RV32-NEXT: flw ft8, 32(s0)
524 ; RV32-NEXT: flw ft9, 36(s0)
525 ; RV32-NEXT: flw ft10, 40(s0)
526 ; RV32-NEXT: flw ft11, 44(s0)
527 ; RV32-NEXT: flw fs0, 60(s0)
528 ; RV32-NEXT: flw fs1, 56(s0)
529 ; RV32-NEXT: flw fs2, 52(s0)
530 ; RV32-NEXT: flw fs3, 48(s0)
531 ; RV32-NEXT: fsw fs0, 124(sp)
532 ; RV32-NEXT: fsw fs1, 120(sp)
533 ; RV32-NEXT: fsw fs2, 116(sp)
534 ; RV32-NEXT: fsw fs3, 112(sp)
535 ; RV32-NEXT: fsw ft11, 108(sp)
536 ; RV32-NEXT: fsw ft10, 104(sp)
537 ; RV32-NEXT: fsw ft9, 100(sp)
538 ; RV32-NEXT: fsw ft8, 96(sp)
539 ; RV32-NEXT: fsw ft7, 92(sp)
540 ; RV32-NEXT: fsw ft6, 88(sp)
541 ; RV32-NEXT: fsw ft5, 84(sp)
542 ; RV32-NEXT: fsw ft4, 80(sp)
543 ; RV32-NEXT: fsw ft3, 76(sp)
544 ; RV32-NEXT: fsw ft2, 72(sp)
545 ; RV32-NEXT: fsw ft1, 68(sp)
546 ; RV32-NEXT: fsw ft0, 64(sp)
547 ; RV32-NEXT: sw a7, 60(sp)
548 ; RV32-NEXT: sw a6, 56(sp)
549 ; RV32-NEXT: sw a5, 52(sp)
550 ; RV32-NEXT: sw a4, 48(sp)
551 ; RV32-NEXT: sw a3, 44(sp)
552 ; RV32-NEXT: sw a2, 40(sp)
553 ; RV32-NEXT: sw a1, 36(sp)
554 ; RV32-NEXT: sw a0, 32(sp)
555 ; RV32-NEXT: fsw fa7, 28(sp)
556 ; RV32-NEXT: fsw fa6, 24(sp)
557 ; RV32-NEXT: fsw fa5, 20(sp)
558 ; RV32-NEXT: fsw fa4, 16(sp)
559 ; RV32-NEXT: fsw fa3, 12(sp)
560 ; RV32-NEXT: fsw fa2, 8(sp)
561 ; RV32-NEXT: fsw fa1, 4(sp)
562 ; RV32-NEXT: fsw fa0, 0(sp)
563 ; RV32-NEXT: li a0, 32
564 ; RV32-NEXT: mv a1, sp
565 ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
566 ; RV32-NEXT: vle32.v v8, (a1)
567 ; RV32-NEXT: addi sp, s0, -256
568 ; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
569 ; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
570 ; RV32-NEXT: fld fs0, 240(sp) # 8-byte Folded Reload
571 ; RV32-NEXT: fld fs1, 232(sp) # 8-byte Folded Reload
572 ; RV32-NEXT: fld fs2, 224(sp) # 8-byte Folded Reload
573 ; RV32-NEXT: fld fs3, 216(sp) # 8-byte Folded Reload
574 ; RV32-NEXT: addi sp, sp, 256
575 ; RV32-NEXT: ret
576 ;
577 ; RV64-LABEL: buildvec_v32f32:
578 ; RV64: # %bb.0:
579 ; RV64-NEXT: addi sp, sp, -256
580 ; RV64-NEXT: .cfi_def_cfa_offset 256
581 ; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
582 ; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
583 ; RV64-NEXT: fsd fs0, 232(sp) # 8-byte Folded Spill
584 ; RV64-NEXT: fsd fs1, 224(sp) # 8-byte Folded Spill
585 ; RV64-NEXT: fsd fs2, 216(sp) # 8-byte Folded Spill
586 ; RV64-NEXT: fsd fs3, 208(sp) # 8-byte Folded Spill
587 ; RV64-NEXT: fsd fs4, 200(sp) # 8-byte Folded Spill
588 ; RV64-NEXT: fsd fs5, 192(sp) # 8-byte Folded Spill
589 ; RV64-NEXT: fsd fs6, 184(sp) # 8-byte Folded Spill
590 ; RV64-NEXT: fsd fs7, 176(sp) # 8-byte Folded Spill
591 ; RV64-NEXT: fsd fs8, 168(sp) # 8-byte Folded Spill
592 ; RV64-NEXT: fsd fs9, 160(sp) # 8-byte Folded Spill
593 ; RV64-NEXT: fsd fs10, 152(sp) # 8-byte Folded Spill
594 ; RV64-NEXT: fsd fs11, 144(sp) # 8-byte Folded Spill
595 ; RV64-NEXT: .cfi_offset ra, -8
596 ; RV64-NEXT: .cfi_offset s0, -16
597 ; RV64-NEXT: .cfi_offset fs0, -24
598 ; RV64-NEXT: .cfi_offset fs1, -32
599 ; RV64-NEXT: .cfi_offset fs2, -40
600 ; RV64-NEXT: .cfi_offset fs3, -48
601 ; RV64-NEXT: .cfi_offset fs4, -56
602 ; RV64-NEXT: .cfi_offset fs5, -64
603 ; RV64-NEXT: .cfi_offset fs6, -72
604 ; RV64-NEXT: .cfi_offset fs7, -80
605 ; RV64-NEXT: .cfi_offset fs8, -88
606 ; RV64-NEXT: .cfi_offset fs9, -96
607 ; RV64-NEXT: .cfi_offset fs10, -104
608 ; RV64-NEXT: .cfi_offset fs11, -112
609 ; RV64-NEXT: addi s0, sp, 256
610 ; RV64-NEXT: .cfi_def_cfa s0, 0
611 ; RV64-NEXT: andi sp, sp, -128
612 ; RV64-NEXT: fmv.w.x ft0, a0
613 ; RV64-NEXT: fmv.w.x ft1, a1
614 ; RV64-NEXT: fmv.w.x ft2, a2
615 ; RV64-NEXT: fmv.w.x ft3, a3
616 ; RV64-NEXT: fmv.w.x ft4, a4
617 ; RV64-NEXT: fmv.w.x ft5, a5
618 ; RV64-NEXT: fmv.w.x ft6, a6
619 ; RV64-NEXT: fmv.w.x ft7, a7
620 ; RV64-NEXT: flw ft8, 0(s0)
621 ; RV64-NEXT: flw ft9, 8(s0)
622 ; RV64-NEXT: flw ft10, 16(s0)
623 ; RV64-NEXT: flw ft11, 24(s0)
624 ; RV64-NEXT: flw fs0, 32(s0)
625 ; RV64-NEXT: flw fs1, 40(s0)
626 ; RV64-NEXT: flw fs2, 48(s0)
627 ; RV64-NEXT: flw fs3, 56(s0)
628 ; RV64-NEXT: flw fs4, 64(s0)
629 ; RV64-NEXT: flw fs5, 72(s0)
630 ; RV64-NEXT: flw fs6, 80(s0)
631 ; RV64-NEXT: flw fs7, 88(s0)
632 ; RV64-NEXT: flw fs8, 120(s0)
633 ; RV64-NEXT: flw fs9, 112(s0)
634 ; RV64-NEXT: flw fs10, 104(s0)
635 ; RV64-NEXT: flw fs11, 96(s0)
636 ; RV64-NEXT: fsw fs8, 124(sp)
637 ; RV64-NEXT: fsw fs9, 120(sp)
638 ; RV64-NEXT: fsw fs10, 116(sp)
639 ; RV64-NEXT: fsw fs11, 112(sp)
640 ; RV64-NEXT: fsw fs7, 108(sp)
641 ; RV64-NEXT: fsw fs6, 104(sp)
642 ; RV64-NEXT: fsw fs5, 100(sp)
643 ; RV64-NEXT: fsw fs4, 96(sp)
644 ; RV64-NEXT: fsw fs3, 92(sp)
645 ; RV64-NEXT: fsw fs2, 88(sp)
646 ; RV64-NEXT: fsw fs1, 84(sp)
647 ; RV64-NEXT: fsw fs0, 80(sp)
648 ; RV64-NEXT: fsw ft11, 76(sp)
649 ; RV64-NEXT: fsw ft10, 72(sp)
650 ; RV64-NEXT: fsw ft9, 68(sp)
651 ; RV64-NEXT: fsw ft8, 64(sp)
652 ; RV64-NEXT: fsw fa7, 28(sp)
653 ; RV64-NEXT: fsw fa6, 24(sp)
654 ; RV64-NEXT: fsw fa5, 20(sp)
655 ; RV64-NEXT: fsw fa4, 16(sp)
656 ; RV64-NEXT: fsw fa3, 12(sp)
657 ; RV64-NEXT: fsw fa2, 8(sp)
658 ; RV64-NEXT: fsw fa1, 4(sp)
659 ; RV64-NEXT: fsw fa0, 0(sp)
660 ; RV64-NEXT: fsw ft7, 60(sp)
661 ; RV64-NEXT: fsw ft6, 56(sp)
662 ; RV64-NEXT: fsw ft5, 52(sp)
663 ; RV64-NEXT: fsw ft4, 48(sp)
664 ; RV64-NEXT: fsw ft3, 44(sp)
665 ; RV64-NEXT: fsw ft2, 40(sp)
666 ; RV64-NEXT: fsw ft1, 36(sp)
667 ; RV64-NEXT: fsw ft0, 32(sp)
668 ; RV64-NEXT: li a0, 32
669 ; RV64-NEXT: mv a1, sp
670 ; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma
671 ; RV64-NEXT: vle32.v v8, (a1)
672 ; RV64-NEXT: addi sp, s0, -256
673 ; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
674 ; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
675 ; RV64-NEXT: fld fs0, 232(sp) # 8-byte Folded Reload
676 ; RV64-NEXT: fld fs1, 224(sp) # 8-byte Folded Reload
677 ; RV64-NEXT: fld fs2, 216(sp) # 8-byte Folded Reload
678 ; RV64-NEXT: fld fs3, 208(sp) # 8-byte Folded Reload
679 ; RV64-NEXT: fld fs4, 200(sp) # 8-byte Folded Reload
680 ; RV64-NEXT: fld fs5, 192(sp) # 8-byte Folded Reload
681 ; RV64-NEXT: fld fs6, 184(sp) # 8-byte Folded Reload
682 ; RV64-NEXT: fld fs7, 176(sp) # 8-byte Folded Reload
683 ; RV64-NEXT: fld fs8, 168(sp) # 8-byte Folded Reload
684 ; RV64-NEXT: fld fs9, 160(sp) # 8-byte Folded Reload
685 ; RV64-NEXT: fld fs10, 152(sp) # 8-byte Folded Reload
686 ; RV64-NEXT: fld fs11, 144(sp) # 8-byte Folded Reload
687 ; RV64-NEXT: addi sp, sp, 256
688 ; RV64-NEXT: ret
689 %v0 = insertelement <32 x float> poison, float %e0, i64 0
690 %v1 = insertelement <32 x float> %v0, float %e1, i64 1
691 %v2 = insertelement <32 x float> %v1, float %e2, i64 2
692 %v3 = insertelement <32 x float> %v2, float %e3, i64 3
693 %v4 = insertelement <32 x float> %v3, float %e4, i64 4
694 %v5 = insertelement <32 x float> %v4, float %e5, i64 5
695 %v6 = insertelement <32 x float> %v5, float %e6, i64 6
696 %v7 = insertelement <32 x float> %v6, float %e7, i64 7
697 %v8 = insertelement <32 x float> %v7, float %e8, i64 8
698 %v9 = insertelement <32 x float> %v8, float %e9, i64 9
699 %v10 = insertelement <32 x float> %v9, float %e10, i64 10
700 %v11 = insertelement <32 x float> %v10, float %e11, i64 11
701 %v12 = insertelement <32 x float> %v11, float %e12, i64 12
702 %v13 = insertelement <32 x float> %v12, float %e13, i64 13
703 %v14 = insertelement <32 x float> %v13, float %e14, i64 14
704 %v15 = insertelement <32 x float> %v14, float %e15, i64 15
705 %v16 = insertelement <32 x float> %v15, float %e16, i64 16
706 %v17 = insertelement <32 x float> %v16, float %e17, i64 17
707 %v18 = insertelement <32 x float> %v17, float %e18, i64 18
708 %v19 = insertelement <32 x float> %v18, float %e19, i64 19
709 %v20 = insertelement <32 x float> %v19, float %e20, i64 20
710 %v21 = insertelement <32 x float> %v20, float %e21, i64 21
711 %v22 = insertelement <32 x float> %v21, float %e22, i64 22
712 %v23 = insertelement <32 x float> %v22, float %e23, i64 23
713 %v24 = insertelement <32 x float> %v23, float %e24, i64 24
714 %v25 = insertelement <32 x float> %v24, float %e25, i64 25
715 %v26 = insertelement <32 x float> %v25, float %e26, i64 26
716 %v27 = insertelement <32 x float> %v26, float %e27, i64 27
717 %v28 = insertelement <32 x float> %v27, float %e28, i64 28
718 %v29 = insertelement <32 x float> %v28, float %e29, i64 29
719 %v30 = insertelement <32 x float> %v29, float %e30, i64 30
720 %v31 = insertelement <32 x float> %v30, float %e31, i64 31
721 ret <32 x float> %v31
722 }
724 define <8 x double> @buildvec_v8f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) {
725 ; RV32-LABEL: buildvec_v8f64:
726 ; RV32: # %bb.0:
727 ; RV32-NEXT: addi sp, sp, -128
728 ; RV32-NEXT: .cfi_def_cfa_offset 128
729 ; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
730 ; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
731 ; RV32-NEXT: .cfi_offset ra, -4
732 ; RV32-NEXT: .cfi_offset s0, -8
733 ; RV32-NEXT: addi s0, sp, 128
734 ; RV32-NEXT: .cfi_def_cfa s0, 0
735 ; RV32-NEXT: andi sp, sp, -64
736 ; RV32-NEXT: fsd fa7, 56(sp)
737 ; RV32-NEXT: fsd fa6, 48(sp)
738 ; RV32-NEXT: fsd fa5, 40(sp)
739 ; RV32-NEXT: fsd fa4, 32(sp)
740 ; RV32-NEXT: fsd fa3, 24(sp)
741 ; RV32-NEXT: fsd fa2, 16(sp)
742 ; RV32-NEXT: fsd fa1, 8(sp)
743 ; RV32-NEXT: fsd fa0, 0(sp)
744 ; RV32-NEXT: mv a0, sp
745 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
746 ; RV32-NEXT: vle64.v v8, (a0)
747 ; RV32-NEXT: addi sp, s0, -128
748 ; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
749 ; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
750 ; RV32-NEXT: addi sp, sp, 128
751 ; RV32-NEXT: ret
752 ;
753 ; RV64-LABEL: buildvec_v8f64:
754 ; RV64: # %bb.0:
755 ; RV64-NEXT: addi sp, sp, -128
756 ; RV64-NEXT: .cfi_def_cfa_offset 128
757 ; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
758 ; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
759 ; RV64-NEXT: .cfi_offset ra, -8
760 ; RV64-NEXT: .cfi_offset s0, -16
761 ; RV64-NEXT: addi s0, sp, 128
762 ; RV64-NEXT: .cfi_def_cfa s0, 0
763 ; RV64-NEXT: andi sp, sp, -64
764 ; RV64-NEXT: fsd fa7, 56(sp)
765 ; RV64-NEXT: fsd fa6, 48(sp)
766 ; RV64-NEXT: fsd fa5, 40(sp)
767 ; RV64-NEXT: fsd fa4, 32(sp)
768 ; RV64-NEXT: fsd fa3, 24(sp)
769 ; RV64-NEXT: fsd fa2, 16(sp)
770 ; RV64-NEXT: fsd fa1, 8(sp)
771 ; RV64-NEXT: fsd fa0, 0(sp)
772 ; RV64-NEXT: mv a0, sp
773 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
774 ; RV64-NEXT: vle64.v v8, (a0)
775 ; RV64-NEXT: addi sp, s0, -128
776 ; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
777 ; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
778 ; RV64-NEXT: addi sp, sp, 128
779 ; RV64-NEXT: ret
780 %v0 = insertelement <8 x double> poison, double %e0, i64 0
781 %v1 = insertelement <8 x double> %v0, double %e1, i64 1
782 %v2 = insertelement <8 x double> %v1, double %e2, i64 2
783 %v3 = insertelement <8 x double> %v2, double %e3, i64 3
784 %v4 = insertelement <8 x double> %v3, double %e4, i64 4
785 %v5 = insertelement <8 x double> %v4, double %e5, i64 5
786 %v6 = insertelement <8 x double> %v5, double %e6, i64 6
787 %v7 = insertelement <8 x double> %v6, double %e7, i64 7
788 ret <8 x double> %v7
789 }
791 define <16 x double> @buildvec_v16f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15) {
792 ; RV32-LABEL: buildvec_v16f64:
793 ; RV32: # %bb.0:
794 ; RV32-NEXT: addi sp, sp, -384
795 ; RV32-NEXT: .cfi_def_cfa_offset 384
796 ; RV32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
797 ; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
798 ; RV32-NEXT: .cfi_offset ra, -4
799 ; RV32-NEXT: .cfi_offset s0, -8
800 ; RV32-NEXT: addi s0, sp, 384
801 ; RV32-NEXT: .cfi_def_cfa s0, 0
802 ; RV32-NEXT: andi sp, sp, -128
803 ; RV32-NEXT: sw a0, 120(sp)
804 ; RV32-NEXT: sw a1, 124(sp)
805 ; RV32-NEXT: fld ft0, 120(sp)
806 ; RV32-NEXT: sw a2, 120(sp)
807 ; RV32-NEXT: sw a3, 124(sp)
808 ; RV32-NEXT: fld ft1, 120(sp)
809 ; RV32-NEXT: sw a4, 120(sp)
810 ; RV32-NEXT: sw a5, 124(sp)
811 ; RV32-NEXT: fld ft2, 120(sp)
812 ; RV32-NEXT: sw a6, 120(sp)
813 ; RV32-NEXT: sw a7, 124(sp)
814 ; RV32-NEXT: fld ft3, 120(sp)
815 ; RV32-NEXT: fld ft4, 24(s0)
816 ; RV32-NEXT: fld ft5, 16(s0)
817 ; RV32-NEXT: fld ft6, 8(s0)
818 ; RV32-NEXT: fld ft7, 0(s0)
819 ; RV32-NEXT: fsd ft4, 248(sp)
820 ; RV32-NEXT: fsd ft5, 240(sp)
821 ; RV32-NEXT: fsd ft6, 232(sp)
822 ; RV32-NEXT: fsd ft7, 224(sp)
823 ; RV32-NEXT: fsd fa7, 184(sp)
824 ; RV32-NEXT: fsd fa6, 176(sp)
825 ; RV32-NEXT: fsd fa5, 168(sp)
826 ; RV32-NEXT: fsd fa4, 160(sp)
827 ; RV32-NEXT: fsd fa3, 152(sp)
828 ; RV32-NEXT: fsd fa2, 144(sp)
829 ; RV32-NEXT: fsd fa1, 136(sp)
830 ; RV32-NEXT: fsd fa0, 128(sp)
831 ; RV32-NEXT: fsd ft3, 216(sp)
832 ; RV32-NEXT: fsd ft2, 208(sp)
833 ; RV32-NEXT: fsd ft1, 200(sp)
834 ; RV32-NEXT: fsd ft0, 192(sp)
835 ; RV32-NEXT: addi a0, sp, 128
836 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
837 ; RV32-NEXT: vle64.v v8, (a0)
838 ; RV32-NEXT: addi sp, s0, -384
839 ; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
840 ; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
841 ; RV32-NEXT: addi sp, sp, 384
842 ; RV32-NEXT: ret
843 ;
844 ; RV64-LABEL: buildvec_v16f64:
845 ; RV64: # %bb.0:
846 ; RV64-NEXT: addi sp, sp, -256
847 ; RV64-NEXT: .cfi_def_cfa_offset 256
848 ; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
849 ; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
850 ; RV64-NEXT: .cfi_offset ra, -8
851 ; RV64-NEXT: .cfi_offset s0, -16
852 ; RV64-NEXT: addi s0, sp, 256
853 ; RV64-NEXT: .cfi_def_cfa s0, 0
854 ; RV64-NEXT: andi sp, sp, -128
855 ; RV64-NEXT: sd a7, 120(sp)
856 ; RV64-NEXT: sd a6, 112(sp)
857 ; RV64-NEXT: sd a5, 104(sp)
858 ; RV64-NEXT: sd a4, 96(sp)
859 ; RV64-NEXT: sd a3, 88(sp)
860 ; RV64-NEXT: sd a2, 80(sp)
861 ; RV64-NEXT: sd a1, 72(sp)
862 ; RV64-NEXT: sd a0, 64(sp)
863 ; RV64-NEXT: fsd fa7, 56(sp)
864 ; RV64-NEXT: fsd fa6, 48(sp)
865 ; RV64-NEXT: fsd fa5, 40(sp)
866 ; RV64-NEXT: fsd fa4, 32(sp)
867 ; RV64-NEXT: fsd fa3, 24(sp)
868 ; RV64-NEXT: fsd fa2, 16(sp)
869 ; RV64-NEXT: fsd fa1, 8(sp)
870 ; RV64-NEXT: fsd fa0, 0(sp)
871 ; RV64-NEXT: mv a0, sp
872 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
873 ; RV64-NEXT: vle64.v v8, (a0)
874 ; RV64-NEXT: addi sp, s0, -256
875 ; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
876 ; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
877 ; RV64-NEXT: addi sp, sp, 256
878 ; RV64-NEXT: ret
879 %v0 = insertelement <16 x double> poison, double %e0, i64 0
880 %v1 = insertelement <16 x double> %v0, double %e1, i64 1
881 %v2 = insertelement <16 x double> %v1, double %e2, i64 2
882 %v3 = insertelement <16 x double> %v2, double %e3, i64 3
883 %v4 = insertelement <16 x double> %v3, double %e4, i64 4
884 %v5 = insertelement <16 x double> %v4, double %e5, i64 5
885 %v6 = insertelement <16 x double> %v5, double %e6, i64 6
886 %v7 = insertelement <16 x double> %v6, double %e7, i64 7
887 %v8 = insertelement <16 x double> %v7, double %e8, i64 8
888 %v9 = insertelement <16 x double> %v8, double %e9, i64 9
889 %v10 = insertelement <16 x double> %v9, double %e10, i64 10
890 %v11 = insertelement <16 x double> %v10, double %e11, i64 11
891 %v12 = insertelement <16 x double> %v11, double %e12, i64 12
892 %v13 = insertelement <16 x double> %v12, double %e13, i64 13
893 %v14 = insertelement <16 x double> %v13, double %e14, i64 14
894 %v15 = insertelement <16 x double> %v14, double %e15, i64 15
895 ret <16 x double> %v15
896 }
898 define <32 x double> @buildvec_v32f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15, double %e16, double %e17, double %e18, double %e19, double %e20, double %e21, double %e22, double %e23, double %e24, double %e25, double %e26, double %e27, double %e28, double %e29, double %e30, double %e31) {
899 ; RV32-LABEL: buildvec_v32f64:
900 ; RV32: # %bb.0:
901 ; RV32-NEXT: addi sp, sp, -512
902 ; RV32-NEXT: .cfi_def_cfa_offset 512
903 ; RV32-NEXT: sw ra, 508(sp) # 4-byte Folded Spill
904 ; RV32-NEXT: sw s0, 504(sp) # 4-byte Folded Spill
905 ; RV32-NEXT: fsd fs0, 496(sp) # 8-byte Folded Spill
906 ; RV32-NEXT: fsd fs1, 488(sp) # 8-byte Folded Spill
907 ; RV32-NEXT: fsd fs2, 480(sp) # 8-byte Folded Spill
908 ; RV32-NEXT: fsd fs3, 472(sp) # 8-byte Folded Spill
909 ; RV32-NEXT: fsd fs4, 464(sp) # 8-byte Folded Spill
910 ; RV32-NEXT: fsd fs5, 456(sp) # 8-byte Folded Spill
911 ; RV32-NEXT: fsd fs6, 448(sp) # 8-byte Folded Spill
912 ; RV32-NEXT: fsd fs7, 440(sp) # 8-byte Folded Spill
913 ; RV32-NEXT: fsd fs8, 432(sp) # 8-byte Folded Spill
914 ; RV32-NEXT: fsd fs9, 424(sp) # 8-byte Folded Spill
915 ; RV32-NEXT: fsd fs10, 416(sp) # 8-byte Folded Spill
916 ; RV32-NEXT: fsd fs11, 408(sp) # 8-byte Folded Spill
917 ; RV32-NEXT: .cfi_offset ra, -4
918 ; RV32-NEXT: .cfi_offset s0, -8
919 ; RV32-NEXT: .cfi_offset fs0, -16
920 ; RV32-NEXT: .cfi_offset fs1, -24
921 ; RV32-NEXT: .cfi_offset fs2, -32
922 ; RV32-NEXT: .cfi_offset fs3, -40
923 ; RV32-NEXT: .cfi_offset fs4, -48
924 ; RV32-NEXT: .cfi_offset fs5, -56
925 ; RV32-NEXT: .cfi_offset fs6, -64
926 ; RV32-NEXT: .cfi_offset fs7, -72
927 ; RV32-NEXT: .cfi_offset fs8, -80
928 ; RV32-NEXT: .cfi_offset fs9, -88
929 ; RV32-NEXT: .cfi_offset fs10, -96
930 ; RV32-NEXT: .cfi_offset fs11, -104
931 ; RV32-NEXT: addi s0, sp, 512
932 ; RV32-NEXT: .cfi_def_cfa s0, 0
933 ; RV32-NEXT: andi sp, sp, -128
934 ; RV32-NEXT: sw a0, 120(sp)
935 ; RV32-NEXT: sw a1, 124(sp)
936 ; RV32-NEXT: fld ft0, 120(sp)
937 ; RV32-NEXT: sw a2, 120(sp)
938 ; RV32-NEXT: sw a3, 124(sp)
939 ; RV32-NEXT: fld ft1, 120(sp)
940 ; RV32-NEXT: sw a4, 120(sp)
941 ; RV32-NEXT: sw a5, 124(sp)
942 ; RV32-NEXT: fld ft2, 120(sp)
943 ; RV32-NEXT: sw a6, 120(sp)
944 ; RV32-NEXT: sw a7, 124(sp)
945 ; RV32-NEXT: fld ft3, 120(sp)
946 ; RV32-NEXT: fld ft4, 0(s0)
947 ; RV32-NEXT: fld ft5, 8(s0)
948 ; RV32-NEXT: fld ft6, 16(s0)
949 ; RV32-NEXT: fld ft7, 24(s0)
950 ; RV32-NEXT: fld ft8, 32(s0)
951 ; RV32-NEXT: fld ft9, 40(s0)
952 ; RV32-NEXT: fld ft10, 48(s0)
953 ; RV32-NEXT: fld ft11, 56(s0)
954 ; RV32-NEXT: fld fs0, 64(s0)
955 ; RV32-NEXT: fld fs1, 72(s0)
956 ; RV32-NEXT: fld fs2, 80(s0)
957 ; RV32-NEXT: fld fs3, 88(s0)
958 ; RV32-NEXT: fld fs4, 96(s0)
959 ; RV32-NEXT: fld fs5, 104(s0)
960 ; RV32-NEXT: fld fs6, 112(s0)
961 ; RV32-NEXT: fld fs7, 120(s0)
962 ; RV32-NEXT: fld fs8, 152(s0)
963 ; RV32-NEXT: fld fs9, 144(s0)
964 ; RV32-NEXT: fld fs10, 136(s0)
965 ; RV32-NEXT: fld fs11, 128(s0)
966 ; RV32-NEXT: fsd fs8, 248(sp)
967 ; RV32-NEXT: fsd fs9, 240(sp)
968 ; RV32-NEXT: fsd fs10, 232(sp)
969 ; RV32-NEXT: fsd fs11, 224(sp)
970 ; RV32-NEXT: fsd fs7, 216(sp)
971 ; RV32-NEXT: fsd fs6, 208(sp)
972 ; RV32-NEXT: fsd fs5, 200(sp)
973 ; RV32-NEXT: fsd fs4, 192(sp)
974 ; RV32-NEXT: fsd fs3, 184(sp)
975 ; RV32-NEXT: fsd fs2, 176(sp)
976 ; RV32-NEXT: fsd fs1, 168(sp)
977 ; RV32-NEXT: fsd fs0, 160(sp)
978 ; RV32-NEXT: fsd ft11, 152(sp)
979 ; RV32-NEXT: fsd ft10, 144(sp)
980 ; RV32-NEXT: fsd ft9, 136(sp)
981 ; RV32-NEXT: fsd ft8, 128(sp)
982 ; RV32-NEXT: fsd ft7, 376(sp)
983 ; RV32-NEXT: fsd ft6, 368(sp)
984 ; RV32-NEXT: fsd ft5, 360(sp)
985 ; RV32-NEXT: fsd ft4, 352(sp)
986 ; RV32-NEXT: fsd fa7, 312(sp)
987 ; RV32-NEXT: fsd fa6, 304(sp)
988 ; RV32-NEXT: fsd fa5, 296(sp)
989 ; RV32-NEXT: fsd fa4, 288(sp)
990 ; RV32-NEXT: fsd fa3, 280(sp)
991 ; RV32-NEXT: fsd fa2, 272(sp)
992 ; RV32-NEXT: fsd fa1, 264(sp)
993 ; RV32-NEXT: fsd fa0, 256(sp)
994 ; RV32-NEXT: fsd ft3, 344(sp)
995 ; RV32-NEXT: fsd ft2, 336(sp)
996 ; RV32-NEXT: fsd ft1, 328(sp)
997 ; RV32-NEXT: fsd ft0, 320(sp)
998 ; RV32-NEXT: addi a0, sp, 128
999 ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
1000 ; RV32-NEXT: vle64.v v16, (a0)
1001 ; RV32-NEXT: addi a0, sp, 256
1002 ; RV32-NEXT: vle64.v v8, (a0)
1003 ; RV32-NEXT: addi sp, s0, -512
1004 ; RV32-NEXT: lw ra, 508(sp) # 4-byte Folded Reload
1005 ; RV32-NEXT: lw s0, 504(sp) # 4-byte Folded Reload
1006 ; RV32-NEXT: fld fs0, 496(sp) # 8-byte Folded Reload
1007 ; RV32-NEXT: fld fs1, 488(sp) # 8-byte Folded Reload
1008 ; RV32-NEXT: fld fs2, 480(sp) # 8-byte Folded Reload
1009 ; RV32-NEXT: fld fs3, 472(sp) # 8-byte Folded Reload
1010 ; RV32-NEXT: fld fs4, 464(sp) # 8-byte Folded Reload
1011 ; RV32-NEXT: fld fs5, 456(sp) # 8-byte Folded Reload
1012 ; RV32-NEXT: fld fs6, 448(sp) # 8-byte Folded Reload
1013 ; RV32-NEXT: fld fs7, 440(sp) # 8-byte Folded Reload
1014 ; RV32-NEXT: fld fs8, 432(sp) # 8-byte Folded Reload
1015 ; RV32-NEXT: fld fs9, 424(sp) # 8-byte Folded Reload
1016 ; RV32-NEXT: fld fs10, 416(sp) # 8-byte Folded Reload
1017 ; RV32-NEXT: fld fs11, 408(sp) # 8-byte Folded Reload
1018 ; RV32-NEXT: addi sp, sp, 512
1019 ; RV32-NEXT: ret
1020 ;
1021 ; RV64-LABEL: buildvec_v32f64:
1022 ; RV64: # %bb.0:
1023 ; RV64-NEXT: addi sp, sp, -384
1024 ; RV64-NEXT: .cfi_def_cfa_offset 384
1025 ; RV64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
1026 ; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
1027 ; RV64-NEXT: fsd fs0, 360(sp) # 8-byte Folded Spill
1028 ; RV64-NEXT: fsd fs1, 352(sp) # 8-byte Folded Spill
1029 ; RV64-NEXT: fsd fs2, 344(sp) # 8-byte Folded Spill
1030 ; RV64-NEXT: fsd fs3, 336(sp) # 8-byte Folded Spill
1031 ; RV64-NEXT: .cfi_offset ra, -8
1032 ; RV64-NEXT: .cfi_offset s0, -16
1033 ; RV64-NEXT: .cfi_offset fs0, -24
1034 ; RV64-NEXT: .cfi_offset fs1, -32
1035 ; RV64-NEXT: .cfi_offset fs2, -40
1036 ; RV64-NEXT: .cfi_offset fs3, -48
1037 ; RV64-NEXT: addi s0, sp, 384
1038 ; RV64-NEXT: .cfi_def_cfa s0, 0
1039 ; RV64-NEXT: andi sp, sp, -128
1040 ; RV64-NEXT: fld ft0, 0(s0)
1041 ; RV64-NEXT: fld ft1, 8(s0)
1042 ; RV64-NEXT: fld ft2, 16(s0)
1043 ; RV64-NEXT: fld ft3, 24(s0)
1044 ; RV64-NEXT: fld ft4, 32(s0)
1045 ; RV64-NEXT: fld ft5, 40(s0)
1046 ; RV64-NEXT: fld ft6, 48(s0)
1047 ; RV64-NEXT: fld ft7, 56(s0)
1048 ; RV64-NEXT: fld ft8, 64(s0)
1049 ; RV64-NEXT: fld ft9, 72(s0)
1050 ; RV64-NEXT: fld ft10, 80(s0)
1051 ; RV64-NEXT: fld ft11, 88(s0)
1052 ; RV64-NEXT: fld fs0, 96(s0)
1053 ; RV64-NEXT: fld fs1, 104(s0)
1054 ; RV64-NEXT: fld fs2, 112(s0)
1055 ; RV64-NEXT: fld fs3, 120(s0)
1056 ; RV64-NEXT: sd a7, 248(sp)
1057 ; RV64-NEXT: sd a6, 240(sp)
1058 ; RV64-NEXT: sd a5, 232(sp)
1059 ; RV64-NEXT: sd a4, 224(sp)
1060 ; RV64-NEXT: sd a3, 216(sp)
1061 ; RV64-NEXT: sd a2, 208(sp)
1062 ; RV64-NEXT: sd a1, 200(sp)
1063 ; RV64-NEXT: sd a0, 192(sp)
1064 ; RV64-NEXT: fsd fa7, 184(sp)
1065 ; RV64-NEXT: fsd fa6, 176(sp)
1066 ; RV64-NEXT: fsd fa5, 168(sp)
1067 ; RV64-NEXT: fsd fa4, 160(sp)
1068 ; RV64-NEXT: fsd fa3, 152(sp)
1069 ; RV64-NEXT: fsd fa2, 144(sp)
1070 ; RV64-NEXT: fsd fa1, 136(sp)
1071 ; RV64-NEXT: fsd fa0, 128(sp)
1072 ; RV64-NEXT: fsd fs3, 120(sp)
1073 ; RV64-NEXT: fsd fs2, 112(sp)
1074 ; RV64-NEXT: fsd fs1, 104(sp)
1075 ; RV64-NEXT: fsd fs0, 96(sp)
1076 ; RV64-NEXT: fsd ft11, 88(sp)
1077 ; RV64-NEXT: fsd ft10, 80(sp)
1078 ; RV64-NEXT: fsd ft9, 72(sp)
1079 ; RV64-NEXT: fsd ft8, 64(sp)
1080 ; RV64-NEXT: fsd ft7, 56(sp)
1081 ; RV64-NEXT: fsd ft6, 48(sp)
1082 ; RV64-NEXT: fsd ft5, 40(sp)
1083 ; RV64-NEXT: fsd ft4, 32(sp)
1084 ; RV64-NEXT: fsd ft3, 24(sp)
1085 ; RV64-NEXT: fsd ft2, 16(sp)
1086 ; RV64-NEXT: fsd ft1, 8(sp)
1087 ; RV64-NEXT: fsd ft0, 0(sp)
1088 ; RV64-NEXT: addi a0, sp, 128
1089 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
1090 ; RV64-NEXT: vle64.v v8, (a0)
1091 ; RV64-NEXT: mv a0, sp
1092 ; RV64-NEXT: vle64.v v16, (a0)
1093 ; RV64-NEXT: addi sp, s0, -384
1094 ; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
1095 ; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
1096 ; RV64-NEXT: fld fs0, 360(sp) # 8-byte Folded Reload
1097 ; RV64-NEXT: fld fs1, 352(sp) # 8-byte Folded Reload
1098 ; RV64-NEXT: fld fs2, 344(sp) # 8-byte Folded Reload
1099 ; RV64-NEXT: fld fs3, 336(sp) # 8-byte Folded Reload
1100 ; RV64-NEXT: addi sp, sp, 384
1101 ; RV64-NEXT: ret
1102 %v0 = insertelement <32 x double> poison, double %e0, i64 0
1103 %v1 = insertelement <32 x double> %v0, double %e1, i64 1
1104 %v2 = insertelement <32 x double> %v1, double %e2, i64 2
1105 %v3 = insertelement <32 x double> %v2, double %e3, i64 3
1106 %v4 = insertelement <32 x double> %v3, double %e4, i64 4
1107 %v5 = insertelement <32 x double> %v4, double %e5, i64 5
1108 %v6 = insertelement <32 x double> %v5, double %e6, i64 6
1109 %v7 = insertelement <32 x double> %v6, double %e7, i64 7
1110 %v8 = insertelement <32 x double> %v7, double %e8, i64 8
1111 %v9 = insertelement <32 x double> %v8, double %e9, i64 9
1112 %v10 = insertelement <32 x double> %v9, double %e10, i64 10
1113 %v11 = insertelement <32 x double> %v10, double %e11, i64 11
1114 %v12 = insertelement <32 x double> %v11, double %e12, i64 12
1115 %v13 = insertelement <32 x double> %v12, double %e13, i64 13
1116 %v14 = insertelement <32 x double> %v13, double %e14, i64 14
1117 %v15 = insertelement <32 x double> %v14, double %e15, i64 15
1118 %v16 = insertelement <32 x double> %v15, double %e16, i64 16
1119 %v17 = insertelement <32 x double> %v16, double %e17, i64 17
1120 %v18 = insertelement <32 x double> %v17, double %e18, i64 18
1121 %v19 = insertelement <32 x double> %v18, double %e19, i64 19
1122 %v20 = insertelement <32 x double> %v19, double %e20, i64 20
1123 %v21 = insertelement <32 x double> %v20, double %e21, i64 21
1124 %v22 = insertelement <32 x double> %v21, double %e22, i64 22
1125 %v23 = insertelement <32 x double> %v22, double %e23, i64 23
1126 %v24 = insertelement <32 x double> %v23, double %e24, i64 24
1127 %v25 = insertelement <32 x double> %v24, double %e25, i64 25
1128 %v26 = insertelement <32 x double> %v25, double %e26, i64 26
1129 %v27 = insertelement <32 x double> %v26, double %e27, i64 27
1130 %v28 = insertelement <32 x double> %v27, double %e28, i64 28
1131 %v29 = insertelement <32 x double> %v28, double %e29, i64 29
1132 %v30 = insertelement <32 x double> %v29, double %e30, i64 30
1133 %v31 = insertelement <32 x double> %v30, double %e31, i64 31
1134 ret <32 x double> %v31
1135 }
1137 define <32 x double> @buildvec_v32f64_exact_vlen(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15, double %e16, double %e17, double %e18, double %e19, double %e20, double %e21, double %e22, double %e23, double %e24, double %e25, double %e26, double %e27, double %e28, double %e29, double %e30, double %e31) vscale_range(2,2) {
1138 ; RV32-LABEL: buildvec_v32f64_exact_vlen:
1139 ; RV32: # %bb.0:
1140 ; RV32-NEXT: addi sp, sp, -112
1141 ; RV32-NEXT: .cfi_def_cfa_offset 112
1142 ; RV32-NEXT: fsd fs0, 104(sp) # 8-byte Folded Spill
1143 ; RV32-NEXT: fsd fs1, 96(sp) # 8-byte Folded Spill
1144 ; RV32-NEXT: fsd fs2, 88(sp) # 8-byte Folded Spill
1145 ; RV32-NEXT: fsd fs3, 80(sp) # 8-byte Folded Spill
1146 ; RV32-NEXT: fsd fs4, 72(sp) # 8-byte Folded Spill
1147 ; RV32-NEXT: fsd fs5, 64(sp) # 8-byte Folded Spill
1148 ; RV32-NEXT: fsd fs6, 56(sp) # 8-byte Folded Spill
1149 ; RV32-NEXT: fsd fs7, 48(sp) # 8-byte Folded Spill
1150 ; RV32-NEXT: fsd fs8, 40(sp) # 8-byte Folded Spill
1151 ; RV32-NEXT: fsd fs9, 32(sp) # 8-byte Folded Spill
1152 ; RV32-NEXT: fsd fs10, 24(sp) # 8-byte Folded Spill
1153 ; RV32-NEXT: fsd fs11, 16(sp) # 8-byte Folded Spill
1154 ; RV32-NEXT: .cfi_offset fs0, -8
1155 ; RV32-NEXT: .cfi_offset fs1, -16
1156 ; RV32-NEXT: .cfi_offset fs2, -24
1157 ; RV32-NEXT: .cfi_offset fs3, -32
1158 ; RV32-NEXT: .cfi_offset fs4, -40
1159 ; RV32-NEXT: .cfi_offset fs5, -48
1160 ; RV32-NEXT: .cfi_offset fs6, -56
1161 ; RV32-NEXT: .cfi_offset fs7, -64
1162 ; RV32-NEXT: .cfi_offset fs8, -72
1163 ; RV32-NEXT: .cfi_offset fs9, -80
1164 ; RV32-NEXT: .cfi_offset fs10, -88
1165 ; RV32-NEXT: .cfi_offset fs11, -96
1166 ; RV32-NEXT: sw a6, 8(sp)
1167 ; RV32-NEXT: sw a7, 12(sp)
1168 ; RV32-NEXT: fld ft6, 8(sp)
1169 ; RV32-NEXT: sw a4, 8(sp)
1170 ; RV32-NEXT: sw a5, 12(sp)
1171 ; RV32-NEXT: fld ft7, 8(sp)
1172 ; RV32-NEXT: sw a2, 8(sp)
1173 ; RV32-NEXT: sw a3, 12(sp)
1174 ; RV32-NEXT: fld ft8, 8(sp)
1175 ; RV32-NEXT: sw a0, 8(sp)
1176 ; RV32-NEXT: sw a1, 12(sp)
1177 ; RV32-NEXT: fld ft9, 8(sp)
1178 ; RV32-NEXT: fld ft0, 264(sp)
1179 ; RV32-NEXT: fld ft1, 256(sp)
1180 ; RV32-NEXT: fld ft2, 248(sp)
1181 ; RV32-NEXT: fld ft3, 240(sp)
1182 ; RV32-NEXT: fld ft4, 232(sp)
1183 ; RV32-NEXT: fld ft5, 224(sp)
1184 ; RV32-NEXT: fld ft10, 216(sp)
1185 ; RV32-NEXT: fld ft11, 208(sp)
1186 ; RV32-NEXT: fld fs0, 200(sp)
1187 ; RV32-NEXT: fld fs1, 192(sp)
1188 ; RV32-NEXT: fld fs2, 184(sp)
1189 ; RV32-NEXT: fld fs3, 176(sp)
1190 ; RV32-NEXT: fld fs4, 152(sp)
1191 ; RV32-NEXT: fld fs5, 144(sp)
1192 ; RV32-NEXT: fld fs6, 168(sp)
1193 ; RV32-NEXT: fld fs7, 160(sp)
1194 ; RV32-NEXT: fld fs8, 136(sp)
1195 ; RV32-NEXT: fld fs9, 128(sp)
1196 ; RV32-NEXT: fld fs10, 120(sp)
1197 ; RV32-NEXT: fld fs11, 112(sp)
1198 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1199 ; RV32-NEXT: vfmv.v.f v8, ft9
1200 ; RV32-NEXT: vfslide1down.vf v12, v8, ft8
1201 ; RV32-NEXT: vfmv.v.f v8, fa2
1202 ; RV32-NEXT: vfslide1down.vf v9, v8, fa3
1203 ; RV32-NEXT: vfmv.v.f v8, fa0
1204 ; RV32-NEXT: vfslide1down.vf v8, v8, fa1
1205 ; RV32-NEXT: vfmv.v.f v10, fa4
1206 ; RV32-NEXT: vfslide1down.vf v10, v10, fa5
1207 ; RV32-NEXT: vfmv.v.f v11, fa6
1208 ; RV32-NEXT: vfslide1down.vf v11, v11, fa7
1209 ; RV32-NEXT: vfmv.v.f v13, ft7
1210 ; RV32-NEXT: vfslide1down.vf v13, v13, ft6
1211 ; RV32-NEXT: vfmv.v.f v14, fs11
1212 ; RV32-NEXT: vfslide1down.vf v14, v14, fs10
1213 ; RV32-NEXT: vfmv.v.f v15, fs9
1214 ; RV32-NEXT: vfslide1down.vf v15, v15, fs8
1215 ; RV32-NEXT: vfmv.v.f v16, fs7
1216 ; RV32-NEXT: vfslide1down.vf v17, v16, fs6
1217 ; RV32-NEXT: vfmv.v.f v16, fs5
1218 ; RV32-NEXT: vfslide1down.vf v16, v16, fs4
1219 ; RV32-NEXT: vfmv.v.f v18, fs3
1220 ; RV32-NEXT: vfslide1down.vf v18, v18, fs2
1221 ; RV32-NEXT: vfmv.v.f v19, fs1
1222 ; RV32-NEXT: vfslide1down.vf v19, v19, fs0
1223 ; RV32-NEXT: vfmv.v.f v20, ft11
1224 ; RV32-NEXT: vfslide1down.vf v20, v20, ft10
1225 ; RV32-NEXT: vfmv.v.f v21, ft5
1226 ; RV32-NEXT: vfslide1down.vf v21, v21, ft4
1227 ; RV32-NEXT: vfmv.v.f v22, ft3
1228 ; RV32-NEXT: vfslide1down.vf v22, v22, ft2
1229 ; RV32-NEXT: vfmv.v.f v23, ft1
1230 ; RV32-NEXT: vfslide1down.vf v23, v23, ft0
1231 ; RV32-NEXT: fld fs0, 104(sp) # 8-byte Folded Reload
1232 ; RV32-NEXT: fld fs1, 96(sp) # 8-byte Folded Reload
1233 ; RV32-NEXT: fld fs2, 88(sp) # 8-byte Folded Reload
1234 ; RV32-NEXT: fld fs3, 80(sp) # 8-byte Folded Reload
1235 ; RV32-NEXT: fld fs4, 72(sp) # 8-byte Folded Reload
1236 ; RV32-NEXT: fld fs5, 64(sp) # 8-byte Folded Reload
1237 ; RV32-NEXT: fld fs6, 56(sp) # 8-byte Folded Reload
1238 ; RV32-NEXT: fld fs7, 48(sp) # 8-byte Folded Reload
1239 ; RV32-NEXT: fld fs8, 40(sp) # 8-byte Folded Reload
1240 ; RV32-NEXT: fld fs9, 32(sp) # 8-byte Folded Reload
1241 ; RV32-NEXT: fld fs10, 24(sp) # 8-byte Folded Reload
1242 ; RV32-NEXT: fld fs11, 16(sp) # 8-byte Folded Reload
1243 ; RV32-NEXT: addi sp, sp, 112
1244 ; RV32-NEXT: ret
1245 ;
1246 ; RV64-LABEL: buildvec_v32f64_exact_vlen:
1247 ; RV64: # %bb.0:
1248 ; RV64-NEXT: addi sp, sp, -96
1249 ; RV64-NEXT: .cfi_def_cfa_offset 96
1250 ; RV64-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill
1251 ; RV64-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill
1252 ; RV64-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill
1253 ; RV64-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill
1254 ; RV64-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill
1255 ; RV64-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill
1256 ; RV64-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill
1257 ; RV64-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill
1258 ; RV64-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill
1259 ; RV64-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill
1260 ; RV64-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill
1261 ; RV64-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill
1262 ; RV64-NEXT: .cfi_offset fs0, -8
1263 ; RV64-NEXT: .cfi_offset fs1, -16
1264 ; RV64-NEXT: .cfi_offset fs2, -24
1265 ; RV64-NEXT: .cfi_offset fs3, -32
1266 ; RV64-NEXT: .cfi_offset fs4, -40
1267 ; RV64-NEXT: .cfi_offset fs5, -48
1268 ; RV64-NEXT: .cfi_offset fs6, -56
1269 ; RV64-NEXT: .cfi_offset fs7, -64
1270 ; RV64-NEXT: .cfi_offset fs8, -72
1271 ; RV64-NEXT: .cfi_offset fs9, -80
1272 ; RV64-NEXT: .cfi_offset fs10, -88
1273 ; RV64-NEXT: .cfi_offset fs11, -96
1274 ; RV64-NEXT: fmv.d.x ft4, a7
1275 ; RV64-NEXT: fmv.d.x ft5, a6
1276 ; RV64-NEXT: fmv.d.x ft6, a5
1277 ; RV64-NEXT: fmv.d.x ft7, a4
1278 ; RV64-NEXT: fmv.d.x ft8, a3
1279 ; RV64-NEXT: fmv.d.x ft9, a2
1280 ; RV64-NEXT: fmv.d.x ft10, a1
1281 ; RV64-NEXT: fmv.d.x ft11, a0
1282 ; RV64-NEXT: fld ft0, 216(sp)
1283 ; RV64-NEXT: fld ft1, 208(sp)
1284 ; RV64-NEXT: fld ft2, 200(sp)
1285 ; RV64-NEXT: fld ft3, 192(sp)
1286 ; RV64-NEXT: fld fs0, 184(sp)
1287 ; RV64-NEXT: fld fs1, 176(sp)
1288 ; RV64-NEXT: fld fs2, 168(sp)
1289 ; RV64-NEXT: fld fs3, 160(sp)
1290 ; RV64-NEXT: fld fs4, 152(sp)
1291 ; RV64-NEXT: fld fs5, 144(sp)
1292 ; RV64-NEXT: fld fs6, 136(sp)
1293 ; RV64-NEXT: fld fs7, 128(sp)
1294 ; RV64-NEXT: fld fs8, 104(sp)
1295 ; RV64-NEXT: fld fs9, 96(sp)
1296 ; RV64-NEXT: fld fs10, 120(sp)
1297 ; RV64-NEXT: fld fs11, 112(sp)
1298 ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1299 ; RV64-NEXT: vfmv.v.f v8, fa2
1300 ; RV64-NEXT: vfslide1down.vf v9, v8, fa3
1301 ; RV64-NEXT: vfmv.v.f v8, fa0
1302 ; RV64-NEXT: vfslide1down.vf v8, v8, fa1
1303 ; RV64-NEXT: vfmv.v.f v10, fa4
1304 ; RV64-NEXT: vfslide1down.vf v10, v10, fa5
1305 ; RV64-NEXT: vfmv.v.f v11, fa6
1306 ; RV64-NEXT: vfslide1down.vf v11, v11, fa7
1307 ; RV64-NEXT: vfmv.v.f v12, ft11
1308 ; RV64-NEXT: vfslide1down.vf v12, v12, ft10
1309 ; RV64-NEXT: vfmv.v.f v13, ft9
1310 ; RV64-NEXT: vfslide1down.vf v13, v13, ft8
1311 ; RV64-NEXT: vfmv.v.f v14, ft7
1312 ; RV64-NEXT: vfslide1down.vf v14, v14, ft6
1313 ; RV64-NEXT: vfmv.v.f v15, ft5
1314 ; RV64-NEXT: vfslide1down.vf v15, v15, ft4
1315 ; RV64-NEXT: vfmv.v.f v16, fs11
1316 ; RV64-NEXT: vfslide1down.vf v17, v16, fs10
1317 ; RV64-NEXT: vfmv.v.f v16, fs9
1318 ; RV64-NEXT: vfslide1down.vf v16, v16, fs8
1319 ; RV64-NEXT: vfmv.v.f v18, fs7
1320 ; RV64-NEXT: vfslide1down.vf v18, v18, fs6
1321 ; RV64-NEXT: vfmv.v.f v19, fs5
1322 ; RV64-NEXT: vfslide1down.vf v19, v19, fs4
1323 ; RV64-NEXT: vfmv.v.f v20, fs3
1324 ; RV64-NEXT: vfslide1down.vf v20, v20, fs2
1325 ; RV64-NEXT: vfmv.v.f v21, fs1
1326 ; RV64-NEXT: vfslide1down.vf v21, v21, fs0
1327 ; RV64-NEXT: vfmv.v.f v22, ft3
1328 ; RV64-NEXT: vfslide1down.vf v22, v22, ft2
1329 ; RV64-NEXT: vfmv.v.f v23, ft1
1330 ; RV64-NEXT: vfslide1down.vf v23, v23, ft0
1331 ; RV64-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload
1332 ; RV64-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload
1333 ; RV64-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload
1334 ; RV64-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload
1335 ; RV64-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload
1336 ; RV64-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload
1337 ; RV64-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload
1338 ; RV64-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload
1339 ; RV64-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload
1340 ; RV64-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload
1341 ; RV64-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload
1342 ; RV64-NEXT: fld fs11, 0(sp) # 8-byte Folded Reload
1343 ; RV64-NEXT: addi sp, sp, 96
1344 ; RV64-NEXT: ret
1345 %v0 = insertelement <32 x double> poison, double %e0, i64 0
1346 %v1 = insertelement <32 x double> %v0, double %e1, i64 1
1347 %v2 = insertelement <32 x double> %v1, double %e2, i64 2
1348 %v3 = insertelement <32 x double> %v2, double %e3, i64 3
1349 %v4 = insertelement <32 x double> %v3, double %e4, i64 4
1350 %v5 = insertelement <32 x double> %v4, double %e5, i64 5
1351 %v6 = insertelement <32 x double> %v5, double %e6, i64 6
1352 %v7 = insertelement <32 x double> %v6, double %e7, i64 7
1353 %v8 = insertelement <32 x double> %v7, double %e8, i64 8
1354 %v9 = insertelement <32 x double> %v8, double %e9, i64 9
1355 %v10 = insertelement <32 x double> %v9, double %e10, i64 10
1356 %v11 = insertelement <32 x double> %v10, double %e11, i64 11
1357 %v12 = insertelement <32 x double> %v11, double %e12, i64 12
1358 %v13 = insertelement <32 x double> %v12, double %e13, i64 13
1359 %v14 = insertelement <32 x double> %v13, double %e14, i64 14
1360 %v15 = insertelement <32 x double> %v14, double %e15, i64 15
1361 %v16 = insertelement <32 x double> %v15, double %e16, i64 16
1362 %v17 = insertelement <32 x double> %v16, double %e17, i64 17
1363 %v18 = insertelement <32 x double> %v17, double %e18, i64 18
1364 %v19 = insertelement <32 x double> %v18, double %e19, i64 19
1365 %v20 = insertelement <32 x double> %v19, double %e20, i64 20
1366 %v21 = insertelement <32 x double> %v20, double %e21, i64 21
1367 %v22 = insertelement <32 x double> %v21, double %e22, i64 22
1368 %v23 = insertelement <32 x double> %v22, double %e23, i64 23
1369 %v24 = insertelement <32 x double> %v23, double %e24, i64 24
1370 %v25 = insertelement <32 x double> %v24, double %e25, i64 25
1371 %v26 = insertelement <32 x double> %v25, double %e26, i64 26
1372 %v27 = insertelement <32 x double> %v26, double %e27, i64 27
1373 %v28 = insertelement <32 x double> %v27, double %e28, i64 28
1374 %v29 = insertelement <32 x double> %v28, double %e29, i64 29
1375 %v30 = insertelement <32 x double> %v29, double %e30, i64 30
1376 %v31 = insertelement <32 x double> %v30, double %e31, i64 31
1377 ret <32 x double> %v31
1378 }
1380 ; FIXME: These constants have enough sign bits that we could use vmv.v.x/i and
1381 ; vsext, but we don't support this for FP yet.
1382 define <2 x float> @signbits() {
1383 ; CHECK-LABEL: signbits:
1384 ; CHECK: # %bb.0: # %entry
1385 ; CHECK-NEXT: lui a0, %hi(.LCPI25_0)
1386 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI25_0)
1387 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1388 ; CHECK-NEXT: vle32.v v8, (a0)
1389 ; CHECK-NEXT: ret
1390 entry:
1391 ret <2 x float> <float 0x36A0000000000000, float 0.000000e+00>
1392 }
1394 define <2 x half> @vid_v2f16() {
1395 ; RV32ZVFH-LABEL: vid_v2f16:
1396 ; RV32ZVFH: # %bb.0:
1397 ; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1398 ; RV32ZVFH-NEXT: vid.v v8
1399 ; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v8
1400 ; RV32ZVFH-NEXT: ret
1401 ;
1402 ; RV64ZVFH-LABEL: vid_v2f16:
1403 ; RV64ZVFH: # %bb.0:
1404 ; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1405 ; RV64ZVFH-NEXT: vid.v v8
1406 ; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v8
1407 ; RV64ZVFH-NEXT: ret
1408 ;
1409 ; RV32ZVFHMIN-LABEL: vid_v2f16:
1410 ; RV32ZVFHMIN: # %bb.0:
1411 ; RV32ZVFHMIN-NEXT: lui a0, 245760
1412 ; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
1413 ; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0
1414 ; RV32ZVFHMIN-NEXT: ret
1415 ;
1416 ; RV64ZVFHMIN-LABEL: vid_v2f16:
1417 ; RV64ZVFHMIN: # %bb.0:
1418 ; RV64ZVFHMIN-NEXT: lui a0, 245760
1419 ; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
1420 ; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0
1421 ; RV64ZVFHMIN-NEXT: ret
1422 ret <2 x half> <half 0.0, half 1.0>
1423 }
1425 define <2 x half> @vid_addend1_v2f16() {
1426 ; RV32ZVFH-LABEL: vid_addend1_v2f16:
1427 ; RV32ZVFH: # %bb.0:
1428 ; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1429 ; RV32ZVFH-NEXT: vid.v v8
1430 ; RV32ZVFH-NEXT: vadd.vi v8, v8, 1
1431 ; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v8
1432 ; RV32ZVFH-NEXT: ret
1433 ;
1434 ; RV64ZVFH-LABEL: vid_addend1_v2f16:
1435 ; RV64ZVFH: # %bb.0:
1436 ; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1437 ; RV64ZVFH-NEXT: vid.v v8
1438 ; RV64ZVFH-NEXT: vadd.vi v8, v8, 1
1439 ; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v8
1440 ; RV64ZVFH-NEXT: ret
1441 ;
1442 ; RV32ZVFHMIN-LABEL: vid_addend1_v2f16:
1443 ; RV32ZVFHMIN: # %bb.0:
1444 ; RV32ZVFHMIN-NEXT: lui a0, 262148
1445 ; RV32ZVFHMIN-NEXT: addi a0, a0, -1024
1446 ; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
1447 ; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0
1448 ; RV32ZVFHMIN-NEXT: ret
1449 ;
1450 ; RV64ZVFHMIN-LABEL: vid_addend1_v2f16:
1451 ; RV64ZVFHMIN: # %bb.0:
1452 ; RV64ZVFHMIN-NEXT: lui a0, 262148
1453 ; RV64ZVFHMIN-NEXT: addi a0, a0, -1024
1454 ; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
1455 ; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0
1456 ; RV64ZVFHMIN-NEXT: ret
1457 ret <2 x half> <half 1.0, half 2.0>
1458 }
1460 define <2 x half> @vid_denominator2_v2f16() {
1461 ; RV32ZVFH-LABEL: vid_denominator2_v2f16:
1462 ; RV32ZVFH: # %bb.0:
1463 ; RV32ZVFH-NEXT: lui a0, %hi(.LCPI28_0)
1464 ; RV32ZVFH-NEXT: addi a0, a0, %lo(.LCPI28_0)
1465 ; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1466 ; RV32ZVFH-NEXT: vle16.v v8, (a0)
1467 ; RV32ZVFH-NEXT: ret
1468 ;
1469 ; RV64ZVFH-LABEL: vid_denominator2_v2f16:
1470 ; RV64ZVFH: # %bb.0:
1471 ; RV64ZVFH-NEXT: lui a0, %hi(.LCPI28_0)
1472 ; RV64ZVFH-NEXT: addi a0, a0, %lo(.LCPI28_0)
1473 ; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1474 ; RV64ZVFH-NEXT: vle16.v v8, (a0)
1475 ; RV64ZVFH-NEXT: ret
1476 ;
1477 ; RV32ZVFHMIN-LABEL: vid_denominator2_v2f16:
1478 ; RV32ZVFHMIN: # %bb.0:
1479 ; RV32ZVFHMIN-NEXT: lui a0, 245764
1480 ; RV32ZVFHMIN-NEXT: addi a0, a0, -2048
1481 ; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
1482 ; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0
1483 ; RV32ZVFHMIN-NEXT: ret
1484 ;
1485 ; RV64ZVFHMIN-LABEL: vid_denominator2_v2f16:
1486 ; RV64ZVFHMIN: # %bb.0:
1487 ; RV64ZVFHMIN-NEXT: lui a0, 245764
1488 ; RV64ZVFHMIN-NEXT: addi a0, a0, -2048
1489 ; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma
1490 ; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0
1491 ; RV64ZVFHMIN-NEXT: ret
1492 ret <2 x half> <half 0.5, half 1.0>
1493 }
1495 define <2 x half> @vid_step2_v2f16() {
1496 ; RV32ZVFH-LABEL: vid_step2_v2f16:
1497 ; RV32ZVFH: # %bb.0:
1498 ; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1499 ; RV32ZVFH-NEXT: vid.v v8
1500 ; RV32ZVFH-NEXT: vadd.vv v8, v8, v8
1501 ; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v8
1502 ; RV32ZVFH-NEXT: ret
1503 ;
1504 ; RV64ZVFH-LABEL: vid_step2_v2f16:
1505 ; RV64ZVFH: # %bb.0:
1506 ; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1507 ; RV64ZVFH-NEXT: vid.v v8
1508 ; RV64ZVFH-NEXT: vadd.vv v8, v8, v8
1509 ; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v8
1510 ; RV64ZVFH-NEXT: ret
1511 ;
1512 ; RV32ZVFHMIN-LABEL: vid_step2_v2f16:
1513 ; RV32ZVFHMIN: # %bb.0:
1514 ; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1515 ; RV32ZVFHMIN-NEXT: vid.v v8
1516 ; RV32ZVFHMIN-NEXT: vsll.vi v8, v8, 14
1517 ; RV32ZVFHMIN-NEXT: ret
1518 ;
1519 ; RV64ZVFHMIN-LABEL: vid_step2_v2f16:
1520 ; RV64ZVFHMIN: # %bb.0:
1521 ; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1522 ; RV64ZVFHMIN-NEXT: vid.v v8
1523 ; RV64ZVFHMIN-NEXT: vsll.vi v8, v8, 14
1524 ; RV64ZVFHMIN-NEXT: ret
1525 ret <2 x half> <half 0.0, half 2.0>
1526 }
1528 define <2 x float> @vid_v2f32() {
1529 ; CHECK-LABEL: vid_v2f32:
1530 ; CHECK: # %bb.0:
1531 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1532 ; CHECK-NEXT: vid.v v8
1533 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
1534 ; CHECK-NEXT: ret
1535 ret <2 x float> <float 0.0, float 1.0>
1536 }
1538 define <2 x float> @vid_addend1_v2f32() {
1539 ; CHECK-LABEL: vid_addend1_v2f32:
1540 ; CHECK: # %bb.0:
1541 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1542 ; CHECK-NEXT: vid.v v8
1543 ; CHECK-NEXT: vadd.vi v8, v8, 1
1544 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
1545 ; CHECK-NEXT: ret
1546 ret <2 x float> <float 1.0, float 2.0>
1547 }
1549 define <2 x float> @vid_denominator2_v2f32() {
1550 ; CHECK-LABEL: vid_denominator2_v2f32:
1551 ; CHECK: # %bb.0:
1552 ; CHECK-NEXT: lui a0, %hi(.LCPI32_0)
1553 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI32_0)
1554 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1555 ; CHECK-NEXT: vle32.v v8, (a0)
1556 ; CHECK-NEXT: ret
1557 ret <2 x float> <float 0.5, float 1.0>
1558 }
1560 define <2 x float> @vid_step2_v2f32() {
1561 ; CHECK-LABEL: vid_step2_v2f32:
1562 ; CHECK: # %bb.0:
1563 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
1564 ; CHECK-NEXT: vid.v v8
1565 ; CHECK-NEXT: vadd.vv v8, v8, v8
1566 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
1567 ; CHECK-NEXT: ret
1568 ret <2 x float> <float 0.0, float 2.0>
1569 }
1571 define <2 x double> @vid_v2f64() {
1572 ; CHECK-LABEL: vid_v2f64:
1573 ; CHECK: # %bb.0:
1574 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1575 ; CHECK-NEXT: vid.v v8
1576 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
1577 ; CHECK-NEXT: ret
1578 ret <2 x double> <double 0.0, double 1.0>
1579 }
1581 define <2 x double> @vid_addend1_v2f64() {
1582 ; CHECK-LABEL: vid_addend1_v2f64:
1583 ; CHECK: # %bb.0:
1584 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1585 ; CHECK-NEXT: vid.v v8
1586 ; CHECK-NEXT: vadd.vi v8, v8, 1
1587 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
1588 ; CHECK-NEXT: ret
1589 ret <2 x double> <double 1.0, double 2.0>
1590 }
1592 define <2 x double> @vid_denominator2_v2f64() {
1593 ; CHECK-LABEL: vid_denominator2_v2f64:
1594 ; CHECK: # %bb.0:
1595 ; CHECK-NEXT: lui a0, %hi(.LCPI36_0)
1596 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI36_0)
1597 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1598 ; CHECK-NEXT: vle64.v v8, (a0)
1599 ; CHECK-NEXT: ret
1600 ret <2 x double> <double 0.5, double 1.0>
1601 }
1603 define <2 x double> @vid_step2_v2f64() {
1604 ; CHECK-LABEL: vid_step2_v2f64:
1605 ; CHECK: # %bb.0:
1606 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
1607 ; CHECK-NEXT: vid.v v8
1608 ; CHECK-NEXT: vadd.vv v8, v8, v8
1609 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
1610 ; CHECK-NEXT: ret
1611 ret <2 x double> <double 0.0, double 2.0>
1612 }
1615 define <8 x float> @buildvec_v8f32_zvl256(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7) vscale_range(4, 128) {
1616 ; CHECK-LABEL: buildvec_v8f32_zvl256:
1617 ; CHECK: # %bb.0:
1618 ; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, mu
1619 ; CHECK-NEXT: vfmv.v.f v8, fa0
1620 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
1621 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa2
1622 ; CHECK-NEXT: vfslide1down.vf v9, v8, fa3
1623 ; CHECK-NEXT: vfmv.v.f v8, fa4
1624 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
1625 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa6
1626 ; CHECK-NEXT: vmv.v.i v0, 15
1627 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa7
1628 ; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t
1629 ; CHECK-NEXT: ret
1630 %v0 = insertelement <8 x float> poison, float %e0, i64 0
1631 %v1 = insertelement <8 x float> %v0, float %e1, i64 1
1632 %v2 = insertelement <8 x float> %v1, float %e2, i64 2
1633 %v3 = insertelement <8 x float> %v2, float %e3, i64 3
1634 %v4 = insertelement <8 x float> %v3, float %e4, i64 4
1635 %v5 = insertelement <8 x float> %v4, float %e5, i64 5
1636 %v6 = insertelement <8 x float> %v5, float %e6, i64 6
1637 %v7 = insertelement <8 x float> %v6, float %e7, i64 7
1638 ret <8 x float> %v7
1639 }
1642 define <8 x double> @buildvec_v8f64_zvl256(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) vscale_range(4, 128) {
1643 ; CHECK-LABEL: buildvec_v8f64_zvl256:
1644 ; CHECK: # %bb.0:
1645 ; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma
1646 ; CHECK-NEXT: vfmv.v.f v8, fa0
1647 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
1648 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa2
1649 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa3
1650 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa4
1651 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
1652 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa6
1653 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa7
1654 ; CHECK-NEXT: ret
1655 %v0 = insertelement <8 x double> poison, double %e0, i64 0
1656 %v1 = insertelement <8 x double> %v0, double %e1, i64 1
1657 %v2 = insertelement <8 x double> %v1, double %e2, i64 2
1658 %v3 = insertelement <8 x double> %v2, double %e3, i64 3
1659 %v4 = insertelement <8 x double> %v3, double %e4, i64 4
1660 %v5 = insertelement <8 x double> %v4, double %e5, i64 5
1661 %v6 = insertelement <8 x double> %v5, double %e6, i64 6
1662 %v7 = insertelement <8 x double> %v6, double %e7, i64 7
1663 ret <8 x double> %v7
1664 }
1666 define <8 x double> @buildvec_v8f64_zvl512(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) vscale_range(8, 128) {
1667 ; CHECK-LABEL: buildvec_v8f64_zvl512:
1668 ; CHECK: # %bb.0:
1669 ; CHECK-NEXT: vsetivli zero, 8, e64, m1, ta, mu
1670 ; CHECK-NEXT: vfmv.v.f v8, fa0
1671 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa1
1672 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa2
1673 ; CHECK-NEXT: vfslide1down.vf v9, v8, fa3
1674 ; CHECK-NEXT: vfmv.v.f v8, fa4
1675 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
1676 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa6
1677 ; CHECK-NEXT: vmv.v.i v0, 15
1678 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa7
1679 ; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t
1680 ; CHECK-NEXT: ret
1681 %v0 = insertelement <8 x double> poison, double %e0, i64 0
1682 %v1 = insertelement <8 x double> %v0, double %e1, i64 1
1683 %v2 = insertelement <8 x double> %v1, double %e2, i64 2
1684 %v3 = insertelement <8 x double> %v2, double %e3, i64 3
1685 %v4 = insertelement <8 x double> %v3, double %e4, i64 4
1686 %v5 = insertelement <8 x double> %v4, double %e5, i64 5
1687 %v6 = insertelement <8 x double> %v5, double %e6, i64 6
1688 %v7 = insertelement <8 x double> %v6, double %e7, i64 7
1689 ret <8 x double> %v7
1690 }