1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -mattr=+v -O0 < %s \
3 ; RUN: | FileCheck --check-prefix=SPILL-O0 %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+v -O2 < %s \
5 ; RUN: | FileCheck --check-prefix=SPILL-O2 %s
7 define <vscale x 1 x i64> @spill_lmul_1(<vscale x 1 x i64> %va) nounwind {
8 ; SPILL-O0-LABEL: spill_lmul_1:
9 ; SPILL-O0: # %bb.0: # %entry
10 ; SPILL-O0-NEXT: addi sp, sp, -16
11 ; SPILL-O0-NEXT: csrr a0, vlenb
12 ; SPILL-O0-NEXT: slli a0, a0, 1
13 ; SPILL-O0-NEXT: sub sp, sp, a0
14 ; SPILL-O0-NEXT: addi a0, sp, 16
15 ; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
17 ; SPILL-O0-NEXT: #NO_APP
18 ; SPILL-O0-NEXT: addi a0, sp, 16
19 ; SPILL-O0-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
20 ; SPILL-O0-NEXT: csrr a0, vlenb
21 ; SPILL-O0-NEXT: slli a0, a0, 1
22 ; SPILL-O0-NEXT: add sp, sp, a0
23 ; SPILL-O0-NEXT: addi sp, sp, 16
26 ; SPILL-O2-LABEL: spill_lmul_1:
27 ; SPILL-O2: # %bb.0: # %entry
28 ; SPILL-O2-NEXT: addi sp, sp, -16
29 ; SPILL-O2-NEXT: csrr a0, vlenb
30 ; SPILL-O2-NEXT: slli a0, a0, 1
31 ; SPILL-O2-NEXT: sub sp, sp, a0
32 ; SPILL-O2-NEXT: addi a0, sp, 16
33 ; SPILL-O2-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
35 ; SPILL-O2-NEXT: #NO_APP
36 ; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
37 ; SPILL-O2-NEXT: csrr a0, vlenb
38 ; SPILL-O2-NEXT: slli a0, a0, 1
39 ; SPILL-O2-NEXT: add sp, sp, a0
40 ; SPILL-O2-NEXT: addi sp, sp, 16
43 call void asm sideeffect "",
44 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
46 ret <vscale x 1 x i64> %va
49 define <vscale x 2 x i64> @spill_lmul_2(<vscale x 2 x i64> %va) nounwind {
50 ; SPILL-O0-LABEL: spill_lmul_2:
51 ; SPILL-O0: # %bb.0: # %entry
52 ; SPILL-O0-NEXT: addi sp, sp, -16
53 ; SPILL-O0-NEXT: csrr a0, vlenb
54 ; SPILL-O0-NEXT: slli a0, a0, 1
55 ; SPILL-O0-NEXT: sub sp, sp, a0
56 ; SPILL-O0-NEXT: addi a0, sp, 16
57 ; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
59 ; SPILL-O0-NEXT: #NO_APP
60 ; SPILL-O0-NEXT: addi a0, sp, 16
61 ; SPILL-O0-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
62 ; SPILL-O0-NEXT: csrr a0, vlenb
63 ; SPILL-O0-NEXT: slli a0, a0, 1
64 ; SPILL-O0-NEXT: add sp, sp, a0
65 ; SPILL-O0-NEXT: addi sp, sp, 16
68 ; SPILL-O2-LABEL: spill_lmul_2:
69 ; SPILL-O2: # %bb.0: # %entry
70 ; SPILL-O2-NEXT: addi sp, sp, -16
71 ; SPILL-O2-NEXT: csrr a0, vlenb
72 ; SPILL-O2-NEXT: slli a0, a0, 1
73 ; SPILL-O2-NEXT: sub sp, sp, a0
74 ; SPILL-O2-NEXT: addi a0, sp, 16
75 ; SPILL-O2-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
77 ; SPILL-O2-NEXT: #NO_APP
78 ; SPILL-O2-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
79 ; SPILL-O2-NEXT: csrr a0, vlenb
80 ; SPILL-O2-NEXT: slli a0, a0, 1
81 ; SPILL-O2-NEXT: add sp, sp, a0
82 ; SPILL-O2-NEXT: addi sp, sp, 16
85 call void asm sideeffect "",
86 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
88 ret <vscale x 2 x i64> %va
91 define <vscale x 4 x i64> @spill_lmul_4(<vscale x 4 x i64> %va) nounwind {
92 ; SPILL-O0-LABEL: spill_lmul_4:
93 ; SPILL-O0: # %bb.0: # %entry
94 ; SPILL-O0-NEXT: addi sp, sp, -16
95 ; SPILL-O0-NEXT: csrr a0, vlenb
96 ; SPILL-O0-NEXT: slli a0, a0, 2
97 ; SPILL-O0-NEXT: sub sp, sp, a0
98 ; SPILL-O0-NEXT: addi a0, sp, 16
99 ; SPILL-O0-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
100 ; SPILL-O0-NEXT: #APP
101 ; SPILL-O0-NEXT: #NO_APP
102 ; SPILL-O0-NEXT: addi a0, sp, 16
103 ; SPILL-O0-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload
104 ; SPILL-O0-NEXT: csrr a0, vlenb
105 ; SPILL-O0-NEXT: slli a0, a0, 2
106 ; SPILL-O0-NEXT: add sp, sp, a0
107 ; SPILL-O0-NEXT: addi sp, sp, 16
110 ; SPILL-O2-LABEL: spill_lmul_4:
111 ; SPILL-O2: # %bb.0: # %entry
112 ; SPILL-O2-NEXT: addi sp, sp, -16
113 ; SPILL-O2-NEXT: csrr a0, vlenb
114 ; SPILL-O2-NEXT: slli a0, a0, 2
115 ; SPILL-O2-NEXT: sub sp, sp, a0
116 ; SPILL-O2-NEXT: addi a0, sp, 16
117 ; SPILL-O2-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
118 ; SPILL-O2-NEXT: #APP
119 ; SPILL-O2-NEXT: #NO_APP
120 ; SPILL-O2-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload
121 ; SPILL-O2-NEXT: csrr a0, vlenb
122 ; SPILL-O2-NEXT: slli a0, a0, 2
123 ; SPILL-O2-NEXT: add sp, sp, a0
124 ; SPILL-O2-NEXT: addi sp, sp, 16
127 call void asm sideeffect "",
128 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
130 ret <vscale x 4 x i64> %va
133 define <vscale x 8 x i64> @spill_lmul_8(<vscale x 8 x i64> %va) nounwind {
134 ; SPILL-O0-LABEL: spill_lmul_8:
135 ; SPILL-O0: # %bb.0: # %entry
136 ; SPILL-O0-NEXT: addi sp, sp, -16
137 ; SPILL-O0-NEXT: csrr a0, vlenb
138 ; SPILL-O0-NEXT: slli a0, a0, 3
139 ; SPILL-O0-NEXT: sub sp, sp, a0
140 ; SPILL-O0-NEXT: addi a0, sp, 16
141 ; SPILL-O0-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
142 ; SPILL-O0-NEXT: #APP
143 ; SPILL-O0-NEXT: #NO_APP
144 ; SPILL-O0-NEXT: addi a0, sp, 16
145 ; SPILL-O0-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
146 ; SPILL-O0-NEXT: csrr a0, vlenb
147 ; SPILL-O0-NEXT: slli a0, a0, 3
148 ; SPILL-O0-NEXT: add sp, sp, a0
149 ; SPILL-O0-NEXT: addi sp, sp, 16
152 ; SPILL-O2-LABEL: spill_lmul_8:
153 ; SPILL-O2: # %bb.0: # %entry
154 ; SPILL-O2-NEXT: addi sp, sp, -16
155 ; SPILL-O2-NEXT: csrr a0, vlenb
156 ; SPILL-O2-NEXT: slli a0, a0, 3
157 ; SPILL-O2-NEXT: sub sp, sp, a0
158 ; SPILL-O2-NEXT: addi a0, sp, 16
159 ; SPILL-O2-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
160 ; SPILL-O2-NEXT: #APP
161 ; SPILL-O2-NEXT: #NO_APP
162 ; SPILL-O2-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
163 ; SPILL-O2-NEXT: csrr a0, vlenb
164 ; SPILL-O2-NEXT: slli a0, a0, 3
165 ; SPILL-O2-NEXT: add sp, sp, a0
166 ; SPILL-O2-NEXT: addi sp, sp, 16
169 call void asm sideeffect "",
170 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
172 ret <vscale x 8 x i64> %va