| blob | bcb008857ad320ab0372cbd0666dacd082a902a6 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh | FileCheck %s
3 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh | FileCheck %s
5 ; Integers
7 define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv32i1(<vscale x 32 x i1> %vec) {
8 ; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
9 ; CHECK: # %bb.0:
10 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
11 ; CHECK-NEXT: vmv.v.i v10, 0
12 ; CHECK-NEXT: csrr a0, vlenb
13 ; CHECK-NEXT: srli a0, a0, 2
14 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
15 ; CHECK-NEXT: vslidedown.vx v8, v0, a0
16 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
17 ; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
18 ; CHECK-NEXT: vmv1r.v v0, v8
19 ; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
20 ; CHECK-NEXT: vnsrl.wi v10, v12, 0
21 ; CHECK-NEXT: vmsne.vi v8, v10, 0
22 ; CHECK-NEXT: vnsrl.wi v10, v12, 8
23 ; CHECK-NEXT: vmsne.vi v9, v10, 0
24 ; CHECK-NEXT: ret
25 %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
26 ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
27 }
29 define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv32i8(<vscale x 32 x i8> %vec) {
30 ; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
31 ; CHECK: # %bb.0:
32 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
33 ; CHECK-NEXT: vnsrl.wi v12, v8, 0
34 ; CHECK-NEXT: vnsrl.wi v14, v8, 8
35 ; CHECK-NEXT: vmv.v.v v8, v12
36 ; CHECK-NEXT: vmv.v.v v10, v14
37 ; CHECK-NEXT: ret
38 %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
39 ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
40 }
42 define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv16i16(<vscale x 16 x i16> %vec) {
43 ; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
44 ; CHECK: # %bb.0:
45 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
46 ; CHECK-NEXT: vnsrl.wi v12, v8, 0
47 ; CHECK-NEXT: vnsrl.wi v14, v8, 16
48 ; CHECK-NEXT: vmv.v.v v8, v12
49 ; CHECK-NEXT: vmv.v.v v10, v14
50 ; CHECK-NEXT: ret
51 %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
52 ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
53 }
55 define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxvv8i32(<vscale x 8 x i32> %vec) {
56 ; CHECK-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
57 ; CHECK: # %bb.0:
58 ; CHECK-NEXT: li a0, 32
59 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
60 ; CHECK-NEXT: vnsrl.wx v12, v8, a0
61 ; CHECK-NEXT: vnsrl.wi v14, v8, 0
62 ; CHECK-NEXT: vmv.v.v v8, v14
63 ; CHECK-NEXT: vmv.v.v v10, v12
64 ; CHECK-NEXT: ret
65 %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
66 ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval
67 }
69 define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv4i64(<vscale x 4 x i64> %vec) {
70 ; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
71 ; CHECK: # %bb.0:
72 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
73 ; CHECK-NEXT: vid.v v12
74 ; CHECK-NEXT: vadd.vv v16, v12, v12
75 ; CHECK-NEXT: vrgather.vv v12, v8, v16
76 ; CHECK-NEXT: vadd.vi v16, v16, 1
77 ; CHECK-NEXT: vrgather.vv v20, v8, v16
78 ; CHECK-NEXT: vmv2r.v v8, v12
79 ; CHECK-NEXT: vmv2r.v v10, v20
80 ; CHECK-NEXT: ret
81 %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
82 ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
83 }
85 declare {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1>)
86 declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
87 declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)
88 declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
89 declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)
91 define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv128i1(<vscale x 128 x i1> %vec) {
92 ; CHECK-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
93 ; CHECK: # %bb.0:
94 ; CHECK-NEXT: addi sp, sp, -16
95 ; CHECK-NEXT: .cfi_def_cfa_offset 16
96 ; CHECK-NEXT: csrr a0, vlenb
97 ; CHECK-NEXT: slli a0, a0, 1
98 ; CHECK-NEXT: sub sp, sp, a0
99 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
100 ; CHECK-NEXT: vmv1r.v v12, v8
101 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
102 ; CHECK-NEXT: vmv.v.i v24, 0
103 ; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
104 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
105 ; CHECK-NEXT: vnsrl.wi v8, v16, 0
106 ; CHECK-NEXT: vmv1r.v v0, v12
107 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
108 ; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
109 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
110 ; CHECK-NEXT: vnsrl.wi v12, v24, 0
111 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
112 ; CHECK-NEXT: vmsne.vi v7, v8, 0
113 ; CHECK-NEXT: addi a0, sp, 16
114 ; CHECK-NEXT: vs1r.v v7, (a0) # Unknown-size Folded Spill
115 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
116 ; CHECK-NEXT: vnsrl.wi v0, v16, 8
117 ; CHECK-NEXT: vnsrl.wi v4, v24, 8
118 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
119 ; CHECK-NEXT: vmsne.vi v9, v0, 0
120 ; CHECK-NEXT: addi a0, sp, 16
121 ; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
122 ; CHECK-NEXT: csrr a0, vlenb
123 ; CHECK-NEXT: slli a0, a0, 1
124 ; CHECK-NEXT: add sp, sp, a0
125 ; CHECK-NEXT: addi sp, sp, 16
126 ; CHECK-NEXT: ret
127 %retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
128 ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval
129 }
131 define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv128i8(<vscale x 128 x i8> %vec) {
132 ; CHECK-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
133 ; CHECK: # %bb.0:
134 ; CHECK-NEXT: vmv8r.v v24, v8
135 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
136 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
137 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
138 ; CHECK-NEXT: vnsrl.wi v0, v24, 8
139 ; CHECK-NEXT: vnsrl.wi v4, v16, 8
140 ; CHECK-NEXT: vmv8r.v v16, v0
141 ; CHECK-NEXT: ret
142 %retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec)
143 ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval
144 }
146 define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_nxv64i16(<vscale x 64 x i16> %vec) {
147 ; CHECK-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
148 ; CHECK: # %bb.0:
149 ; CHECK-NEXT: vmv8r.v v24, v8
150 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
151 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
152 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
153 ; CHECK-NEXT: vnsrl.wi v0, v24, 16
154 ; CHECK-NEXT: vnsrl.wi v4, v16, 16
155 ; CHECK-NEXT: vmv8r.v v16, v0
156 ; CHECK-NEXT: ret
157 %retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec)
158 ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval
159 }
161 define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_nxvv32i32(<vscale x 32 x i32> %vec) {
162 ; CHECK-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
163 ; CHECK: # %bb.0:
164 ; CHECK-NEXT: vmv8r.v v24, v16
165 ; CHECK-NEXT: li a0, 32
166 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
167 ; CHECK-NEXT: vnsrl.wx v20, v24, a0
168 ; CHECK-NEXT: vnsrl.wx v16, v8, a0
169 ; CHECK-NEXT: vnsrl.wi v0, v8, 0
170 ; CHECK-NEXT: vnsrl.wi v4, v24, 0
171 ; CHECK-NEXT: vmv8r.v v8, v0
172 ; CHECK-NEXT: ret
173 %retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec)
174 ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval
175 }
177 define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
178 ; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
179 ; CHECK: # %bb.0:
180 ; CHECK-NEXT: addi sp, sp, -16
181 ; CHECK-NEXT: .cfi_def_cfa_offset 16
182 ; CHECK-NEXT: csrr a0, vlenb
183 ; CHECK-NEXT: slli a0, a0, 5
184 ; CHECK-NEXT: sub sp, sp, a0
185 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
186 ; CHECK-NEXT: csrr a0, vlenb
187 ; CHECK-NEXT: li a1, 24
188 ; CHECK-NEXT: mul a0, a0, a1
189 ; CHECK-NEXT: add a0, sp, a0
190 ; CHECK-NEXT: addi a0, a0, 16
191 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
192 ; CHECK-NEXT: vmv8r.v v24, v8
193 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
194 ; CHECK-NEXT: vid.v v8
195 ; CHECK-NEXT: vadd.vv v0, v8, v8
196 ; CHECK-NEXT: vrgather.vv v8, v24, v0
197 ; CHECK-NEXT: csrr a0, vlenb
198 ; CHECK-NEXT: slli a0, a0, 3
199 ; CHECK-NEXT: add a0, sp, a0
200 ; CHECK-NEXT: addi a0, a0, 16
201 ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
202 ; CHECK-NEXT: csrr a0, vlenb
203 ; CHECK-NEXT: li a1, 24
204 ; CHECK-NEXT: mul a0, a0, a1
205 ; CHECK-NEXT: add a0, sp, a0
206 ; CHECK-NEXT: addi a0, a0, 16
207 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
208 ; CHECK-NEXT: vrgather.vv v16, v8, v0
209 ; CHECK-NEXT: csrr a0, vlenb
210 ; CHECK-NEXT: slli a0, a0, 4
211 ; CHECK-NEXT: add a0, sp, a0
212 ; CHECK-NEXT: addi a0, a0, 16
213 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
214 ; CHECK-NEXT: vadd.vi v8, v0, 1
215 ; CHECK-NEXT: vrgather.vv v0, v24, v8
216 ; CHECK-NEXT: csrr a0, vlenb
217 ; CHECK-NEXT: li a1, 24
218 ; CHECK-NEXT: mul a0, a0, a1
219 ; CHECK-NEXT: add a0, sp, a0
220 ; CHECK-NEXT: addi a0, a0, 16
221 ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
222 ; CHECK-NEXT: vrgather.vv v16, v24, v8
223 ; CHECK-NEXT: addi a0, sp, 16
224 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
225 ; CHECK-NEXT: csrr a0, vlenb
226 ; CHECK-NEXT: slli a0, a0, 4
227 ; CHECK-NEXT: add a0, sp, a0
228 ; CHECK-NEXT: addi a0, a0, 16
229 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
230 ; CHECK-NEXT: csrr a0, vlenb
231 ; CHECK-NEXT: slli a0, a0, 3
232 ; CHECK-NEXT: add a0, sp, a0
233 ; CHECK-NEXT: addi a0, a0, 16
234 ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
235 ; CHECK-NEXT: vmv4r.v v20, v8
236 ; CHECK-NEXT: addi a0, sp, 16
237 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
238 ; CHECK-NEXT: vmv4r.v v4, v8
239 ; CHECK-NEXT: vmv8r.v v8, v16
240 ; CHECK-NEXT: vmv8r.v v16, v0
241 ; CHECK-NEXT: csrr a0, vlenb
242 ; CHECK-NEXT: slli a0, a0, 5
243 ; CHECK-NEXT: add sp, sp, a0
244 ; CHECK-NEXT: addi sp, sp, 16
245 ; CHECK-NEXT: ret
246 %retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
247 ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
248 }
250 declare {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1>)
251 declare {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.vector.deinterleave2.nxv128i8(<vscale x 128 x i8>)
252 declare {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.vector.deinterleave2.nxv64i16(<vscale x 64 x i16>)
253 declare {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.vector.deinterleave2.nxv32i32(<vscale x 32 x i32>)
254 declare {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64>)
256 ; Floats
258 define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv4f16(<vscale x 4 x half> %vec) {
259 ; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
260 ; CHECK: # %bb.0:
261 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
262 ; CHECK-NEXT: vnsrl.wi v10, v8, 0
263 ; CHECK-NEXT: vnsrl.wi v9, v8, 16
264 ; CHECK-NEXT: vmv1r.v v8, v10
265 ; CHECK-NEXT: ret
266 %retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
267 ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval
268 }
270 define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv8f16(<vscale x 8 x half> %vec) {
271 ; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
272 ; CHECK: # %bb.0:
273 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
274 ; CHECK-NEXT: vnsrl.wi v10, v8, 0
275 ; CHECK-NEXT: vnsrl.wi v11, v8, 16
276 ; CHECK-NEXT: vmv.v.v v8, v10
277 ; CHECK-NEXT: vmv.v.v v9, v11
278 ; CHECK-NEXT: ret
279 %retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
280 ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval
281 }
283 define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv4f32(<vscale x 4 x float> %vec) {
284 ; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
285 ; CHECK: # %bb.0:
286 ; CHECK-NEXT: li a0, 32
287 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
288 ; CHECK-NEXT: vnsrl.wx v10, v8, a0
289 ; CHECK-NEXT: vnsrl.wi v11, v8, 0
290 ; CHECK-NEXT: vmv.v.v v8, v11
291 ; CHECK-NEXT: vmv.v.v v9, v10
292 ; CHECK-NEXT: ret
293 %retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
294 ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
295 }
297 define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv16f16(<vscale x 16 x half> %vec) {
298 ; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
299 ; CHECK: # %bb.0:
300 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
301 ; CHECK-NEXT: vnsrl.wi v12, v8, 0
302 ; CHECK-NEXT: vnsrl.wi v14, v8, 16
303 ; CHECK-NEXT: vmv.v.v v8, v12
304 ; CHECK-NEXT: vmv.v.v v10, v14
305 ; CHECK-NEXT: ret
306 %retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
307 ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval
308 }
310 define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv8f32(<vscale x 8 x float> %vec) {
311 ; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
312 ; CHECK: # %bb.0:
313 ; CHECK-NEXT: li a0, 32
314 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
315 ; CHECK-NEXT: vnsrl.wx v12, v8, a0
316 ; CHECK-NEXT: vnsrl.wi v14, v8, 0
317 ; CHECK-NEXT: vmv.v.v v8, v14
318 ; CHECK-NEXT: vmv.v.v v10, v12
319 ; CHECK-NEXT: ret
320 %retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
321 ret {<vscale x 4 x float>, <vscale x 4 x float>} %retval
322 }
324 define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv4f64(<vscale x 4 x double> %vec) {
325 ; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
326 ; CHECK: # %bb.0:
327 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
328 ; CHECK-NEXT: vid.v v12
329 ; CHECK-NEXT: vadd.vv v16, v12, v12
330 ; CHECK-NEXT: vrgather.vv v12, v8, v16
331 ; CHECK-NEXT: vadd.vi v16, v16, 1
332 ; CHECK-NEXT: vrgather.vv v20, v8, v16
333 ; CHECK-NEXT: vmv2r.v v8, v12
334 ; CHECK-NEXT: vmv2r.v v10, v20
335 ; CHECK-NEXT: ret
336 %retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
337 ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
338 }
340 declare {<vscale x 2 x half>,<vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half>)
341 declare {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half>)
342 declare {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float>)
343 declare {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half>)
344 declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
345 declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double>)
347 define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f16_nxv64f16(<vscale x 64 x half> %vec) {
348 ; CHECK-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
349 ; CHECK: # %bb.0:
350 ; CHECK-NEXT: vmv8r.v v24, v8
351 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
352 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
353 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
354 ; CHECK-NEXT: vnsrl.wi v0, v24, 16
355 ; CHECK-NEXT: vnsrl.wi v4, v16, 16
356 ; CHECK-NEXT: vmv8r.v v16, v0
357 ; CHECK-NEXT: ret
358 %retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec)
359 ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval
360 }
362 define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16f32_nxv32f32(<vscale x 32 x float> %vec) {
363 ; CHECK-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
364 ; CHECK: # %bb.0:
365 ; CHECK-NEXT: vmv8r.v v24, v16
366 ; CHECK-NEXT: li a0, 32
367 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
368 ; CHECK-NEXT: vnsrl.wx v20, v24, a0
369 ; CHECK-NEXT: vnsrl.wx v16, v8, a0
370 ; CHECK-NEXT: vnsrl.wi v0, v8, 0
371 ; CHECK-NEXT: vnsrl.wi v4, v24, 0
372 ; CHECK-NEXT: vmv8r.v v8, v0
373 ; CHECK-NEXT: ret
374 %retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec)
375 ret {<vscale x 16 x float>, <vscale x 16 x float>} %retval
376 }
378 define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f64_nxv16f64(<vscale x 16 x double> %vec) {
379 ; CHECK-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
380 ; CHECK: # %bb.0:
381 ; CHECK-NEXT: addi sp, sp, -16
382 ; CHECK-NEXT: .cfi_def_cfa_offset 16
383 ; CHECK-NEXT: csrr a0, vlenb
384 ; CHECK-NEXT: slli a0, a0, 5
385 ; CHECK-NEXT: sub sp, sp, a0
386 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
387 ; CHECK-NEXT: csrr a0, vlenb
388 ; CHECK-NEXT: li a1, 24
389 ; CHECK-NEXT: mul a0, a0, a1
390 ; CHECK-NEXT: add a0, sp, a0
391 ; CHECK-NEXT: addi a0, a0, 16
392 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
393 ; CHECK-NEXT: vmv8r.v v24, v8
394 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
395 ; CHECK-NEXT: vid.v v8
396 ; CHECK-NEXT: vadd.vv v0, v8, v8
397 ; CHECK-NEXT: vrgather.vv v8, v24, v0
398 ; CHECK-NEXT: csrr a0, vlenb
399 ; CHECK-NEXT: slli a0, a0, 3
400 ; CHECK-NEXT: add a0, sp, a0
401 ; CHECK-NEXT: addi a0, a0, 16
402 ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
403 ; CHECK-NEXT: csrr a0, vlenb
404 ; CHECK-NEXT: li a1, 24
405 ; CHECK-NEXT: mul a0, a0, a1
406 ; CHECK-NEXT: add a0, sp, a0
407 ; CHECK-NEXT: addi a0, a0, 16
408 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
409 ; CHECK-NEXT: vrgather.vv v16, v8, v0
410 ; CHECK-NEXT: csrr a0, vlenb
411 ; CHECK-NEXT: slli a0, a0, 4
412 ; CHECK-NEXT: add a0, sp, a0
413 ; CHECK-NEXT: addi a0, a0, 16
414 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
415 ; CHECK-NEXT: vadd.vi v8, v0, 1
416 ; CHECK-NEXT: vrgather.vv v0, v24, v8
417 ; CHECK-NEXT: csrr a0, vlenb
418 ; CHECK-NEXT: li a1, 24
419 ; CHECK-NEXT: mul a0, a0, a1
420 ; CHECK-NEXT: add a0, sp, a0
421 ; CHECK-NEXT: addi a0, a0, 16
422 ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
423 ; CHECK-NEXT: vrgather.vv v16, v24, v8
424 ; CHECK-NEXT: addi a0, sp, 16
425 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
426 ; CHECK-NEXT: csrr a0, vlenb
427 ; CHECK-NEXT: slli a0, a0, 4
428 ; CHECK-NEXT: add a0, sp, a0
429 ; CHECK-NEXT: addi a0, a0, 16
430 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
431 ; CHECK-NEXT: csrr a0, vlenb
432 ; CHECK-NEXT: slli a0, a0, 3
433 ; CHECK-NEXT: add a0, sp, a0
434 ; CHECK-NEXT: addi a0, a0, 16
435 ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
436 ; CHECK-NEXT: vmv4r.v v20, v8
437 ; CHECK-NEXT: addi a0, sp, 16
438 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
439 ; CHECK-NEXT: vmv4r.v v4, v8
440 ; CHECK-NEXT: vmv8r.v v8, v16
441 ; CHECK-NEXT: vmv8r.v v16, v0
442 ; CHECK-NEXT: csrr a0, vlenb
443 ; CHECK-NEXT: slli a0, a0, 5
444 ; CHECK-NEXT: add sp, sp, a0
445 ; CHECK-NEXT: addi sp, sp, 16
446 ; CHECK-NEXT: ret
447 %retval = call {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.vector.deinterleave2.nxv16f64(<vscale x 16 x double> %vec)
448 ret {<vscale x 8 x double>, <vscale x 8 x double>} %retval
449 }
451 declare {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.vector.deinterleave2.nxv64f16(<vscale x 64 x half>)
452 declare {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.vector.deinterleave2.nxv32f32(<vscale x 32 x float>)
453 declare {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.vector.deinterleave2.nxv16f64(<vscale x 16 x double>)