| blob | 097d1e0f6ee55b38631df3fe0b790d3c90703603 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
3 ; RUN: -verify-machineinstrs -target-abi ilp32f -disable-strictnode-mutation \
4 ; RUN: | FileCheck -check-prefix=RV32IZFHMIN %s
5 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
6 ; RUN: -verify-machineinstrs -target-abi lp64f -disable-strictnode-mutation \
7 ; RUN: | FileCheck -check-prefix=RV64IZFHMIN %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
9 ; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d \
10 ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IZFHMIN %s
11 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
12 ; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d \
13 ; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IZFHMIN %s
14 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \
15 ; RUN: -verify-machineinstrs -target-abi ilp32 -disable-strictnode-mutation \
16 ; RUN: | FileCheck -check-prefix=RV32IZHINXMIN-STRICT %s
17 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \
18 ; RUN: -verify-machineinstrs -target-abi lp64 -disable-strictnode-mutation \
19 ; RUN: | FileCheck -check-prefix=RV64IZHINXMIN-STRICT %s
20 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
21 ; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \
22 ; RUN: FileCheck -check-prefix=RV32IZDINXZHINXMIN %s
23 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
24 ; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
25 ; RUN: FileCheck -check-prefix=RV64IZDINXZHINXMIN %s
27 declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
29 define half @sqrt_f16(half %a) nounwind strictfp {
30 ; RV32IZFHMIN-LABEL: sqrt_f16:
31 ; RV32IZFHMIN: # %bb.0:
32 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
33 ; RV32IZFHMIN-NEXT: fsqrt.s fa5, fa5
34 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
35 ; RV32IZFHMIN-NEXT: ret
36 ;
37 ; RV64IZFHMIN-LABEL: sqrt_f16:
38 ; RV64IZFHMIN: # %bb.0:
39 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
40 ; RV64IZFHMIN-NEXT: fsqrt.s fa5, fa5
41 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
42 ; RV64IZFHMIN-NEXT: ret
43 ;
44 ; RV32IZHINXMIN-STRICT-LABEL: sqrt_f16:
45 ; RV32IZHINXMIN-STRICT: # %bb.0:
46 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
47 ; RV32IZHINXMIN-STRICT-NEXT: fsqrt.s a0, a0
48 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
49 ; RV32IZHINXMIN-STRICT-NEXT: ret
50 ;
51 ; RV64IZHINXMIN-STRICT-LABEL: sqrt_f16:
52 ; RV64IZHINXMIN-STRICT: # %bb.0:
53 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
54 ; RV64IZHINXMIN-STRICT-NEXT: fsqrt.s a0, a0
55 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
56 ; RV64IZHINXMIN-STRICT-NEXT: ret
57 ;
58 ; RV32IZDINXZHINXMIN-LABEL: sqrt_f16:
59 ; RV32IZDINXZHINXMIN: # %bb.0:
60 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
61 ; RV32IZDINXZHINXMIN-NEXT: fsqrt.s a0, a0
62 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
63 ; RV32IZDINXZHINXMIN-NEXT: ret
64 ;
65 ; RV64IZDINXZHINXMIN-LABEL: sqrt_f16:
66 ; RV64IZDINXZHINXMIN: # %bb.0:
67 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
68 ; RV64IZDINXZHINXMIN-NEXT: fsqrt.s a0, a0
69 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
70 ; RV64IZDINXZHINXMIN-NEXT: ret
71 %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
72 ret half %1
73 }
75 declare half @llvm.experimental.constrained.floor.f16(half, metadata)
77 define half @floor_f16(half %a) nounwind strictfp {
78 ; RV32IZFHMIN-LABEL: floor_f16:
79 ; RV32IZFHMIN: # %bb.0:
80 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
81 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
82 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
83 ; RV32IZFHMIN-NEXT: call floorf
84 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
85 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
86 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
87 ; RV32IZFHMIN-NEXT: ret
88 ;
89 ; RV64IZFHMIN-LABEL: floor_f16:
90 ; RV64IZFHMIN: # %bb.0:
91 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
92 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
93 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
94 ; RV64IZFHMIN-NEXT: call floorf
95 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
96 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
97 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
98 ; RV64IZFHMIN-NEXT: ret
99 ;
100 ; RV32IZHINXMIN-STRICT-LABEL: floor_f16:
101 ; RV32IZHINXMIN-STRICT: # %bb.0:
102 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
103 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
104 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
105 ; RV32IZHINXMIN-STRICT-NEXT: call floorf
106 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
107 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
108 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
109 ; RV32IZHINXMIN-STRICT-NEXT: ret
110 ;
111 ; RV64IZHINXMIN-STRICT-LABEL: floor_f16:
112 ; RV64IZHINXMIN-STRICT: # %bb.0:
113 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
114 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
115 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
116 ; RV64IZHINXMIN-STRICT-NEXT: call floorf
117 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
118 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
119 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
120 ; RV64IZHINXMIN-STRICT-NEXT: ret
121 ;
122 ; RV32IZDINXZHINXMIN-LABEL: floor_f16:
123 ; RV32IZDINXZHINXMIN: # %bb.0:
124 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
125 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
126 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
127 ; RV32IZDINXZHINXMIN-NEXT: call floorf
128 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
129 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
130 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
131 ; RV32IZDINXZHINXMIN-NEXT: ret
132 ;
133 ; RV64IZDINXZHINXMIN-LABEL: floor_f16:
134 ; RV64IZDINXZHINXMIN: # %bb.0:
135 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16
136 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
137 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
138 ; RV64IZDINXZHINXMIN-NEXT: call floorf
139 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
140 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
141 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16
142 ; RV64IZDINXZHINXMIN-NEXT: ret
143 %1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
144 ret half %1
145 }
147 declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
149 define half @ceil_f16(half %a) nounwind strictfp {
150 ; RV32IZFHMIN-LABEL: ceil_f16:
151 ; RV32IZFHMIN: # %bb.0:
152 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
153 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
154 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
155 ; RV32IZFHMIN-NEXT: call ceilf
156 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
157 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
158 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
159 ; RV32IZFHMIN-NEXT: ret
160 ;
161 ; RV64IZFHMIN-LABEL: ceil_f16:
162 ; RV64IZFHMIN: # %bb.0:
163 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
164 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
165 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
166 ; RV64IZFHMIN-NEXT: call ceilf
167 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
168 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
169 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
170 ; RV64IZFHMIN-NEXT: ret
171 ;
172 ; RV32IZHINXMIN-STRICT-LABEL: ceil_f16:
173 ; RV32IZHINXMIN-STRICT: # %bb.0:
174 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
175 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
176 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
177 ; RV32IZHINXMIN-STRICT-NEXT: call ceilf
178 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
179 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
180 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
181 ; RV32IZHINXMIN-STRICT-NEXT: ret
182 ;
183 ; RV64IZHINXMIN-STRICT-LABEL: ceil_f16:
184 ; RV64IZHINXMIN-STRICT: # %bb.0:
185 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
186 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
187 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
188 ; RV64IZHINXMIN-STRICT-NEXT: call ceilf
189 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
190 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
191 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
192 ; RV64IZHINXMIN-STRICT-NEXT: ret
193 ;
194 ; RV32IZDINXZHINXMIN-LABEL: ceil_f16:
195 ; RV32IZDINXZHINXMIN: # %bb.0:
196 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
197 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
198 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
199 ; RV32IZDINXZHINXMIN-NEXT: call ceilf
200 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
201 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
202 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
203 ; RV32IZDINXZHINXMIN-NEXT: ret
204 ;
205 ; RV64IZDINXZHINXMIN-LABEL: ceil_f16:
206 ; RV64IZDINXZHINXMIN: # %bb.0:
207 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16
208 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
209 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
210 ; RV64IZDINXZHINXMIN-NEXT: call ceilf
211 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
212 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
213 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16
214 ; RV64IZDINXZHINXMIN-NEXT: ret
215 %1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
216 ret half %1
217 }
219 declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
221 define half @trunc_f16(half %a) nounwind strictfp {
222 ; RV32IZFHMIN-LABEL: trunc_f16:
223 ; RV32IZFHMIN: # %bb.0:
224 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
225 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
226 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
227 ; RV32IZFHMIN-NEXT: call truncf
228 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
229 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
230 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
231 ; RV32IZFHMIN-NEXT: ret
232 ;
233 ; RV64IZFHMIN-LABEL: trunc_f16:
234 ; RV64IZFHMIN: # %bb.0:
235 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
236 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
237 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
238 ; RV64IZFHMIN-NEXT: call truncf
239 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
240 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
241 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
242 ; RV64IZFHMIN-NEXT: ret
243 ;
244 ; RV32IZHINXMIN-STRICT-LABEL: trunc_f16:
245 ; RV32IZHINXMIN-STRICT: # %bb.0:
246 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
247 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
248 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
249 ; RV32IZHINXMIN-STRICT-NEXT: call truncf
250 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
251 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
252 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
253 ; RV32IZHINXMIN-STRICT-NEXT: ret
254 ;
255 ; RV64IZHINXMIN-STRICT-LABEL: trunc_f16:
256 ; RV64IZHINXMIN-STRICT: # %bb.0:
257 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
258 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
259 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
260 ; RV64IZHINXMIN-STRICT-NEXT: call truncf
261 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
262 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
263 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
264 ; RV64IZHINXMIN-STRICT-NEXT: ret
265 ;
266 ; RV32IZDINXZHINXMIN-LABEL: trunc_f16:
267 ; RV32IZDINXZHINXMIN: # %bb.0:
268 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
269 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
270 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
271 ; RV32IZDINXZHINXMIN-NEXT: call truncf
272 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
273 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
274 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
275 ; RV32IZDINXZHINXMIN-NEXT: ret
276 ;
277 ; RV64IZDINXZHINXMIN-LABEL: trunc_f16:
278 ; RV64IZDINXZHINXMIN: # %bb.0:
279 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16
280 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
281 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
282 ; RV64IZDINXZHINXMIN-NEXT: call truncf
283 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
284 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
285 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16
286 ; RV64IZDINXZHINXMIN-NEXT: ret
287 %1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
288 ret half %1
289 }
291 declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
293 define half @rint_f16(half %a) nounwind strictfp {
294 ; RV32IZFHMIN-LABEL: rint_f16:
295 ; RV32IZFHMIN: # %bb.0:
296 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
297 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
298 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
299 ; RV32IZFHMIN-NEXT: call rintf
300 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
301 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
302 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
303 ; RV32IZFHMIN-NEXT: ret
304 ;
305 ; RV64IZFHMIN-LABEL: rint_f16:
306 ; RV64IZFHMIN: # %bb.0:
307 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
308 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
309 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
310 ; RV64IZFHMIN-NEXT: call rintf
311 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
312 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
313 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
314 ; RV64IZFHMIN-NEXT: ret
315 ;
316 ; RV32IZHINXMIN-STRICT-LABEL: rint_f16:
317 ; RV32IZHINXMIN-STRICT: # %bb.0:
318 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
319 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
320 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
321 ; RV32IZHINXMIN-STRICT-NEXT: call rintf
322 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
323 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
324 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
325 ; RV32IZHINXMIN-STRICT-NEXT: ret
326 ;
327 ; RV64IZHINXMIN-STRICT-LABEL: rint_f16:
328 ; RV64IZHINXMIN-STRICT: # %bb.0:
329 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
330 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
331 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
332 ; RV64IZHINXMIN-STRICT-NEXT: call rintf
333 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
334 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
335 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
336 ; RV64IZHINXMIN-STRICT-NEXT: ret
337 ;
338 ; RV32IZDINXZHINXMIN-LABEL: rint_f16:
339 ; RV32IZDINXZHINXMIN: # %bb.0:
340 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
341 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
342 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
343 ; RV32IZDINXZHINXMIN-NEXT: call rintf
344 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
345 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
346 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
347 ; RV32IZDINXZHINXMIN-NEXT: ret
348 ;
349 ; RV64IZDINXZHINXMIN-LABEL: rint_f16:
350 ; RV64IZDINXZHINXMIN: # %bb.0:
351 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16
352 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
353 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
354 ; RV64IZDINXZHINXMIN-NEXT: call rintf
355 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
356 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
357 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16
358 ; RV64IZDINXZHINXMIN-NEXT: ret
359 %1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
360 ret half %1
361 }
363 declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
365 define half @nearbyint_f16(half %a) nounwind strictfp {
366 ; RV32IZFHMIN-LABEL: nearbyint_f16:
367 ; RV32IZFHMIN: # %bb.0:
368 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
369 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
370 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
371 ; RV32IZFHMIN-NEXT: call nearbyintf
372 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
373 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
374 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
375 ; RV32IZFHMIN-NEXT: ret
376 ;
377 ; RV64IZFHMIN-LABEL: nearbyint_f16:
378 ; RV64IZFHMIN: # %bb.0:
379 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
380 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
381 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
382 ; RV64IZFHMIN-NEXT: call nearbyintf
383 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
384 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
385 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
386 ; RV64IZFHMIN-NEXT: ret
387 ;
388 ; RV32IZHINXMIN-STRICT-LABEL: nearbyint_f16:
389 ; RV32IZHINXMIN-STRICT: # %bb.0:
390 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
391 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
392 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
393 ; RV32IZHINXMIN-STRICT-NEXT: call nearbyintf
394 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
395 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
396 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
397 ; RV32IZHINXMIN-STRICT-NEXT: ret
398 ;
399 ; RV64IZHINXMIN-STRICT-LABEL: nearbyint_f16:
400 ; RV64IZHINXMIN-STRICT: # %bb.0:
401 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
402 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
403 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
404 ; RV64IZHINXMIN-STRICT-NEXT: call nearbyintf
405 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
406 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
407 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
408 ; RV64IZHINXMIN-STRICT-NEXT: ret
409 ;
410 ; RV32IZDINXZHINXMIN-LABEL: nearbyint_f16:
411 ; RV32IZDINXZHINXMIN: # %bb.0:
412 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
413 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
414 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
415 ; RV32IZDINXZHINXMIN-NEXT: call nearbyintf
416 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
417 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
418 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
419 ; RV32IZDINXZHINXMIN-NEXT: ret
420 ;
421 ; RV64IZDINXZHINXMIN-LABEL: nearbyint_f16:
422 ; RV64IZDINXZHINXMIN: # %bb.0:
423 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16
424 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
425 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
426 ; RV64IZDINXZHINXMIN-NEXT: call nearbyintf
427 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
428 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
429 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16
430 ; RV64IZDINXZHINXMIN-NEXT: ret
431 %1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
432 ret half %1
433 }
435 declare half @llvm.experimental.constrained.round.f16(half, metadata)
437 define half @round_f16(half %a) nounwind strictfp {
438 ; RV32IZFHMIN-LABEL: round_f16:
439 ; RV32IZFHMIN: # %bb.0:
440 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
441 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
442 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
443 ; RV32IZFHMIN-NEXT: call roundf
444 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
445 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
446 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
447 ; RV32IZFHMIN-NEXT: ret
448 ;
449 ; RV64IZFHMIN-LABEL: round_f16:
450 ; RV64IZFHMIN: # %bb.0:
451 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
452 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
453 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
454 ; RV64IZFHMIN-NEXT: call roundf
455 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
456 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
457 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
458 ; RV64IZFHMIN-NEXT: ret
459 ;
460 ; RV32IZHINXMIN-STRICT-LABEL: round_f16:
461 ; RV32IZHINXMIN-STRICT: # %bb.0:
462 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
463 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
464 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
465 ; RV32IZHINXMIN-STRICT-NEXT: call roundf
466 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
467 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
468 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
469 ; RV32IZHINXMIN-STRICT-NEXT: ret
470 ;
471 ; RV64IZHINXMIN-STRICT-LABEL: round_f16:
472 ; RV64IZHINXMIN-STRICT: # %bb.0:
473 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
474 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
475 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
476 ; RV64IZHINXMIN-STRICT-NEXT: call roundf
477 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
478 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
479 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
480 ; RV64IZHINXMIN-STRICT-NEXT: ret
481 ;
482 ; RV32IZDINXZHINXMIN-LABEL: round_f16:
483 ; RV32IZDINXZHINXMIN: # %bb.0:
484 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
485 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
486 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
487 ; RV32IZDINXZHINXMIN-NEXT: call roundf
488 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
489 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
490 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
491 ; RV32IZDINXZHINXMIN-NEXT: ret
492 ;
493 ; RV64IZDINXZHINXMIN-LABEL: round_f16:
494 ; RV64IZDINXZHINXMIN: # %bb.0:
495 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16
496 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
497 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
498 ; RV64IZDINXZHINXMIN-NEXT: call roundf
499 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
500 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
501 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16
502 ; RV64IZDINXZHINXMIN-NEXT: ret
503 %1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
504 ret half %1
505 }
507 declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
509 define half @roundeven_f16(half %a) nounwind strictfp {
510 ; RV32IZFHMIN-LABEL: roundeven_f16:
511 ; RV32IZFHMIN: # %bb.0:
512 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
513 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
514 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
515 ; RV32IZFHMIN-NEXT: call roundevenf
516 ; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
517 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
518 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
519 ; RV32IZFHMIN-NEXT: ret
520 ;
521 ; RV64IZFHMIN-LABEL: roundeven_f16:
522 ; RV64IZFHMIN: # %bb.0:
523 ; RV64IZFHMIN-NEXT: addi sp, sp, -16
524 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
525 ; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
526 ; RV64IZFHMIN-NEXT: call roundevenf
527 ; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
528 ; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
529 ; RV64IZFHMIN-NEXT: addi sp, sp, 16
530 ; RV64IZFHMIN-NEXT: ret
531 ;
532 ; RV32IZHINXMIN-STRICT-LABEL: roundeven_f16:
533 ; RV32IZHINXMIN-STRICT: # %bb.0:
534 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
535 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
536 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
537 ; RV32IZHINXMIN-STRICT-NEXT: call roundevenf
538 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
539 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
540 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
541 ; RV32IZHINXMIN-STRICT-NEXT: ret
542 ;
543 ; RV64IZHINXMIN-STRICT-LABEL: roundeven_f16:
544 ; RV64IZHINXMIN-STRICT: # %bb.0:
545 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
546 ; RV64IZHINXMIN-STRICT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
547 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
548 ; RV64IZHINXMIN-STRICT-NEXT: call roundevenf
549 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.h.s a0, a0
550 ; RV64IZHINXMIN-STRICT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
551 ; RV64IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
552 ; RV64IZHINXMIN-STRICT-NEXT: ret
553 ;
554 ; RV32IZDINXZHINXMIN-LABEL: roundeven_f16:
555 ; RV32IZDINXZHINXMIN: # %bb.0:
556 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
557 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
558 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
559 ; RV32IZDINXZHINXMIN-NEXT: call roundevenf
560 ; RV32IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
561 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
562 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
563 ; RV32IZDINXZHINXMIN-NEXT: ret
564 ;
565 ; RV64IZDINXZHINXMIN-LABEL: roundeven_f16:
566 ; RV64IZDINXZHINXMIN: # %bb.0:
567 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, -16
568 ; RV64IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
569 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
570 ; RV64IZDINXZHINXMIN-NEXT: call roundevenf
571 ; RV64IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
572 ; RV64IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
573 ; RV64IZDINXZHINXMIN-NEXT: addi sp, sp, 16
574 ; RV64IZDINXZHINXMIN-NEXT: ret
575 %1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
576 ret half %1
577 }
579 declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
581 define iXLen @lrint_f16(half %a) nounwind strictfp {
582 ; RV32IZFHMIN-LABEL: lrint_f16:
583 ; RV32IZFHMIN: # %bb.0:
584 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
585 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5
586 ; RV32IZFHMIN-NEXT: ret
587 ;
588 ; RV64IZFHMIN-LABEL: lrint_f16:
589 ; RV64IZFHMIN: # %bb.0:
590 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
591 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5
592 ; RV64IZFHMIN-NEXT: ret
593 ;
594 ; RV32IZHINXMIN-STRICT-LABEL: lrint_f16:
595 ; RV32IZHINXMIN-STRICT: # %bb.0:
596 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
597 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.w.s a0, a0
598 ; RV32IZHINXMIN-STRICT-NEXT: ret
599 ;
600 ; RV64IZHINXMIN-STRICT-LABEL: lrint_f16:
601 ; RV64IZHINXMIN-STRICT: # %bb.0:
602 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
603 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.l.s a0, a0
604 ; RV64IZHINXMIN-STRICT-NEXT: ret
605 ;
606 ; RV32IZDINXZHINXMIN-LABEL: lrint_f16:
607 ; RV32IZDINXZHINXMIN: # %bb.0:
608 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
609 ; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0
610 ; RV32IZDINXZHINXMIN-NEXT: ret
611 ;
612 ; RV64IZDINXZHINXMIN-LABEL: lrint_f16:
613 ; RV64IZDINXZHINXMIN: # %bb.0:
614 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
615 ; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0
616 ; RV64IZDINXZHINXMIN-NEXT: ret
617 %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
618 ret iXLen %1
619 }
621 declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata)
623 define iXLen @lround_f16(half %a) nounwind strictfp {
624 ; RV32IZFHMIN-LABEL: lround_f16:
625 ; RV32IZFHMIN: # %bb.0:
626 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
627 ; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm
628 ; RV32IZFHMIN-NEXT: ret
629 ;
630 ; RV64IZFHMIN-LABEL: lround_f16:
631 ; RV64IZFHMIN: # %bb.0:
632 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
633 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm
634 ; RV64IZFHMIN-NEXT: ret
635 ;
636 ; RV32IZHINXMIN-STRICT-LABEL: lround_f16:
637 ; RV32IZHINXMIN-STRICT: # %bb.0:
638 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
639 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.w.s a0, a0, rmm
640 ; RV32IZHINXMIN-STRICT-NEXT: ret
641 ;
642 ; RV64IZHINXMIN-STRICT-LABEL: lround_f16:
643 ; RV64IZHINXMIN-STRICT: # %bb.0:
644 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
645 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.l.s a0, a0, rmm
646 ; RV64IZHINXMIN-STRICT-NEXT: ret
647 ;
648 ; RV32IZDINXZHINXMIN-LABEL: lround_f16:
649 ; RV32IZDINXZHINXMIN: # %bb.0:
650 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
651 ; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm
652 ; RV32IZDINXZHINXMIN-NEXT: ret
653 ;
654 ; RV64IZDINXZHINXMIN-LABEL: lround_f16:
655 ; RV64IZDINXZHINXMIN: # %bb.0:
656 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
657 ; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm
658 ; RV64IZDINXZHINXMIN-NEXT: ret
659 %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
660 ret iXLen %1
661 }
663 declare i64 @llvm.experimental.constrained.llrint.i64.f16(half, metadata, metadata)
665 define i64 @llrint_f16(half %a) nounwind strictfp {
666 ; RV32IZFHMIN-LABEL: llrint_f16:
667 ; RV32IZFHMIN: # %bb.0:
668 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
669 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
670 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
671 ; RV32IZFHMIN-NEXT: call llrintf
672 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
673 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
674 ; RV32IZFHMIN-NEXT: ret
675 ;
676 ; RV64IZFHMIN-LABEL: llrint_f16:
677 ; RV64IZFHMIN: # %bb.0:
678 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
679 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5
680 ; RV64IZFHMIN-NEXT: ret
681 ;
682 ; RV32IZHINXMIN-STRICT-LABEL: llrint_f16:
683 ; RV32IZHINXMIN-STRICT: # %bb.0:
684 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
685 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
686 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
687 ; RV32IZHINXMIN-STRICT-NEXT: call llrintf
688 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
689 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
690 ; RV32IZHINXMIN-STRICT-NEXT: ret
691 ;
692 ; RV64IZHINXMIN-STRICT-LABEL: llrint_f16:
693 ; RV64IZHINXMIN-STRICT: # %bb.0:
694 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
695 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.l.s a0, a0
696 ; RV64IZHINXMIN-STRICT-NEXT: ret
697 ;
698 ; RV32IZDINXZHINXMIN-LABEL: llrint_f16:
699 ; RV32IZDINXZHINXMIN: # %bb.0:
700 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
701 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
702 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
703 ; RV32IZDINXZHINXMIN-NEXT: call llrintf
704 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
705 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
706 ; RV32IZDINXZHINXMIN-NEXT: ret
707 ;
708 ; RV64IZDINXZHINXMIN-LABEL: llrint_f16:
709 ; RV64IZDINXZHINXMIN: # %bb.0:
710 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
711 ; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0
712 ; RV64IZDINXZHINXMIN-NEXT: ret
713 %1 = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
714 ret i64 %1
715 }
717 declare i64 @llvm.experimental.constrained.llround.i64.f16(half, metadata)
719 define i64 @llround_f16(half %a) nounwind strictfp {
720 ; RV32IZFHMIN-LABEL: llround_f16:
721 ; RV32IZFHMIN: # %bb.0:
722 ; RV32IZFHMIN-NEXT: addi sp, sp, -16
723 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
724 ; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
725 ; RV32IZFHMIN-NEXT: call llroundf
726 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
727 ; RV32IZFHMIN-NEXT: addi sp, sp, 16
728 ; RV32IZFHMIN-NEXT: ret
729 ;
730 ; RV64IZFHMIN-LABEL: llround_f16:
731 ; RV64IZFHMIN: # %bb.0:
732 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
733 ; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm
734 ; RV64IZFHMIN-NEXT: ret
735 ;
736 ; RV32IZHINXMIN-STRICT-LABEL: llround_f16:
737 ; RV32IZHINXMIN-STRICT: # %bb.0:
738 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, -16
739 ; RV32IZHINXMIN-STRICT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
740 ; RV32IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
741 ; RV32IZHINXMIN-STRICT-NEXT: call llroundf
742 ; RV32IZHINXMIN-STRICT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
743 ; RV32IZHINXMIN-STRICT-NEXT: addi sp, sp, 16
744 ; RV32IZHINXMIN-STRICT-NEXT: ret
745 ;
746 ; RV64IZHINXMIN-STRICT-LABEL: llround_f16:
747 ; RV64IZHINXMIN-STRICT: # %bb.0:
748 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.s.h a0, a0
749 ; RV64IZHINXMIN-STRICT-NEXT: fcvt.l.s a0, a0, rmm
750 ; RV64IZHINXMIN-STRICT-NEXT: ret
751 ;
752 ; RV32IZDINXZHINXMIN-LABEL: llround_f16:
753 ; RV32IZDINXZHINXMIN: # %bb.0:
754 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, -16
755 ; RV32IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
756 ; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
757 ; RV32IZDINXZHINXMIN-NEXT: call llroundf
758 ; RV32IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
759 ; RV32IZDINXZHINXMIN-NEXT: addi sp, sp, 16
760 ; RV32IZDINXZHINXMIN-NEXT: ret
761 ;
762 ; RV64IZDINXZHINXMIN-LABEL: llround_f16:
763 ; RV64IZDINXZHINXMIN: # %bb.0:
764 ; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
765 ; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm
766 ; RV64IZDINXZHINXMIN-NEXT: ret
767 %1 = call i64 @llvm.experimental.constrained.llround.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
768 ret i64 %1
769 }