| blob | 7af5775c61d7bf4a5d1f8a158509f49d80a5c23b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-unknown-eabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=ARM
4 declare i4 @llvm.umul.fix.i4 (i4, i4, i32)
5 declare i32 @llvm.umul.fix.i32 (i32, i32, i32)
6 declare i64 @llvm.umul.fix.i64 (i64, i64, i32)
8 define i32 @func(i32 %x, i32 %y) nounwind {
9 ; ARM-LABEL: func:
10 ; ARM: @ %bb.0:
11 ; ARM-NEXT: .save {r7, lr}
12 ; ARM-NEXT: push {r7, lr}
13 ; ARM-NEXT: mov r2, r1
14 ; ARM-NEXT: movs r1, #0
15 ; ARM-NEXT: mov r3, r1
16 ; ARM-NEXT: bl __aeabi_lmul
17 ; ARM-NEXT: lsrs r0, r0, #2
18 ; ARM-NEXT: lsls r1, r1, #30
19 ; ARM-NEXT: adds r0, r1, r0
20 ; ARM-NEXT: pop {r7, pc}
21 %tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 2)
22 ret i32 %tmp
23 }
25 define i64 @func2(i64 %x, i64 %y) nounwind {
26 ; ARM-LABEL: func2:
27 ; ARM: @ %bb.0:
28 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
29 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
30 ; ARM-NEXT: .pad #28
31 ; ARM-NEXT: sub sp, #28
32 ; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill
33 ; ARM-NEXT: mov r4, r1
34 ; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
35 ; ARM-NEXT: movs r6, #0
36 ; ARM-NEXT: mov r5, r0
37 ; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
38 ; ARM-NEXT: mov r1, r6
39 ; ARM-NEXT: mov r7, r2
40 ; ARM-NEXT: str r2, [sp, #20] @ 4-byte Spill
41 ; ARM-NEXT: mov r3, r6
42 ; ARM-NEXT: bl __aeabi_lmul
43 ; ARM-NEXT: str r0, [sp, #24] @ 4-byte Spill
44 ; ARM-NEXT: str r1, [sp, #16] @ 4-byte Spill
45 ; ARM-NEXT: mov r0, r4
46 ; ARM-NEXT: mov r1, r6
47 ; ARM-NEXT: mov r2, r7
48 ; ARM-NEXT: mov r3, r6
49 ; ARM-NEXT: bl __aeabi_lmul
50 ; ARM-NEXT: mov r4, r1
51 ; ARM-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
52 ; ARM-NEXT: adds r0, r0, r1
53 ; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
54 ; ARM-NEXT: adcs r4, r6
55 ; ARM-NEXT: mov r0, r5
56 ; ARM-NEXT: mov r1, r6
57 ; ARM-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
58 ; ARM-NEXT: mov r2, r5
59 ; ARM-NEXT: mov r3, r6
60 ; ARM-NEXT: bl __aeabi_lmul
61 ; ARM-NEXT: mov r7, r1
62 ; ARM-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
63 ; ARM-NEXT: adds r0, r0, r1
64 ; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
65 ; ARM-NEXT: adcs r7, r4
66 ; ARM-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
67 ; ARM-NEXT: mov r0, r4
68 ; ARM-NEXT: mov r1, r6
69 ; ARM-NEXT: mov r2, r5
70 ; ARM-NEXT: mov r3, r6
71 ; ARM-NEXT: bl __aeabi_lmul
72 ; ARM-NEXT: adds r7, r0, r7
73 ; ARM-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
74 ; ARM-NEXT: mov r1, r5
75 ; ARM-NEXT: mov r2, r6
76 ; ARM-NEXT: mov r3, r6
77 ; ARM-NEXT: bl __aeabi_lmul
78 ; ARM-NEXT: mov r5, r0
79 ; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
80 ; ARM-NEXT: mov r1, r4
81 ; ARM-NEXT: mov r2, r6
82 ; ARM-NEXT: mov r3, r6
83 ; ARM-NEXT: bl __aeabi_lmul
84 ; ARM-NEXT: adds r0, r0, r5
85 ; ARM-NEXT: adds r0, r7, r0
86 ; ARM-NEXT: lsls r0, r0, #30
87 ; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
88 ; ARM-NEXT: lsrs r1, r2, #2
89 ; ARM-NEXT: adds r1, r0, r1
90 ; ARM-NEXT: lsls r0, r2, #30
91 ; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
92 ; ARM-NEXT: lsrs r2, r2, #2
93 ; ARM-NEXT: adds r0, r0, r2
94 ; ARM-NEXT: add sp, #28
95 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
96 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 2)
97 ret i64 %tmp
98 }
100 define i4 @func3(i4 %x, i4 %y) nounwind {
101 ; ARM-LABEL: func3:
102 ; ARM: @ %bb.0:
103 ; ARM-NEXT: .save {r7, lr}
104 ; ARM-NEXT: push {r7, lr}
105 ; ARM-NEXT: movs r2, #15
106 ; ARM-NEXT: ands r0, r2
107 ; ARM-NEXT: ands r2, r1
108 ; ARM-NEXT: movs r1, #0
109 ; ARM-NEXT: mov r3, r1
110 ; ARM-NEXT: bl __aeabi_lmul
111 ; ARM-NEXT: lsrs r0, r0, #2
112 ; ARM-NEXT: lsls r1, r1, #30
113 ; ARM-NEXT: adds r0, r1, r0
114 ; ARM-NEXT: pop {r7, pc}
115 %tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 2)
116 ret i4 %tmp
117 }
119 ;; These result in regular integer multiplication
120 define i32 @func4(i32 %x, i32 %y) nounwind {
121 ; ARM-LABEL: func4:
122 ; ARM: @ %bb.0:
123 ; ARM-NEXT: muls r0, r1, r0
124 ; ARM-NEXT: bx lr
125 %tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 0)
126 ret i32 %tmp
127 }
129 define i64 @func5(i64 %x, i64 %y) nounwind {
130 ; ARM-LABEL: func5:
131 ; ARM: @ %bb.0:
132 ; ARM-NEXT: .save {r7, lr}
133 ; ARM-NEXT: push {r7, lr}
134 ; ARM-NEXT: bl __aeabi_lmul
135 ; ARM-NEXT: pop {r7, pc}
136 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 0)
137 ret i64 %tmp
138 }
140 define i4 @func6(i4 %x, i4 %y) nounwind {
141 ; ARM-LABEL: func6:
142 ; ARM: @ %bb.0:
143 ; ARM-NEXT: movs r2, #15
144 ; ARM-NEXT: ands r1, r2
145 ; ARM-NEXT: ands r0, r2
146 ; ARM-NEXT: muls r0, r1, r0
147 ; ARM-NEXT: bx lr
148 %tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 0)
149 ret i4 %tmp
150 }
152 define i64 @func7(i64 %x, i64 %y) nounwind {
153 ; ARM-LABEL: func7:
154 ; ARM: @ %bb.0:
155 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
156 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
157 ; ARM-NEXT: .pad #20
158 ; ARM-NEXT: sub sp, #20
159 ; ARM-NEXT: str r3, [sp, #4] @ 4-byte Spill
160 ; ARM-NEXT: mov r7, r1
161 ; ARM-NEXT: str r1, [sp] @ 4-byte Spill
162 ; ARM-NEXT: movs r5, #0
163 ; ARM-NEXT: mov r4, r0
164 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
165 ; ARM-NEXT: mov r1, r5
166 ; ARM-NEXT: mov r6, r2
167 ; ARM-NEXT: str r2, [sp, #16] @ 4-byte Spill
168 ; ARM-NEXT: mov r3, r5
169 ; ARM-NEXT: bl __aeabi_lmul
170 ; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill
171 ; ARM-NEXT: mov r0, r7
172 ; ARM-NEXT: mov r1, r5
173 ; ARM-NEXT: mov r2, r6
174 ; ARM-NEXT: mov r3, r5
175 ; ARM-NEXT: bl __aeabi_lmul
176 ; ARM-NEXT: mov r7, r1
177 ; ARM-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
178 ; ARM-NEXT: adds r0, r0, r1
179 ; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
180 ; ARM-NEXT: adcs r7, r5
181 ; ARM-NEXT: mov r0, r4
182 ; ARM-NEXT: mov r1, r5
183 ; ARM-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
184 ; ARM-NEXT: mov r2, r4
185 ; ARM-NEXT: mov r3, r5
186 ; ARM-NEXT: bl __aeabi_lmul
187 ; ARM-NEXT: mov r6, r1
188 ; ARM-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
189 ; ARM-NEXT: adds r0, r0, r1
190 ; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
191 ; ARM-NEXT: adcs r6, r7
192 ; ARM-NEXT: ldr r7, [sp] @ 4-byte Reload
193 ; ARM-NEXT: mov r0, r7
194 ; ARM-NEXT: mov r1, r5
195 ; ARM-NEXT: mov r2, r4
196 ; ARM-NEXT: mov r3, r5
197 ; ARM-NEXT: bl __aeabi_lmul
198 ; ARM-NEXT: adds r6, r0, r6
199 ; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
200 ; ARM-NEXT: mov r1, r4
201 ; ARM-NEXT: mov r2, r5
202 ; ARM-NEXT: mov r3, r5
203 ; ARM-NEXT: bl __aeabi_lmul
204 ; ARM-NEXT: mov r4, r0
205 ; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
206 ; ARM-NEXT: mov r1, r7
207 ; ARM-NEXT: mov r2, r5
208 ; ARM-NEXT: mov r3, r5
209 ; ARM-NEXT: bl __aeabi_lmul
210 ; ARM-NEXT: adds r0, r0, r4
211 ; ARM-NEXT: adds r1, r6, r0
212 ; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
213 ; ARM-NEXT: add sp, #20
214 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
215 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 32)
216 ret i64 %tmp
217 }
219 define i64 @func8(i64 %x, i64 %y) nounwind {
220 ; ARM-LABEL: func8:
221 ; ARM: @ %bb.0:
222 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
223 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
224 ; ARM-NEXT: .pad #28
225 ; ARM-NEXT: sub sp, #28
226 ; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
227 ; ARM-NEXT: mov r7, r2
228 ; ARM-NEXT: str r2, [sp, #16] @ 4-byte Spill
229 ; ARM-NEXT: mov r4, r1
230 ; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
231 ; ARM-NEXT: movs r5, #0
232 ; ARM-NEXT: mov r6, r0
233 ; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
234 ; ARM-NEXT: mov r1, r5
235 ; ARM-NEXT: mov r3, r5
236 ; ARM-NEXT: bl __aeabi_lmul
237 ; ARM-NEXT: str r1, [sp, #20] @ 4-byte Spill
238 ; ARM-NEXT: mov r0, r4
239 ; ARM-NEXT: mov r1, r5
240 ; ARM-NEXT: mov r2, r7
241 ; ARM-NEXT: mov r3, r5
242 ; ARM-NEXT: bl __aeabi_lmul
243 ; ARM-NEXT: mov r7, r1
244 ; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
245 ; ARM-NEXT: adds r4, r0, r1
246 ; ARM-NEXT: adcs r7, r5
247 ; ARM-NEXT: mov r0, r6
248 ; ARM-NEXT: mov r1, r5
249 ; ARM-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
250 ; ARM-NEXT: mov r2, r6
251 ; ARM-NEXT: mov r3, r5
252 ; ARM-NEXT: bl __aeabi_lmul
253 ; ARM-NEXT: adds r0, r0, r4
254 ; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
255 ; ARM-NEXT: adcs r1, r5
256 ; ARM-NEXT: adds r0, r7, r1
257 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
258 ; ARM-NEXT: mov r4, r5
259 ; ARM-NEXT: adcs r4, r5
260 ; ARM-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
261 ; ARM-NEXT: mov r0, r7
262 ; ARM-NEXT: mov r1, r5
263 ; ARM-NEXT: mov r2, r6
264 ; ARM-NEXT: mov r3, r5
265 ; ARM-NEXT: bl __aeabi_lmul
266 ; ARM-NEXT: mov r6, r1
267 ; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
268 ; ARM-NEXT: adds r0, r0, r1
269 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
270 ; ARM-NEXT: adcs r6, r4
271 ; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
272 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
273 ; ARM-NEXT: mov r2, r5
274 ; ARM-NEXT: mov r3, r5
275 ; ARM-NEXT: bl __aeabi_lmul
276 ; ARM-NEXT: mov r4, r0
277 ; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
278 ; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
279 ; ARM-NEXT: mov r1, r7
280 ; ARM-NEXT: mov r2, r5
281 ; ARM-NEXT: mov r3, r5
282 ; ARM-NEXT: bl __aeabi_lmul
283 ; ARM-NEXT: adds r0, r0, r4
284 ; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
285 ; ARM-NEXT: adcs r1, r2
286 ; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
287 ; ARM-NEXT: adds r0, r2, r0
288 ; ARM-NEXT: adcs r1, r6
289 ; ARM-NEXT: lsls r1, r1, #1
290 ; ARM-NEXT: lsrs r2, r0, #31
291 ; ARM-NEXT: adds r1, r1, r2
292 ; ARM-NEXT: lsls r0, r0, #1
293 ; ARM-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
294 ; ARM-NEXT: lsrs r2, r2, #31
295 ; ARM-NEXT: adds r0, r0, r2
296 ; ARM-NEXT: add sp, #28
297 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
298 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 63)
299 ret i64 %tmp
300 }
302 define i64 @func9(i64 %x, i64 %y) nounwind {
303 ; ARM-LABEL: func9:
304 ; ARM: @ %bb.0:
305 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
306 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
307 ; ARM-NEXT: .pad #20
308 ; ARM-NEXT: sub sp, #20
309 ; ARM-NEXT: str r3, [sp, #16] @ 4-byte Spill
310 ; ARM-NEXT: mov r7, r2
311 ; ARM-NEXT: str r2, [sp, #12] @ 4-byte Spill
312 ; ARM-NEXT: mov r4, r1
313 ; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
314 ; ARM-NEXT: movs r5, #0
315 ; ARM-NEXT: mov r6, r0
316 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
317 ; ARM-NEXT: mov r1, r5
318 ; ARM-NEXT: mov r3, r5
319 ; ARM-NEXT: bl __aeabi_lmul
320 ; ARM-NEXT: str r1, [sp] @ 4-byte Spill
321 ; ARM-NEXT: mov r0, r4
322 ; ARM-NEXT: mov r1, r5
323 ; ARM-NEXT: mov r2, r7
324 ; ARM-NEXT: mov r3, r5
325 ; ARM-NEXT: bl __aeabi_lmul
326 ; ARM-NEXT: mov r7, r1
327 ; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
328 ; ARM-NEXT: adds r4, r0, r1
329 ; ARM-NEXT: adcs r7, r5
330 ; ARM-NEXT: mov r0, r6
331 ; ARM-NEXT: mov r1, r5
332 ; ARM-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
333 ; ARM-NEXT: mov r2, r6
334 ; ARM-NEXT: mov r3, r5
335 ; ARM-NEXT: bl __aeabi_lmul
336 ; ARM-NEXT: adds r0, r0, r4
337 ; ARM-NEXT: adcs r1, r5
338 ; ARM-NEXT: adds r0, r7, r1
339 ; ARM-NEXT: str r0, [sp] @ 4-byte Spill
340 ; ARM-NEXT: mov r4, r5
341 ; ARM-NEXT: adcs r4, r5
342 ; ARM-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
343 ; ARM-NEXT: mov r0, r7
344 ; ARM-NEXT: mov r1, r5
345 ; ARM-NEXT: mov r2, r6
346 ; ARM-NEXT: mov r3, r5
347 ; ARM-NEXT: bl __aeabi_lmul
348 ; ARM-NEXT: mov r6, r1
349 ; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
350 ; ARM-NEXT: adds r0, r0, r1
351 ; ARM-NEXT: str r0, [sp] @ 4-byte Spill
352 ; ARM-NEXT: adcs r6, r4
353 ; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
354 ; ARM-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
355 ; ARM-NEXT: mov r2, r5
356 ; ARM-NEXT: mov r3, r5
357 ; ARM-NEXT: bl __aeabi_lmul
358 ; ARM-NEXT: mov r4, r0
359 ; ARM-NEXT: str r1, [sp, #16] @ 4-byte Spill
360 ; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
361 ; ARM-NEXT: mov r1, r7
362 ; ARM-NEXT: mov r2, r5
363 ; ARM-NEXT: mov r3, r5
364 ; ARM-NEXT: bl __aeabi_lmul
365 ; ARM-NEXT: adds r0, r0, r4
366 ; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
367 ; ARM-NEXT: adcs r1, r2
368 ; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload
369 ; ARM-NEXT: adds r0, r2, r0
370 ; ARM-NEXT: adcs r1, r6
371 ; ARM-NEXT: add sp, #20
372 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
373 %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 64)
374 ret i64 %tmp
375 }